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mosel vitelic 1 v826664g24s 512 mb 200-pin ddr unbuffered sodimm 64m x 64 preliminary v826664g24s rev. 1.2 may 2003 features jedec 200 pin ddr unbuffered small-outline, dual in-line memory module (sodimm); 67,108,864 x 64 bit organization. utilizes high performance 32m x 8 ddr sdram in soc packages single +2.5v ( 0.2v) power supply single +2.6v ( 0.1v) power supply for ddr400 programmable cas latency, burst length, and wrap sequence (sequential & interleave) auto refresh (cbr) and self refresh all inputs, outputs are sstl-2 compatible 8192 refresh cycles every 64 ms serial presence detect (spd) description the v826664g24s memory module is organized 67,108,864 x 64 bits in a 200 pin memory module. the 64m x 64 memory module uses 16 mosel- vitelic 32m x 8 ddr sdram. the x64 modules are ideal for use in high performance computer systems where increased memory density and fast access times are required. module speed a1 pc1600 (100mhz @ cl2) b0 pc2100b (133mhz @ cl2.5) b1 pc2100a (133mhz @ cl2) c0 pc2700 (166mhz @ cl2.5) module speed d4 d3 d0 c0 b1 b0 a1 units t ck clock frequency (max.) 200 (pc400c) 200 (pc400b) 200 (pc400a) 166 (pc333) 143 (pc266a) 133 (pc266b) 125 (pc200) mhz t ac clock cycle time cas latency = 2 7.57.57.57.57.51010ns t ac clock cycle time cas latency = 2.5 665677.58ns t ac clock cycle time cas latency = 3 555 ----ns t rcd trp parameter4333232clk t rp trcd parameter 4333232clk
2 mosel vitelic v826664g24s v826664g24s rev. 1.2 may 2003 part number information v 8 2 66 64 g 2 4 s x s g - xx ddr sdram 2.5v width depth 200 pin unbuffered sodimm x8 component refresh rate 8k 4 banks sttl component rev level component package, s = soc lead finish g = gold speed a1 (100mhz@cl2) mosel vitelic manufactured b0 (133mhz@cl2.5) b1 (133mhz@cl2) c0 (166mhz@cl2.5) 2.6v for ddr400 d0 (200mhz@2.5-3-3) d3 (200mhz@3-3-3) d4 (200mhz@3-4-4)
mosel vitelic v826664g24s 3 v826664g24s rev. 1.2 may 2003 block diagram a0 sa0 serial pd u20 sda a1 sa1 a2 sa2 ba0, ba1 a0-a12 ras# ba0, ba1: ddr sdrams u1-u8 a0-a12: ddr sdrams u1-u8 ras#: ddr sdrams u1-u8 cas#: ddr sdrams u1-u8 cke0: ddr sdrams u1 0 -u8 0 cke1: ddr sdrams u1 1 -u8 1 we#: ddr sdrams u1-u8 cas# cke0 cke1 we# v ref v ss ddr sdrams ddr sdrams dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 u8 0 dq dq dq dq dq dq dq dq dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 u6 0 dq dq dq dq dq dq dq dq dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 u5 0 dq dq dq dq dq dq dq dq dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 u4 0 dq dq dq dq dq dq dq dq dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 u2 0 dq dq dq dq dq dq dq dq dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dm cs# dqs u1 0 dq dq dq dq dq dq dq dq dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dm0 cs0# u3 0 dq dq dq dq dq dq dq dq wp scl u1 1 dq dq dq dq dq dq dq dq u2 1 dq dq dq dq dq dq dq dq u3 1 dq dq dq dq dq dq dq dq u5 1 dq dq dq dq dq dq dq dq cs1# dm cs# dqs dm cs# dqs dm cs# dqs dm cs# dqs dm cs# dqs dm cs# dqs dqs0 dm7 dqs7 dm2 dqs2 dm5 dqs5 u6 1 dq dq dq dq dq dq dq dq dm cs# dqs dm4 dqs4 dm3 dqs3 dm cs# dqs dm cs# dqs u7 0 dq dq dq dq dq dq dq dq u7 1 dq dq dq dq dq dq dq dq dm cs# dqs dm cs# dqs dm cs# dqs dm cs# dqs dm6 dqs6 dm1 dqs1 u4 1 dq dq dq dq dq dq dq dq dm cs# dqs u8 1 dq dq dq dq dq dq dq dq dm cs# dqs v ddq v dd ddr sdrams ddr sdrams ddr sdram x 8 ck0 ck0# 120 ddr sdram x 8 ck1 ck1# 120 120 ck2 ck2#
4 mosel vitelic v826664g24s v826664g24s rev. 1.2 may 2003 pin configurations (front side/back side) notes: * these pins are not used in this module. pin front pin front pin front pin back pin back pin back 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 vref vss dq0 dq1 vdd dqs0 dq2 vss dq3 dq8 vdd dq9 dqs1 vss dq10 dq11 vdd ck0 ck0 vss dq16 dq17 vdd dqs2 dq18 vss dq19 dq24 vdd dq25 dqs3 vss dq26 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 dq27 vdd cb0 cb1 vss dqs8 cb2 vdd cb3 du vss ck2 ck2 vdd cke1 du(a13) a12 a9 vss a7 a5 a3 a1 vdd a10/ap ba0 we s0 du vss dq32 dq33 vdd dqs4 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 dq34 vss dq35 dq40 vdd dq41 dqs5 vss dq42 dq43 vdd vdd vss vss dq48 dq49 vdd dqs6 dq50 vss dq51 dq56 vdd dq57 dqs7 dq58 dq58 dq59 vdd sda scl vddspd vddid 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 vref vss dq4 dq5 vdd dm0 dq6 vss dq7 dq12 vdd dq13 dm1 vss dq14 dq15 vdd vdd vss vss dq20 dq21 vdd dm2 dq22 vss dq23 dq28 vdd dq29 dm3 vss dq30 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 dq31 vdd cb4 cb5 vss dm8 cb6 vdd cb7 du/(reset) vss vss vdd vdd cke0 du(ba2) a11 a8 vss a6 a4 a2 a0 vdd ba1 ras cas s1 du vss dq36 dq37 vdd dm4 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 dq38 vss dq39 dq44 vdd dq45 dm5 vss dq46 dq47 vdd ck1 ck1 vss dq52 dq53 vdd dm6 dq54 vss dq55 dq60 vdd dq61 dm7 vss dq62 dq63 vdd sa0 sa1 sa2 du pin names pin pin description a0~a12 address input (multiplexed) ba0~ba1 bank select address dq0~dq63 data input/output dqs0~dqs7 data strobe input/output ck0~ck2, ck0 ~ck2 , clock input cke0, cke1 clock enable input cs0 , cs1 chip select input ras row address strobe cas column address strobe we write enable dm0~dm7 data - in mask vdd power supply 2.5v, ddr400 2.6v vddq power supply for dqs 2.5v, ddr400 2.6v vss ground vref power supply for reference vddspd serial eepom power supply (2.3v to 3.6v) sda serial data i/o scl serial clock sa0~2 address in eeprom vddid vdd identification flag nc no connection pin pin description key key
mosel vitelic v826664g24s 5 v826664g24s rev. 1.2 may 2003 serial presence detect information bin sort: a1 (pc1600 @ cl2) b0 (pc2100b @ cl2.5) b1 (pc2100a @ cl2) c0 (pc2700 @ cl2.5) byte # function described function supported hex value a1 b0 b1 c0 d0 d3 d4 a1 b0 b1 c0 d0 d3 d4 0 defines # of bytes written into serial memory at module manufacturer 128bytes 80h 1 total # of bytes of spd memory device 256bytes 08h 2 fundamental memory type sdram ddr 07h 3 # of row address on this assembly 13 0dh 4 # of column address on this assembly 10 0ah 5 # of module rows on this assembly 2 bank 02h 6 data width of this assembly 64 bits 40h 7 .........data width of this assembly - 00h 8 vddq and interface standard of this assembly sstl 2.5v 04h 9 ddr sdram cycle time at highest cas latency 8ns 7.5ns 7ns 6ns 5ns 5ns 5ns 80h 75h 70h 60h 50h 50h 50h 10 ddr sdram access time from clock at highest cl 0.8 ns 0.75 ns 0.75 ns 0.70 ns 0.65 ns 0.65 ns 0.65 ns 80h 75h 75h 70h 65h 65h 65h 11 dimm configuration type(non-parity, parity, ecc) non-parity, ecc 00h 12 refresh rate & type 7.8us & self refresh 82h 13 primary ddr sdram width x8 08h 14 error checking ddr sdram data width n/a 00h 15 minimum clock delay for back-to-back random column address t ccd =1clk 01h 16 ddr sdram device attributes : burst lengths supported 2,4,8 0eh 17 ddr sdram device attributes : # of banks on each ddr sdram 4 banks 04h 18 ddr sdram device attributes : cas latency supported 2,2.5,3 0ch 0ch 0ch 0ch 1ch 1ch 1ch 19 ddr sdram device attributes : cs latency 0clk 01h 20 ddr sdram device attributes : we latency 1clk 02h 21 ddr sdram module attributes differential clock / non registered 20h 22 ddr sdram device attributes : general +/-0.2v voltage tolerance 00h 23 ddr sdram cycle time at second highest cl 10ns 10ns 7.5ns 7.5ns 5.0ns 6.0ns 6.0ns a0h a0h 75h 75h 50h 60h 60h d0 (pc3200 @ 2.5-3-3) d3 (pc3200 @ 3-3-3 ) d4 (pc3200 @ 3-4-4)
6 mosel vitelic v826664g24s v826664g24s rev. 1.2 may 2003 24 ddr sdram access time from clock at highest cl 0.8 ns 0.75 ns 0.75 ns 0.70 ns 0.65 ns 0.70 ns 0.70 ns 80h 75h 75h 70h 65h 70h 70h 25 ddr sdram cycle time at third highest cl - - - - 7.5ns 7.5ns 7.5ns 00h 00h 00h 00h 75h 75h 75h 26 ddr sdram access time from clock at third highest cl - - - - 0.75 ns 0.75 ns 0.75 ns 00h 00h 00h 00h 75h 75h 75h 27 minimum row precharge time (=t rp ) 20ns 20ns 15ns 18ns 15ns 15ns 20ns 50h 50h 3ch 48h 3ch 3ch 50h 28 minimum row activate to row active delay(=t rrd ) 15ns 15ns 15ns 12ns 10ns 10ns 10ns 3ch 3ch 3ch 30h 28h 28h 28h 29 minimum ras to cas delay(=t rcd ) 20ns 20ns 15ns 18ns 15ns 15ns 20ns 50h 50h 3ch 48h 3ch 3ch 50h 30 minimum active to precharge time(=t ras ) 50ns 45ns 45ns 42ns 40ns 40ns 40ns 32h 2dh 2dh 2ah 28h 28h 28h 31 module row density 256mb 40h 32 command and address signal input setup time 1.1ns 0.9ns 0.9ns 0.75 ns 0.6ns 0.6ns 0.6ns b0h 90h 90h 75h 60h 60h 60h 33 command and address signal input hold time 1.1ns 0.9ns 0.9ns 0.75 ns 0.6ns 0.6ns 0.6ns b0h 90h 90h 75h 60h 60h 60h 34 data signal input setup time 0.6ns 0.5ns 0.5ns 0.45 ns 0.4ns 0.4ns 0.4ns 60h 50h 50h 45h 40h 40h 40h 35 data signal input hold time 0.6ns 0.5ns 0.5ns 0.45 ns 0.4ns 0.4ns 0.4ns 60h 50h 50h 45h 40h 40h 40h 36-40 superset information (may be used in future) 00h 41 sdram device minimum active to active/auto- refresh time (=t rc ) 70ns 65ns 65ns 60ns 60ns 60ns 60ns 46h 41h 41h 3ch 3ch 3ch 3ch 42 sdram device minimum active to autorefresh to active/auto-refresh time (=t rfc ) 80ns 75ns 75ns 72ns 70ns 70ns 70ns 50h 4bh 4bh 48h 46h 46h 46h 43 sdram device maximum device cycle time (=t ck max ) 12ns 12ns 12ns 12ns 12ns 12ns 12ns 30h 30h 30h 30h 30h 30h 30h 44 sdram device maximum skew between dqs and dq signals (=t dqsq ) 0.6ns 0.5ns 0.5ns 0.45 ns 0.4ns 0.4ns 0.4ns 3ch 32h 32h 2dh 28h 28h 28h 45 sdram device maximum read datahold skew factor (=t qhs ) 1ns 0.75 ns 0.75 ns 0.60 ns 0.55 ns 0.55 ns 0.55 ns a0h 75h 75h 60h 55h 55h 55h 46-61 superset information (may be used in future) - 00h 62 spd data revision code initial release 00h 00h 00h 00h 11h 11h 11h 63 checksum for bytes 0 ~ 62 - e8h 23h cbh 4ch a4h bfh e7h 64 manufacturer jedec id code mosel vitelic 40h byte # function described function supported hex value a1 b0 b1 c0 d0 d3 d4 a1 b0 b1 c0 d0 d3 d4 serial presence detect information (cont.)
mosel vitelic v826664g24s 7 v826664g24s rev. 1.2 may 2003 dc operating conditions (t a = 0 to 70c, voltage referenced to v ss = 0v) notes: 1. v ddq must not exceed the level of v dd . 2. v il (min) is acceptable -1.5v ac pulse width with <=5ns of duration. 3. the value of v ref is approximately equal to 0.5v ddq . 65 - 71 ....... manufacturer jedec id code 00h 72 manufacturing location 02=taiwan 05=china 0a=s-ch 73-90 module part number (ascii) v826664g24s 91 manufacturer revison code (for pcb) 0 00 92 manufacturer revison code (for component) 0 00 93 manufacturing date (week) - - 94 manufacturing date (year) - - 95~9 8 assembly serial # - - 99~1 27 manufacturer specific data (may be used in fu- ture) undefined 00h 128~ 255 open for customer use undefined 00h parameter symbol min typ. max unit note power supply voltage v dd 2.3 2.5 2.7 v power supply voltage for ddr400 v dd 2.5 2.6 2.7 v power supply voltage v ddq 2.3 2.5 2.7 v 1 power supply voltage for ddr400 v ddq 2.5 2.6 2.7 v 1 input high voltage v ih v ref + 0.15 - v ddq + 0.3 v input low voltage v il -0.3 - v ref - 0.15 v 2 i/o termination voltage v tt v ref - 0.04 v ref v ref + 0.04 v reference voltage v ref v ddq/2 - 0.05 - v ddq/2 + 0.05 v input leakage current i i -2 - 2 a output leakage current io z -5 - 5 a output high current (v out = 1.95v) io h -16.8 - - ma output low current (v out = 0.35v) io l 16.8 - - ma byte # function described function supported hex value a1 b0 b1 c0 d0 d3 d4 a1 b0 b1 c0 d0 d3 d4
8 mosel vitelic v826664g24s v826664g24s rev. 1.2 may 2003 ac operating conditions (t a = 0 to 70 c, voltage referenced to v ss = 0v) notes: 1. vid is the magnitude of the difference between the input level on ck and the input on ck. 2. the value of vix is expected to equal 0.5*v ddq of the transmitting device and must track variations in the dc level of the same. ac operating test conditions (t a = 0 to 70c, voltage referenced to v ss = 0v) parameter symbol min max unit note input high (logic 1) voltage, dq, dqs and dm signals v ih(ac) v ref + 0.31 v input low (logic 0) voltage, dq, dqs and dm signals v il(ac) v ref - 0.31 v input differential voltage, ck and ck inputs v id(ac) 0.7 v ddq + 0.6 v 1 input crossing point voltage, ck and ck inputs v ix(ac) 0.5*v ddq-0.2 0.5*v ddq+0.2 v2 parameter value unit reference voltage v ddq x 0.5 v termination voltage v ddq x 0.5 v ac input high level voltage (v ih , min) v ref + 0.31 v ac input low level voltage (v il , max) v ref - 0.31 v input timing measurement reference level voltage v ref v output timing measurement reference level voltage v tt v input signal maximum peak swing 1.5 v input minimum signal slew rate 1 v/ns termination resistor (r t ) 50 ohm series resistor (r s ) 25 ohm output load capacitance for access time measurement (c l ) 30 pf
mosel vitelic v826664g24s 9 v826664g24s rev. 1.2 may 2003 ddr sdram i dd spec table * module i dd was calculated on the basis of component i dd and can be differently measured according to dq loading cap. detailed test conditions for ddr sdram idd1 & idd idd1 : operating current: one bank operation 1. typical case : vdd = 2.5v, t=25? c 2. worst case : vdd = 2.7v, t= 10? c 3. only one bank is accessed with trc(min), burst mode, address and control inputs on nop edge are changing once per clock cycle. lout = 0ma 4. timing patterns - ddr200(100mhz, cl=2) : tck = 10ns, cl2, bl=4, trcd = 2*tck, tras = 5*tck read : a0 n r0 n n p0 n a0 n - repeat the same timing with random address changing *50% of data changing at every burst - ddr266b(133mhz, cl=2.5) : tck = 7.5ns, cl=2.5, bl=4, trcd = 3*tck, trc = 9*tck, tras = 5*tck read : a0 n n r0 n p0 n n n a0 n - repeat the same timing with random address changing *50% of data changing at every burst - ddr266a (133mhz, cl=2) : tck = 7.5ns, cl=2, bl=4, trcd = 3*tck, trc = 9*tck, tras = 5*tck read : a0 n n r0 n p0 n n n a0 n - repeat the same timing with random address changing *50% of data changing at every burst legend : a=activate, r=read, w=write, p=precharge, n=nop symbol a1 pc1600 cl=2 b0 pc2100b cl=2.5 b1 pc2100a cl=2 c0 pc2700a cl=2.5 d0/d3/d4 pc3200a cl=3 unit symbol idd0 720 800 800 880 960 ma idd0 idd1 800 960 960 1120 1280 ma idd1 idd2p 120 120 120 120 120 ma idd2p idd2f 440 500 500 560 620 ma idd2f idd2q 280 340 340 380 420 ma idd2q idd3p 480 500 500 580 660 ma idd3p idd3n 720 740 740 900 1060 ma idd3n idd4r 1200 1520 1520 1840 2160 ma idd4r idd4w 1040 1360 1360 1680 2000 ma idd4w idd5 1440 1520 1520 1600 1680 ma idd5 idd6 normal 48 48 48 48 48 ma idd6 low power 29 29 29 29 29 ma idd7 2000 2400 2400 2800 3200 ma idd7
10 mosel vitelic v826664g24s v826664g24s rev. 1.2 may 2003 input/output capacitance (v dd = 2.5v, v dd = 2.6v, v ddq = 2.5v, v ddq = 2.6v, t a = 25c, f = 1mhz) ac characteristics (ac operating conditions unless otherwise noted) parameter symbol min max unit input capacitance (a 0 ~ a 11 , ba 0 ~ ba 1 , ras , cas , we ) cin 1 36 45 pf input capacitance (cke 0 ) cin 2 36 45 pf input capacitance (cs 0 ) cin 3 34 42 pf input capacitance (clk 1 , clk 2 ) cin 4 34 38 pf data & dqs input/output capacitance (dq 0 ~dq 63 ) c out 89pf input capacitance (dm0~dm8) cin 5 89pf parameter sym- bol (ddr400a) d0 (ddr400b) d3 (ddr400c) d4 (ddr333) c0 (ddr266a) b1 (ddr266b) b0 (ddr200) a1 unit note min max min max min max min max min max min max min max row cycle time t rc 60 - 60 - 60 - 60 - 65 - 65 - 70 - ns auto refresh row cycle time t rfc 70 - 70 - 70 - 72 - 75 - 75 - 80 - ns row active time t ras 40 120k 40 120k 40 120k 42 120k 45 120k 45 120k 50 120k ns row address to column address delay t rcd 15 - 15 - 20 - 18 - 15 - 20 - 20 - ns row active to row active delay t rrd 10 - 10 - 10 - 12 - 15 - 15 - 15 - ns column address to column ad- dress delay t ccd 1 - 1 - 1 - 1 - 1 - 1 - 1 - clk row precharge time t rp 15 - 15 - 20 - 18 - 15 - 20 - 20 - ns write recovery time t wr 15 - 15 - 15 - 12 - 15 - 15 - 15 - ns last data-in to read command t drl 1 - 1 - 1 - 1 - 1 - 1 - 1 - clk output load circuit (sstl_2) o utput z0=50 ? c load =30pf v ref =0.5*v dd q r t =50 ? v tt =0.5*v ddq
mosel vitelic v826664g24s 11 v826664g24s rev. 1.2 may 2003 ac characteristics (cont.) auto precharge write recovery + precharge time t dal 35 - 35 - 35 - 35 - 35 - 35 - 35 - ns system clock cy- cle time cas latency = 3 t ck 5 12 5 12 5 12 - 12 - 12 - 12 - 12 ns cas latency = 2.5 5 12 6 12 6 12 6 12 7 12 7.5 12 8 12 ns cas latency = 2 7.5 12 7.5 12 7.5 12 7.5 12 7.5 12 10 12 10 12 ns clock high level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 clk clock low level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 clk data-out edge to clock edge skew t ac -0.65 0.65 -0.65 0.65 -0.65 0.65 -0.75 0.75 -0.75 0.75 -0.75 0.75 -0.8 0.8 ns dqs-out edge to clock edge skew t dqsck -0.60 0.60 -0.60 0.60 -0.60 0.60 -0.75 0.75 -0.75 0.75 -0.75 0.75 -0.8 0.8 ns dqs-out edge to data-out edge skew t dqsq - 0.40 - 0.40 - 0.40 - 0.45 - 0.5 - 0.5 - 0.6 ns data-out hold time from dqs t qh t hpmin - 0.75ns - t hpmin - 0.75ns - t hpmin - 0.75ns - t hpmin - 0.75ns - t hpmin - 0.75ns - t hpmin - 0.75ns - t hpmin - 0.75n s - ns 1 clock half period t hp t ch/l min - t ch/l min - t ch/l min - t ch/l min - t ch/l min - t ch/l min - t ch/l min - ns 1 input setup time (fast slew rate) t is 0.6 - 0.6 - 0.6 - 0.75 - 0.9 - 0.9 - 1.1 - ns 2,3,5, 6 input hold time (fast slew rate) t ih 0.6 - 0.6 - 0.6 - 0.75 - 0.9 - 0.9 - 1.1 - ns 2,3,5, 6 input setup time (slow slew rate) t is 0.75 - 0.75 - 0.75 - 0.8 - 1.0 - 1.0 - 1.1 - ns 2,4,5, 6 input hold time (slow slew rate) t ih 0.75 - 0.75 - 0.75 - 0.8 - 1.0 - 1.0 - 1.1 - ns 2,4,5, 6 input pulse width t ipw 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 2.2 - 2.2 - - - ns 6 write dqs high level width t dqsh 0.35 0.35 0.35 0.35 0.35 0.35 0.35 clk write dqs low level width t dqsl 0.35 0.35 0.35 0.35 0.35 0.35 0.35 clk clk to first rising edge of dqs- in t dqss 0.72 1.25 0.72 1.25 0.72 1.25 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 clk parameter sym- bol (ddr400a) d0 (ddr400b) d3 (ddr400c) d4 (ddr333) c0 (ddr266a) b1 (ddr266b) b0 (ddr200) a1 unit note min max min max min max min max min max min max min max
12 mosel vitelic v826664g24s v826664g24s rev. 1.2 may 2003 notes: 1. this calculation accounts for tdqsq(max), the pulse width distortion of on-chip circuit and jitter. 2. data sampled at the rising edges of the clock : a0~a11, ba0~ba1, cke, cs , ras , cas , we . 3. for command/address input slew rate >=1.0v/ns 4. for command/address input slew rate >=0.5v/ns and <1.0v/ns 5. ck, ck slew rates are >=1.0v/ns 6. these parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by design or tester correlation. 7. data latched at both rising and falling edges of data strobes(dqs) : dq, dm 8. minimum of 200 cycles of stable input clocks after self refresh exit command, where cke is held high, is required to complet e self refresh exit and lock the internal dll circuit of ddr sdram. absolute maximum ratings note: operation at above absolute maximum rating can adversely affect device reliability data-in setup time to dqs-in (dq & dm) t ds 0.40 - 0.40 - 0.40 - 0.45 - 0.5 - 0.5 - 0.6 - ns 7 data-in hold time to dqs-in (dq & dm) t dh 0.40 - 0.40 - 0.40 - 0.45 - 0.5 - 0.5 - 0.6 - ns 7 dq & dm input pulse width t dipw 1.75 - 1.75 - 1.75 - 1.75 - 1.75 - 1.75 - 2 - ns read dqs preamble time t rpre 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 clk read dqs postamble time t rpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 clk write dqs preamble setup time t wpres 0 - 0 - 0 - 0 - 0 - 0 - 0 - clk write dqs preamble hold time t wpreh 0.25 - 0.25 - 0.25 - 0.25 - 0.25 - 0.25 - 0.25 - clk write dqs postamble time t wpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 clk mode register set delay t mrd 2- 2- 2- 2- 2 - 2 - 2 - clk power down exit time to any command t xpdn 1 - 1 - 1 - 1 - 1 - 1 - 1 - clk exit self refresh to non-read command t xsnr 200 - 200 - 200 - 200 - 75 - 75 - 80 - clk exit self refresh to read com- mand t xsrd 200 - 200 - 200 - 200 - 200 - 200 - 200 - clk 8 average periodic refresh interval t refi - 7.8 - 7.8 - 7.8 - 7.8 - 7.8 - 7.8 - 7.8 us parameter symbol rating unit ambient temperature t a 0 ~ 70 c storage temperature t stg -55 ~ 125 c voltage on any pin relative to v ss v in , v out -0.5 ~ 3.6 v voltage on v dd relative to v ss v dd -0.5 ~ 3.6 v voltage on v ddq relative to v ss v ddq -0.5 ~ 3.6 v output short circuit current i os 50 ma power dissipation p d 9.5 w soldering temperature time t solder 260 10 c sec parameter sym- bol (ddr400a) d0 (ddr400b) d3 (ddr400c) d4 (ddr333) c0 (ddr266a) b1 (ddr266b) b0 (ddr200) a1 unit note min max min max min max min max min max min max min max
mosel vitelic v826664g24s 13 v826664g24s rev. 1.2 may 2003 package dim ensions tolerances : .006(.15) unless otherwise specified 2.70 2.50 units : inches (millimeters) full r 2x 0.17 (4.20) 0.456 11.40 1.896 (47.40) 0.24 (6.0) 0.086 0.79 (20.00) 2.15 (63.60) (67.60) detail z 0.16 0.0039 (4.00 0.10) 0.04 0.0039 (1.00 0.1) 2- 0.07 (1.80) 1.25 (31.75) 0.16 0.039 (4.00 0.10) 0.096 (2.40) 0.07 (1.8) 0.150 max 0.04 0.0039 (1.00 0.10) 0.157 min (4.00 min) (3.80 max) 0.157 min (4.00 min) 1 0.024 typ 0.018 0.001 0.01 (0.25) (0.45 0.03) (0.60 typ) 0.102 min (2.55 min) detail y 2 0.098 2.45 40 42 39 41 z y 199 200 0.008 (0.20) (0.20) 0.008 bevel edge
14 mosel vitelic v826664g24s v826664g24s rev. 1.2 may 2003 label information c l = 2.5 (clk) t rcd = 3 (clk) t rp = 3 (clk) 2533 u unbuffered dimm pcxxxx x spd revision v826664g24sxxx-xx 512mb clxx pcxxxxu-2533-x-xx xxxx-xxxxxxx assembly in taiwan x -- mosel vitelic part number module density dimm manufacture date code criteria of pc2700 or pc3200 cas latency x - gerber ? file ? used ? for ? this ? design "a" ? : ? reference ? design ? for ? raw ? card ? a ? is ? used ? for ? this ? assembly "b" ? : ? reference ? design ? for ? raw ? card ? b ? is ? used ? for ? this ? assembly "c" ? : ? reference ? design ? for ? raw ? card ? c ? is ? used ? for ? this ? assembly "z" ? : ? none ? of ? the ? reference ? design ? were ? used ? for ? this ? assembly revision ? number ? of ? the ? reference ? design ? used "1" ? : ? 1st ? revision "2" ? : ? 2nd ? revision blank ? : ? not ? applicable c l = 2.5 (clk) t rcd = 3 (clk) t rp = 3 (clk) 2533 u unbuffered sodimm pc2100 08 spd revision 0 v826664g24sxxx-xx 512mb clxx pc2100u-2533-080-a xxxx-xxxxxxx assembly in taiwan a gerber file -- - mosel vitelic part number module density dimm manufacture date code criteria of pc2100 or pc1600 cas latency
mosel vitelic v826664g24s 15 v826664g24s rev. 1.2 may 2003 worldwide offices ? copyright , mosel vitelic corp. printed in u.s.a. the information in this document is subject to change without notice. mosel vitelic makes no commitment to update or keep cur- rent the information contained in this document. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of mosel-vitelic. mosel vitelic subjects its products to normal quality contr ol sampling techniques which are intended to provide an assuranc e of high quality products suitable for usual commercial applica - tions. mosel vitelic does not do testing appropriate to provid e 100% product quality assurance and does not assume any liab il- ity for consequential or incidental arising from any use of its prod - ucts. if such products are to be used in applications in whic h personal injury might occur from failure, purchaser must do i ts own quality assurance testing appropriate to such applications. u.s. sales offices u .s.a. 3 910 north first street s an jose, ca 95134 p hone: 408-433-6000 fax: 408-433-0952 taiwan 7f, no. 102 min-chuan e. road, sec. 3 taipei phone: 886-2-2545-1213 fax: 886-2-2545-1209 no 19 li hsin road science based ind. park hsin chu, taiwan, r.o.c. phone: 886-3-579-5888 fax: 886-3-566-5888 singapore 10 anson road #23-13 international plaza singapore 079903 phone: 65-6323-1801 fax: 65-6323-7013 japan onze 1852 building 6f 2-14-6 shintomi, chuo-ku tokyo 104-0041 phone: 81-3-3537-1400 fax: 81-3-3537-1402 uk & ireland suite 50, grovewood business centre strathclyde business park bellshill, lanarkshire, scotland, ml4 3nq phone: 44-1698-748515 fax: 44-1698-748516 w est 3 910 north first street s an jose, ca 95134 p hone: 408-433-6000 fax: 408-433-0952 central / east 604 fieldwood circle richardson, tx 75081 phone: 214-352-3775 fax: 214-904-9029

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