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d a t a sh eet preliminary speci?cation file under integrated circuits, ic02 1997 feb 03 integrated circuits SAA4961 integrated multistandard comb filter
1997 feb 03 2 philips semiconductors preliminary speci?cation integrated multistandard comb ?lter SAA4961 features one chip adaptive multistandard comb filter time discrete but continuous amplitude signal processing with analog interfaces internal delay lines, filters, clock processing and signal switches alignment-free no hanging dots or residual cross colour on vertical transients few external components. general description the SAA4961 is an adaptive alignment-free one chip comb filter compatible with both pal and ntsc systems and provides high performance in y/c separation. quick reference data ordering information symbol parameter min. typ. max. unit v cca analog supply voltage 4.75 5 5.5 v v ddd digital supply voltage 4.75 5 5.5 v v cco analog supply voltage output buffer 4.75 5 5.5 v v ccpll analog supply voltage pll 4.75 5 5.5 v i cco analog supply current output buffer - 70 90 ma i ddd digital supply current - 10 20 ma i cca analog supply current - 35 40 ma i ccpll analog supply current pll - 1.5 3.0 ma v 17(p-p) cvbs and y input signal (peak-to-peak value) 0.7 1 1.4 v v 10(p-p) chrominance input signal (peak-to-peak value) - 0.7 1 v v 1(p-p) subcarrier input signal (peak-to-peak value) 100 200 400 mv v 14(p-p) luminance output signal (peak-to-peak value) 0.6 1 1.54 v v 12(p-p) chrominance output signal (peak-to-peak value) - 0.7 1.1 v v 15(p-p) cvbs and y output signal (peak-to-peak value) 0.6 1 1.54 v type number package name description version SAA4961 dip28 plastic dual in-line package; 28 leads (600 mil) sot117-1
1997 feb 03 3 philips semiconductors preliminary speci?cation integrated multistandard comb ?lter SAA4961 block diagram handbook, full pagewidth mha546 100 m f 100 nf 100 nf 100 nf 100 nf s2b s2a s2c s1 lpfo1 lpfo1 lpfo2 cont1 cont1 cont1 cvbsdl ccomb ycomb - 1 cl3 cl3 cl3 bpf cl3 bpf cl3 bpf cl3 cl3 cl3 bpf comb filter delay lines hsel syspal delay compensation lpfi clamp sync separator h det v det cont2 + 5 v + 5 v + 5 v lpf control lpfo1 cl3 cont1 cont2 stops 100 m f 100 nf + 5 v 100 m f 100 nf + 5 v 100 m f 100 nf + 5 v bias d a pllgnd 26 27 v ccpll agnd v cca 97 ognd 11 8 v cco dgnd 21 22 v ddd 524 15 14 12 c o y o cvbso 4162 28 i.c. i.c. i.c. i.c. h det v det clock control sys1 sys2 hsel syspal cl3 stops fsc byp ssyn fscsw sys2 sys1 combena 1 3 6 13 23 20 25 19 17 csy y ext /cvbs lpfion 18 c ext 10 a a a d 47 w 100 nf 100 nf current reference voltage reference refbp refdl a a a SAA4961 fig.1 block diagram. remark: all switches in low position.
1997 feb 03 4 philips semiconductors preliminary speci?cation integrated multistandard comb ?lter SAA4961 pinning symbol pin description fsc 1 subcarrier frequency input i.c. 2 internally connected byp 3 bypass mode forcing input i.c. 4 internally connected refbp 5 decoupling capacitor for band-pass ?lter reference ssyn 6 bypass de?nition input v cca 7 analog supply voltage v cco 8 analog supply voltage output buffer agnd 9 analog ground (signal reference) c ext 10 external chrominance input signal ognd 11 analog ground output buffer c o 12 chrominance output signal fscsw 13 f sc reference selection input y o 14 luminance output signal cvbso 15 uncombed cvbs output signal i.c. 16 internally connected y ext /cvbs 17 cvbs (vbs) input signal lpfion 18 disable alias-?lter csy 19 storage capacitor sys1 20 standard select 1 input dgnd 21 digital ground v ddd 22 digital supply voltage sys2 23 standard select 2 input refdl 24 decoupling capacitor for delay lines combena 25 comb-mode output signal pllgnd 26 analog ground pll v ccpll 27 analog supply voltage pll i.c. 28 internally connected fig.2 pin configuration. handbook, halfpage fsc i.c. byp i.c. refbp ssyn v cca v cco agnd c ext ognd c o fscsw y o i.c. v ccpll pllgnd combena sys2 v ddd refdl dgnd sys1 csy lpfion y ext /cvbs i.c. cvbso 1 2 3 4 5 6 7 8 9 10 11 12 13 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 SAA4961 mha547
1997 feb 03 5 philips semiconductors preliminary speci?cation integrated multistandard comb ?lter SAA4961 functional description functional requirements the multistandard comb filter processes the video standards pal b, g, h, m, n and ntsc m. pal d and i signals can also be processed but with the drawback of a slightly reduced bandwidth. for secam and svhs signals the input signals can be bypassed to the output without processing by selecting the bypass-mode. a sync separation circuit is incorporated to generate control signals for the internal clock processing. with a sync compression of up to 12 db the sync separator works properly (see fig.4). the ic is controlled via six pins: 1. byp forces the ic into the bypass-mode (comb filter function off) 2. ssyn defines whether the comb-mode is entered synchronously or not and defines the polarity of the byp pin 3. sys1 selects the video standard 4. sys2 selects the video standard 5. fscsw selects the reference frequency f sc or 2 f sc 6. lpfion enables the internal pre-filter. it is possible to select the following modes of operation: comb-mode: luminance and chrominance comb filter function active if bypass-mode not active. bypass-mode: signal processing not active, all clocks inactive, c ext (pin 10) is bypassed to c o (pin 12) and y ext /cvbs (pin 17) is bypassed to y o (pin 14) and cvbso (pin 15). this mode is forced via byp (pin 3). if the stimulus of the mode is changed, the ic is following the new mode after the stabilization time given in table 1. table 1 stabilization time after mode change the mode change from bypass to comb depends on ssyn (pin 6) and can be asynchronous or synchronous related to the vertical pulse. the mode change from comb to bypass is always performed asynchronously. mode change maximum stabilization time comb-mode to bypass-mode 1 line bypass-mode to comb-mode 1 ?eld pin description fsc ( pin 1) input for the reference frequency f sc (see note 2 of chapter characteristics) or 2 f sc . for secam standard signals the best signal performance in bypass-mode is achieved by switching the fsc input signal off externally. byp ( pin 3) input signal that controls the operation mode. a low-pass filter is added to the input for suppression of subcarrier frequencies. thus applications are supported where the operation mode (comb or bypass) is controlled by the dc-level of the fsc input signal at pin 1. for those applications the byp input can be externally connected to fsc (pin 1). depending on ssyn (pin 6) the function of byp can be adapted to a certain application with respect to the polarity of the logic level and with respect to the behaviour when entering the comb-mode. depending on ssyn the byp input can be either inverted or non-inverted with the function as shown in table 2. table 2 bypass function depending on ssyn the behaviour when entering the comb-mode is different for the both selectable logic polarities while the bypass-mode is always entered asynchronously (immediately). table 3 behaviour when entering the comb-mode the pll and the clock processing are always stopped if the selected level for bypass is applied to byp (independent of the vertical pulse). ssyn byp selected mode low low comb-mode low high bypass-mode high low bypass-mode high high comb-mode ssyn entering comb-mode low immediately if byp = low high synchronized by vertical pulse if byp = high
1997 feb 03 6 philips semiconductors preliminary speci?cation integrated multistandard comb ?lter SAA4961 refbp ( pin 5) decoupling capacitor for the band-pass filter reference voltage. ssyn ( pin 6) input signal that controls the function of byp (pin 3). v cca ,v cco ,v ddd and v ccpll ( pins 7, 8, 22 and 27) supply voltages. agnd, ognd, dgnd and pllgnd ( pins 9, 11, 21 and 26) ground connection. agnd is used as signal reference for all analog input and output signals. c ext ( pin 10) input for an external chrominance signal which is correlated to the external vbs signal. c o ( pin 12) chrominance output signal. this output can be switched between the comb filtered chrominance from the cvbs signal and the external chrominance signal from the input c ext if the ic is forced into bypass-mode. table 4 c o output signal fscsw ( pin 13) input signal to select between f sc or 2 f sc as reference at the fsc input pin. table 5 reference frequency selection mode c o output signal comb comb ?ltered chrominance signal bypass external chrominance signal of c ext input fscsw selected reference high 2 f sc low f sc y o ( pin 14) vbs output signal. this output can be switched between the comb filtered luminance signal (including synchronization) and the external (c)vbs signal from the input y ext /cvbs. in comb-mode the output signal is delayed by 2 lines (1 line at ntsc) and by an additional processing delay. table 6 y o output signal cvbso ( pin 15) cvbs output signal directly from the input in bypass-mode or delayed by the signal processing time of 2 lines (1 line at ntsc) and an additional processing delay. table 7 cvbso output signal y ext /cvbs ( pin 17) input for the cvbs signal or for an external vbs signal. lpfion ( pin 18) input signal to disable the internal pre-filter lpfi. table 8 pre-?lter mode csy ( pin 19) sync top capacitor for the sync separator. mode y o output signal comb comb ?ltered luminance signal bypass external cvbs signal of y ext /cvbs input mode cvbso output signal comb delay compensated cvbs signal bypass external cvbs signal of y ext /cvbs input lpfion selected mode low lpfi inactive high lpfi active floating lpfi active
1997 feb 03 7 philips semiconductors preliminary speci?cation integrated multistandard comb ?lter SAA4961 sys1 and sys2 ( pins 20 and 23) system switch input signals to adapt the signal processing to the different cvbs standards. table 9 system switch input signals note 1. the standard pal b, g, h, d and i is internally preset as default. refdl ( pin 24) decoupling capacitor for the delay line reference voltage. combena ( pin 25) output signal that indicates the current mode of operation. this output is forced to low if the comb filter is in bypass-mode. table 10 mode of operation internal functional description s witched capacitor delay line delays the cvbs input signal by 2 lines and 4 lines (all pal standards) or by 1 line and 2 lines (ntsc standard). input signals for the delay lines are the cvbs signal, the clock cl3 (3 f sc ), the control signal hsel and the standard selection signal syspal. output signals are the non-delayed, the 2-line delayed and the 4-line delayed cvbs signal (pal) or the 1-line delayed and the 2-line delayed cvbs signal (ntsc). s witched capacitor b and -p ass f ilters (bpf s ) the comb filter input bpfs attenuate the low frequencies to guarantee a correct signal processing within the logical comb filter. sys1 sys2 standard low low pal m low high pal b, g, h, d and i; note 1 high low ntsc m high high pal n combena selected mode low bypass-mode; pll and clock processing stopped high comb-mode the comb filter output bpf reduces the alias components that are the result of the non-linear signal processing within the logical comb filter. l ogical comb filter separates the chrominance from the band-pass filtered cvbs signal. c ompensation delay compensates the internal processing time of the band-pass filters and the logical comb filter section. a dder the comb filtered luminance output signal is obtained by adding the delayed cvbs signal and the inverted comb filtered chrominance signal. l ow - pass f ilter i nput (lpfi) analog input low-pass filter to reduce the outband frequencies of emc. the input low-pass filter is included in the signal path but it can be switched off via the input signal lpfion. l ow - pass f ilter o utputs (lpfo1 and lpfo2) two different types of output low-pass filters (lpfo1 and lpfo2) are necessary to get equal signal delays within the luminance path and the chrominance path (important for good transient behaviour). the low-pass output filter type lpfo1 is used for the luminance output while lpfo2 is used for the chrominance output. the filters are analog 3rd order elliptic low-pass filters that convert the output signals from the time discrete to the time continuous domain (reconstruction filter). lpf control automatic tuning of the low-pass filters is achieved by adjusting the filter delays. the control information for all filters (cont1 and cont2) is derived from a built-in reference filter (lpfo1-type) that is part of a control loop. the control loop tunes the reference filter delay and thus all other filter delays to a time constant derived from the system clock cl3. c ontrol and clock processing (clock control) the control and clock processing block (see fig.9) consists of the sub-blocks pll, the clock processing and the mode control. the pll and the clock processing are released for operation if the input level at byp selects the comb-mode.
1997 feb 03 8 philips semiconductors preliminary speci?cation integrated multistandard comb ?lter SAA4961 main tasks of the control and clock processing are: clock generation of system clock cl3 delay line start control mode control. the signal processing is based on a 3 f sc system clock (cl3), that is generated by the clock processing from the f sc signal at fsc (pin 1) via a pll. because the subcarrier frequency divided by the line frequency results not in an integer value a clock phase correction of 180 is necessary every second line for pal standards or every line for ntsc standard. the clock phase correction is controlled by the input signals horizontal sync. additionally the delay line start is synchronized once a field to the input signals horizontal sync. the 25 hz pal offset is corrected in this way. the pll provides a master clock mck of 6 f sc , which is locked to the subcarrier frequency at fsc (pin 1). the system clock cl3 (3 f sc ) is obtained from mck by a divide-by-two circuit. the 180 phase shift is generated by stopping the divide-by-two circuit for one mck clock cycle. the generated clock is a pseudo-line-locked clock that is referenced to f sc . the sync separator generates the necessary signals h det and v det indicating the line (h) and the field (v) sync periods. the current mode of operation (bypass or comb) is external readable via combena (pin 25). the input signals of the control and clock processing (clock control) are: h det : analog horizontal pulse from sync separator v det : analog vertical pulse from sync separator fsc: subcarrier frequency (f sc or 2 f sc ) fscsw: reference frequency selection byp: bypass control signal ssyn: vertical synchronous mode selection for byp and polarity selection of byp. the output signals are: cl3: system clock (3 f sc ) hsel: line start signals for the delay lines stops: forces the comb filter via the switches s2a, s2b and s2c into the bypass-mode (always asynchronous) or comb-mode (synchronous or asynchronous with v int ; depending on ssyn) combena: high during comb-mode; otherwise low. table 11 function of stops signal h orizontal and vertical sync separator a built-in sync separator circuit generates the h det and v det signals from the y ext /cvbs input signal. this circuit is still operating properly at input signals with a 12 db attenuated sync in a normal 700 mv black-to-white video signal (see fig.4). c lamp the black level clamping of the video input signal is performed by the sync separator stage. the clamping level is nearly adequate to the voltage at refdl (pin 24). s ignal switch s1 the switch is included to bypass the low-pass input filter. for the cvbs input of the delay line block two signals can be selected via the slow signal switch s1. table 12 function of signal switch s1 s ignal switch s2a for the cvbso output two signals can be selected via the signal switch s2a. table 13 cvbso output signal s ignal switch s2b and s2c two switches are included to bypass the comb filter signal processing. the input video signal c ext for the switch s2c is internally biased. stops-state selected mode low comb high bypass lpfion-state delay line input low non-pre-?ltered input signal y ext /cvbs high pre-?ltered input signal y ext /cvbs floating pre-?ltered input signal y ext /cvbs stops-state cvbso output signal mode low delayed input cvbsdl comb high non-delayed input y ext /cvbs bypass
1997 feb 03 9 philips semiconductors preliminary speci?cation integrated multistandard comb ?lter SAA4961 for the y o output two signals can be selected via s2b (see table 14). table 14 y o output signal stops-state y o output signal mode low ycomb (combed luminance) comb high input y ext /cvbs bypass for the c o output two signals can be selected via s2c (see table 15). table 15 c o output signal stops-state c o output signal mode low ccomb (combed chrominance) comb high input c ext bypass limiting values in accordance with the absolute maximum rating system (iec 134). note 1. human body model: c = 100 pf; r = 1.5 k w ; v = 2 kv; machine model: c = 200 pf; r = 0 w ; v = 300 v. thermal characteristics symbol parameter conditions min. max. unit v cc supply voltage - 6.5 v v input voltage protection threshold except pin 1 - 0.3 v cc + 0.3 v i cc total supply current - 155 ma i o output current (c o , y o and cvbso) - 15 ma output current (combena) - 10 ma p tot total power dissipation - 900 mw t amb operating ambient temperature 0 70 c t stg storage temperature - 25 +150 c v es electrostatic handling note 1 symbol parameter value unit r th j-a thermal resistance from junction to ambient in free air 31 k/w
1997 feb 03 10 philips semiconductors preliminary speci?cation integrated multistandard comb ?lter SAA4961 characteristics v ddd =v cca =v cco =v ccpll =5v; t amb =25 c; input signal y ext /cvb s=1v (p-p) (0 db); input signal c = 0.7 v (p-p) (0 db); input signal fsc = 200 mv (p-p), sine wave, dc level = 2 v; input signal lpfion = 5 v; test signal: ebu colour bar 100/0/75/0 ccir471-1 ; source impedance for y ext /cvbs, c ext =75 w decoupled with 100 nf; source impedance for fsc = 75 w ; load impedance for cvbso, y o , c o =1k w and 20 pf in parallel; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supply voltage v cca analog supply voltage (pin 7) note 1 4.75 5 5.5 v v cco analog supply voltage output buffer (pin 8) note 1 4.75 5 5.5 v v ddd digital supply voltage (pin 22) note 1 4.75 5 5.5 v v ccpll analog supply voltage pll (pin 27) note 1 4.75 5 5.5 v fsc (pin 1) v 1(p-p) input ac voltage (peak-to-peak value) 100 200 400 mv input ac voltage is valid for sine wave ---- square wave 0.4 0.5 0.6 duty cycle v 1 input dc level 0 - 5.3 v c 1 input capacitance -- 10 pf i leak input leakage current -- 10 m a z 1 source impedance -- 800 w byp (pin 3) v ih high level input voltage 2.4 - v cc v v il low level input voltage 0 0.85 1.5 v i leak input leakage current -- 10 m a c 3 input capacitance -- 10 pf refbp (pin 5) v 5 dc voltage 1.1 1.25 1.4 v ssyn (pin 6) v ih high level input voltage 2.4 - v cc v v il low level input voltage 0 0.85 1.5 v i leak input leakage current -- 10 m a c 6 input capacitance -- 10 pf v cca (pin 7) i cca analog supply current - 35 40 ma v cco (pin 8) i cco supply current - 70 90 ma
1997 feb 03 11 philips semiconductors preliminary speci?cation integrated multistandard comb ?lter SAA4961 c ext (pin 10) v 10 input voltage (ac coupled) - 03db r 10 input resistance 1.25 v 500 700 1000 k w c 10 input capacitance -- 10 pf z 10 source impedance -- 1k w c o (pin 12) v 10 /v 12 bypass-mode: c o /c ext f sc 0.3f sc ; note 2 - 1 0 +1 db comb-mode: transfer function c-path see fig.10 v 12 dc offset voltage related to input - 400 0 +400 mv ?d v 12 ? dc jump when forcing into bypass-mode - 100 450 mv r 12 output resistance - 10 100 w r l load resistance (to ground) 0.3 -- k w c l load capacitance (to ground) -- 25 pf v 17 /v 12 suppression (comb depth) see figs 5 and 7; note 3 pal b, g, h, d, i 283 f h 26 30 - db (283 - 43) f h 20 24 - db (283 + 35) f h 20 24 - db pal m, ntsc m 227 f h 26 30 - db (227 - 35) f h 20 24 - db (227 + 28) f h 20 24 - db pal n 229 f h 26 30 - db (229 - 35) f h 20 24 - db (229 + 28) f h 20 24 - db fpn ?xed pattern noise for divided clock frequencies referenced to 0.7 v (p-p) 0.75f sc --- 30 db f sc --- 50 db 1.5f sc --- 37 db 2f sc --- 30 db a cr crosstalk suppression at vertical transients no-colour ? colour (0.7 v/v eff ) see fig.3 26 30 - db s/n signal-to-noise ratio (0.7 v/v eff noise) unweighted; f sc 0.3f sc ; note 2 56 72 - db a cr crosstalk between different inputs 0 to 5 mhz -- 60 - 40 db v 12(p-p) fsc residue in bypass-mode related to 700 mv (p-p) --- 60 db g d differential gain 0.95 -- symbol parameter conditions min. typ. max. unit
1997 feb 03 12 philips semiconductors preliminary speci?cation integrated multistandard comb ?lter SAA4961 fscsw (pin 13) v ih high level input voltage 2 - v cc v v il low level input voltage 0 - 0.8 v c 13 input capacitance -- 10 pf i leak input leakage current -- 10 m a y o (pin 14) v 14 /v 17 bypass-mode: c o /c ext 0 to 5 mhz - 1 0 +1 db comb-mode: transfer function y-path see fig.11 v 14 dc offset voltage related to input - 400 0 +400 mv ?d v 14 ? dc jump when forcing into bypass-mode - 200 450 mv r 14 output resistance - 10 100 w r l load resistance (to ground) 0.3 -- k w c l load capacitance (to ground) -- 25 pf v 17 /v 14 suppression (comb depth) see figs 6 and 8; note 3 pal b, g, h, d, i 283.75 f h 26 30 - db (283.75 - 43) f h 10 12 - db (283.75 + 35) f h 18 24 - db pal m 227.25 f h 26 30 - db (227.25 - 35) f h 10 12 - db (227.25 + 28) f h 18 24 - db pal n 229.25 f h 26 30 - db (229.25 - 35) f h 10 12 - db (229.25 + 28) f h 18 24 - db ntsc m 227.5 f h 26 30 - db (227.5 - 35) f h 10 12 - db (227.5 + 28) f h 18 24 - db fpn ?xed pattern noise for divided clock frequencies referenced to 0.7 v (p-p) black-to-white 0.75f sc --- 40 db f sc --- 30 db 1.5f sc --- 30 db 2f sc --- 20 db a cr crosstalk suppression at vertical transients gray ? multi-burst (0.7 v/v eff ) see fig.3 26 30 - db s/n signal-to-noise ratio (0.7 v/v eff noise) unweighted; 200 khz to 5 mhz 56 72 - db a cr crosstalk between different inputs 0 to 5 mhz -- 60 - 40 db v 14(p-p) fsc residue in bypass-mode related to 700 mv (p-p) --- 60 db g d differential gain 0.95 -- symbol parameter conditions min. typ. max. unit
1997 feb 03 13 philips semiconductors preliminary speci?cation integrated multistandard comb ?lter SAA4961 cvbso (pin 15) v 15 /v 17 bypass-mode: cvbso/cvbs 0 to 5 mhz - 1 0 +1 db comb-mode: transfer function cvbs-path see fig.11 v 15 dc offset voltage - 400 0 +400 mv ?d v 15 ? dc jump when forcing into bypass-mode - 200 450 mv r 15 output resistance - 10 100 w r l load resistance (to ground) 0.3 -- k w c l load capacitance (to ground) -- 25 pf fpn ?xed pattern noise for divided clock frequencies referenced to 0.7 v (p-p) black-to-white 0.75f sc --- 40 db f sc --- 30 db 1.5f sc --- 30 db 2f sc --- 20 db s/n signal-to-noise ratio (0.7 v/v eff noise) unweighted; 200 khz to 5 mhz 56 72 - db a cr crosstalk between different inputs 0 to 5 mhz -- 60 - 40 db v 15(p-p) fsc residue in bypass-mode related to 700 mv (p-p) --- 60 db g d differential gain 0.95 -- p d differential phase - 2 3 deg y ext /cvbs (pin 17) v 17 input voltage (ac coupled) 12 db sync attenuation possible; see fig.4 - 3 0 +3 db i 17 input current during sync pulse - 10 - 8.0 -m a during active video - 0.84 1.5 m a v 17 dc voltage during black level 1.1 1.25 1.4 v z 17 source impedance -- 1k w lpfion (pin 18) v ih high level input voltage 2 - v cc v v il low level input voltage 0 - 0.8 v i 18 input current 0.8 v - 820 m a 2.0 v - 820 m a c 18 input capacitance -- 10 pf csy (pin 19) v 19 dc voltage 0 2 v cc v symbol parameter conditions min. typ. max. unit
1997 feb 03 14 philips semiconductors preliminary speci?cation integrated multistandard comb ?lter SAA4961 notes 1. all voltages are related to agnd. 2. f sc = subcarrier frequency f sc = 4.43361875 mhz for pal b, g, h, d, i f sc = 3.57561149 mhz for pal m f sc = 3.58205625 mhz for pal n f sc = 3.579545 mhz for ntsc m. 3. f h = line frequency f h = 15.625 khz for pal b, g, h, n, d, i f h = 15.734264 khz for pal m, ntsc m. sys1 (pin 20) v ih high level input voltage 2 - v cc v v il low level input voltage 0 - 0.8 v i 20 input current 0.8 v - 7.5 20 m a 2.0 v - 7.5 20 m a c 20 input capacitance -- 10 pf v ddd (pin 22) i ddd supply current - 10 20 ma sys2 (pin 23) v ih high level input voltage 2 - v cc v v il low level input voltage 0 - 0.8 v i 23 input current 0.8 v - 820 m a 2.0 v - 820 m a c 23 input capacitance -- 10 pf refdl (pin 24) v 24 dc voltage 1.1 1.25 1.4 v combena (pin 25) v ol low level output voltage 3 ma 0.26 0.4 0.55 v v oh high level output voltage 4 - v cc v i oh high level output current 2.4 v - 55 - 24 -m a v ccpll (pin 27) i 27 supply current - 1.5 3 ma symbol parameter conditions min. typ. max. unit d vv cca v ddd C 300 mv = d vv cca v ccpll C 300 mv = d vv cca v cco C 300 mv = d vv cco v ccpll C 300 mv = d vv cco v ddd C 300 mv = d vv ddd v ccpll C 300 mv =
1997 feb 03 15 philips semiconductors preliminary speci?cation integrated multistandard comb ?lter SAA4961 fig.3 vertical transmission by different video signals from line to line. handbook, full pagewidth line 1 line 2 line 3 line 4 line 5 line 6 line 7 line 8 input output vertical transient mha367 output voltage measured in v eff related to 0.7 v input voltage. fig.4 ebu colour bar 100/0/75/0 with 12 db sync attenuation. handbook, full pagewidth mha370 0 0.15 0.225 0.3 0.45 1.0 (v)
1997 feb 03 16 philips semiconductors preliminary speci?cation integrated multistandard comb ?lter SAA4961 fig.5 principle frequency response of a comb filtered pal chrominance signal. handbook, full pagewidth mha548 u, v: pal b, g, h, d, i (u, v: pal m, n) y y v (u) u (v) f sc (n - 1)f h (n - 0.75)f h (n - 0.25)f h nf h fig.6 principle frequency response of a comb filtered pal luminance signal. handbook, full pagewidth u, v: pal b, g, h, d, i (u, v: pal m, n) nf h y y u (v) v (u) (n - 1)f h (n - 0.75)f h (n - 0.25)f h mha549 f sc
1997 feb 03 17 philips semiconductors preliminary speci?cation integrated multistandard comb ?lter SAA4961 fig.7 principle frequency response of a comb filtered ntsc chrominance signal. handbook, full pagewidth mha550 y y c f sc (n - 1)f h (n - 0.5)f h nf h fig.8 principle frequency response of a comb filtered ntsc luminance signal. handbook, full pagewidth mha551 y y (n - 1)f h (n - 0.5)f h nf h c f sc
1997 feb 03 18 philips semiconductors preliminary speci?cation integrated multistandard comb ?lter SAA4961 fig.9 clock control. handbook, full pagewidth mha552 & & 1 = 1 1 1 1 v int clock processing pll 4 cl3 cl3 hsel syspal v int combena stops mck stop byp ssyn h det v det fsc sys1 sys2 fscsw
1997 feb 03 19 philips semiconductors preliminary speci?cation integrated multistandard comb ?lter SAA4961 fig.10 chrominance path: tolerance band with anti-alias filter. handbook, full pagewidth mgl067 + 1 0 - 2 - 3 - 25 - 30 0.4 0.66 0.85 1 1.12 1.35 2.0 frequency (f sc ) gain (db) fig.11 luminance and cvbso path: tolerance band with anti-alias filter. handbook, full pagewidth mha373 + 1 0 - 1 - 2 - 3 - 5 - 32 gain (db) 0.7 1 1.12 1.5 2.26 2.7 frequency (f sc )
1997 feb 03 20 philips semiconductors preliminary speci?cation integrated multistandard comb ?lter SAA4961 test and application information handbook, full pagewidth mha553 10 k w 10 k w 75 w 75 w 47 w 100 m f 33 m h 10 nf 100 nf 100 m f 10 nf 100 nf 100 m f 10 nf 100 nf 100 m f 10 nf 100 nf 100 nf 1 2 33 m h 1 2 33 m h 1 2 33 m h 1 2 v ddd v ddds v cco v ccos v cca v ccas v ccpll v ccplls fsc i.c. byp i.c. refbp ssyn v cca v cco v cca v cco agnd c ext ognd c o fscsw y o i.c. v ccpll v ccpll pllgnd combena v ddd v ddd refdl dgnd sys1 csy lpfion y ext /cvbs i.c. cvbso SAA4961 v ddd 10 k w 75 w 100 m f 100 nf 100 nf 100 nf 100 nf combena cvbs svhs svhs-c svhs-y c ext fsc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 22 21 20 19 18 17 16 15 4 3 2 1 sys2 23 fig.12 test circuit.
1997 feb 03 21 philips semiconductors preliminary speci?cation integrated multistandard comb ?lter SAA4961 handbook, full pagewidth mha554 tda8540 switch y ext /cvbs 17 10 12 15 14 c ext c o y o cvbso cvbso tda9141 msd tda4665 bbdl byp combena fsc 3 25 1 ssyn fscsw + 5 v i 2 c-bus i 2 c-bus svhs-c cvbs1 cvbs2 svhs-vbs - (r - y) - (b - y) vb SAA4961 comb filter 613 5.6 k w sys2 sys1 23 20 pcf8574 i 2 c-i/o port i 2 c-bus fig.13 application diagram: SAA4961 with tda9141. fig.14 application diagram: SAA4961 with tda9160/62. handbook, full pagewidth mha555 tda8540 switch y ext /cvbs 17 10 12 15 14 c ext c o y o cvbso tda9160/62 msd tda4665 bbdl sys2 sys1 byp combena 3 23 20 25 1 ssyn fscsw + 5 v i 2 c-bus i 2 c-bus svhs-c cvbs1 cvbs2 svhs-vbs - (r - y) - (b - y) txt vb SAA4961 comb filter 613 pcf8574 i 2 c-i/o port i 2 c-bus fsc 1 k w 3.3 k w + 5 v bc548 4.43 mhz 3.58 mhz
1997 feb 03 22 philips semiconductors preliminary speci?cation integrated multistandard comb ?lter SAA4961 fig.15 application diagram: SAA4961 with tda8366. handbook, full pagewidth pcf8574 i 2 c-i/o port i 2 c-bus cvbs int if input mha556 tda8540 switch y ext /cvbs 17 10 12 15 14 c ext c o y o cvbso cvbso tda8366 msd tda4665 bbdl byp sys1 sys2 fsc 3 20 23 1 ssyn fscsw i 2 c-bus i 2 c-bus svhs-c cvbs1 svhs-vbs r g b SAA4961 comb filter 613
1997 feb 03 23 philips semiconductors preliminary speci?cation integrated multistandard comb ?lter SAA4961 handbook, full pagewidth mha557 tda8540 switch y ext /cvbs 17 10 12 15 14 c ext c o y o cvbso tda4655 msd tda4665 bbdl 23 20 3 1 ssyn fscsw pa l + 5 v i 2 c-bus svhs-c cvbs1 cvbs2 svhs-vbs - (r - y) - (b - y) vbs cvbso SAA4961 comb filter 613 pcf8574 i 2 c-i/o port i 2 c-bus sys2 sys1 byp fsc 2 fsc chrominance bandpass luminance trap secam nt4 nt3 pa l secam pa l secam nt3 nt4 nt4 nt3 fig.16 application diagram: SAA4961 with tda4655. remark: all switches in low position.
1997 feb 03 24 philips semiconductors preliminary speci?cation integrated multistandard comb ?lter SAA4961 package outline unit a max. 1 2 b 1 (1) (1) (1) cd e w em h l references outline version european projection issue date iec jedec eiaj mm inches dimensions (inch dimensions are derived from the original mm dimensions) sot117-1 92-11-17 95-01-14 a min. a max. b z max. m e e 1 1.7 1.3 0.53 0.38 0.32 0.23 36.0 35.0 14.1 13.7 3.9 3.4 0.25 2.54 15.24 15.80 15.24 17.15 15.90 1.7 5.1 0.51 4.0 0.066 0.051 0.020 0.014 0.013 0.009 1.41 1.34 0.56 0.54 0.15 0.13 0.01 0.10 0.60 0.62 0.60 0.68 0.63 0.067 0.20 0.020 0.16 051g05 mo-015ah m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 28 1 15 14 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. handbook, full pagewidth dip28: plastic dual in-line package; 28 leads (600 mil) sot117-1
1997 feb 03 25 philips semiconductors preliminary speci?cation integrated multistandard comb ?lter SAA4961 soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). soldering by dipping or by wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joint for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (t stg max ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. repairing soldered joints apply a low voltage soldering iron (less than 24 v) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds. definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
1997 feb 03 26 philips semiconductors preliminary speci?cation integrated multistandard comb ?lter SAA4961 notes
1997 feb 03 27 philips semiconductors preliminary speci?cation integrated multistandard comb ?lter SAA4961 notes
internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1997 sca53 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 1231, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: rua do rocio 220, 5th floor, suite 51, 04552-903 s?o paulo, s?o paulo - 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