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rev. 1.1 july 2008 vlp rdimm ddr2 sdram 1 of 29 ddr2 vlp registered sdram module 240pin vlp registered module based on 1gb q-die 72-bit ecc 60fbga / 63fbga / 65fbga wit h lead-free and halogen-free (rohs compliant) * samsung electronics reserves the right to change products or specification without notice. information in this document is provided in relation to samsung products, and is subject to change without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or other- wise, to any intellectual property rights in samsung products or technol- ogy. all information in this document is provided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about sa msung products, contact your nearest samsung office. 2. samsung products are not intended for use in life support, critical care, me dical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmen tal procurement to which special terms or provisions may apply.
rev. 1.1 july 2008 vlp rdimm ddr2 sdram 2 of 29 1.0 ddr2 registered dimm ordering information ................................................................................. ........ 4 2.0 features .................................................................................................................. ..................................... 4 3.0 address configuration ..................................................................................................... .......................... 4 4.0 pin configurations (front side/back side) ................................................................................. .............. 5 5.0pin description ............................................................................................................ ................................. 5 6.0 input/output function description ......................................................................................... ................... 6 7.0 functional block diagram .................................................................................................. ........................ 7 7.1 1gb, 128mx72 module - m392t2863qza ........................................................................................................... 7 7.2 2gb, 256mx72 module - m392t5663qza ........................................................................................................... 8 7.3 2gb, 256mx72 module - m392t5660qza ........................................................................................................... 9 7.4 4gb, ddp 512mx72 module - m392t5160qja .................................................................................................. 10 7.5 8gb, qdp 1gx72 module - m392t1g60qqa .................................................................................................... 11 8.0 absolute maximum dc ratings ............................................................................................... ................ 12 9.0 ac & dc operating conditions .............................................................................................. ................. 12 9.1 recommended dc operating conditions (sstl - 1.8) ...................................................................................... 12 9.2 operating temperature condition ................................................................................................................. 13 9.3 input dc logic level .............................................................................................................................. ..... 13 9.4 input ac logic level .............................................................................................................................. ..... 13 9.5 ac input test conditions ............................................................................................................................. 1 3 10.0 idd specification parameters definition .................................................................................. ............ 14 11.0 operating current table .................................................................................................. ....................... 15 11.1 m392t2863qza : 1gb(128mx8 *9) module .................................................................................................. 15 11.2 m392t2863qza : 1gb(128mx8 *9) module - considering register and pll current value .................................. 15 11.3 m392t5663qza : 2gb(128mx8 *18) module ................................................................................................ 16 11.4 m392t5663qza : 2gb(128mx8 *18) module - considering register and pll current value ............................... 16 11.5 m392t5660qza : 2gb(256mx4 *18) module ............................................................................................... 17 11.6 m392t5660qza : 2gb(256mx4 *18) module - considering register and pll current value ................................ 17 11.7 m392t5160qja : 4gb(ddp 512mx4 *18) module ......................................................................................... 18 11.8 m392t5160qja : 4gb(ddp 512mx4 *18) module - considering register and pll current value ........................ 18 11.9 m392t1g60qqa : 8gb(qdp 1gx4 *18) module ........................................................................................... 19 11.10 m392t1g60qqa : 8gb(qdp 1gx4 *18) module - considering register and pll current value ......................... 19 12.0 input/output capacitance ................................................................................................. ..................... 20 13.0 electrical characteristics & ac timing for ddr2-800/667/533 ........................................................... 20 13.1 refresh parameters by device density ...................................................................................................... 20 13.2 speed bins and cl, trcd , trp, trc and tras for corresponding bin ............................................................. 20 13.3 timing parameters by sp eed grade (ddr2-800 and ddr2-667) ....................................................................... 21 13.4 timing parameters by speed grade (ddr2-533) ........................................................................................... 23 14.0 physical dimensions : .................................................................................................... ........................ 25 14.1 128mbx8 based 128mx72 module (1 rank) .................................................................................................. 25 14.2 128mbx8/256mbx4 based 256mx72 module (2/1 ranks) ................................................................................. 26 14.3 ddp 512mbx4 based 512mx72 module (2 ranks) ......................................................................................... 27 14.4 qdp 1g x4 based 1gx72 module (4 ranks) ................................................................................................. 28 15.0 240 pin ddr2 registered dimm clock topology .............................................................................. ... 29 table of contents
rev. 1.1 july 2008 vlp rdimm ddr2 sdram 3 of 29 revision history revision month year history 1.0 april 2008 - initial release 1.1 july 2008 - applied jedec update(jesd79-2e) on ac timing table
rev. 1.1 july 2008 vlp rdimm ddr2 sdram 4 of 29 1.0 ddr2 registered di mm ordering information note : 1. ?z? of part number(11th digit) stands for lead-free and rohs compliant products. 2. "j" of part number(11th digit) stands for lead-free and rohs compliant dual-die package products. 3. "q" of part number(11th digit) stands for lead-free and rohs compliant quad-die package products. 4. "a" of part number(12th digit) stands for parity register products. 5. "92" of part number(3~4th digit) stands for vlp(very low profile) register products. part number density organization component composition number of rank parity register height M392T2863QZA-CF7/e6 1gb 128mx72 128mx8(k4t1g084qq)*9ea 1 o 18.30mm m392t5663qza-cf7/e6 2gb 256mx72 128mx8(k4t1g084qq)*18ea 2 o 18.30mm m392t5660qza-cf7/e6 2gb 256mx72 256mx4(k4t1g044qq)*18ea 1 o 18.30mm m392t5160qja-cf7/e6 4gb 512mx72 ddp 512mx4(k4t2g044qq)*18ea 2 o 18.30mm m392t1g60qqa-cd5 8gb 1gx72 qdp 1g x4(k4t4g044qq)*18ea 4 o 18.30mm organization row address column address bank address auto precharge 256mx4(1gb) based module a0-a13 a0-a9, a11 ba0-ba2 a10 128mx8(1gb) based module a0-a13 a0-a9 ba0-ba2 a10 ? performance range ? jedec standard v dd = 1.8v 0.1v power supply ?v ddq = 1.8v 0.1v ? 266mhz f ck for 533mb/sec/pin, 333mhz f ck for 667mb/sec/pin, 400mhz f ck for 800mb/sec/pin ?8 banks ? posted cas ? programmable cas latency: 3, 4, 5, 6 ? programmable additive latency: 0, 1 , 2 , 3, 4 and 5 ? write latency(wl) = read latency(rl) -1 ? burst length: 4 , 8(interleave/nibble sequential) ? programmable sequential / interleave burst mode ? bi-directional differential data-strobe (si ngle-ended data-strobe is an optional feature) ? off-chip driver(ocd) impedance adjustment ? on die termination with selectabl e values(50/75/150 ohms or disable) ? average refresh period 7.8us at lower than a t case 85 c, 3.9us at 85 c < t case < 95 c - support high temperature self-refresh rate enable feature ? serial presence detect with eeprom ? ddr2 sdram package: 60ball fbga - 256mx4/128mx8, 63ball fbga - ddp 512mx4, 65ball fbga - qdp 1gx4 ? all of base components are lead-free, halogen-free, and rohs compliant note: for detailed ddr2 sdram operation, please refe r to samsung?s device operation & timing diagram. speed ddr2-800 6-6-6 ddr2-667 5-5-5 ddr2-533 4-4-4 units cas latency 65 4 tck trcd(min) 15 15 15 ns trp(min) 15 15 15 ns trc(min) 60 60 60 ns 2.0 features 3.0 address configuration
rev. 1.1 july 2008 vlp rdimm ddr2 sdram 5 of 29 nc = no connect, rfu = reserved for future use 1. reset (pin 18) is connected to both oe of pll and reset of register. 2. the test pin (pin 102) is reserved for bus analysis probes and is not connec ted on normal memory modules (dimms) 3. nc/err_out ( pin 55) and nc/par_in (pin 68) are fo r optional function to check address and command parity. pin front pin back pin front pin back pin front pin back pin front pin back 1v ref 121 v ss 31 dq19 151 v ss 61 a4 181 v ddq 91 v ss 211 dm5/dqs14 2v ss 122 dq4 32 v ss 152 dq28 62 v ddq 182 a3 92 dqs 5 212 nc/dqs 14 3 dq0 123 dq5 33 dq24 153 dq29 63 a2 183 a1 93 dqs5 213 v ss 4dq1124v ss 34 dq25 154 v ss 64 v dd 184 v dd 94 v ss 214 dq46 5v ss 125 dm0/dqs9 35 v ss 155 dm3/dqs12 key 95 dq42 215 dq47 6dqs 0 126 nc/dqs 936 dqs 3 156 nc/dqs 12 65 v ss 185 ck0 96 dq43 216 v ss 7dqs0127v ss 37 dqs3 157 v ss 66 v ss 186 ck 097 v ss 217 dq52 8v ss 128 dq6 38 v ss 158 dq30 67 v dd 187 v dd 98 dq48 218 dq53 9 dq2 129 dq7 39 dq26 159 dq31 68 nc/par_in 188 a0 99 dq49 219 v ss 10 dq3 130 v ss 40 dq27 160 v ss 69 v dd 189 v dd 100 v ss 220 s 2 11 v ss 131 dq12 41 v ss 161 cb4 70 a10/ap 190 ba1 101 sa2 221 s 3 12 dq8 132 dq13 42 cb0 162 cb5 71 ba0 191 v ddq 102 nc(test) 222 v ss 13 dq9 133 v ss 43 cb1 163 v ss 72 v ddq 192 ras 103 v ss 223 dm6/dqs15 14 v ss 134 dm1/dqs10 44 v ss 164 dm8/dqs17 73 we 193 s 0104dqs 6 224 nc/dqs 15 15 dqs 1 135 nc/dqs 10 45 dqs 8 165 nc/dqs 17 74 cas 194 v ddq 105dqs6225 v ss 16 dqs1 136 v ss 46 dqs8 166 v ss 75 v ddq 195 odt0 106 v ss 226 dq54 17 v ss 137 rfu 47 v ss 167 cb6 76 s 1 196 a13 107 dq50 227 dq55 18 reset 138 rfu 48 cb2 168 cb7 77 odt1 197 v dd 108dq51228 v ss 19 nc 139 v ss 49 cb3 169 v ss 78 v ddq 198 v ss 109 v ss 229 dq60 20 v ss 140 dq14 50 v ss 170 v ddq 79 v ss 199 dq36 110 dq56 230 dq61 21 dq10 141 dq15 51 v ddq 171 cke1 80 dq32 200 dq37 111 dq57 231 v ss 22 dq11 142 v ss 52 cke0 172 v dd 81 dq33 201 v ss 112 v ss 232 dm7/dqs16 23 v ss 143 dq20 53 v dd 173 nc 82 v ss 202 dm4/dqs13 113 dqs 7 233 nc/dqs 16 24 dq16 144 dq21 54 ba2 174 nc 83 dqs 4 203 nc/dqs 13 114 dqs7 234 v ss 25 dq17 145 v ss 55 nc/err_out 175 v ddq 84 dqs4 204 v ss 115 v ss 235 dq62 26 v ss 146 dm2/dqs11 56 v ddq 176 a12 85 v ss 205 dq38 116 dq58 236 dq63 27 dqs 2 147 nc/dqs 11 57 a11 177 a9 86 dq34 206 dq39 117 dq59 237 v ss 28 dqs2 148 v ss 58 a7 178 v dd 87 dq35 207 v ss 118 v ss 238 v ddspd 29 v ss 149 dq22 59 v dd 179 a8 88 v ss 208 dq44 119 sda 239 sa0 30 dq18 150 dq23 60 a5 180 a6 89 dq40 209 dq45 120 scl 240 sa1 90 dq41 210 v ss * the v dd and v ddq pins are tied to the single power-plane on pcb. pin name description pin name description ck0 clock inputs, positive line odt0~odt1 on die termination ck 0 clock inputs, negative line dq0~dq63 data input/output cke0, cke1 clock enables cb0~cb7 data check bits input/output ras row address strobe dqs0~dqs8 data strobes cas column address strobe dqs 0~dqs 8 data strobes, negative line we write enable dm(0~8), dqs(9~17) data masks / data strobes (read) s 0~ s 3chip selects dqs 9~dqs 17 data strobes (read), negative line a0~a9, a11~a13 address inputs rfu reserved for future use a10/ap address input/autoprecharge nc no connect ba0~ba2 ddr2 sdram bank address test memory bus test tool (not connect and not useable on dimms) scl serial presence detect (spd) clock input v dd core power sda spd data input/output v ddq i/o power sa0~sa2 spd address v ss ground par_in parity bit for the address and control bus v ref input/output reference err_out parity error found in the address and control bus v ddspd spd power reset register and pll control pin 5.0pin description 4.0 pin configurations (front side/back side)
rev. 1.1 july 2008 vlp rdimm ddr2 sdram 6 of 29 symbol type description ck0 input positive line of the differential pair of system clock inputs that drives input to the on-dimm pll. ck 0 input negative line of the differential pair of system cl ock inputs that drives the input to the on-dimm pll. cke0~cke1 input activates the sdram ck signal when hi gh and deactivates the ck signal when low. by deactivating the clocks, cke low initiates the power down mode, or the self refresh mode. s 0~s 3 input enables the associated sdram command decoder when low an d disables decoder when high . when decoder is dis- abled, new commands are ignored but previous operations continue. these input signals also dis able all outputs (except cke and odt) of the register(s) on the dimm when both inputs are high. odt0~odt1 input i/o bus impedance control signals. r as , cas , we input when sampled at the positive rising edge of the clock, cas , ras , and we define the operation to be executed by the sdram. v ref supply reference voltage for sstl_18 inputs v ddq supply isolated power supply for the ddr sdram out put buffers to provide improved noise immunity ba0~ba2 input selects which sdram bank of eight is activated. a0~a9,a10/ap a11~a13 input during a bank activate command cycle , address defines the row address. during a read or write command cycle, address defines the co lumn address. in addition to the column address, ap is used to invoke autoprecharge operation at the end of the burst read or write cycle. if ap is high, autoprecharge is selected and ba0, ba1, ba2 defines the bank to be precharged. if ap is low, autoprecharge is disabled. during a precharge com- mand cycle, ap is used in conjunction with ba0, ba1, ba2 to control which bank(s) to pr echarge. if ap is high, all banks will be precharged regardless of the state of ba0 or ba1 or ba2. if ap is low, ba0 and ba1 and ba2 are used to define which bank to precharge. dq0~63, cb0~cb7 in/out data and check bit input/output pins dm0~dm8 input masks write data when high, issued concurrently with input data. both dm and dq have a write latency of one clock once the write command is registered into the sdram. v dd , v ss supply power and ground for the ddr sdram input buffers and core logic dqs0~dqs17 in/out positive line of the differential data strobe for input and output data. dqs 0~dqs 17 in/out negative line of the differential data strobe for input and output data. sa0~sa2 input these signals are tied at the system planar to either v ss or v ddspd to configure the serial spd eeprom address range. sda in/out this bidirectional pin is used to transfer data into or out of the spd eeprom. a resistor must be connected from the sda bus line to v ddspd to act as a pullup. scl input this signal is used to clock data into and out of the spd eeprom. a resistor may be connected from the scl bus time to v ddspd to act as a pullup. v ddspd supply serial eeprom positive power supply (wired to a separate power pin at the connector which supports from 1.7 volt to 3.6 volt operation). reset input the reset pin is connected to the rst pin on the register and to the oe pin on the pll. when low, all register outputs will be driven low and the pll clocks to the drams and registe r(s) will be set to low level (the pll will remain synchro- nized with the input clock ) par_in input parity bit for the address and control bus. ( ?1 ? : odd, ?0 ? : even) err_out output parity error found in the address and control bus test in/out used by memory bus analys is tools (unused on memory dimms) 6.0 input/output fu nction description
rev. 1.1 july 2008 vlp rdimm ddr2 sdram 7 of 29 (populated as 1 rank of x8 ddr2 sdrams) 7.1 1gb, 128mx72 module - m392t2863qza rs 0 dqs0 dqs 0 dm0/dqs9 nc/dqs 9 dm/ rdqs nu/ rdqs cs dqs dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d0 dqs1 dqs 1 dm1/dqs10 nc/dqs 10 dm/ rdqs nu/ rdqs cs dqs dqs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d1 dqs2 dqs 2 dm2/dqs11 nc/dqs 11 dm/ rdqs nu/ rdqs cs dqs dqs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d2 dqs3 dqs 3 dm3/dqs12 nc/dqs 12 dm/ rdqs nu/ rdqs cs dqs dqs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d3 dqs8 dqs 8 dm8/dqs17 nc/dqs 17 dm/ rdqs nu/ rdqs cs dqs dqs cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d8 dqs4 dqs 4 dm4/dqs13 nc/dqs 13 dm/ rdqs nu/ rdqs cs dqs dqs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d4 dqs5 dqs 5 dm5/dqs14 nc/dqs 14 dm/ rdqs nu/ rdqs cs dqs dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d5 dqs6 dqs 6 dm6/dqs15 nc/dqs 15 dm/ rdqs nu/ rdqs cs dqs dqs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d6 dqs7 dqs 7 dm7/dqs16 nc/dqs 16 dm/ rdqs nu/ rdqs cs dqs dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d7 a0 serial pd a1 a2 sa0 sa1 sa2 scl sda v ss d0 - d8 v dd /v ddq d0 - d8 d0 - d8 v ref v ddspd serial pd wp note : 1. dq-to-i/o wiring may be changed within a byte. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. unless otherwise noted, resister values are 22 ohms 5% 1:1 r e g i s t e r rst s0 * ba0-ba2 a0-a13 ras cas we cke0 odt0 reset pck7 pck 7 rs o-> cs : ddr2 sdrams d0-d8 rba0-rba2 -> ba0-ba2 : ddr2 sdrams d0-d8 ra0-ra13 -> a0-a13 : ddr2 sdrams d0-d8 rras -> ras : ddr2 sdrams d0-d8 rcas -> cas : ddr2 sdrams d0-d8 rwe -> we : ddr2 sdrams d0-d8 rcke0 -> cke : ddr2 sdrams d0-d8 rodt0 -> odt0 : ddr2 sdrams d0-d8 p l l oe ck 0 ck0 reset pck0-pck6, pck8, pck9 -> ck : ddr2 sdrams d0-d8 pck 0-pck 6, pck 8, pck 9 -> ck : ddr2 sdrams d0-d8 pck7 -> ck : register pck 7 -> ck : register * s 0 connects to dcs and v dd connects to csr on the register. s 1, cke1 and odt are nc. 7.0 functional block diagram signals for address and command parity function v ss v ss par_in c0 c1 ppo qerr err_out register par_in 100k ohms the resistors on par_in, a14, a15, and the signal line of err_out refer to the section: "register options for unused address inputs"
rev. 1.1 july 2008 vlp rdimm ddr2 sdram 8 of 29 rs 0 dqs0 dqs 0 dm0/dqs9 nc/dqs 9 dm/ rdqs nu/ rdqs cs dqs dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d0 dqs1 dqs 1 dm1/dqs10 nc/dqs 10 dm/ rdqs nu/ rdqs cs dqs dqs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d1 dqs2 dqs 2 dm2/dqs11 nc/dqs 11 dm/ rdqs nu/ rdqs cs dqs dqs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d2 dqs3 dqs 3 dm3/dqs12 nc/dqs 12 dm/ rdqs nu/ rdqs cs dqs dqs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d3 dqs8 dqs 8 dm8/dqs17 nc/dqs 17 dm/ rdqs nu/ rdqs cs dqs dqs cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d8 dqs4 dqs 4 dm4/dqs13 nc/dqs 13 dm/ rdqs nu/ rdqs cs dqs dqs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d4 dqs5 dqs 5 dm5/dqs14 nc/dqs 14 dm/ rdqs nu/ rdqs cs dqs dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d5 dqs6 dqs 6 dm6/dqs15 nc/dqs 15 dm/ rdqs nu/ rdqs cs dqs dqs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d6 dqs7 dqs 7 dm7/dqs16 nc/dqs 16 dm/ rdqs nu/ rdqs cs dqs dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d7 dm/ rdqs nu/ rdqs cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d9 dm/ rdqs nu/ rdqs cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d10 dm/ rdqs nu/ rdqs cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d11 dm/ rdqs nu/ rdqs cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d12 dm/ rdqs nu/ rdqs cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d17 dm/ rdqs nu/ rdqs cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d13 dm/ rdqs nu/ rdqs cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d14 dm/ rdqs nu/ rdqs cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d15 dm/ rdqs nu/ rdqs cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d16 rs 1 a0 serial pd a1 a2 sa0 sa1 sa2 scl sda v ss d0 - d17 v dd /v ddq d0 - d17 d0 - d17 v ref v ddspd serial pd wp note : 1. dq-to-i/o wiring may be changed per nibble. 2. unless otherwise noted, resister values are 22 ohms 5% 3. rs 0 and rs 1 alternate between the back and front sides of the dimm 1:2 r e g i s t e r rst s1 * ba0-ba2 a0-a13 ras cas we cke0 cke1 reset ** pck7** pck 7** rs 1-> cs : ddr2 sdrams d9-d17 rba0-rba2 -> ba0-ba2: ddr2 sdrams d0-d17 ra0-ra13 -> a0-a13 : ddr2 sdrams d0-d17 rras -> ras : ddr2 sdrams d0-d17 rcas -> cas : ddr2 sdrams d0-d17 rwe -> we : ddr2 sdrams d0-d17 rcke0 -> cke : ddr2 sdrams d0-d8 rcke1 -> cke : ddr2 sdrams d9-d17 p l l oe ck 0 ck0 reset pck0-pck6, pck8, pck9 -> ck : ddr2 sdrams d0-d17 pck 0-pck 6, pck 8, pck 9 -> ck : ddr2 sdrams d0-d17 pck7 -> ck : register pck 7 -> ck : register odt0 odt1 rodt0 -> odt0 : ddr2 sdrams d0-d8 rodt1 -> odt1 : ddr2 sdrams d9-d17 s0 * rs o-> cs : ddr2 sdrams d0-d8 (populated as 2 rank of x8 ddr2 sdrams) 7.2 2gb, 256mx72 module - m392t5663qza * s 0 connects to dcs and s 1 connects to csr on a register, s 1 connects to dcs and s 0 connects to csr on another register. ** reset , pck7 and pck 7 connects to both registers. other signals connect to one of two registers. signals for address and command parity function v ss v dd par_in c0 c1 ppo qerr register a par_in 100k ohms the resistors on par_in, a14, a15, and the signal line of err_out refer to the section: "register options for unused address inputs" v dd v dd c0 c1 ppo qerr err_out register b par_in
rev. 1.1 july 2008 vlp rdimm ddr2 sdram 9 of 29 v ss rs 0 dqs0 dqs 0 dm cs dqs dqs dq0 dq1 dq2 dq3 i/o 0 i/o 1 i/o 2 i/o 3 d0 dm0/dqs9 nc/dqs 9 dm cs dqs dqs dq4 dq5 dq6 dq7 i/o 0 i/o 1 i/o 2 i/o 3 d9 dqs1 dqs 1 dm cs dqs dqs dq8 dq9 dq10 dq11 i/o 0 i/o 1 i/o 2 i/o 3 d1 dm1/dqs10 nc/dqs 10 dm cs dqs dqs dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 d10 dqs2 dqs 2 dm cs dqs dqs dq16 dq17 dq18 dq19 i/o 0 i/o 1 i/o 2 i/o 3 d2 dm2/dqs11 nc/dqs 11 dm cs dqs dqs dq20 dq21 dq22 dq23 i/o 0 i/o 1 i/o 2 i/o 3 d11 dqs3 dqs 3 dm cs dqs dqs dq24 dq25 dq26 dq27 i/o 0 i/o 1 i/o 2 i/o 3 d3 dm3/dqs12 nc/dqs 12 dm cs dqs dqs dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 d12 dqs5 dqs 5 dm cs dqs dqs dq40 dq41 dq42 dq43 i/o 0 i/o 1 i/o 2 i/o 3 d5 dm5/dqs14 nc/dqs 14 dm cs dqs dqs dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 d14 dqs4 dqs 4 dm cs dqs dqs dq32 dq33 dq34 dq35 i/o 0 i/o 1 i/o 2 i/o 3 d4 dm4/dqs13 nc/dqs 13 dm cs dqs dqs dq36 dq37 dq38 dq39 i/o 0 i/o 1 i/o 2 i/o 3 d13 dqs6 dqs 6 dm cs dqs dqs dq48 dq49 dq50 dq51 i/o 0 i/o 1 i/o 2 i/o 3 d6 dm6/dqs15 nc/dqs 15 dm cs dqs dqs dq52 dq53 dq54 dq55 i/o 0 i/o 1 i/o 2 i/o 3 d15 dqs8 dqs 8 dm cs dqs dqs cb0 cb1 cb2 cb3 i/o 0 i/o 1 i/o 2 i/o 3 d8 dm8/dqs17 nc/dqs 17 dm cs dqs dqs cb4 cb5 cb6 cb7 i/o 0 i/o 1 i/o 2 i/o 3 d17 dqs7 dqs 7 dm cs dqs dqs dq56 dq57 dq58 dq59 i/o 0 i/o 1 i/o 2 i/o 3 d7 dm7dqs16 nc/dqs 16 dm cs dqs dqs dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 d16 a0 serial pd a1 a2 sa0 sa1 sa2 scl sda v ss d0 - d17 v dd /v ddq d0 - d17 d0 - d17 v ref v ddspd serial pd wp note : 1. dq-to-i/o wiring may be changed per nibble. 2. unless otherwise noted, resister values are 22 ohms 5% 1:2 r e g i s t e r rst s0 * ba0-ba2 a0-a13 ras cas we cke0 odt0 reset ** pck7** pck 7** rs o-> cs : ddr2 sdrams d0-d17 rba0-rba2 -> ba0-ba2 : ddr2 sdrams d0-d17 ra0-ra13 -> a0-a13 : ddr2 sdrams d0-d17 rras -> ras : ddr2 sdrams d0-d17 rcas -> cas : ddr2 sdrams d0-d17 rwe -> we : ddr2 sdrams d0-d17 rcke0 -> cke : ddr2 sdrams d0-d17 rodt0 -> odt0 : ddr2 sdrams d0-d17 p l l oe ck 0 ck0 reset pck0-pck6, pck8, pck9 -> ck : ddr2 sdrams d0-d8 pck 0-pck 6, pck 8, pck 9 -> ck : ddr2 sdrams d0-d8 pck7 -> ck : register pck 7 -> ck : register (populated as 1 rank of x4 ddr2 sdrams) 7.3 2gb, 256mx72 module - m392t5660qza * s 0 connects to dcs of register1 and csr of register2. csr of reg- ister 1 and dcs of register 2 connects to vdd. ** reset , pck7 and pck 7 connects to both registers. other signals connect to one of two registers. s 1, cke1 and odt1 are nc. signals for address and command parity function v ss v dd par_in c0 c1 ppo qerr register a par_in 100k ohms the resistors on par_in, a14, a15, and the signal line of err_out refer to the section: "register options for unused address inputs" v dd v dd c0 c1 ppo qerr err_out register b par_in
rev. 1.1 july 2008 vlp rdimm ddr2 sdram 10 of 29 (populated as 2 rank of x4 ddr2 sdrams) 7.4 4gb, ddp 512mx72 module - m392t5160qja a0 serial pd a1 a2 sa0 sa1 sa2 scl sda v ss d0 - d35 v dd /v ddq d0 - d35 d0 - d35 v ref v ddspd serial pd wp p l l oe ck 0 ck0 reset pck0-pck6, pck8, pck9 -> ck : ddr2 sdrams d0-d35 pck 0-pck 6, pck 8, pck 9 -> ck : ddr2 sdrams d0-d35 pck7 -> ck : register pck 7 -> ck : register 1:2 r e g i s t e r rst s1 * ba0-ba1 a0-a13 ras cas we cke0 cke1 reset ** pck7** pck 7** rs 1-> cs : ddr2 sdrams d18-d35 rba0-rba1 -> ba0-ba1 : ddr2 sdrams d0-d35 ra0-ra13 -> a0-a13 : ddr2 sdrams d0-d35 rras -> ras : ddr2 sdrams d0-d35 rcas -> cas : ddr2 sdrams d0-d35 rwe -> we : ddr2 sdrams d0-d35 rcke0 -> cke : ddr2 sdrams d0-d17 rcke1 -> cke : ddr2 sdrams d18-d35 odt0 odt1 rodt0 -> odt0 : ddr2 sdrams d0-d17 rodt1 -> odt1 : ddr2 sdrams d18-d35 s0 * rs o-> cs : ddr2 sdrams d0-d17 v ss rs 0 dqs0 dqs 0 dm cs dqs dqs dq0 dq1 dq2 dq3 i/o 0 i/o 1 i/o 2 i/o 3 d0 dm0/dqs9 nc/dqs 9 dm cs dqs dqs dq4 dq5 dq6 dq7 i/o 0 i/o 1 i/o 2 i/o 3 d9 dqs1 dqs 1 dm cs dqs dqs dq8 dq9 dq10 dq11 i/o 0 i/o 1 i/o 2 i/o 3 d1 dm1/dqs10 nc/dqs 10 dm cs dqs dqs dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 d10 dqs2 dqs 2 dm cs dqs dqs dq16 dq17 dq18 dq19 i/o 0 i/o 1 i/o 2 i/o 3 d2 dm2/dqs11 nc/dqs 11 dm cs dqs dqs dq20 dq21 dq22 dq23 i/o 0 i/o 1 i/o 2 i/o 3 d11 dqs3 dqs 3 dm cs dqs dqs dq24 dq25 dq26 dq27 i/o 0 i/o 1 i/o 2 i/o 3 d3 dm3/dqs12 nc/dqs 12 dm cs dqs dqs dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 d12 dqs5 dqs 5 dm cs dqs dqs dq40 dq41 dq42 dq43 i/o 0 i/o 1 i/o 2 i/o 3 d5 dm5/dqs14 nc/dqs 14 dm cs dqs dqs dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 d14 dqs4 dqs 4 dm cs dqs dqs dq32 dq33 dq34 dq35 i/o 0 i/o 1 i/o 2 i/o 3 d4 dm4/dqs13 nc/dqs 13 dm cs dqs dqs dq36 dq37 dq38 dq39 i/o 0 i/o 1 i/o 2 i/o 3 d13 dqs6 dqs 6 dm cs dqs dqs dq48 dq49 dq50 dq51 i/o 0 i/o 1 i/o 2 i/o 3 d6 dm6/dqs15 nc/dqs 15 dm cs dqs dqs dq52 dq53 dq54 dq55 i/o 0 i/o 1 i/o 2 i/o 3 d15 dqs8 dqs 8 dm cs dqs dqs cb0 cb1 cb2 cb3 i/o 0 i/o 1 i/o 2 i/o 3 d8 dm8/dqs17 nc/dqs 17 dm cs dqs dqs cb4 cb5 cb6 cb7 i/o 0 i/o 1 i/o 2 i/o 3 d17 dqs7 dqs 7 dm cs dqs dqs dq56 dq57 dq58 dq59 i/o 0 i/o 1 i/o 2 i/o 3 d7 dm7dqs16 nc/dqs 16 dm cs dqs dqs dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 d16 dm/ cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d18 dm/ cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d19 dm/ cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d20 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d21 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d23 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d22 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d24 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d26 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d25 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d27 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d28 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d29 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d30 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d32 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d31 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d33 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d35 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d34 rs 1 * s 0 connects to dcs and s 1 connects to csr on a pair of registers, s 1 connects to dcs and s 0 connects to csr on another pair of registers. ** reset , pck7 and pck 7 connects to all registers. other signals connect to one pair of four registers. signals for address and command parity function par_in ppo qerr register a par_in 100k ohms the resistors on par_in, a14, a15, and the signal line of err_out refer to the section: "reg- ister options for unused address inputs" ppo qerr err_out register b par_in
rev. 1.1 july 2008 vlp rdimm ddr2 sdram 11 of 29 (populated as 4 rank of x4 ddr2 sdrams) rodt0 rs 1 22 ? dqs dqs dq3~0 dm d0 rcke0 rs 0 cs 0 cs 1 cke0 cke1 odt0 odt0 dqs0 dqs 0 dq3~0 dqs dqs dq3~0 dm d18 cs 0 cs 1 cke0 cke1 odt0 odt0 rodt1 rs 3 rcke1 rs 2 dqs dqs dq3~0 dm d1 cs 0 cs 1 cke0 cke1 odt0 odt0 dqs1 dqs 1 dq11~8 dqs dqs dq3~0 dm d19 cs 0 cs 1 cke0 cke1 odt0 odt0 dqs dqs dq3~0 dm d3 cs 0 cs 1 cke0 cke1 odt0 odt0 dqs3 dqs 3 dq27~24 dqs dqs dq3~0 dm d21 cs 0 cs 1 cke0 cke1 odt0 odt0 dqs dqs dq3~0 dm d2 cs 0 cs 1 cke0 cke1 odt0 odt0 dqs2 dqs 2 dq19~16 dqs dqs dq3~0 dm d20 cs 0 cs 1 cke0 cke1 odt0 odt0 dqs dqs dq3~0 dm d8 cs 0 cs 1 cke0 cke1 odt0 odt0 dqs8 dqs 8 cb3~0 dqs dqs dq3~0 dm d26 cs 0 cs 1 cke0 cke1 odt0 odt0 dqs dqs dq3~0 dm d4 cs 0 cs 1 cke0 cke1 odt0 odt0 dqs4 dqs 4 dq35~32 dqs dqs dq3~0 dm d22 cs 0 cs 1 cke0 cke1 odt0 odt0 dqs dqs dq3~0 dm d5 cs 0 cs 1 cke0 cke1 odt0 odt0 dqs5 dqs 5 dq43~40 dqs dqs dq3~0 dm d23 cs 0 cs 1 cke0 cke1 odt0 odt0 dqs dqs dq3~0 dm d7 cs 0 cs 1 cke0 cke1 odt0 odt0 dqs7 dqs 7 dq59~56 dqs dqs dq3~0 dm d25 cs 0 cs 1 cke0 cke1 odt0 odt0 dqs dqs dq3~0 dm d6 cs 0 cs 1 cke0 cke1 odt0 odt0 dqs6 dqs 6 dq51~48 dqs dqs dq3~0 dm d24 cs 0 cs 1 cke0 cke1 odt0 odt0 rodt0 rs 1 rcke0 rs 0 rodt1 rs 3 rcke1 rs 2 rodt0 rs 1 0 ? dqs dqs dq3~0 dm d9 rcke0 rs 0 cs 0 cs 1 cke0 cke1 odt0 odt0 dqs9 dqs 9 dq7~4 dqs dqs dq3~0 dm d27 cs 0 cs 1 cke0 cke1 odt0 odt0 rodt1 rs 3 rcke1 rs 2 dqs dqs dq3~0 dm d10 cs 0 cs 1 cke0 cke1 odt0 odt0 dqs10 dqs 10 dq15~12 dqs dqs dq3~0 dm d28 cs 0 cs 1 cke0 cke1 odt0 odt0 dqs dqs dq3~0 dm d12 cs 0 cs 1 cke0 cke1 odt0 odt0 dqs12 dqs 12 dq31~28 dqs dqs dq3~0 dm d30 cs 0 cs 1 cke0 cke1 odt0 odt0 dqs dqs dq3~0 dm d11 cs 0 cs 1 cke0 cke1 odt0 odt0 dqs11 dqs 11 dq23~20 dqs dqs dq3~0 dm d29 cs 0 cs 1 cke0 cke1 odt0 odt0 dqs dqs dq3~0 dm d17 cs 0 cs 1 cke0 cke1 odt0 odt0 dqs17 dqs 17 cb7~4 dqs dqs dq3~0 dm d35 cs 0 cs 1 cke0 cke1 odt0 odt0 dqs dqs dq3~0 dm d13 cs 0 cs 1 cke0 cke1 odt0 odt0 dqs13 dqs 13 dq39~36 dqs dqs dq3~0 dm d31 cs 0 cs 1 cke0 cke1 odt0 odt0 dqs dqs dq3~0 dm d14 cs 0 cs 1 cke0 cke1 odt0 odt0 dqs14 dqs 14 dq47~44 dqs dqs dq3~0 dm d32 cs 0 cs 1 cke0 cke1 odt0 odt0 dqs dqs dq3~0 dm d16 cs 0 cs 1 cke0 cke1 odt0 odt0 dqs16 dqs 16 dq63~60 dqs dqs dq3~0 dm d34 cs 0 cs 1 cke0 cke1 odt0 odt0 dqs dqs dq3~0 dm d15 cs 0 cs 1 cke0 cke1 odt0 odt0 dqs15 dqs 15 dq55~52 dqs dqs dq3~0 dm d33 cs 0 cs 1 cke0 cke1 odt0 odt0 rodt0 rs 1 rcke0 rs 0 rodt1 rs 3 rcke1 rs 2 p l l oe ck 0 ck0 reset pck7-> ck : register pck 7-> ck : register pck0-pck6, pck8, pck9-> ck : ddr2 sdrams d0-d35 1:2 r e g i s t e r rst s 1,3** ba0-ba2 a0-a15 ras cas we cke0 cke1 reset ** pck7** pck 7** rs 1-> cs 1 : ddr2 sdrams d0-d17, rs 3-> cs 1 : ddr2 sdrams d18-d35 rba0-rba1 -> ba0-ba1 : ddr2 sdrams d0-d35 ra0-ra13 -> a0-a13 : ddr2 sdrams d0-d35 rras -> ras : ddr2 sdrams d0-d35 rcas -> cas : ddr2 sdrams d0-d35 rwe -> we : ddr2 sdrams d0-d35 rcke0 -> cke : ddr2 sdrams d0-d17 rcke1 -> cke : ddr2 sdrams d18-d35 odt0 odt1 rodt0 -> odt0 : ddr2 sdrams d0-d17 rodt1 -> odt1 : ddr2 sdrams d18-d35 s 0,2* rs 0-> cs 0 : ddr2 sdrams d0-d17, rs 2-> cs 0 : ddr2 sdrams d18-d35 * s 0 connects to dcs 0, s 1 to dcs 1 on the first register, s 2 connects dcs 0, s 3 connects dcs 1, on the secon register s 2 and s 3 have required pull up resistors (100k ohms), not indicated here. **a14-15 have optional pull down resistors (100k ohms), not indicated here. a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp register par_in parin ptyerr register parin ptyerr 100 k ? err_out 0 ? pck0-pck6, pck8, pck9-> ck : ddr2 sdrams d0-d35 7.5 8gb, qdp 1gx72 module - m392t1g60qqa
rev. 1.1 july 2008 vlp rdimm ddr2 sdram 12 of 29 note : there is no specific device v dd supply voltage requirement for sstl-1.8 co mpliance. however under all conditions v ddq must be less than or equal to v dd . 1. the value of v ref may be selected by the user to provide optimum noise margin in the system. typically the value of v ref is expected to be about 0.5 x v ddq of the transmitting device and v ref is expected to track variations in v ddq . 2. peak to peak ac noise on v ref may not exceed +/-2% v ref (dc). 3. v tt of transmitting device must track v ref of receiving device. 4. ac parameters are measured with v dd , v ddq and v ddl tied together. symbol parameter rating units notes min. typ. max. v dd supply voltage 1.7 1.8 1.9 v v ddl supply voltage for dll 1.7 1.8 1.9 v 4 v ddq supply voltage for output 1.7 1.8 1.9 v 4 v ref input reference voltage 0.49*v ddq 0.50*v ddq 0.51*v ddq mv 1,2 v tt termination voltage v ref -0.04 v ref v ref +0.04 v 3 note : 1. stresses greater than those listed under ?absolute maximum ra tings? may cause permanent damage to the device. this is a stre ss rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this s pecification is not implied. exposure to absolute maximum ra ting conditions for extended peri ods may affect reliability. 2. storage temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions, plea se refer to jesd51-2 standard. symbol parameter rating units notes v dd voltage on v dd pin relative to v ss - 1.0 v ~ 2.3 v v 1 v ddq voltage on v ddq pin relative to v ss - 0.5 v ~ 2.3 v v 1 v ddl voltage on v ddl pin relative to v ss - 0.5 v ~ 2.3 v v 1 v in, v out voltage on any pin relative to v ss - 0.5 v ~ 2.3 v v 1 t stg storage temperature -55 to +100 c 1, 2 9.0 ac & dc operating conditions 9.1 recommended dc operating conditions (sstl - 1.8) 8.0 absolute maxi mum dc ratings
rev. 1.1 july 2008 vlp rdimm ddr2 sdram 13 of 29 note: 1. input waveform timing is referenced to the input signal crossing through the v ih/il (ac) level applied to the device under test. 2. the input signal minimum slew rate is to be maintained over the range from v ref to v ih (ac) min for rising edges and the range from v ref to v il (ac) max for falling edges as shown in the below figure. 3. ac timings are referenced with input waveforms switching from v il (ac) to v ih (ac) on the positive transitions and v ih (ac) to v il (ac) on the negative transitions. symbol condition value units notes v ref input reference voltage 0.5 * v ddq v1 v swing(max) input signal maximum peak to peak swing 1.0 v 1 slew input signal minimum slew rate 1.0 v/ns 2, 3 v ddq v ih (ac) min v ih (dc) min v ref v il (dc) max v il (ac) max v ss < ac input test signal waveform > v swing(max) delta tr delta tf v ref - v il (ac) max delta tf falling slew = rising slew = v ih (ac) min - v ref delta tr note : 1. operating temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions, pl ease refer to jesd51.2 standard. 2. at 85 - 95 c operation temperature range, doubling refresh commands in frequenc y to a 32ms period ( trefi=3.9 us ) is required, and to ent er to self refresh mode at this temperature range, an emrs command is required to change internal refresh rate. symbol parameter rating units notes t oper operating temperature 0 to 95 c 1, 2 9.3 input dc logic level symbol parameter min. max. units notes v ih (dc) dc input logic high v ref + 0.125 v ddq + 0.3 v v il (dc) dc input logic low - 0.3 v ref - 0.125 v 9.4 input ac logic level symbol parameter ddr2-533 ddr2-667, ddr2-800 units min. max. min. max. v ih (ac) ac input logic high v ref + 0.250 - v ref + 0.200 - v v il (ac) ac input logic low - v ref - 0.250 - v ref - 0.200 v 9.5 ac input test conditions 9.2 operating temperature condition
rev. 1.1 july 2008 vlp rdimm ddr2 sdram 14 of 29 (idd values are for full operating range of voltage and temperature) symbol proposed conditions units note idd0 operating one bank active-precharge current; tck = tck(idd), trc = trc(idd), tras = trasmin(idd); cke is high, cs is high between valid commands; address bus inputs are switching; data bus inputs are switching ma idd1 operating one bank active-read-precharge current; iout = 0ma; bl = 4, cl = cl(idd), al = 0; tck = tck(idd), trc = trc (idd), tras = trasmin(idd), trcd = trcd(idd); cke is high, cs is high between valid commands; address bus inputs are switching; data pattern is same as idd4w ma idd2p precharge power-down current; all banks idle; tck = tck(idd); cke is low; other cont rol and address bus inputs are stable; data bus inputs are floating ma idd2q precharge quiet standby current; all banks idle; tck = tck(idd); cke is high, cs is high; other control and address bus inputs are stable; data bus inputs are floating ma idd2n precharge standby current; all banks idle; tck = tck(idd); cke is high, cs is high; other control and address bus inputs are switching; data bus inputs are switching ma idd3p active power-down current; all banks open; tck = tck(idd); cke is low; other control and address bus inputs are stable; data bus inputs are floating fast pdn exit mrs(12) = 0ma ma slow pdn exit mrs(12) = 1ma ma idd3n active standby current; all banks open; tck = tck(idd), tras = trasmax(idd), trp = trp(idd); cke is high, cs is high between valid commands; other control and address bus inputs ar e switching; data bus inputs are switching ma idd4w operating burst write current; all banks open, continuous burst writes; bl = 4, cl = cl (idd), al = 0; tck = tck(idd), tras = trasmax(idd), trp = trp(idd); cke is high, cs is high between valid commands; addr ess bus inputs are switching; data bus inputs are switching ma idd4r operating burst read current; all banks open, continuous burst reads, iout = 0ma; bl = 4, cl = cl(idd), al = 0; tck = tck(idd), tras = tras- max(idd), trp = trp(idd); cke is high, cs is high between valid commands; address bus inputs are switch- ing; data pattern is same as idd4w ma idd5b burst auto refresh current; tck = tck(idd); refresh command at every trfc(idd) interval; cke is high, cs is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching ma idd6 self refresh current; ck and ck at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating normal ma low power ma idd7 operating bank interleave read current; all bank interleaving reads, iout = 0ma; bl = 4, cl = cl(idd), al = trcd(idd)-1*tck(idd); tck = tck(idd), trc = trc(idd), trrd = trrd(idd), tfaw = tfaw(idd), trcd = 1*tck(idd); cke is high, cs is high between valid com- mands; address bus inputs are stable during deselects; data pattern is same as idd4r; refer to the following page for detailed timing conditions ma 10.0 idd specification parameters definition
rev. 1.1 july 2008 vlp rdimm ddr2 sdram 15 of 29 11.0 operating current table (t a =0 o c, v dd = 1.9v) * module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol f7(800@cl=6) e6(667@cl=5) units notes idd0 675 630 ma idd1 765 720 ma idd2p 135 135 ma idd2q 270 270 ma idd2n 315 315 ma idd3p-f 315 315 ma idd3p-s 162 162 ma idd3n 495 450 ma idd4w 1,035 945 ma idd4r 1,215 1,080 ma idd5b 1,305 1,260 ma idd6* 135 135 ma idd7 2,250 2,070 ma (t a =0 o c, v dd = 1.9v) * idd6 = dram current + standby current of pll and register ** module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol f7(800@cl=6) e6(667@cl=5) units notes idd0 1,265 1,130 ma idd1 1,405 1,270 ma idd2p 615 575 ma idd2q 800 730 ma idd2n 795 735 ma idd3p-f 865 785 ma idd3p-s 712 632 ma idd3n 1,035 920 ma idd4w 1,555 1,395 ma idd4r 1,805 1,590 ma idd5b 1,975 1,810 ma idd6* 135 135 ma idd7 2,940 2,650 ma 11.1 m392t2863qza : 1gb(128mx8 *9) module 11.2 m392t2863qza : 1gb(128mx8 *9) module - considering register and pll current value
rev. 1.1 july 2008 vlp rdimm ddr2 sdram 16 of 29 (t a =0 o c, v dd = 1.9v) * module idd was calculated on the basis of component idd and can be differently measured ac cording to dq loading cap. symbol f7(800@cl=6) e6(667@cl=5) units notes idd0 990 945 ma idd1 1,080 1,035 ma idd2p 270 270 ma idd2q 540 540 ma idd2n 630 630 ma idd3p-f 630 630 ma idd3p-s 324 324 ma idd3n 810 765 ma idd4w 1,350 1,260 ma idd4r 1,530 1,395 ma idd5b 1,620 1,575 ma idd6* 270 270 ma idd7 2,565 2,385 ma (t a =0 o c, v dd = 1.9v) * idd6 = dram current + standby current of pll and register ** module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol f7(800@cl=6) e6(667@cl=5) units notes idd0 1,680 1,535 ma idd1 1,850 1,695 ma idd2p 910 850 ma idd2q 1,250 1,160 ma idd2n 1,200 1,130 ma idd3p-f 1,360 1,260 ma idd3p-s 1,054 954 ma idd3n 1,370 1,255 ma idd4w 2,000 1,820 ma idd4r 2,320 2,075 ma idd5b 2,450 2,255 ma idd6* 270 270 ma idd7 3,595 3,255 ma 11.4 m392t5663qza : 2gb(128mx8 *18) module - considering register and pll current value 11.3 m392t5663qza : 2gb(128mx8 *18) module
rev. 1.1 july 2008 vlp rdimm ddr2 sdram 17 of 29 (t a =0 o c, v dd = 1.9v) * module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol f7(800@cl=6) e6(667@cl=5) units notes idd0 1,350 1,260 ma idd1 1,530 1,440 ma idd2p 270 270 ma idd2q 540 540 ma idd2n 630 630 ma idd3p-f 630 630 ma idd3p-s 324 324 ma idd3n 990 900 ma idd4w 1,980 1,800 ma idd4r 2,340 2,070 ma idd5b 2,520 2,430 ma idd6* 270 270 ma idd7 4,410 4,050 ma (t a =0 o c, v dd = 1.9v) * idd6 = dram current + standby current of pll and register ** module idd was calculated on the basis of component idd an d can be differently measured according to dq loading cap. symbol f7(800@cl=6) e6(667@cl=5) units notes idd0 2,040 1,850 ma idd1 2,300 2,100 ma idd2p 910 850 ma idd2q 1,250 1,160 ma idd2n 1,200 1,130 ma idd3p-f 1,360 1,260 ma idd3p-s 1,054 954 ma idd3n 1,550 1,390 ma idd4w 2,630 2,360 ma idd4r 3,130 2,750 ma idd5b 3,350 3,110 ma idd6* 270 270 ma idd7 5,440 4,920 ma 11.6 m392t5660qza : 2gb(256mx4 *18) module - considering register and pll current value 11.5 m392t5660qza : 2gb(256mx4 *18) module
rev. 1.1 july 2008 vlp rdimm ddr2 sdram 18 of 29 (t a =0 o c, v dd = 1.9v) * module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol f7(800@cl=6) e6(667@cl=5) units notes idd0 1,980 1,890 ma idd1 2,160 2,070 ma idd2p 540 540 ma idd2q 1,080 1,080 ma idd2n 1,260 1,260 ma idd3p-f 1,260 1,260 ma idd3p-s 648 648 ma idd3n 1,620 1,530 ma idd4w 2,610 2,430 ma idd4r 2,970 2,700 ma idd5b 3,150 3,060 ma idd6* 540 540 ma idd7 5,040 4,680 ma (t a =0 o c, v dd = 1.9v) * idd6 = dram current + standby current of pll and register ** module idd was calculated on the basis of component idd an d can be differently measured according to dq loading cap. symbol f7(800@cl=6) e6(667@cl=5) units notes idd0 3,000 2,760 ma idd1 3,320 3,070 ma idd2p 1,490 1,400 ma idd2q 2,140 2,000 ma idd2n 2,060 1,960 ma idd3p-f 2,350 2,200 ma idd3p-s 1,738 1,588 ma idd3n 2,410 2,220 ma idd4w 3,600 3,280 ma idd4r 4,060 3,640 ma idd5b 4,370 4,060 ma idd6* 540 540 ma idd7 6,750 6,130 ma 11.8 m392t5160qja : 4gb(ddp 512mx4 *18) module - considering register and pll current value 11.7 m392t5160qja : 4gb(ddp 512mx4 *18) module
rev. 1.1 july 2008 vlp rdimm ddr2 sdram 19 of 29 (t a =0 o c, v dd = 1.9v) * module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol d5(533@cl=4) units notes idd0 3,060 ma idd1 3,240 ma idd2p 1,080 ma idd2q 2,160 ma idd2n 2,520 ma idd3p-f 2,520 ma idd3p-s 1,296 ma idd3n 2,700 ma idd4w 3,510 ma idd4r 3,510 ma idd5b 4,230 ma idd6* 1,080 ma idd7 5,940 ma (t a =0 o c, v dd = 1.9v) * idd6 = dram current + standby current of pll and register ** module idd was calculated on the basis of component idd an d can be differently measured according to dq loading cap. symbol d5(533@cl=4) units notes idd0 3,780 ma idd1 4,080 ma idd2p 1,850 ma idd2q 2,940 ma idd2n 3,120 ma idd3p-f 3,310 ma idd3p-s 2,086 ma idd3n 3,290 ma idd4w 4,220 ma idd4r 4,300 ma idd5b 5,010 ma idd6* 1,080 ma idd7 7,130 ma 11.10 m392t1g60qqa : 8gb(qdp 1gx4 *18) module - considering register and pll current value 11.9 m392t1g60qqa : 8gb(qdp 1gx4 *18) module
rev. 1.1 july 2008 vlp rdimm ddr2 sdram 20 of 29 (v dd =1.8v, v ddq =1.8v, t a =25 o c) * dm is internally loaded to match dq and dqs identically. parameter sym. min max min max min max min max min max units part-number m392t2863qza m392t5663qza m392t5660qza m392t5160qja m392t1g60qqa input capacitance, ck and ck cck - 11 - 11 - 11 - 11 - 11 pf input capacitance, cke and cs ci1 - 12 - 12 - 12 - 12 - 12 input capacitance, address, ras ,cas ,we ci2 - 12 - 12 - 12 - 12 - 12 input/output capacitance, dq, dm, dqs, dqs cio - 10 - 10 - 10 - 10 - 10 parameter symbol 256mb 512mb 1gb 2gb 4gb units refresh to active/refresh command time trfc 75 105 127.5 195 327.5 ns average periodic refresh interval trefi 0 c t case 85 c 7.8 7.8 7.8 7.8 7.8 s 85 c < t case 95 c 3.9 3.9 3.9 3.9 3.9 s speed ddr2-800(f7) ddr2-667(e6) ddr2-533(d5) units bin (cl - trcd - trp) 6 - 6 - 6 5 - 5 - 5 4 - 4 - 4 parameter min max min max min max tck, cl=3 - - 5 8 5 8 ns tck, cl=4 3.75 8 3.75 8 3.75 8 ns tck, cl=5 3 8 3 8 3.75 8 ns tck, cl=6 2.5 8 - - - - ns trcd 15 - 15 - 15 - ns trp 15 - 15 - 15 - ns trc 60 - 60 - 60 - ns tras 45 70000 45 70000 45 70000 ns 13.0 electrical characteristics & ac timing for ddr2-800/667/533 (0 c < t oper < 95 c; v ddq = 1.8v + 0.1v; v dd = 1.8v + 0.1v) 13.1 refresh parameters by device density 13.2 speed bins and cl, trcd, trp, trc and tras for corresponding bin 12.0 input/output capacitance
rev. 1.1 july 2008 vlp rdimm ddr2 sdram 21 of 29 (refer to notes for informations related to this table at the component datasheet) parameter symbol ddr2-800 ddr2-667 units notes min max min max dq output access time from ck/ck tac -400 400 -450 450 ps 40 dqs output access time from ck/ck tdqsck -350 350 -400 400 ps 40 average clock high pulse width tch(avg) 0.48 0.52 0.48 0.52 tck(avg) 35,36 average clock low pulse width tcl(avg) 0.48 0.52 0.48 0.52 tck(avg) 35,36 ck half pulse period thp min(tcl(abs), tch(abs)) x min(tcl(abs), tch(abs)) x ps 37 average clock period tck(avg) 2500 8000 3000 8000 ps 35,36 dq and dm input hold time tdh(base) 125 x 175 x ps 6,7,8,21,28,31 dq and dm input setup time tds(base) 50 x 100 x ps 6,7,8,20,28,31 control & address input pulse width for each input tipw 0.6 x 0.6 x tck(avg) dq and dm input pulse width for each input tdipw 0.35 x 0.35 x tck(avg) data-out high-impedance time from ck/ck thz x tac(max) x tac(max) ps 18,40 dqs/dqs low-impedance time from ck/ck tlz(dqs) tac(min) tac(max) tac(min) tac(max) ps 18,40 dq low-impedance time from ck/ck tlz(dq) 2* tac(min) tac(max) 2* tac(min) tac(max) ps 18,40 dqs-dq skew for dqs and associated dq signals tdqsq x 200 x 240 ps 13 dq hold skew factor tqhs x 300 x 340 ps 38 dq/dqs output hold time from dqs tqh thp - tqhs x thp - tqhs x ps 39 dqs latching rising transitions to associated clock edges tdqss - 0.25 0.25 -0.25 0.25 tck(avg) 30 dqs input high pulse width tdqsh 0.35 x 0.35 x tck(avg) dqs input low pulse width tdqsl 0.35 x 0.35 x tck(avg) dqs falling edge to ck setup time tdss 0.2 x 0.2 x tck(avg) 30 dqs falling edge hold time from ck tdsh 0.2 x 0.2 x tck(avg) 30 mode register set command cycle time tmrd 2 x 2 x nck mrs command to odt update delay tmod 0 12 0 12 ns 32 write postamble twpst 0.4 0.6 0.4 0.6 tck(avg) 10 write preamble twpre 0.35 x 0.35 x tck(avg) address and control input hold time tih(base) 250 x 275 x ps 5,7,9,23,29 address and control input setup time tis(base) 175 x 200 x ps 5,7,9,22,29 read preamble trpre 0.9 1.1 0.9 1.1 tck(avg) 19,41 read postamble trpst 0.4 0.6 0.4 0.6 tck(avg) 19,42 activate to activate command period for 1kb page size products trrd 7.5 x 7.5 x ns 4,32 activate to activate command period for 2kb page size products trrd 10 x 10 x ns 4,32 13.3 timing parameters by speed grade (ddr2-800 and ddr2-667)
rev. 1.1 july 2008 vlp rdimm ddr2 sdram 22 of 29 parameter symbol ddr2-800 ddr2-667 units notes min max min max four activate window for 1kb page size products tfaw 35 x 37.5 x ns 32 four activate window for 2kb page size products tfaw 45 x 50 x ns 32 cas to cas command delay tccd 2 x 2 x nck write recovery time twr 15 x 15 x ns 32 auto precharge write recovery + precharge time tdal wr + tnrp x wr + tnrp x nck 33 internal write to read command delay twtr 7.5 x7.5 x ns 24,32 internal read to precharge command delay trtp 7.5 x7.5 x ns 3,32 exit self refresh to a non-read command txsnr trfc + 10 x trfc + 10 x ns 32 exit self refresh to a read command txsrd 200 x 200 x nck exit precharge power down to any command txp 2 x 2 x nck exit active power down to read command txard 2 x 2 x nck 1 exit active power down to read command (slow exit, lower power) txards 8 - al x 7 - al x nck 1,2 cke minimum pulse width (high and low pulse width) tcke 3 x 3 x nck 27 odt turn-on delay taond 2 2 2 2 nck 16 odt turn-on taon tac(min) tac(max)+0.7 tac(min) tac(max)+0.7 ns 6,16,40 odt turn-on (power-down mode) taonpd tac(min)+2 2*tck(avg) +tac(max)+1 tac(min)+2 2*tck(avg) +tac(max)+1 ns odt turn-off delay taofd 2.5 2.5 2.5 2.5 nck 17,45 odt turn-off taof tac(min) tac(max)+0.6 tac(min) tac(max)+0.6 ns 17,43,45 odt turn-off (power-down mode) taofpd tac(min)+2 2.5*tck(avg) +tac(max)+1 tac(min)+2 2.5*tck(avg) +tac(max)+1 ns odt to power down entry latency tanpd 3 x3 x nck odt power down exit latency taxpd 8 x8 x nck ocd drive mode output delay toit 0 12 0 12 ns 32 minimum time clocks remains on after cke asynchronously drops low tdelay tis+tck(avg) +tih x tis+tck(avg) +tih xns 15
rev. 1.1 july 2008 vlp rdimm ddr2 sdram 23 of 29 (refer to notes for informations related to this table at the component datasheet) parameter symbol ddr2-533 units notes min max dq output access time from ck/ck tac -500 500 ps dqs output access time from ck/ck tdqsck -450 450 ps ck high pulse width tch 0.45 0.55 tck ck low pulse width tcl 0.45 0.55 tck ck half pulse period thp min(tcl, tch) x ps 11,12 clock cycle time, cl=x tck 3750 8000 ps 15 dq and dm input hold time (differential strobe) tdh(base) 225 x ps 6,7,8,21,28 dq and dm input setup time (differential strobe) tds(base) 100 x ps 6,7,8,20,28 dq and dm input hold time (single-ended strobe) tdh1(base) -25 x ps 6,7,8,26 dq and dm input setup time (single-ended strobe) tds1(base) -25 x ps 6,7,8,25 control & address input pulse width for each input tipw 0.6 x tck dq and dm input pulse width for each input tdipw 0.35 x tck data-out high-impedance time from ck/ck thz x tac(max) ps 18 dqs(/dqs ) low-impedance time from ck/ck tlz(dqs) tac(min) tac(max) ps 18 dq low-impedance time from ck/ck tlz(dq) 2* tac(min) tac(max) ps 18 dqs-dq skew for dqs and associated dq signals tdqsq x 300 ps 13 dq hold skew factor tqhs x 400 ps 12 dq/dqs output hold time from dqs tqh thp - tqhs x ps dqs latching rising transitions to associated clock edges tdqss -0.25 0.25 tck dqs input high pulse width tdqsh 0.35 x tck dqs input low pulse width tdqsl 0.35 x tck dqs falling edge to ck setup time tdss 0.2 x tck dqs falling edge hold time from ck tdsh 0.2 x tck mode register set command cycle time tmrd 2x tck mrs command to odt update delay tmod 0 12 ns write postamble twpst 0.4 0.6 tck 10 write preamble twpre 0.35 x tck address and control input hold time tih(base) 375 x ps 5,7,9,23 address and control input setup time tis(base) 250 x ps 5,7,9,22 read preamble trpre 0.9 1.1 tck 19 read postamble trpst 0.4 0.6 tck 19 active to active command period for 1kb page size products trrd 7.5 x ns 4 active to active command period for 2kb page size products trrd 10 x ns 4 13.4 timing parameters by speed grade (ddr2-533)
rev. 1.1 july 2008 vlp rdimm ddr2 sdram 24 of 29 parameter symbol ddr2-533 units notes min max four activate window for 1kb page size products tfaw 37.5 x ns four activate window for 2kb page size products tfaw 50 x ns cas to cas command delay tccd 2 x tck write recovery time twr 15 x ns auto precharge write recovery + precharge time tdal wr+trp x tck 14 internal write to read command delay twtr 7.5 x ns 24 internal read to precharge command delay trtp 7.5 x ns 3 exit self refresh to a non-read command txsnr trfc + 10 x ns exit self refresh to a read command txsrd 200 x tck exit precharge power down to any non-read command txp 2 x tck exit active power down to read command txard 2 x tck 1 exit active power down to read command (slow exit, lower power) txards 6 - al x tck 1,2 cke minimum pulse width (high and low pulse width) tcke 3 xtck 27 odt turn-on delay taond 2 2 tck 16 odt turn-on taon tac(min) tac(max)+1 ns 16 odt turn-on (power-down mode) taonpd tac(min)+2 2tck+ tac(max)+1 ns odt turn-off delay taofd 2.5 2.5 tck 17,44 odt turn-off taof tac(min) tac(max) + 0.6 ns 17,44 odt turn-off (power-down mode) taofpd tac(min)+2 2.5tck+ tac(max)+1 ns odt to power down entry latency tanpd 3 xtck odt power down exit latency taxpd 8 xtck ocd drive mode output delay toit 0 12 ns 32 minimum time clocks remains on after cke asynchronously drops low tdelay tis+tck+tih xns 15
rev. 1.1 july 2008 vlp rdimm ddr2 sdram 25 of 29 units : millimeters 14.1 128mbx8 based 128mx72 module (1 rank) 14.0 physical dimensions : - m392t2863qza the used device is 128m x8 ddr2 sdram, fbga. ddr2 sdram part no : k4t1g084qq 2.50 1.00 0.20 2.500.20 detail b 5.00 detail a 4.00 1.500.10 0.800.05 4.00 3.80 133.35 18.30 0.15 17.80 2.30 5.175 63 123 10.00 55 2x 3.00 min 2.20 128.95 133.35 18.30 0.15 a b 1.27 0.10 4.00 max 1.0 max 1.7 max register pll
rev. 1.1 july 2008 vlp rdimm ddr2 sdram 26 of 29 units : millimeters 14.2 128mbx8/256mbx4 based 256mx72 module (2/1 ranks) - m392t5663qza/m392t5660qza the used device is 128m x8 / 256m x4 ddr2 sdram, fbga. ddr2 sdram part no : k4t1g084qq / k4t1g044qq register 133.35 18.30 0.15 17.80 2.30 5.175 63 123 10.00 55 2x 3.00 min 2.20 128.95 133.35 2.50 1.00 0.20 2.500.20 detail b 5.00 detail a 4.00 1.500.10 0.800.05 4.00 3.80 18.30 0.15 a b 1.27 0.10 4.00 max 1.0 max register pll
rev. 1.1 july 2008 vlp rdimm ddr2 sdram 27 of 29 units : millimeters the used device is ddp 512m x4 ddr2 sdram, fbga. ddr2 sdram part no : k4t2g044qq - m392t5160qja 14.3 ddp 512mbx4 based 512mx72 module (2 ranks) register 133.35 18.30 0.15 17.80 2.30 5.175 63 123 10.00 55 2x 3.00 min 2.20 128.95 133.35 2.50 1.00 0.20 2.500.20 detail b 5.00 detail a 4.00 1.500.10 0.800.05 4.00 3.80 18.30 0.15 a b 1.27 0.10 1.0 max pll register 7.55 max
rev. 1.1 july 2008 vlp rdimm ddr2 sdram 28 of 29 units : millimeters the used device is qdp 1g x4 ddr2 sdram, fbga. ddr2 sdram part no : k4t4g044qq - m392t1g60qqa 2.50 1.00 0.20 2.500.20 detail b 5.00 detail a 4.00 1.500.10 0.800.05 4.00 3.80 3.00 4.00 2.50 1.00 0.20 2.500.20 detail b 5.00 detail a 4.00 1.500.10 0.800.05 4.00 3.80 3.00 4.00 133.35 18.30 0.15 5.175 63 123 10.00 55 133.35 18.30 0.15 a b 1.27 0.10 1.0 max pll 7.55 max register register 14.4 qdp 1g x4 based 1gx72 module (4 ranks) (without hs)
rev. 1.1 july 2008 vlp rdimm ddr2 sdram 29 of 29 ck0 ck 0 pll out1 outn reg.a reg.b feedback in feedback out in 0ns (nominal) c 120 ohms 120 ohms 120 ohms 120 ohms c note: 1. the clock delay from the input of the pll clock to the input of any ddr2 sdram or register will be set to 0ns (nominal). 2. input, output, and feedback clock lines are terminated from line to line as shown, and not from line to ground. 3. only one pll output is shown per output type. any ad ditional pll outputs will be wired in a similar manner. 4. termination resistors for the pll feedbac k path clocks are located as close to the input pin of the pll as possible. ddr2 sdram ddr2 sdram 15.0 240 pin ddr2 register ed dimm clock topology

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