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1 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com wed2zl361mv september 2000 rev. 0 eco #13181 description the wedc syncburst - sram family employs high-speed, low- power cmos designs that are fabricated using an advanced cmos process. wedc? 32mb syncburst srams integrate two 1m x 18 srams into a single bga package to provide 1m x 36 configuration. all synchronous inputs pass through registers controlled by a positive-edge-triggered single-clock input (clk). the nbl or no bus latency memory utilizes all the bandwidth in any combination of operating cycles. address, data inputs, and all control signals except output enable and linear burst order are synchronized to input clock. burst order control must be tied ?igh or low.? asynchro- nous inputs include the sleep mode enable (zz). output enable controls the outputs at any given time. write cycles are internally self-timed and initiated by the rising edge of the clock input. this feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incoming signals. * this data sheet describes a product under development, not fully characterized, and is subject to change without notice. 1m x 36 synchronous pipeline burst nbl sram preliminary* fig. 1 block diagram pin configuration (top view) address bus (sa 0 ?sa 19 ) dqa, dqb dqpa, dqpb dqc, dqd dqpc, dqpd dqa dqd dqpa dqpd 1m x 18 1m x 18 clk cke adv lbo cs1 cs2 cs2 oe we zz clk cke adv lbo ce1 ce2 ce2 oe we zz clk cke adv lbo cs1 cs2 cs2 oe we zz bwd bwa bwc bwb features fast clock speed: 166, 150, 133, and 100mhz fast access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns fast oe access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns single +3.3v 5% power supply (v dd ) snooze mode for reduced-standby power individual byte write control clock-controlled and registered addresses, data i/os and control signals burst control (interleaved or linear burst) packaging: 119-bump bga package low capacitive bus loading 123 4 5 67 a v dd sa sa sa sa sa v dd b sa ce2 sa adv sa ce2 nc c nc sa sa v dd sa sa nc d dq c dqp c v ss nc v ss dqp b dq b e dq c dq c v ss ce1 v ss dq b dq b f v dd dq c v ss oe v ss dq b v dd g dq c dq c bw c sa bw b dq b dq b h dq c dq c v ss we v ss dq b dq b j v dd v dd nc v dd nc v dd v dd k dq d dq d v ss clk v ss dq a dq a l dq d dq d bw d nc bw a dq a dq a m v dd dq d v ss cke v ss dq a v dd n dq d dq d v ss sa1 v ss dq a dq a p dq d dqp d v ss sa0 v ss dqp a dq a r nc sa lbo v dd nc sa nc t nc nc sa sa sa nc zz u v dd nc nc nc nc nc v dd
2 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com wed2zl361mv september 2000 rev. 0 burst sequence table note 1: lbo pin must be tied to high or low, and floating state must not be allowed. write operation occurs when we is driven low at the rising edge of the clock. bw[d:a] can be used for byte write operation. the pipe- lined nbl ssram uses a late-late write cycle to utilize 100% of the bandwidth. at the first rising edge of the clock, we and address are registered, and the data associated with that address is required two cycle later. subsequent addresses are generated by adv high for the burst access as shown below. the starting point of the burst seguence is provided by the external address. the burst address counter wraps around to its initial state upon completion. the burst sequence is determined by the state of the lbo pin. when this pin is low, linear burst sequence is selected. and when this pin is high, interleaved burst sequence is selected. during normal operation, zz must be driven low. when zz is driven high, the sram will enter a power sleep mode after 2 cycles. at this time, internal state of the sram is preserved. when zz returns to low, the sram operates after 2 cycles of wake up time. (interleaved burst, lbo = high) case 1 case 2 case 3 case 4 lbo pin high a1 a0 a1 a0 a1 a0 a1 a0 first address 0 0 011011 01001110 10110001 fourth address 1 1 100100 (linear burst, lbo = low) case 1 case 2 case 3 case 4 lbo pin high a1 a0 a1 a0 a1 a0 a1 a0 first address 00011011 01101100 10110001 fourth address 11000110 function description the wed2zl361ms is an nbl ssram designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is tran- sition from read to write, or vice versa. all inputs (with the exception of oe, lbo and zz) are synchronized to rising clock edges. all read, write and deselect cycles are initiated by the adv input. subsequent burst addresses can be internally generated by the burst advance pin (adv). adv should be driven to low once the device has been deselected in order to load a new address for next operation. clock enable (cke) pin allows the operation of the chip to be suspended as long as necessary. when cke is high, all synchronous inputs are ignored and the internal device registers will hold their previous values. nbl ssram latches external address and initiates a cycle when cke and adv are driven low at the rising edge of the clock. output enable (oe) can be used to disable the output at any given time. read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the address register, cke is driven low, the write enable input signals we are driven high, and adv driven low. the internal array is read between the first rising edge and the second rising edge of the clock and the data is latched in the output register. at the second clock edge the data is driven out of the sram. during read operation oe must be driven low for the device to drive out the requested data.
3 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com wed2zl361mv september 2000 rev. 0 truth tables synchronous truth table write truth table we bwa bwb bwc bwd operation hxxxx read l l h h h write byte a l h l h h write byte b l h h l h write byte c l h h h l write byte d lllll write all bytes lhhhh write abort/nop notes: 1. x means ?on? care. 2. all inputs in this table must meet setup and hold time around the rising edge of clk ( ). cex adv we bwx oe cke clk address accessed operation h l x x x l n/a deselect x h x x x l n/a continue deselect l l h x l l external address begin burst read cycle x h x x l l next address continue burst read cycle l l h x h l external address nop/dummy read x h x x h l next address dummy read llllxl external address begin burst write cycle x h x l x l next address continue burst write cycle l l l h x l n/a nop/write abort x h x h x l next address write abort xxxxxh current address ignore clock notes: 1. x means ?on? care. 2. the rising edge of clock is symbolized by ( ) 3. a continue deselect cycle can only be entered if a deselect cycle is executed first. 4. write = l means write operation in write truth table. write = h means read operation in write truth table. 5. operation finally depends on status of asynchronous input pins (zz and oe). 6. cex refers to the combination of ce1, ce2 and ce2.
4 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com wed2zl361mv september 2000 rev. 0 absolute maximum ratings* voltage on v dd supply relative to v ss -0.3v to +4.6v vin (dqx) -0.3v to +4.6v vin (inputs) -0.3v to +4.6v storage temperature (bga) -65 c to +150 c short circuit output current 100ma electrical characteristics (0 c t a 70 c) *stress greater than those listed under ?bsolute maximum ratings: may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating condtions for extended periods may affect reliability. description symbol conditions min max units notes input high (logic 1) voltage v ih 2.0 v dd +0.5 v 1 input low (logic 0) voltage v il -0.3 0.8 v 1 input leakage current ili 0v v in v dd -5 5 a2 output leakage current i lo output(s) disabled, 0v v in v dd -5 5 a output high voltage v oh i oh = -4.0ma 2.4 --- v 1 output low voltage v ol i ol = 8.0ma --- 0.4 v 1 supply voltage v dd 3.135 3.465 v 1 notes: 1. all voltages referenced to v ss (gnd) 2. zz pin has an internal pull-up, and input leakage = 10 a. dc characteristics notes: 1. i dd is specified with no output current and increases with faster cycle times. i dd increases with faster cycle times and greater output loading. 2. typical values are measured at 3.3v, 25 c, and 10ns cycle time. bga capacitance notes: 1. this parameter is sampled. description symbol conditions typ max units notes control input capacitance c i t a = 25 c; f = 1mhz 5 7 pf 1 input/output capacitance (dq) c o t a = 25 c; f = 1mhz 6 8 pf 1 address capacitance c a t a = 25 c; f = 1mhz 5 7 pf 1 clock capacitance c ck t a = 25 c; f = 1mhz 3 5 pf 1 166 150 133 100 description symbol conditions typ mhz mhz mhz mhz units notes power supply i dd device selected; all inputs v il or v ih ; cycle 840 800 760 640 ma 1, 2 current: operating time = t cyc min; v dd = max; output open power supply i sb2 device deselected; v dd = max; all inputs v ss + 0.2 30 60 60 60 60 ma 2 current: standby or v dd - 0.2; all inputs static; clk frequency = 0; zz v il power supply i sb3 device selected; all inputs v il or v ih ; cycle 30 60 60 60 60 ma 2 current: current time = t cyc min; v dd = max; output open; zz v dd - 0.2v clock running i sb4 device deselected; v dd = max; all inputs 240 220 180 160 ma 2 standby current v ss + 0.2 or v dd - 0.2; cycle time = t cyc min; zz v il
5 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com wed2zl361mv september 2000 rev. 0 ac characteristics notes: 1. all address inputs must meet the specified setup and hold times for all rising clock (clk) edges when adv is sampled low and cex is sampled valid. all other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 2. chip enable must be valid at each rising edge of clk (when adv is low) to remain enabled. 3. a write cycle is defined by we low having been registered into the device at adv low. a read cycle is defined by we high with adv low. both cases must meet setup and hold times. output load (a) output load (b) (for t lzc , t lzoe , t hzoe , and t hzc ) symbol 166mhz 150mhz 133mhz 100mhz parameter min max min max min max min max units clock time t cyc 6.0 6.7 7.5 10.0 ns clock access time t cd -- 3.5 -- 3.8 -- 4.2 -- 5.0 ns output enable to data valid t oe -- 3.5 -- 3.8 -- 4.2 -- 5.0 ns clock high to output low-z t lzc 1.5 -- 1.5 -- 1.5 -- 1.5 -- ns output hold from clock high t oh 1.5 -- 1.5 -- 1.5 -- 1.5 -- ns output enable low to output low-z t lzoe 0.0 -- 0.0 -- 0.0 -- 0.0 -- ns output enable high to output high-z t hzoe -- 3.0 -- 3.0 -- 3.5 -- 3.5 ns clock high to output high-z t hzc -- 3.0 -- 3.0 -- 3.5 -- 3.5 ns clock high pulse width t ch 2.2 -- 2.5 -- 3.0 -- 3.0 -- ns clock low pulse width t cl 2.2 -- 2.5 -- 3.0 -- 3.0 -- ns address setup to clock high t as 1.5 -- 1.5 -- 1.5 -- 1.5 -- ns cke setup to clock high t ces 1.5 -- 1.5 -- 1.5 -- 1.5 -- ns data setup to clock high t ds 1.5 -- 1.5 -- 1.5 -- 1.5 -- ns write setup to clock high t ws 1.5 -- 1.5 -- 1.5 -- 1.5 -- ns address advance to clock high t advs 1.5 1.5 1.5 1.5 ns chip select setup to clock high t css 1.5 1.5 1.5 1.5 ns address hold to clock high t ah 0.5 -- 0.5 -- 0.5 -- 0.5 -- ns cke hold to clock high t ceh 0.5 -- 0.5 -- 0.5 -- 0.5 -- ns data hold to clock high t dh 0.5 -- 0.5 -- 0.5 -- 0.5 -- ns write hold to clock high t wh 0.5 -- 0.5 -- 0.5 -- 0.5 -- ns address advance to clock high t advh 0.5 -- 0.5 -- 0.5 -- 0.5 -- ns chip select hold to clock high t csh 0.5 -- 0.5 -- 0.5 -- 0.5 -- ns dout zo=50 ? rl=50 ? vl=1.5v 30pf* dout 353 ? 5pf* +3.3v 319 ? *including scope and jig capacitance ac test conditions (t a = 0 to 70 c, v dd = 3.3v 5%, unless otherwise specified) parameter value input pulse level 0 to 3.0v input rise and fall time (measured at 20% to 80%) 1.0v/ns input and output timing reference levels 1.5v output load see output load (a)
6 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com wed2zl361mv september 2000 rev. 0 snooze mode snooze mode is a low-current, power-down mode in which the device is deselected and current is reduced to i sb2z . the duration of snooze mode is dictated by the length of time z is in a high state. after the device enters snooze mode, all inputs except zz become gated inputs and are ignored. zz is an asynchronous, active high input that causes the device to enter snooze mode. when zz becomes a logic high, i sb2z is guaranteed after the setup time t zz is met. any read or write operation pending when the device enters snooze mode is not guaranteed to complete suc- cessfully. therefore, snooze mode must not be initiated until valid pending operations are completed. snooze mode description conditions symbol min max units notes current during snooze mode zz vih i sb2z 10 ma zz active to input ignored t zz 2(t kc )ns 1 zz inactive to input sampled t rzz 2(t kc )ns1 zz active to snooze current t zzi 2(t kc )ns 1 zz inactive to exit snooze current t rzzi ns 1 fig. 2 snooze mode timing diagram zz i supply clock all inputs (except zz) output (q) t zz t zzi t rzz t rzzi high-z deselect or read only i isb2z don't care
7 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com wed2zl361mv september 2000 rev. 0 clock cke address write adv oe data out t ch t cl t ces t ceh t as t ah a1 a2 a3 t ws t wh t css t csh t oe t hzoe t lzoe t cd t oh t hzc q3-4 q3-3 q3-2 q3-1 q2-4 q2-3 q2-2 q2-1 q1-1 don t care undefined t cyc t advs t advh cex notes: write = l means we = l, and bwx = l cex refers to the combination of ce1, ce2 and ce2. fig. 3 timing waveform of read cycle
8 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com wed2zl361mv september 2000 rev. 0 fig. 4 timing waveform of write cycle clock address write adv data in t ch t cl a2 a3 d2-1 d1-1 d2-2 d2-3 d2-4 d3-1 d3-2 d3-3 oe data out t ds t dh don t care undefined t cyc cke a1 d3-4 t ces t ceh q0-4 t hzoe q0-3 cex notes: write = l means we = l, and bwx = l cex refers to the combination of ce1, ce2 and ce2.
9 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com wed2zl361mv september 2000 rev. 0 fig. 5 timing waveform of single read/write cloc address write adv oe data in t ch t cl t ds t dh data out a2 a4 a5 d2 t oe t lzoe q1 don t care undefined t cyc cke t ces t ceh a1 a3 a7 a6 q3 q4 q7 q6 d5 a9 a8 cex k notes: write = l means we = l, and bwx = l cex refers to the combination of ce1, ce2 and ce2.
10 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com wed2zl361mv september 2000 rev. 0 fig. 6 timing waveform of cke operation clock address write adv oe data in t ch t cl data out a1 a2 a3 a4 a5 t ces t ceh don t care undefined t cyc cke t ds t dh d2 q4 q1 t cd t lzc t hzc q3 a6 cex notes: write = l means we = l, and bwx = l cex refers to the combination of ce1, ce2 and ce2.
11 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com wed2zl361mv september 2000 rev. 0 clock address write adv oe data in t ch t cl data out a1 a2 a3 a4 a5 don t care undefined t cyc cke d5 q4 t ces t ceh q1 q2 t oe t lzoe d3 t cd t lzc t hzc t dh t ds cex notes: write = l means we = l, and bwx = l cex refers to the combination of ce1, ce2 and ce2. fig. 7 timing waveform of ce operation
12 white electronic designs corporation ?(508) 366-5151 ?www.whiteedc.com wed2zl361mv september 2000 rev. 0 package dimension: 119 bump pbga all linear dimensions are in millimeters and parenthetically in inches 2.79 (0.110) max 0.711 (0.028) max 1.27 (0.050) typ 1.27 (0.050) typ a b c d e f g h j k l m n p r t u 17.00 (0.669) typ a1 corner 20.32 (0.800) typ 23.00 (0.905) typ 7.62 (0.300) typ r 1.52 (0.060) max (4x) ordering information commercial temp range (0 c to 70 c) part number configuration t cd clock (ns) (mhz) wed2zl361mv35bc 1m x 36 3.5 166 wed2zl361mv38bc 1m x 36 3.8 150 wed2zl361mv42bc 1m x 36 4.2 133 WED2ZL361MV50BC 1m x 36 5.0 100

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