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zl2006 data sheet december 15, 2010 fn6850.1 1 1-888-intersil or 1-888-468-3774 | intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. copyright ? intersil americas inc. 2009, 2010. all rights reserved all other trademarks mentioned are the property of their respective owners n o t r e c o m m e n d e d f o r n e w d e s i g n s r e c o m m e n d e d r e p l a c e m e n t p a r t z l 6 1 0 0 adaptive digital dc-dc controller with drivers and current sharing description the zl2006 is a digital dc-dc controller with integrated mosfet drivers. current sharing allows multiple devices to be connected in parallel to source loads with very high current demands. adaptive performance optimization algorithms improve power conversion efficiency across the entire load range. zilker labs digital-dc? technology enables a blend of power conversion pe rformance and power management features. the zl2006 is designed to be a flexible building block for dc power and can be easily adapted to designs ranging from a single-phase power supply operating from a 3.3 v input to a multi-phase supply operating from a 12 v input. the zl2006 eliminates the need for complicated power supply managers as well as numerous external discrete components. all operating features can be configured by simple pin- strap/resistor selection or through the smbus? serial interface. the zl2006 uses the pmbus? protocol for communication with a host controller and the digital- dc bus for communication between other zilker labs devices. features power conversion ? efficient synchronous buck controller ? adaptive light load e fficiency optimization ? 3 v to 14 v input range ? 0.54 v to 5.5 v output range (with margin) ? 1% output voltage accuracy ? internal 3 a mosfet drivers ? fast load transient response ? current sharing and phase interleaving ? snapshot? parameter capture ? rohs compliant (6 x 6 mm) qfn package power management ? digital soft start / stop ? precision delay and ramp-up ? power good / enable ? voltage tracking, sequencing, and margining ? voltage / current / temperature monitoring ? i 2 c/smbus interface, pmbus compatible ? output voltage and current protection ? internal non-volatile memory (nvm) applications ? servers / storage equipment ? telecom / datacom equipment ? power supplies (memory, dsp, asic, fpga) figure 1. block diagram figure 2. efficiency vs. load current
zl2006 2 fn6850.1 december 15, 2010 table of contents 1. electrical char acteristics .................................................................................................... ......................................................... 3 2. pin descriptions .............................................................................................................. ............................................................. 7 3. typical applica tion circuit ................................................................................................... ...................................................... 9 4. zl2006 over view ............................................................................................................... ....................................................... 10 4.1 digital-dc ar chitecture ....................................................................................................... .............................................. 10 4.2 power conversion overview ..................................................................................................... ......................................... 11 4.3 power management overview ..................................................................................................... ....................................... 12 4.4 multi-mode pins ............................................................................................................... .................................................. 13 5. power conversion fu nctional desc ription..................................................................................... ............................................... 14 5.1 internal bias regulators an d input supply connections ......................................................................... ........................... 14 5.2 high-side driver boost circuit ................................................................................................ ........................................... 14 5.3 output voltage selec tion ...................................................................................................... .............................................. 14 5.4 start-up procedure ............................................................................................................ .................................................. 17 5.5 soft start delay and ramp times ............................................................................................... ....................................... 17 5.6 power good .................................................................................................................... .................................................... 18 5.7 switching frequency and pll ................................................................................................... ........................................ 19 5.8 power train component selection ............................................................................................... ...................................... 20 5.9 current limit thre shold sele ction ............................................................................................. ........................................ 24 5.10 loop comp ensation ............................................................................................................. ............................................... 27 5.11 adaptive comp ensatio n ......................................................................................................... ............................................. 28 5.12 non-linear response (nlr) settings ............................................................................................ ..................................... 28 5.13 efficiency optimized driv er dead-tim e control ................................................................................. ............................... 28 5.14 adaptive diode emulation ...................................................................................................... ........................................... 29 5.15 adaptive frequency control .................................................................................................... ........................................... 29 6. power management func tional desc ription ....................................................................................... ....................................... 30 6.1 input undervolta ge lockout .................................................................................................... ........................................... 30 6.2 output overvolta ge prot ection ................................................................................................. .......................................... 30 6.3 output pre-bias protection .................................................................................................... ............................................. 31 6.4 output overcurrent protection ................................................................................................. ........................................... 32 6.5 thermal overload protec tion ................................................................................................... ........................................... 32 6.6 voltage tracking .............................................................................................................. .................................................. 32 6.7 voltage ma rgini ng ............................................................................................................. ................................................. 33 6.8 i 2 c/smbus comm unications ........................................................................................................ ...................................... 34 6.9 i 2 c/smbus device addr ess sel ection .............................................................................................. .................................. 34 6.10 digital-dc bus ................................................................................................................ ................................................... 35 6.11 phase spre adi ng ............................................................................................................... ................................................... 35 6.12 output sequencing ............................................................................................................. ................................................. 36 6.13 fault spre adi ng ............................................................................................................... .................................................... 36 6.14 temperature monitoring using the xtemp pin .................................................................................... ............................ 37 6.15 active curren t shar ing ........................................................................................................ ............................................... 37 6.16 phase adding/dropping ......................................................................................................... ............................................. 38 6.17 monitoring via i 2 c/smbus ....................................................................................................................... .......................... 39 6.18 snapshot? parameter capture ............................................................................................................ ............................... 39 6.19 non-volatile memory and de vice security features .............................................................................. ........................... 40 7. package dimensions ............................................................................................................ ...................................................... 41 8. ordering information .......................................................................................................... ....................................................... 42 9. related tools and documentation ............................................................................................... .............................................. 42 10. revision histor y .............................................................................................................. .......................................................... 43
zl2006 3 fn6850.1 december 15, 2010 1. electrical characteristics table 1. absolute maximum ratings operating beyond these limits may cause permanent dama ge to the device. functional operation beyond the recommended operating conditions is not implied. voltage measured with respect to sgnd. parameter pin value unit dc supply voltage vdd - 0.3 to 17 v mosfet drive reference vr - 0.3 to 6.5 v 120 ma 2.5 v logic reference v25 - 0.3 to 3 v 120 ma logic i/o voltage cfg, dly(0,1), ddc, en, fc(0,1), ilim(0,1), mgn, pg, sa(0,1), salrt, scl, sda, ss, sync, uvlo, v(0,1) - 0.3 to 6.5 v analog input voltages isenb, vsen, vtrk, xtemp - 0.3 to 6.5 v isena - 1.5 to 30 v high side supply voltage bst - 0.3 to 30 v boost to switch voltage bst - sw - 0.3 to 8 v high side drive voltage gh (v sw -0.3) to (v bst +0.3) v low side drive voltage gl (pgnd-0.3) to (vr+0.3) v switch node continuous sw (pgnd-0.3) to 30 v switch node transient (<100ns) sw (pgnd-5) to 30 v ground differential dgnd ? sgnd, pgnd - sgnd - 0.3 to 0.3 v junction temperature ? - 55 to 150 c storage temperature ? - 55 to 150 c lead temperature (soldering, 10 s) all 300 c table 2. recommended operating c onditions and thermal information parameter symbol min typ max unit input supply voltage range, v dd (see figure 9) v dd tied to v r 3.0 ? 5.5 v v r floating 4.5 ? 14 v output voltage range 1 v out 0.54 ? 5.5 v operating junction temperature range t j - 40 ? 125 c junction to ambient thermal impedance 2 ja ? 35 ? c/w junction to case thermal impedance 3 jc ? 5 ? c/w notes: 1. includes margin limits 2. ja is measured in free air with the device mounted on a multi-layer fr4 test board and the exposed metal pad soldered to a low impedance ground plane using multiple vias. 3. for jc , the ?case? temperature is measured at the center of the exposed metal pad
zl2006 4 fn6850.1 december 15, 2010 table 3. electrical specifications v dd = 12 v, t a = -40 c to 85 c unless otherwise noted. typical values are at t a = 25 c. parameter conditions min (note 10) typ max (note 10) unit input and supply characteristics i dd supply current at f sw = 200 khz i dd supply current at f sw = 1.4 mhz gh, gl no load; misc_config[7] = 1 ? ? 16 25 30 50 ma ma i dds shutdown current en = 0 v no i 2 c/smbus activity ? 6.5 8 ma vr reference output voltage v dd > 6 v, i vr < 50 ma 4.5 5.2 5.5 v v25 reference output voltage v r > 3 v, i v25 < 50 ma 2.25 2.5 2.75 v output characteristics output voltage adjustment range 1 v in > v out 0.6 ? 5.0 v output voltage set-point resolution set using resistors ? 10 ? mv set using i 2 c/smbus ? 0.025 ? % fs 2 output voltage accuracy 3 includes line, load, temp - 1 ? 1 % vsen input bias current vsen = 5.5 v ? 110 200 a current sense differential input voltage (ground referenced) v isena - v isenb - 100 ? 100 mv current sense differential input voltage (v out referenced) (v out must be less than 4.0 v) v isena - v isenb - 50 ? 50 mv current sense input bias current ground referenced - 100 ? 100 a current sense input bias current (v out referenced, v out < 4.0 v) isena - 1 ? 1 a isenb - 100 ? 100 a soft start delay duration range 4 set using dly pin or resistor 2 ? 200 ms set using i 2 c/smbus 0.002 ? 500 s soft start delay duration accuracy turn-on delay (precise mode) 4,5 turn-on delay (normal mode) 6 turn-off delay 6 ? ? ? 0.25 - 0.25/+4 - 0.25/+4 ? ? ? ms ms ms soft start ramp duration range set using ss pin or resistor 0 ? 200 ms set using i 2 c 0 ? 200 ms soft start ramp duration accuracy ? 100 ? s notes: 1. does not include margin limits. 2. percentage of full scale (fs) with temperature compensation applied. 3. v out measured at the termination of the vsen+ and vsen- sense points. 4. the device requires a delay period foll owing an enable signal and prior to rampi ng its output. precise timing mode limits t his delay period to approx 2 ms, where in normal mode it may vary up to 4 ms. 5. precise ramp timing mode is only valid when using en pin to enable the device rather than pmbus enable. 6. the devices may require up to a 4 ms delay following the a ssertion of the enable signal (normal mode) or following the de-a ssertion of the enable signal.
zl2006 5 fn6850.1 december 15, 2010 table 3. electrical characteristics (continued) v dd = 12 v, t a = -40 c to 85 c unless otherwise noted. typical values are at t a = 25 c. parameter conditions min (note 10) typ max (note 10) unit logic input/output characteristics logic input bias current en,pg,scl,sda,salrt pins - 10 ? 10 a mgn input bias current - 1 ? 1 ma logic input low, v il ? ? 0.8 v logic input open (n/c) multi-mode logic pins ? 1.4 ? v logic input high, v ih 2.0 ? ? v logic output low, v ol i ol 4 ma ? ? 0.4 v logic output high, v oh i oh -2 ma 2.25 ? ? v oscillator and switching characteristics switching frequency range 200 ? 1400 khz switching frequency set-point accuracy predefined settings (see table 16) - 5 ? 5 % maximum pwm duty cycle factory default 95 ? ? % minimum sync pulse width 150 ? ? ns input clock frequency drift tolerance external clock source - 13 ? 13 % gate drivers high-side driver voltage (v bst - v sw ) ? 4.5 ? v high-side driver peak gate drive current (pull down) (v bst - v sw ) = 4.5 v 2 3 ? a high-side driver pull-up resistance (v bst - v sw ) = 4.5 v, (v bst - v gh ) = 50 mv ? 0.8 2 ? high-side driver pull-down resistance (v bst - v sw ) = 4.5 v, (v gh - v sw ) = 50 mv ? 0.5 2 ? low-side driver peak gate drive current (pull-up) v r = 5 v ? 2.5 ? a low-side driver peak gate drive current (pull-down) v r = 5 v ? 1.8 ? a low-side driver pull-up resistance v r = 5 v, (v r - v gl ) = 50 mv ? 1.2 2 ? low-side driver pull-down resistance v r = 5 v, (v gl - pgnd) = 50 mv ? 0.5 2 ? switching timing gh rise and fall time gl rise and fall time (v bst - v sw ) = 4.5 v, c load = 2.2 nf ? 5 20 ns v r = 5 v, c load = 2.2 nf ? 5 20 ns tracking vtrk input bias current vtrk = 5.5 v ? 110 200 a vtrk tracking ramp accuracy 100% tracking, v out - vtrk - 100 ? + 100 mv vtrk regulation accuracy 100% tracking, v out - vtrk - 1 ? 1 %
zl2006 6 fn6850.1 december 15, 2010 table 3. electrical characteristics (continued) v dd = 12 v, t a = -40 c to 85 c unless otherwise noted. typical values are at t a = 25 c. parameter conditions min (note 10) typ max (note 10) unit fault protection characteristics uvlo threshold range configurable via i 2 c/smbus 2.85 ? 16 v uvlo set-point accuracy - 150 ? 150 mv uvlo hysteresis factory default ? 3 ? % configurable via i 2 c/smbus 0 ? 100 % uvlo delay ? ? 2.5 s power good v out low threshold factory default ? 90 ? % v out power good v out high threshold factory default ? 115 ? % v out power good v out hysteresis factory default ? 5 ? % power good delay using pin-strap or resistor 7 0 ? 200 ms configurable via i 2 c/smbus 0 ? 500 s vsen undervoltage threshold factory default ? 85 ? % v out configurable via i 2 c/smbus 0 ? 110 % v out vsen overvoltage threshold factory default ? 115 ? % v out configurable via i 2 c/smbus 0 ? 115 % v out vsen undervoltage hysteresis ? 5 ? % v out vsen undervoltage/ overvoltage fault response time factory default ? 16 ? s configurable via i 2 c/smbus 5 ? 60 s current limit set-point accuracy (v out referenced) ? 10 ? % fs 8 current limit set-point accuracy (ground referenced) ? 10 ? % fs 8 current limit protection delay factory default ? 5 ? t sw 9 configurable via i 2 c/smbus 1 ? 32 t sw 9 temperature compensation of current limit protection threshold factory default 4400 ppm / c configurable via i 2 c/smbus 100 12700 thermal protection threshold (junction temperature) factory default ? 125 ? c configurable via i 2 c/smbus - 40 ? 125 c thermal protection hysteresis ? 15 ? c notes: 7. factory default power good delay is set to the same value as the soft start ramp time. 8. percentage of full scale (fs) w ith temperature compensation applied 9. t sw = 1/f sw , where f sw is the switching frequency. 10. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
zl2006 7 fn6850.1 december 15, 2010 2. pin descriptions sa1 ilim0 ilim1 scl sda salrt dgnd sa0 sync 36-pin qfn 6 x 6 mm sw pgnd gl vr isena isenb vdd gh bst en cfg mgn ddc xtemp v25 pg dly0 dly1 v1 uvlo ss vsen+ vtrk vsen- fc0 v0 fc1 exposed paddle connect to sgnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 27 26 25 24 23 22 21 20 19 36 35 34 33 32 31 30 29 28 figure 3. zl2006 pin configurations (top view) table 4. pin descriptions pin label type 1 description 1 dgnd pwr digital ground. common return for digital signals. connect to low impedance ground plane. 2 sync i/o,m 2 clock synchronization input. used to set switching frequency of internal clock or for synchronization to external frequency reference. 3 sa0 i, m serial address select pins. used to assign unique smbus address to each ic or to enable certain management features. 4 sa1 5 ilim0 i, m current limit select. sets the overcurrent threshold voltage for isena, isenb. 6 ilim1 7 scl i/o serial clock. connect to external host and/or to other zl2006s. 8 sda i/o serial data. connect to external host and/or to other zl2006s. 9 salrt o serial alert. connect to ex ternal host if desired. 10 fc0 i loop compensation selection pins. 11 fc1 12 v0 i output voltage selection pins. used to set v out set-point and v out max. 13 v1 14 uvlo i, m undervoltage lockout selection. sets the minimum value for v dd voltage to enable v out . 15 ss i, m soft start pin. set the output voltage ramp time during turn-on and turnoff. 16 vtrk i tracking sense input. used to tr ack an external voltage source. 17 vsen+ i output voltage feedback. connect to output regulation point. notes: 1. i = input, o = output, pwr = power or ground. m = multi-mode pins. 2. the sync pin can be used as a logic pin, a clock input or a clock output.
zl2006 8 fn6850.1 december 15, 2010 table 4. pin descriptions (continued) pin label type 1 description 18 vsen- i output voltage feedback. connect to load return or ground regulation point. 19 isenb i differential voltage input for current limit. 20 isena i differential voltage input for current limit. high voltage tolerant. 21 vr pwr internal 5v reference used to power internal drivers. 22 gl o low side fet gate drive. 23 pgnd pwr power ground. connect to low impedance ground plane. 24 sw pwr drive train switch node. 25 gh o high-side fet gate drive. 26 bst pwr high-side drive boost voltage. 27 vdd 3 pwr supply voltage. 28 v25 pwr internal 2.5 v reference used to power internal circuitry. 29 xtemp i external temperature sensor input. connect to external 2n3904 diode connected transistor. 30 ddc i/o digital-dc bus. (open drain) communication between zilker labs devices. 31 mgn i signal that enables margining of output voltage. 32 cfg i, m configuration pin. used to control the switching phase offset, sequencing and other management features. 33 en i enable input. active high signal enables pwm switching. 34 dly0 i, m softstart delay select. sets the delay from when en is asserted until the output voltage starts to ramp. 35 dly1 36 pg o power good output. epad sgnd pwr exposed thermal pad. common return for analog signals; internal connection to sgnd. connect to low impedance ground plane. notes: 1. i = input, o = output, pwr = power or ground. m = multi-mode pins. please refer to section 4.4?multi-mode pins,? on page 13. 2. the sync pin can be used as a logic pin, a clock input or a clock output. 3. v dd is measured internally and the value is used to modify the pwm loop gain.
zl2006 9 fn6850.1 december 15, 2010 3. typical application circuit the following application circuit re presents a typical implementation of the zl2006. for pmbus operation, it is recommended to tie the enable pin (en) to sgnd. zl2006 1 35 34 33 32 31 30 29 28 10 11 12 13 14 15 16 17 18 2 3 4 5 6 7 8 9 27 26 25 24 23 22 21 20 19 36 dgnd sync sa0 sa1 ilim0 ilim1 scl sda salrt fc0 fc1 v0 v1 uvlo ss vrtk vsen+ vdd bst gh sw pgnd gl vr isena isenb pg dly1 dly0 en cfg mgn ddc xtemp v25 v in 10 f 4 v c in 3 x 10 f 25 v l out i 2 c/smbus 2 power good output c v25 db bat54 cb 1 f 16 v qh ql 2.2 h c out 2 x 47 f 6.3 v 4.7 f c vr 6.3 v v out rtn sgnd epad 12v v25 470 f 2.5 v pos-cap 2*220 f 6.3 v 100 m vsen- enable f.b. 1 ground unification 4.7 f 25 v ddc bus 3 notes: 1. ferrite bead is optional for input noise suppression 2. the i 2 c/smbus requires pull-up resistors. please refer to the i 2 c/smbus specifications for more details. 3. the ddc bus requires a pull-up resistor. the resistance will vary based on the capacitive loading of the bus (and on the nu mber of devices connected). the 10 k default value, assuming a maximum of 100 pf per device, provides the necessary 1 s pull-up rise time. please refer to the ddc bus section for more details. figure 4. 12 v to 1.8 v / 20 a application circuit (4.5 v uvlo, 10 ms ss delay, 5 ms ss ramp)
zl2006 10 fn6850.1 december 15, 2010 4. zl2006 overview 4.1 digital-dc architecture the zl2006 is an innovative mixed-signal power conversion and power manage ment ic based on zilker labs patented digital-dc technology that provides an integrated, high performance step-down converter for a wide variety of power supply applications. today?s embedded power systems are typically designed for optimal efficiency at maximum load, reducing the peak thermal stress by limiting the total thermal dissipation inside the system. unfortunately, many of these systems are often operated at load levels far below the peak where th e power system has been optimized, resulting in reduced efficiency. while this may not cause thermal stress to occur, it does contribute to higher electricity usage and results in higher overall system operating costs. zilker labs? efficiency-adaptive zl2006 dc-dc controller helps mitigate this scenario by enabling the power converter to automatically change their operating state to increase efficiency and overall performance with little or no user interaction needed. its unique pwm loop utilizes an ideal mix of analog and digital blocks to enable precise control of the entire power conversion process with no software required, resulting in a very flexible device that is also very easy to use. an extensive set of power management functions are fully integrated and can be configured using simple pin connections. the user configuration can be saved in an internal non-volatile memory (nvm). additionally, all functions can be configured and monitored via the smbus hardware interface using standard pmbus commands, allowing ultimate flexibility. once enabled, the zl2006 is immediately ready to regulate power and perform power management tasks with no programming required. advanced configuration options and real-time configuration changes are available via the i 2 c/smbus interface if desired and continuous monitoring of multiple operating parameters is possible with minimal interaction from a host controller. integrated sub- regulation circuitry enables single supply operation from any supply between 3 v and 14 v with no secondary bias supplies needed. the zl2006 can be configured by simply connecting its pins according to the tables provided in the following sections. additionally, a comprehensive set of online tools and application notes are available to help simplify the design process. an evaluation board is also available to help th e user become familiar with the device. this board can be evaluated as a standalone platform using pin configuration settings. a windows?-based gui is also provided to enable full configuration and monitoring capability via the i 2 c/smbus interface using an available computer and the included usb cable. application notes and reference designs are available to assist the user in designing to specific application demands. please register for my zl on www.zilkerlabs.com to access the most up-to-date documentation or call your local zilker labs sales office to order an evaluation kit.
zl2006 11 fn6850.1 december 15, 2010 4.2 power conversion overview the zl2006 operates as a voltage-mode, synchronous buck converter with a sel ectable constant frequency pulse width modulator (pwm) control scheme that uses external mosfets, capacitors, and an inductor to perform power conversion. figure 6. synchronous buck converter figure 6 illustrates the basic synchronous buck converter topology showing the primary power train components. this converter is also called a step-down converter, as the output voltage must always be lower than the input voltage. in its most simple configuration, the zl2006 requires two external n-channel power mosfets, one for the top control mosfet (qh) and one for the bottom synchronous mosfet (ql). the amount of time that qh is on as a fraction of the total switching period is known as the duty cycle d , which is described by the following equation: in out v v d during time d, qh is on and v in ? v out is applied across the inductor. the current ramps up as shown in figure 7. when qh turns off (time 1-d), the current flowing in the inductor must continue to flow from the ground up through ql, during which the current ramps down. since the output capacitor c out exhibits a low impedance at the switching frequency, the ac component of the inductor current is filtered from the output voltage so the load sees nearly a dc voltage. figure 5. zl2006 block diagram digital compensator i 2 c nlr input voltage bus v out bst sw d-pwm + - vsen+ sync pll power management temp sensor mux xtemp dly(0,1) mgn en v(0,1) pg sa(0,1) ss vr sw vsen isena ilim(0,1) vdd mosfet drivers sync gen vtrk isenb vdd scl sda salrt > adc adc adc communication dac refcn fc(0,1) ddc voltage sensor vsen- nvm digital compensator i 2 c nlr input voltage bus v out bst sw d-pwm + - vsen+ sync pll power management temp sensor mux xtemp dly(0,1) mgn en v(0,1) pg sa(0,1) ss vr sw vsen isena ilim(0,1) vdd mosfet drivers sync gen vtrk isenb vdd scl sda salrt > adc adc adc communication dac refcn fc(0,1) ddc voltage sensor vsen- nvm
zl2006 12 fn6850.1 december 15, 2010 typically, buck converters specify a maximum duty cycle that effectively limits the maximum output voltage that can be realized for a given input voltage. this duty cycle limit ensures that the lowside mosfet is allowed to turn on for a minimum amount of time during each switching cycle, which enables the bootstrap capacitor (cb in figure 6) to be charged up and provide adequate gate drive voltage for the high- side mosfet. see section 5.2, ?high-side driver boost circuit,? for more details. in general, the size of components l1 and c out as well as the overall efficiency of the circuit are inversely proportional to the switching frequency, f sw . therefore, the highest efficiency circuit may be realized by switching the mosfets at the lowest possible frequency; however, this will result in the largest component size. conversely, the smallest possible footprint may be realized by switching at the fastest possible frequency but this gives a somewhat lower efficiency. each user should determine the optimal combination of size and efficiency when determining the switching frequency for each application. the block diagram for the zl2006 is illustrated in figure 5. in this circuit, the target output voltage is regulated by connecting the differential vsen pins directly to the output regulation point. the vsen signal is then compared to a reference voltage that has been set to the desired output voltage level by the user. the error signal derived from this comparison is converted to a digital value with a low-resolution, analog to digital (a/d) converter. the digital signal is applied to an adjustable digital compensation filter, and the compensated signal is used to derive the appropriate pwm duty cycle for driving the external mosfets in a way that produces the desired output. the zl2006 has several features to improve the power conversion efficiency. a non-linear response (nlr) loop improves the response time and reduces the output deviation as a result of a load transient. the zl2006 monitors the power converter?s operating conditions and continuously adjusts the turn-on and turn-off timing of the high-side and low-side mosfets to optimize the overall efficiency of the power supply. adaptive performance optimization algorithms such as dead-time control, diode emulation, and frequency control are available to provide greater efficiency improvement. 4.3 power management overview the zl2006 incorporates a wide range of configurable power management features that are simple to implement with no external components. additionally, the zl2006 includes circuit protection features that continuously safeguard the device and load from damage due to unexpected system faults. the zl2006 can continuously monitor input voltage, output voltage/current, internal temperature, and the temperature of an external thermal diode. a power good output signal is also included to enable power-on reset functionality for an external processor. all power management functions can be configured using either pin configurat ion techniques (see figure 8) or via the i 2 c/smbus interface. monitoring parameters can also be pre-configured to provide alerts for specific conditions. see application note an33 for more details on smbus monitoring. time v in -v out 0 -v out 1 - d i o il pk il v d figure 7. inductor waveform
zl2006 13 fn6850.1 december 15, 2010 4.4 multi-mode pins in order to simplify circuit design, the zl2006 incorporates patented multi-mode pins that allow the user to easily configure many aspects of the device with no programming. most power management features can be configured using these pins. the multi- mode pins can respond to f our different connections as shown in table 5. these pins are sampled when power is applied or by issuing a pmbus restore command (see application note an33). pin-strap settings: this is the simplest implementation method, as no external components are required. using this method, each pin can take on one of three possible states: low, open, or high. these pins can be connected to the v25 pin for logic high settings as this pin provides a regulated voltage higher than 2 v. using a single pin, one of three settings can be selected. using two pins, one of nine settings can be selected. table 5. multi-mode pin configuration pin tied to value low (logic low) < 0.8 vdc open (n/c) no connection high (logic high) > 2.0 vdc resistor to sgnd set by resistor value figure 8. pin-strap and resistor setting examples resistor settings: this method allows a greater range of adjustability when connecti ng a finite value resistor (in a specified range) between the multi-mode pin and sgnd. standard 1% resistor values are used, and only every fourth e96 resistor value is used so the device can reliably recognize the value of resistance connected to the pin while eliminating the error associated with the resistor accuracy. up to 31 unique selections are available using a single resistor. i 2 c/smbus method: almost any zl2006 function can be configured via the i 2 c/smbus interface using standard pmbus commands. additionally, any value that has been configured using the pin-strap or resistor setting methods can also be re-configured and/or verified via the i 2 c/smbus. see application note an33 for more details. the smbus device address and vout_max are the only parameters that must be set by external pins. all other device parameters can be set via the i 2 c/smbus. the device address is set using the sa0 and sa1 pins. vout_max is determined as 10% greater than the voltage set by the v0 and v1 pins.
zl2006 14 fn6850.1 december 15, 2010 5. power conversion functional description 5.1 internal bias regulators and input supply connections the zl2006 employs two internal low dropout (ldo) regulators to supply bias voltages for internal circuitry, allowing it to operate from a single input supply. the internal bias regulators are as follows: vr: the vr ldo provides a regulated 5 v bias supply for the mosfet driver circuits. it is powered from the vdd pin. a 4.7 f filter capacitor is required at the vr pin. v25: the v25 ldo provides a regulated 2.5 v bias supply for the main controller circuitry. it is powered from an internal 5v node. a 10 f filter capacitor is required at the v25 pin. when the input supply (vdd) is higher than 5.5 v, the vr pin should not be connected to any other pins. it should only have a filter capacitor attached as shown in figure 9. due to the dropout voltage associated with the vr bias regulator, the vdd pin must be connected to the vr pin for designs operating from a supply below 5.5 v. figure 9 illustrates the required connections for both cases. figure 9. input supply connections note : the internal bias regulators are not designed to be outputs for powering other circuitry. do not attach external loads to any of these pins. the multi-mode pins may be connected to the v25 pin for logic high settings. 5.2 high-side driver boost circuit the gate drive voltage for the high-side mosfet driver is generated by a floating bootstrap capacitor, cb (see figure 6). when the lower mosfet (ql) is turned on, the sw node is pulled to ground and the capacitor is charged from the internal vr bias regulator through diode db. when ql turns off and the upper mosfet (qh) turns on, the sw node is pulled up to v dd and the voltage on the bootstrap capacitor is boosted approximately 5 v above v dd to provide the necessary voltage to power the high-side driver. a schottky diode should be used for db to help maximize the high-side drive supply voltage. 5.3 output voltage selection 5.3.1 standard mode the output voltage may be set to any voltage between 0.6 v and 5.0 v provided that the input voltage is higher than the desired output voltage by an amount sufficient to prevent the device from exceeding its maximum duty cycle specification. using the pin-strap method, v out can be set to any of nine standard voltages as shown in table 6. table 6. pin-strap output voltage settings v0 low open high v1 low 0.6 v 0.8 v 1.0 v open 1.2 v 1.5 v 1.8 v high 2.5 v 3.3 v 5.0 v the resistor setting method can be used to set the output voltage to levels not available in table 6. resistors r0 and r1 are selected to produce a specific voltage between 0.6 v and 5.0 v in 10 mv steps. resistor r1 provides a coarse setting and resistor r0 provides a fine adjustment, thus eliminating the additional errors associated with using two 1% resistors (this typically adds approx 1.4% error).
zl2006 15 fn6850.1 december 15, 2010 to set v out using resistors, follow the steps below to calculate an index value and then use table 7 to select the resistor that corresponds to the calculated index value as follows: 1. calculate index1: index1 = 4 x v out (v out in 10 mv steps) 2. round the result down to the nearest whole number. 3. select the value of r1 from table 7 using the index1 rounded value from step 2. 4. calculate index0: index0 = 100 x v out ? (25 x index1) 5. select the value of r0 from table 7 using the index0 value from step 4. table 7. resistors for setting output voltage index r0 or r1 index r0 or r1 0 10 k 13 34.8 k 1 11 k 14 38.3 k 2 12.1 k 15 42.2 k 3 13.3 k 16 46.4 k 4 14.7 k 17 51.1 k 5 16.2 k 18 56.2 k 6 17.8 k 19 61.9 k 7 19.6 k 20 68.1 k 8 21.5 k 21 75 k 9 23.7 k 22 82.5 k 10 26.1 k 23 90.9 k 11 28.7 k 24 100 k 12 31.6 k example from figure 10: for v out = 1.33 v, index1 = 4 x 1.33 v = 5.32; from table 7, r1 = 16.2 k ? index0 = (100 x 1.33 v) ? (25 x 5) = 8; from table 7, r0 = 21.5 k ? the output voltage can be determined from the r0 (index0) and r1 (index1) values using the following equation: 100 ) 1 25 ( 0 index index v out + = 5.3.2 smbus mode the output voltage may be set to any value between 0.6 v and 5.0 v using a pmbus command over the i 2 c/smbus interface. see application note an33 for details. figure 10. output voltage resistor setting example 5.3.3 pola voltage trim mode the output voltage mapping can be changed to match the voltage setting equations for pola and dosa standard modules. the standard method for adjusting the output voltage for a pola module is defined by the following equation: ? ? = k v v v k r out set 43 . 1 69 . 0 69 . 0 10 the resistor, r set , is external to the pola module. see figure 11. figure 11. output voltage setting on pola module
zl2006 16 fn6850.1 december 15, 2010 to stay compatible with this existing method for adjusting the output voltage, the module manufacturer should add a 10k ? resistor on the module as shown in figure 12. now, the same r set used for an analog pola module will provide the same output voltage when using a digital pola module based on the zl2006. zl2006 10 k ? pola module rset v1 v0 110 k ? figure 12. r set on a pola module the pola mode is activated through pin-strap by connecting a 110 k ? resistor on v0 to sgnd. the v1 pin is then used to adjust the output voltage as shown in table 8. table 8. pola mode v out settings (r0 = 110 k ? , r1 = r set + 10 k ? ) v out r set in series with 10k ? resistor v out r set in series with 10k ? resistor 0.700 v 162 k 0.991 v 21.5 k 1.000 v 19.6 k 1.100 v 16.2 k 1.158 v 13.3 k 1.200 v 12.1 k 1.250 v 9.09 k 1.500 v 7.50 k 1.669 v 5.62 k 1.800 v 4.64 k 2.295 v 2.87 k 2.506 v 2.37 k 3.300 v 1.21 k 5.000 v 0.162 k 5.3.4 dosa voltage trim mode on a dosa module, the v out setting follows this equation: v v r out set 69 . 0 6900 ? = to maintain dosa compatibility, the same scheme is used as with a pola module except the 10 k ? resistor is replaced with a 8.66 k ? resistor as shown in figure 13. figure 13. r set on a dosa module the dosa mode v out settings are listed in table 9. table 9. dosa mode v out settings (r0 = 110 k ? , r1 = r set + 8.66 k ? ) v out r set in series with 8.66k ? resistor v out r set in series with 8.66k ? resistor 0.700 v 162 k
zl2006 17 fn6850.1 december 15, 2010 5.4 start-up procedure the zl2006 follows a specific internal start-up procedure after power is applied to the vdd pin. table 10 describes the start-up sequence. if the device is to be synchronized to an external clock source, the clock frequency must be stable prior to asserting the en pin. the device requires approximately 5-10 ms to check for specific values stored in its internal memo ry. if the user has stored values in memory, those values will be loaded. the device will then check the status of all multi-mode pins and load the values associated with the pin settings. once this process is completed, the device is ready to accept commands via the i 2 c/smbus interface and the device is ready to be enabled. once enabled, the device requires approximately 2 ms before its output voltage may be allowed to start its ramp-up process. if a soft- start delay period less than 2 ms has been configured (using dly pins or pmbus commands), the device will default to a 2 ms delay period. if a delay period greater than 2 ms is configured, the device will wait for the configured delay period prior to starting to ramp its output. after the delay period has expired, the output will begin to ramp towards its target voltage according to the pre-configured soft-start ramp time that has been set using the ss pin. it should be noted that if the en pin is tied to vdd, the device will still require approx 5-10 ms before the output can begin its ramp-up as described in table 10 below. 5.5 soft start delay and ramp times it may be necessary to set a delay from when an enable signal is received until the output voltage starts to ramp to its target value. in addition, the designer may wish to precisely set the time required for v out to ramp to its target value after the delay period has expired. these features may be used as part of an overall inrush current management strategy or to precisely control how fast a load ic is turned on. the zl2006 gives the system designer several options for precisely and independently controlling bot h the delay and ramp time periods. the soft-start delay period begins when the en pin is asserted and ends when the delay time expires. the soft-start delay period is set using the dly (0,1) pins. precise ramp delay timing reduces the delay time variations but is only available when the appropriate bit in the misc_config register has been set. please refer to application note an33 for details. the soft-start ramp timer enables a precisely controlled ramp to the nominal v out value that begins once the delay period has expired. the ramp-up is guaranteed monotonic and its slope may be precisely set using the ss pin. the soft start delay and ramp times can be set to standard values according to table 11 and table 12 respectively. table 10. zl2006 start-up sequence step # step name description time duration 1 power applied input voltage is applied to the zl2006?s vdd pin depends on input supply ramp time 2 internal memory check the device will check for values stored in its internal memory. this step is also performed after a restore command. approx 5-10 ms (device will ignore an enable signal or pmbus traffic during this period) 3 multi-mode pin check the device loads values configured by the multi-mode pins. 4 device ready the device is ready to accept an enable signal. ? 5 pre-ramp delay the device requires approximately 2 ms following an enable signal and prior to ramping its output. additional pre-ramp delay may be configured using the delay pins. approximately 2 ms
zl2006 18 fn6850.1 december 15, 2010 table 11. soft start delay settings dly0 low open high dly1 low 0 ms 1 1 ms 1 2 ms open 5 ms 10 ms 20 ms high 50 ms 100 ms 200 ms note: 1. when the device is set to 0 ms or 1 ms delay, it will begin its ramp up after the internal circuitr y has initialized (approx. 2 ms). table 12. soft start ramp settings ss ramp time low 0 ms 2 open 5 ms high 10 ms note: 2. when the device is set to 0 ms ramp, it will attempt to ramp as fast as the external load capacitance and loop settings will allow. it is generally recommended to set the soft-start ramp to a value greater than 500 s to prevent inadvertent fault conditions due to excessive inrush current. if the desired soft start delay and ramp times are not one of the values listed in table 11 and table 12, the times can be set to a custom value by connecting a resistor from the dly0 or ss pin to sgnd using the appropriate resistor value from table 13. the value of this resistor is measured upon start-up or restore and will not change if the resistor is varied after power has been applied to the zl2006. see figure 14 for typical connections using resistors. ss dly0 dly1 figure 14. dly and ss pin resistor connections table 13. dly and ss resistor settings dly or ss r dly or r ss dly or ss r dly or r ss 0 ms 2 10 k note : do not connect a resistor to the dly1 pin. this pin is not utilized for setting soft-start delay times. connecting an external resistor to this pin may cause conflicts with other device settings. the soft start delay and ramp times can also be set to custom values via the i 2 c/smbus interface. when the ss delay time is set to 0 ms, the device will begin its ramp-up after the internal circuitry has initialized (approx. 2 ms). when the soft-start ramp period is set to 0 ms, the output will ramp up as quickly as the output load capacitance and loop settings will allow. it is generally recommended to set the soft-start ramp to a value greater than 500 s to prevent inadvertent fault conditions due to excessive inrush current. 5.6 power good the zl2006 provides a power good (pg) signal that indicates the output voltage is within a specified tolerance of its target le vel and no fault condition exists. by default, the pg pin will assert if the output is within -10%/+15% of the target voltage. these limits and the polarity of the pin may be changed via the i 2 c/smbus interface. see application note an33 for details. a pg delay period is defined as the time from when all conditions within the zl2006 for asserting pg are met to when the pg pin is actually asserted. this feature is commonly used instead of using an external reset controller to control external digital logic. by default, the zl2006 pg delay is set equal to the soft-start ramp time setting. therefore, if the soft-start ramp time is set to 10 ms, the pg delay will be set to 10 ms. the pg delay may be set independently of the soft-start ramp using the i 2 c/smbus as described in application note an33.
zl2006 19 fn6850.1 december 15, 2010 5.7 switching frequency and pll the zl2006 incorporates an internal phase-locked loop (pll) to clock the internal circuitry. the pll can be driven by an external clock source connected to the sync pin. when using the internal oscillator, the sync pin can be configured as a clock source for other zilker labs devices. the sync pin is a unique pin that can perform multiple functions depending on how it is configured. the cfg pin is used to select the operating mode of the sync pin as shown in table 14. figure 15 illustrates the typical connections for each mode. table 14. sync pin function selection cfg pin sync pin function low sync is configured as an input open auto detect mode high sync is configured as an output f sw = 400 khz configuration a: sync output when the sync pin is configured as an output (cfg pin is tied high), the device will run from its internal oscillator and will drive the resulting internal oscillator signal (preset to 400 khz) onto the sync pin so other devices can be synchronized to it. the sync pin will not be checked for an incoming clock signal while in this mode. configuration b: sync input when the sync pin is configured as an input (cfg pin is tied low), the device will automatically check for a clock signal on the sync pin each time en is asserted. the zl2006?s oscillator will then synchronize with the rising edge of the external clock. the incoming clock signal must be in the range of 200 khz to 1.4 mhz and must be stable when the enable pin is asserted. the clock signal must also exhibit the necessary performance requirements (see table 3). in the event of a loss of the external clock signal, the output voltage may show transient over/undershoot. if this happens, the zl2006 will automatically switch to its internal oscillator an d switch at a frequency close to the previous incoming frequency. configuration c: sync auto detect when the sync pin is configured in auto detect mode (cfg pin is left open), the device will automatically check for a clock signal on the sync pin after enable is asserted. if a clock signal is present, the zl2006?s oscillator will then synchronize the rising edge of the external clock. refer to sync input description. if no incoming clock signal is present, the zl2006 will configure the switching frequency according to the state of the sync pin as listed in table 15. in this mode, the zl2006 will only read the sync pin connection during the start-up sequence. changes to sync pin connections will not affect f sw until the power (vdd) is cycled off and on. table 15. switching frequency selection sync pin frequency low 200 khz open 400 khz high 1 mhz resistor see table 16 if the user wishes to run the zl2006 at a frequency not listed in table 15, the switching frequency can be set using an external resistor, r sync , connected between sync and sgnd using table 16.
zl2006 20 fn6850.1 december 15, 2010 table 16. r sync resistor values r sync f sw r sync f sw 10 k ? 200 khz 26.1 k ? 533 khz 11 k ? 222 khz 28.7 k ? 571 khz 12.1 k ? 242 khz 31.6 k ? 615 khz 13.3 k ? 267 khz 34.8 k ? 727 khz 14.7 k ? 296 khz 38.3 k ? 800 khz 16.2 k ? 320 khz 46.4 k ? 889 khz 17.8 k ? 364 khz 51.1 k ? 1000 khz 19.6 k ? 400 khz 56.2 k ? 1143 khz 21.5 k ? 421 khz 68.1 k ? 1333 khz 23.7 k ? 471 khz the switching frequency can also be set to any value between 200 khz and 1.33 mhz using the i 2 c/smbus interface. the available frequencies below 1.4 mhz are defined by f sw = 8 mhz/n, where the whole number n is 6 n 40. see application note an33 for details. if a value other than f sw = 8 mhz/n is entered using a pmbus command, the internal circuitry will select the valid switching frequency value that is closest to the entered value. for example, if 810 khz is entered, the device will select 800 khz (n=10). when multiple zilker labs devices are used together, connecting the sync pins together will force all devices to synchronize with each other. the cfg pin of one device must set its sync pin as an output and the remaining devices must have their sync pins set as auto detect. note : the switching frequency read back using the appropriate pmbus command will differ slightly from the selected values in table 16. the difference is due to hardware quantization. 5.8 power train component selection the zl2006 is a synchronous buck converter that uses external mosfets, inductor and capacitors to perform the power conversion process. the proper selection of the external components is critical for optimized performance. to select the appropriate external components for the desired performance goals, the power supply requirements listed in table 17 must be known. figure 15. sync pin configurations
zl2006 21 fn6850.1 december 15, 2010 table 17. power supply requirements parameter range example value input voltage (v in ) 3.0 ? 14.0 v 12 v output voltage (v out ) 0.6 ? 5.0 v 1.2 v output current (i out ) 0 to ~25 a 20 a output voltage ripple (v orip ) < 3% of v out 1% of v out output load step (i ostep ) < io 50% of i o output load step rate ? 10 a/s output deviation due to load step ? 50 mv maximum pcb temp. 120c 85c desired efficiency ? 85% other considerations various optimize for small size 5.8.1 design goal trade-offs the design of the buck power stage requires several compromises among size, efficiency, and cost. the inductor core loss increases w ith frequency, so there is a trade-off between a small output filter made possible by a higher switching fre quency and getting better power supply efficiency. size can be decreased by increasing the switching frequency at the expense of efficiency. cost can be minimized by using through- hole inductors and capacitors; however these components are physically large. to start the design, select a switching frequency based on table 18. this frequency is a starting point and may be adjusted as the design progresses. table 18. circuit design considerations frequency range efficiency circuit size 200?400 khz highest larger 400?800 khz moderate smaller 800 khz ? 1.4 mhz lower smallest 5.8.2 inductor selection the output inductor selection process must include several trade-offs. a high inductance value will result in a low ripple current (i opp ), which will reduce output capacitance and produce a low output ripple voltage, but may also compromise output transient load performance. therefore, a balance must be struck between output ripple and optimal load transient performance. a good starting point is to select the output inductor ripple equal to the expected load transient step magnitude (i ostep ): ostep opp i i = now the output inductance can be calculated using the following equation, where v inm is the maximum input voltage: opp inm out out out i fsw v v v l ? ? ? ? ? ? ? ? ? = 1 the average inductor current is equal to the maximum output current. the peak inductor current (i lpk ) is calculated using the following equation where i out is the maximum output current: 2 opp out lpk i i i + = select an inductor rated for the average dc current with a peak current rati ng above the peak current computed above. in over-current or short-circuit conditions, the inductor may have currents greater than 2x the normal maximum rated output current. it is desirable to use an inductor that still provides some inductance to protect the load and the mosfets from damaging currents in this situation. once an inductor is selected, the dcr and core losses in the inductor are calculate d. use the dcr specified in the inductor manufacturer?s datasheet.
zl2006 22 fn6850.1 december 15, 2010 2 lrms ldcr i dcr p = i lrms is given by () 12 2 2 opp out lrms i i i + = where i out is the maximum output current. next, calculate the core loss of the selected inductor. since this calculation is specific to each inductor and manufacturer, refer to the chosen inductor datasheet. add the core loss and the esr loss and compare the total loss to the maximum power dissipation recommendation in the inductor datasheet. 5.8.3 output capacitor selection several trade-offs must also be considered when selecting an output capacitor. low esr values are needed to have a small output deviation during transient load steps (v osag ) and low output voltage ripple (v orip ). however, capacitors with low esr, such as semi-stable (x5r and x7r) dielectric ceramic capacitors, also have relatively low capacitance values. many designs can use a combination of high capacitance devices and low esr devices in parallel. for high ripple currents, a low capacitance value can cause a significant amount of output voltage ripple. likewise, in high transient lo ad steps, a relatively large amount of capacitance is needed to minimize the output voltage deviation while the inductor current ramps up or down to the new steady state output current value. as a starting point, apportion one-half of the output ripple voltage to the capacitor esr and the other half to capacitance, as shown in the following equations: 2 8 orip sw opp out v f i c = opp orip i v esr = 2 use these values to make an initial capacitor selection, using a single capacitor or several capacitors in parallel. after a capacitor has been selected, the resulting output voltage ripple can be calculated using the following equation: out sw opp opp orip c f i esr i v + = 8 because each part of this equation was made to be less than or equal to half of the allowed output ripple voltage, the v orip should be less than the desired maximum output ripple. 5.8.4 input capacitor it is highly recommended that dedicated input capacitors be used in any point-of-load design, even when the supply is powered from a heavily filtered 5 or 12 v ?bulk? supply from an off-line power supply. this is because of the high rms ripple current that is drawn by the buck converter topology. this ripple (i cinrms ) can be determined from the following equation: ) 1 ( d d i i out cinrms ? = without capacitive filtering near the power supply circuit, this current would flow through the supply bus and return planes, coupling noise into other system circuitry. the input capacitors should be rated at 1.2x the ripple current calculated above to avoid overheating of the capacitors due to the high ripple current, which can cause premature failure. ceramic capacitors with x7r or x5r dielectric with low esr and 1.1x the maximum expected input voltage are recommended. 5.8.5 bootstrap capacitor selection the high-side driver boost circuit utilizes an external schottky diode (d b ) and an external bootstrap capacitor (c b ) to supply sufficient gate drive for the high-side mosfet driver. d b should be a 20 ma, 30 v schottky diode or equivalent device and c b should be a 1 f ceramic type rated for at least 6.3v.
zl2006 23 fn6850.1 december 15, 2010 5.8.6 ql selection the bottom mosfet should be selected primarily based on the device?s r ds(on) and secondarily based on its gate charge. to choose ql, use the following equation and allow 2?5% of the output power to be dissipated in the r ds(on) of ql (lower output voltages and higher step-down ratios will be closer to 5%): out out ql i v p = 05 . 0 calculate the rms current in ql as follows: d i i lrms botrms ? = 1 calculate the desired maximum r ds(on) as follows: () 2 ) ( botrms ql on ds i p r = note that the r ds(on) given in the manufacturer?s datasheet is measured at 25c. the actual r ds(on) in the end-use application will be much higher. for example, a vishay si7114 mosfet with a junction temperature of 125c has an r ds(on) that is 1.4 times higher than the value at 25c. select a candidate mosfet, and calculate the required gate drive current as follows: g sw g q f i = keep in mind that the total allowed gate drive current for both qh and ql is 80 ma. mosfets with lower r ds(on) tend to have higher gate charge requirements, which increases the current and resulting power required to turn them on and off. since the mosfet gate drive circuits are integrated in the zl2006, this power is dissipated in the zl2006 according to the following equation: inm g sw ql v q f p = 5.8.7 qh selection in addition to the r ds(on) loss and gate charge loss, qh also has switching loss. the procedure to select qh is similar to the procedure for ql. first, assign 2?5% of the output power to be dissipated in the r ds(on) of qh using the equation for ql above. as was done with ql, calculate the rms current as follows: d i i lrms toprms = calculate a starting r ds(on) as follows, in this example using 5%: out out qh i v p = 05 . 0 () 2 ) ( toprms qh on ds i p r = select a mosfet and calculate the resulting gate drive current. verify that the combined gate drive current from ql and qh does not exceed 80 ma. next, calculate the switching time using: gdr g sw i q t = where q g is the gate charge of the selected qh and i gdr is the peak gate drive current available from the zl2006. although the zl2006 has a typical gate drive current of 3 a, use the minimum guaranteed current of 2 a for a conservative design. using the calculated switching time, calculate the switching power loss in qh using: sw out sw inm swtop f i t v p = the total power dissipated by qh is given by the following equation: swtop qh qhtot p p p + = 5.8.8 mosfet thermal check once the power dissipations for qh and ql have been calculated, the mosfets junction temperature can be estimated. using the junction-to-case thermal resistance (r th ) given in the mosfet manufacturer?s datasheet and the expected maximum printed circuit board temperature, calculate the junction temperature as follows: ( ) th q pcb j r p t t + = max
zl2006 24 fn6850.1 december 15, 2010 5.8.9 current sensing components once the current sense method has been selected (refer to section 5.9, ?current limit threshold selection,?), the components are selected as follows. when using the inductor dcr sensing method, the user must also select an r/c network comprised of r1 and cl (see figure 16). figure 16. dcr current sensing for the voltage across c l to reflect the voltage across the dcr of the inductor, the time constant of the inductor must match the time constant of the rc network. that is: dcr l c r l dcr l rc = ? = 1 / l , use the average of th e nominal value and the minimum value. include the effects of tolerance, dc bias and switching frequency on the inductance when determining the minimum value of l . use the typical value for dcr . the value of r 1 should be as small as feasible and no greater than 5 k ? for best signal-to-noise ratio. the designer should make sure the resistor package size is appropriate for the power dissipated and include this loss in efficiency calculations. in calculating the minimum value of r 1 , the average voltage across c l (which is the average i out ? dcr product) is small and can be neglected. therefore, the minimum value of r 1 may be approximated by the following equation: ()() p pkg r out out in p v d v v d r ? ? ? + ? = ? ? ? max 1 2 2 max min 1 1 , where p r1pkg- max is the maximum power dissipation specification for the resistor package and p is the derating factor for the same parameter (eg.: p r1pkg- max = 0.0625w for 0603 package, p = 50% @ 85c). once r 1- min has been calculated, solve for the maximum value of c l from dcr r l c l ? = ? ? min 1 max and choose the next-lowest readily available value (eg.: for c l- max = 1.86uf, c l = 1.5uf is a good choice). then substitute the chosen value into the same equation and re-calculate the value of r 1 . choose the 1% resistor standard value closest to this re-calculated value of r 1 . the error due to the mismatch of the two time constants is % 100 1 1 ? ? ? ? ? ? ? ? ? ? ? ? = avg l l dcr c r the value of r 2 should be simply five times that of r 1 : 1 2 5 r r ? = for the r ds(on) current sensing method, the external low side mosfet will act as the sensing element as indicated in figure 17. 5.9 current limit threshold selection it is recommended that the user include a current limiting mechanism in their design to protect the power supply from damage and prevent excessive current from being drawn from the input supply in the event that the output is shorted to ground or an overload condition is imposed on the output. current limiting is accomplished by sensing the current through the circuit during a portion of the duty cycle. output current sensing can be accomplished by measuring the voltage across a series resistive sensing element according to the following equation: sense lim lim r i v = where: i lim is the desired maximum current that should flow in the circuit r sense is the resistance of the sensing element v lim is the voltage across the sensing element at the point the circuit should start limiting the output current.
zl2006 25 fn6850.1 december 15, 2010 the zl2006 supports ?lossless? current sensing by measuring the voltage across a resistive element that is already present in the circuit. this eliminates additional efficiency losses incurred by devices that must use an additional series resistance in the circuit. to set the current limit threshold, the user must first select a current sensing method. the zl2006 incorporates two methods for current sensing, synchronous mosfet r ds(on) sensing and inductor dc resistance (dcr) sensing; figure 17 shows a simplified schematic for each method. the current sensing method can be selected using the ilim1 pin using table 19. the ilim0 pin must have a finite resistor connected to ground in order for table 19 to be valid. if no resistor is connected between ilim0 and ground, the default method is mosfet r ds(on) sensing. the current sensing method can be modified via the i 2 c/smbus interface. please refer to application note an33 for details. in addition to selecting the current sensing method, the zl2006 gives the power supply designer several choices for the fault response during over or under current condition. the user can select the number of violations allowed before declaring fault, a blanking time and the action taken when a fault is detected. table 19. resistor settings for current sensing ilim0 pin 1 ilim1 pin current limiting configuration number of violations allowed 2 comments r ilim0 low ground-referenced, r ds(on) , sensing blanking time: 672 ns 5 best for low duty cycle and low f sw r ilim0 open output-referenced, down-slope sensing (inductor dcr sensing) blanking time: 352 ns 5 best for low duty cycle and high f sw r ilim0 high output-referenced, up-slope sensing (inductor dcr sensing) blanking time: 352 ns 5 best for high duty cycle resistor depends on resistor value used; see table 20 notes : 1. 10 k ? < r ilim0 < 100 k ? 2. the number of violations allowed prior to issuing a fault response. figure 17. current sensing methods
zl2006 26 fn6850.1 december 15, 2010 table 20. resistor configured current sensing method selection r ilimi1 current sensing method number of violations allowed 1 10 k ? ground-referenced, r ds(on) , sensing best for low duty cycle and low f sw blanking time: 672 ns 1 11 k ? 3 12.1 k ? 5 13.3 k ? 7 14.7 k ? 9 16.2 k ? 11 17.8 k ? 13 19.6 k ? 15 21.5 k ? output-referenced, down-slope sensing (inductor dcr sensing) best for low duty cycle and high f sw blanking time: 352 ns 1 23.7 k ? 3 26.1 k ? 5 28.7 k ? 7 31.6 k ? 9 34.8 k ? 11 38.3 k ? 13 42.2 k ? 15 46.4 k ? output-referenced, up-slope sensing (inductor dcr sensing) best for high duty cycle blanking time: 352 ns 1 51.1 k ? 3 56.2 k ? 5 61.9 k ? 7 68.1 k ? 9 75 k ? 11 82.5 k ? 13 90.9 k ? 15 notes : 1. the number of violations allowe d prior to issuing a fault response the blanking time represents the time when no current measurement is taken. this is to avoid taking a reading just after a current load step (less accurate due to potential ringing). it is a configurable parameter. table 19 includes default parameters for the number of violations and the blanking time using pin-strap. once the sensing method has been selected, the user must select the voltage threshold (vlim), the desired current limit threshold, and the resistance of the sensing element. the current limit threshold can be selected by simply connecting the ilim0 and ilim1 pins as shown in table 21. the ground-referenced sensing method is being used in this mode. table 21. current limit threshold voltage pin-strap settings ilim0 low open high ilim1 low 20 mv 30 mv 40 mv open 50 mv 60 mv 70 mv high 80 mv 90 mv 100 mv the threshold voltage can also be selected in 5 mv increments by connecting a resistor, r lim0 , between the ilim0 pin and ground according to table 22. this method is preferred if the user does not desire to use or does not have access to the i 2 c/smbus interface and the desired threshold value is contained in table 22. the current limit threshold can also be set to a custom value via the i 2 c/smbus interface. please refer to application note an33 for further details.
zl2006 27 fn6850.1 december 15, 2010 table 22. current limit threshold voltage resistor settings r lim0 v lim for rds v lim for dcr 10 k ? 0 mv 0 mv 11 k ? 5 mv 2.5 mv 12.1 k ? 10 mv 5 mv 13.3 k ? 15 mv 7.5 mv 14.7 k ? 20 mv 10 mv 16.2 k ? 25 mv 12.5 mv 17.8 k ? 30 mv 15 mv 19.6 k ? 35 mv 17.5 mv 21.5 k ? 40 mv 20 mv 23.7 k ? 45 mv 22.5 mv 26.1 k ? 50 mv 25 mv 28.7 k ? 55 mv 27.5 mv 31.6 k ? 60 mv 30 mv 34.8 k ? 65 mv 32.5 mv 38.3 k ? 70 mv 35 mv 46.4 k ? 80 mv 40 mv 51.1 k ? 85 mv 42.5 mv 56.2 k ? 90 mv 45 mv 68.1 k ? 100 mv 50 mv 82.5 k ? 110 mv 55 mv 100 k ? 120 mv 60 mv 5.10 loop compensation the zl2006 operates as a voltage-mode synchronous buck controller with a fixed frequency pwm scheme. although the zl2006 uses a digital control loop, it operates much like a traditional analog pwm controller. figure 18 is a simplified block diagram of the zl2006 control loop, which differs from an analog control loop only by the constants in the pwm and compensation blocks. as in the analog controller case, the compensation block compares the output voltage to the desired voltage reference and compensation zeroes are added to keep the loop stable. the resulting integrated error signal is used to drive the pwm logic, converting the error signal to a duty cycle to drive the external mosfets. figure 18. control loop block diagram in the zl2006, the compensation zeros are set by configuring the fc0 and fc1 pins or via the i 2 c/smbus interface once the user has calculated the required settings. this method eliminates the inaccuracies due to the component tolerances associated with using extern al resistors and capacitors required with traditional analog controllers. utilizing the loop compensation settings shown in table 23 will yield a conservative crossover frequency at a fixed fraction of the switching frequency (f sw /20) and 60 of phase margin. step 1: using the following equation, calculate the resonant frequency of the lc filter, f n . c l f n = 2 1 step 2: based on table 23 determine the fc0 settings. step 3: calculate the esr zero frequency (f zesr ). crc f zesr 2 1 = step 4: based on table 23 determine the fc1 setting.
zl2006 28 fn6850.1 december 15, 2010 5.11 adaptive compensation loop compensation can be a time-consuming process, forcing the designer to accommodate design trade-offs related to performance and stability across a wide range of operating conditions. the zl2006 offers an adaptive compensation mode th at enables the user to increase the stability over a wider range of loading conditions by automatically adapting the loop compensation coefficients fo r changes in load current. setting the loop compensation coefficients through the i 2 c/smbus interface allows for a second set of coefficients to be stored in the device in order to utilize adaptive loop compensation. this algorithm uses the two sets of compensation coefficients to determine optimal compensation settings as the output load changes. please refer to application note an33 for further details on pmbus commands. table 23. pin-strap settings for loop compensation fc0 range fc0 pin fc1 range fc1 pin f sw /60 < f n < f sw /30 high f zesr > f sw /10 high f sw /10 > f zesr > f sw /30 open reserved low f sw /120 < f n < f sw /60 open f zesr > f sw /10 high f sw /10 > f zesr > f sw /30 open reserved low f sw /240 < f n < f sw /120 low f zesr > f sw /10 high f sw /10 > f zesr > f sw /30 open reserved low 5.12 non-linear response (nlr) settings the zl2006 incorporates a non-linear response (nlr) loop that decreases the response time and the output voltage deviation in the event of a sudden output load current step. the nlr loop incorporates a secondary error signal processing path that bypasses the primary error loop when the output begins to transition outside of the standard regulation limits. this scheme results in a higher equivalent loop bandwidth than what is possible using a traditional linear loop. when a load current step function imposed on the output causes the output voltage to drop below the lower regulation limit, the nlr circuitry will force a positive correction signal that will turn on the upper mosfet and quickly force the output to increase. conversely, a negative load step (i.e. removing a large load current) will cause the nlr circuitry to force a negative correction signal that will turn on the lower mosfet and quickly force the output to decrease. the zl2006 has been pre-configured with appropriate nlr settings that correspond to the loop compensation settings in table 23. please refer to application note an32 for more details regarding nlr settings. 5.13 efficiency optimized driver dead-time control the zl2006 utilizes a closed loop algorithm to optimize the dead-time applied between the gate drive signals for the top and bottom fets. in a synchronous buck converter, the mosfet drive circuitry must be designed such that the top and bottom mosfets are never in the conducting state at the same time. potentially damaging currents flow in the circuit if both top and bottom mosfets are simultaneously on for periods of time exceeding a few nanoseconds. conversely, long periods of time in which both mosfets are off reduce overall circuit efficiency by allowing current to flow in their parasitic body diodes. it is therefore advantageous to minimize this dead- time to provide optimum circuit efficiency. in the first order model of a buck converter, the duty cycle is determined by the equation: in out v v d however, non-idealities exist that cause the real duty cycle to extend beyond the ideal. dead-time is one of
zl2006 29 fn6850.1 december 15, 2010 those non-idealities that can be manipulated to improve efficiency. the zl2006 has an internal algorithm that constantly adjusts dead-time non-overlap to minimize duty cycle, thus maximizing e fficiency. this circuit will null out dead-time differences due to component variation, temperature, and loading effects. this algorithm is independent of application circuit parameters such as mosfet type, gate driver delays, rise and fall times and circuit layout. in addition, it does not require drive or mosfet voltage or current waveform measurements. 5.14 adaptive diode emulation most power converters use synchronous rectification to optimize efficiency over a wide range of input and output conditions. however, at light loads the synchronous mosfet will typically sink current and introduce additional energy losses associated with higher peak inductor currents, resulting in reduced efficiency. adaptive diode emulation mode turns off the low-side fet gate drive at low load currents to prevent the inductor current from going negative, reducing the energy losses and increasing overall efficiency. diode emulation is available to single-phase devices or current sharing devices that have dropped all but a single phase. note: the overall bandwidth of the device may be reduced when in diode emulation mode. it is recommended that diode emulation is disabled prior to applying significant load steps. 5.15 adaptive frequency control since switching losses contribute to the efficiency of the power converter, reducing th e switching frequency will reduce the switching losses and increase efficiency. the zl2006 includes adaptive frequency control mode, which effectively reduces the observed switching frequency as the load decreases. adaptive frequency mode is enabled by setting bit 0 of misc_config to 1 and is only available while the device is operating within adaptive diode emulation mode. as the load current is decreased, diode emulation mode decreases the gl on-time to prevent negative inductor current from flowing. as the load is decreased further, the gh pulse width will begin to decrease while maintaining the programmed frequency, f prog (set by the freq_switch command). once the gh pulse width (d) reaches 50% of the nominal duty cycle, d nom (determined by vin and vout), the switching frequency will start to decrease according to the following equation: if then f sw (d) = otherwise f sw (d) = f prog this is illustrated in figure 19. due to quantizing effects inside the ic, th e zl2006 will decrease its frequency in steps between f sw and f min . the quantity and magnitude of the steps will depend on the difference between f sw and f min as well as the frequency range. it should be noted that adaptive frequency mode is not available for current sharing groups and is not allowed when the device is placed in auto-detect mode and a clock source is present on the sync pin, or if the device is outputting a clock signal on its sync pin. figure 19. adaptive frequency min nom min sw f d d f f + ? ? ? ? ? ? ? ) ( 2 2 nom d d < switching frequency
zl2006 30 fn6850.1 december 15, 2010 6. power management functional description 6.1 input undervoltage lockout the input undervoltage lockout (uvlo) prevents the zl2006 from operating when the input falls below a preset threshold, indicating the input supply is out of its specified range. the uvlo threshold (v uvlo ) can be set between 2.85 v and 16 v using the uvlo pin. the simplest implementation is to connect the uvlo pin as shown in table 24. if the uvlo pin is left unconnected, the uvlo threshold will default to 4.5 v. table 24. uvlo threshold settings pin setting uvlo threshold low 3 v open 4.5 v high 10.8 v if the desired uvlo threshold is not one of the listed choices, the user can configure a threshold between 2.85 v and 16 v by connecting a resistor between the uvlo pin and sgnd by selecting the appropriate resistor from table 25. table 25. uvlo resistor values r uvlo uvlo r uvlo uvlo 17.8 k ? 2.85 v 46.4 k ? 7.42 v 19.6 k ? 3.14 v 51.1 k ? 8.18 v 21.5 k ? 3.44 v 56.2 k ? 8.99 v 23.7 k ? 3.79 v 61.9 k ? 9.9 v 26.1 k ? 4.18 v 68.1 k ? 10.9 v 28.7 k ? 4.59 v 75 k ? 12 v 31.6 k ? 5.06 v 82.5 k ? 13.2 v 34.8 k ? 5.57 v 90.9 k ? 14.54 v 38.3 k ? 6.13 v 100 k ? 16 v 42.2 k ? 6.75 v the uvlo voltage can also be set to any value between 2.85 v and 16 v via the i 2 c/smbus interface. once an input undervoltage fault condition occurs, the device can respond in a number of ways as follows: 1. continue operating w ithout interruption. 2. continue operating for a given delay period, followed by shutdown if the fault still exists. the device will remain in shutdown until instructed to restart. 3. initiate an immediate shutdown until the fault has been cleared. the user can select a specific number of retry attempts. the default response from a uvlo fault is an immediate shutdown of the device. the device will continuously check for the presence of the fault condition. if the fault condition is no longer present, the zl2006 will be re-enabled. please refer to application note an33 for details on how to configure the uvlo threshold or to select specific uvlo fault response options via the i 2 c/smbus interface. 6.2 output overvoltage protection the zl2006 offers an internal output overvoltage protection circuit that can be used to protect sensitive load circuitry from being subjected to a voltage higher than its prescribed limits. a hardware comparator is used to compare the actual output voltage (seen at the vsen pin) to a threshold set to 15% higher than the target output voltage (the default setting). if the vsen voltage exceeds this threshold, the pg pin will de- assert and the device can then respond in a number of ways as follows: 1. initiate an immediate shutdown until the fault has been cleared. the user can select a specific number of retry attempts. 2. turn off the high-side mosfet and turn on the low-side mosfet. the low-side mosfet remains on until the device attempts a restart. the default response from an overvoltage fault is to immediately shut down. the device will continuously check for the presence of the fault condition, and when the fault condition no longer exists the device will be re-enabled.
zl2006 31 fn6850.1 december 15, 2010 for continuous overvoltage protection when operating from an external clock, the only allowed response is an immediate shutdown. please refer to application note an33 for details on how to select specific overvoltage fault response options via i 2 c/smbus. 6.3 output pre-bias protection an output pre-bias condition ex ists when an externally applied voltage is present on a power supply?s output before the power supply?s control ic is enabled. certain applications require that the converter not be allowed to sink current during start up if a pre-bias condition exists at the output. the zl2006 provides pre-bias protection by sampling the output voltage prior to initiating an output ramp. if a pre-bias voltage lower than the target voltage exists after the pre-configured delay period has expired, the target voltage is set to match the existing pre-bias voltage and both drivers are enabled. the output voltage is then ramped to the final regulation value at the ramp rate set by the ss pin. the actual time the output will take to ramp from the pre-bias voltage to the target voltage will vary depending on the pre-bias voltage but the total time elapsed from when the delay period expires and when the output reaches its target value will match the pre- configured ramp time. see figure 20. if a pre-bias voltage higher than the target voltage exists after the pre-configured delay period has expired, the target voltage is set to match the existing pre-bias voltage and both drivers are enabled with a pwm duty cycle that would ideally create the pre-bias voltage. figure 20. output responses to pre-bias voltages once the pre-configured soft-start ramp period has expired, the pg pin will be asserted (assuming the pre- bias voltage is not higher than the overvoltage limit). the pwm will then adjust its duty cycle to match the original target voltage and the output will ramp down to the pre-configured output voltage. if a pre-bias voltage higher than the overvoltage limit exists, the device will not initiate a turn-on sequence and will declare an overvoltage fault condition to exist. in this case, the device will respond based on the output overvoltage fault response method that has been selected. see section 6.2 ?output overvoltage protection,? for response options due to an overvoltage condition. pre-bias protection is not offered for current sharing groups that also have tracking enabled.
zl2006 32 fn6850.1 december 15, 2010 6.4 output overcurrent protection the zl2006 can protect the power supply from damage if the output is shorted to ground or if an overload condition is imposed on the output. once the current limit threshold has been selected (see section 5.9 ?current limit threshold selection?), the user may determine the desired course of action in response to the fault condition. the following overcurrent protection response options are available: 1. initiate a shutdown and attempt to restart an infinite number of times with a preset delay period between attempts. 2. initiate a shutdown and attempt to restart a preset number of times with a preset delay period between attempts. 3. continue operating for a given delay period, followed by shutdown if the fault still exists. 4. continue operating through the fault (this could result in permanent damage to the power supply). 5. initiate an immediate shutdown. the default response from an overcurrent fault is an immediate shutdown of the device. the device will continuously check for the presence of the fault condition, and if the fault c ondition no longer exists the device will be re-enabled. please refer to application note an33 for details on how to select specific overcurrent fault response options via i 2 c/smbus. 6.5 thermal overload protection the zl2006 includes an on-ch ip thermal sensor that continuously measures the internal temperature of the die and shuts down the device when the temperature exceeds the preset limit. the default temperature limit is set to 125c in the factory, but the user may set the limit to a different value if desired. see application note an33 for details. note that setting a higher thermal limit via the i 2 c/smbus interface may result in permanent damage to the device. once the device has been disabled due to an internal temperature fault, the user may select one of several fault response options as follows: 1. initiate a shutdown and attempt to restart an infinite number of times with a preset delay period between attempts. 2. initiate a shutdown and attempt to restart a preset number of times with a preset delay period between attempts. 3. continue operating for a given delay period, followed by shutdown if the fault still exists. 4. continue operating through the fault (this could result in permanent damage to the power supply). 5. initiate an immediate shutdown. if the user has configured the device to restart, the device will wait the preset delay period (if configured to do so) and will then check the device temperature. if the temperature has dropped below a threshold that is approx 15c lower than the selected temperature fault limit, the device will attempt to re-start. if the temperature still exceeds the fa ult limit the device will wait the preset delay period and retry again. the default response from a temperature fault is an immediate shutdown of the device. the device will continuously check for the fault condition, and once the fault has cleared the zl2006 will be re-enabled. please refer to application note an33 for details on how to select specific temperature fault response options via i 2 c/smbus. 6.6 voltage tracking numerous high performance systems place stringent demands on the order in which the power supply voltages are turned on. this is particularly true when powering fpgas, asics, and other advanced processor devices that require multiple supply voltages to power a single die. in most cases, the i/o interface operates at a higher voltage than the core and therefore the core supply voltage must not exceed the i/o supply voltage according to the manufacturers' specifications. voltage tracking protects these sensitive ics by limiting the differential voltage between multiple power supplies during the power-up and power down sequence. the zl2006 integrates a lossless tracking scheme that allows its output to track a voltage that is applied to the vtrk pin with no external components required. the vtrk pin is an analog input that, when tracking mode is enabled, configures the voltage applied to the vtrk pin to act as a reference for the device?s output regulation.
zl2006 33 fn6850.1 december 15, 2010 the zl2006 offers two mode of tracking as follows: 1. coincident . this mode configures the zl2006 to ramp its output voltage at the same rate as the voltage applied to the vtrk pin. 2. ratiometric . this mode configures the zl2006 to ramp its output voltage at a rate that is a percentage of the voltage applied to the vtrk pin. the default setting is 50%, but an external resistor string may be used to configure a different tracking ratio. figure 21 illustrates the typical connection and the two tracking modes. the master zl2006 device in a tracking group is defined as the device that has the highest target output voltage within the group. this master device will control the ramp rate of all tracking devices and is not configured for tracking mode. a delay of at least 10 ms must be configured into the master device using the dly(0,1) pins, and the user may also configure a specific ramp rate using the ss pin. any device that is configured for tracking mode will ignore its soft-start delay and ramp time settings (ss and dly(0,1) pins) and its output will take on the turn-on/turn-off characteristics of the reference voltage present at the vtrk pin. all of the enable pins in the tracking group must be connected together and driven by a single logic source. tracking is configured via the i 2 c/smbus interface by using the track_config pmbus command. please refer to application note an33 for more information on configuring tracking mode using pmbus. it should be noted that current sharing groups that are also configured to track another voltage do not offer pre-bias protection; a minimum load should therefore be enforced to avoid the output voltage from being held up by an outside force. additionally, a device set up for tracking must have both alternate ramp control and precise ramp-up delay disabled. v out v out time coincident ratiometric v trk v in v out q1 q2 l1 c1 gh gl sw zl2006 vtrk v trk v out v out time v trk figure 21. tracking modes 6.7 voltage margining the zl2006 offers a simple means to vary its output higher or lower than its nominal voltage setting in order to determine whether the load device is capable of operating over its specified supply voltage range. the mgn command is set by driving the mgn pin or through the i 2 c/smbus interface. the mgn pin is a tri-level input that is c ontinuously monitored and can be driven directly by a processor i/o pin or other logic- level output.
zl2006 34 fn6850.1 december 15, 2010 the zl2006?s output will be forced higher than its nominal set point when the mgn command is set high, and the output will be forced lower than its nominal set point when the mgn command is set low. default margin limits of v nom 5% are pre- loaded in the factory, but the margin limits can be modified through the i 2 c/smbus interface to as high as v nom + 10% or as low as 0v, where v nom is the nominal output voltage set point determined by the v0 and v1 pins. a safety feature prevents the user from configuring the output voltage to exceed v nom + 10% under any conditions. the margin limits and the mgn command can both be set individually through the i 2 c/smbus interface. additionally, the transition rate between the nominal output voltage and either margin limit can be configured through the i 2 c interface. please refer to application note an33 for detailed instructions on modifying the margining configurations. 6.8 i 2 c/smbus communications the zl2006 provides an i 2 c/smbus digital interface that enables the user to configure all aspects of the device operation as well as monitor the input and output parameters. the zl2006 can be used with any standard 2-wire i 2 c host device. in addition, the device is compatible with smbus version 2.0 and includes an salrt line to help mitigate bandwidth limitations related to continuous fault monitoring. pull-up resistors are required on the i 2 c/smbus as specified in the smbus 2.0 specification. the zl2006 accepts most standard pmbus commands. when controlling the device with pmbus commands, it is recommended that the enable pin is tied to sgnd. 6.9 i 2 c/smbus device address selection when communicating with multiple smbus devices using the i 2 c/smbus interface, each device must have its own unique address so the host can distinguish between the devices. the device address can be set according to the pin-strap options listed in table 26. address values are right-justified. table 26. smbus device address selection sa0 low open high sa1 low 0x20 0x21 0x22 open 0x23 0x24 0x25 high 0x26 0x27 reserved if additional device addresses are required, a resistor can be connected to the sa0 pin according to table 27 to provide up to 25 uniq ue device addresses. in this case, the sa1 pin should be tied to sgnd. table 27. smbus address values r sa smbus address r sa smbus address 10 k 0x15 23.7 k if more than 25 unique device addresses are required or if other smbus address values are desired, both the sa0 and sa1 pins can be configured with a resistor to sgnd according to the following equation and table 28. smbus address = 25 x (sa1 index) + (sa0 index) (in decimal)
zl2006 35 fn6850.1 december 15, 2010 using this method, the user can theoretically configure up to 625 unique smbus addresses, however the smbus is inherently limited to 128 devices so attempting to configure an address higher than 128 (0x80) will cause the device address to repeat (i.e, attempting to configure a device address of 129 (0x81) would result in a device address of 1). therefore, the user should use index values 0-4 on the sa1 pin and the full range of index values on the sa0 pin, which will provide 125 device address combinations. table 28. smbus address index values r sa sa0 or sa1 index r sa sa0 or sa1 index 10 k 0 34.8 k 13 11 k 1 38.3 k 14 12.1 k 2 42.2 k 15 13.3 k 3 46.4 k 16 14.7 k 4 51.1 k 17 16.2 k 5 56.2 k 18 17.8 k 6 61.9 k 19 19.6 k 7 68.1 k 20 21.5 k 8 75 k 21 23.7 k 9 82.5 k 22 26.1 k 10 90.9 k 23 28.7 k 11 100 k 24 31.6 k 12 to determine the sa0 and sa 1 resistor values given an smbus address (in decimal), follow the steps below to calculate an index value and then use table 28 to select the resistor that corresponds to the calculated index value as follows: 1. calculate sa1 index: sa1 index = address (in decimal) 25 2. round the result down to the nearest whole number. 3. select the value of r1 from table 28 using the sa1 index rounded value from step 2. 4. calculate sa0 index: sa0 index = address ? (25 x sa1 index) 5. select the value of r0 from table 28 using the sa0 index value from step 4. 6.10 digital-dc bus the digital-dc (ddc) communications bus is used to communicate between zilker labs digital-dc devices. this dedicated bus provides the communication channel between devices for features such as sequencing, fault spreading, and current sharing. the ddc pin on all digital-dc devices in an application should be connected together. a pull-up resistor is required on the ddc bus in order to guarantee the rise time as follows: rise time = r pu * c load 1 s, where r pu is the ddc bus pull-up resistance and c load is the bus loading. the pull-up resistor may be tied to vr or to an external 3.3 v or 5 v supply as long as this voltage is present pr ior to or during device power-up. as rules of thumb, each device connected to the ddc bus presents approx 10 pf of capacitive loading, and each inch of fr4 pcb trace introduces approx 2 pf. the ideal design will use a central pull-up resistor that is well-matched to the total load capacitance. in power module applications, the user should consider whether to place the pull-up resistor on the module or on the pcb of the end application. the minimum pull-up resistance should be limited to a value that enables any device to assert the bus to a voltage that will ensure a logic 0 (typically 0.8 v at the device monitoring point) given the pull-up voltage (5 v if tied to vr) and the pull-down current capability of the zl2006 (nominally 4 ma). 6.11 phase spreading when multiple point of load converters share a common dc input supply, it is desirable to adjust the clock phase offset of each device such that not all devices start to switch simultaneously. setting each converter to start its switching cycle at a different point in time can dramatically reduce input capacitance requirements and efficiency losses. since the peak current drawn from the input supply is effectively spread out over a period of time, the peak current drawn at any given moment is reduced and the power losses proportional to the i rms 2 are reduced dramatically.
zl2006 36 fn6850.1 december 15, 2010 in order to enable phase spreading, all converters must be synchronized to the same switching clock. the cfg pin is used to set the configuration of the sync pin for each device as described in section 5.7 ?switching frequency and pll? on page 19. selecting the phase offset for the device is accomplished by selecting a device address according to the following equation: phase offset = device address x 45 for example: ? a device address of 0x00 or 0x20 would configure no phase offset ? a device address of 0x01 or 0x21 would configure 45 of phase offset ? a device address of 0x02 or 0x22 would configure 90 of phase offset the phase offset of each device may also be set to any value between 0 and 360 in 22.5 increments via the i 2 c/smbus interface. refer to application note an33 for further details. 6.12 output sequencing a group of digital-dc devices may be configured to power up in a predetermined sequence. this feature is especially useful when powering advanced processors, fpgas, and asics that require one supply to reach its operating voltage prior to another supply reaching its operating voltage in order to avoid latch-up from occurring. multi-device sequencing can be achieved by configuring each device through the i 2 c/smbus interface or by using zilker labs patented autonomous sequencing mode. autonomous sequencing mode configures sequencing by using events transmitted between devices over the ddc bus. this mode is not available on current sharing rails. the sequencing order is determined using each device?s smbus address. using autonomous sequencing mode (configured using the cfg pin), the devices must be assigned sequential smbus addresses with no missing addresses in the chain. this mode will also constrain each device to have a phase offset according to its smbus address as described in section 6.11 ?phase spreading?. the sequencing group will turn on in order starting with the device with the lowest smbus address and will continue through to turn on each device in the address chain until all devices connected have been turned on. when turning off, the device with the highest smbus address will turn off first followed in reverse order by the other devices in the group. sequencing is configured by connecting a resistor from the cfg pin to ground as described in table 29. the cfg pin is also used to set the configuration of the sync pin as well as to determine the sequencing method and order. please refer to 5.7 ?switching frequency and pll? for more details on the operating parameters of the sync pin. multiple device sequencing may also be achieved by issuing pmbus commands to assign the preceding device in the sequencing chain as well as the device that will follow in the sequencing chain. this method places fewer restrictions on smbus address (no need of sequential address) and also allows the user to assign any phase offset to any device irrespective of its smbus device address. the enable pins of all de vices in a sequencing group must be tied together and driven high to initiate a sequenced turn-on of the group. enable must be driven low to initiate a sequenced turnoff of the group. refer to application note an33 for details on sequencing via the i 2 c/smbus interface. 6.13 fault spreading digital dc devices can be configured to broadcast a fault event over the ddc bus to the other devices in the group. when a non-destructive fault occurs and the device is configured to shut down on a fault, the device will shut down and broadcast the fault event over the ddc bus. the other devices on the ddc bus will shut down together if configured to do so, and will attempt to re-start in their prescribed order if configured to do so.
zl2006 37 fn6850.1 december 15, 2010 6.14 temperature monitoring using the xtemp pin the zl2006 supports measurement of an external device temperature using either a thermal diode integrated in a processor, fpga or asic, or using a discrete diode-connected 2n3904 npn transistor. figure 22 illustrates the typical connections required. figure 22. external temperature monitoring 6.15 active current sharing paralleling multiple zl2006 devices can be used to increase the output current capability of a single power rail. by connecting the ddc pins of each device together and configuring the devices as a current sharing rail, the units will share the current equally within a few percent. figure 23 illustrates a typical connection for three devices. figure 23. current sharing group the zl2006 uses a low-bandwidth digital current sharing technique to balance the unequal device output loading by aligning the load lines of member devices to a reference device. table 29. cfg pin configurations for sequencing r cfg sync pin config sequencing configuration 10 k input sequencing is disabled 11 k auto detect 12.1 k output 14.7 k input the zl2006 is configured as the first device in a nested sequencing group. turn on order is based on the device smbus address. 16.2 k auto detect 17.8 k output 21.5 k input the zl2006 is configured as a last device in a nested sequencing group. turn on order is based on the device smbus address. 23.7 k auto detect 26.1 k output 31.6 k input the zl2006 is configured as the middle device in a nested sequencing group. turn on order is based on the device smbus address. 34.8 k auto detect 38.3 k output
zl2006 38 fn6850.1 december 15, 2010 droop resistance is used to add artificial resistance in the output voltage path to control the slope of the load line curve, calibrating out the physical parasitic mismatches due to power train components and pcb layout. upon system start-up, the device with the lowest member position as selected in ishare_config is defined as the reference device. the remaining devices are members. the reference device broadcasts its current over the ddc bus. the members use the reference current information to trim their voltages (v member ) to balance the current loading of each device in the system. figure 24. active current sharing figure 24 shows that, for lo ad lines with identical slopes, the member voltage is increased towards the reference voltage which closes the gap between the inductor currents. the relation between reference and member current and voltage is given by the following equation: () member reference out member i i r v v ? + = where r is the value of the droop resistance. the ishare_config command is used to configure the device for active current sharing. the default setting is a stand-alone non-current sharing device. a current sharing rail can be part of a system sequencing group. for fault configuration, the current share rail is configured in a quasi-redundant mode. in this mode, when a member device fails, the remaining members will continue to operate and attempt to maintain regulation. of the remaining devices, the device with the lowest member position will become the reference. if fault spreading is enabled, the current share rail failure is not broadcast until the entire current share rail fails. up to eight (8) devices can be configured in a given current sharing rail. 6.16 phase adding/dropping the zl2006 allows multiple power converters to be connected in parallel to supply higher load currents than can be addressed using a single-phase design. in doing so, the power converter is optimized at a load current range that requires all phases to be operational. during periods of light loading, it may be beneficial to disable one or more phases in order to eliminate the current drain and switching losses associated with those phases, resulting in higher efficiency. the zl2006 offers the ability to add and drop phases using a simple command in response to an observed load current change, enabling the system to continuously optimize overall efficiency across a wide load range. all phases in a current share rail are considered active prior to th e current sharing rail ramp to power-good. phases can be dropped after power-good is reached. any member of the current sharing rail can be dropped. if the reference device is dropped, the remaining active device with the lowest member position will become the new reference. additionally, any change to the number of members of a current sharing rail will pr ecipitate autonomous phase distribution within the rail where all active phases realign their phase position based on their order within the number of active members. if the members of a current sharing rail are forced to shut down due to an observed fault, all members of the rail will attempt to re-start simultaneously after the fault has cleared. v out
zl2006 39 fn6850.1 december 15, 2010 6.17 monitoring via i 2 c/smbus a system controller can monitor a wide variety of different zl2006 system parameters through the i 2 c/smbus interface. the device can monitor for fault conditions by monitoring the salrt pin, which will be pulled low when any number of pre-configured fault conditions occur. the device can also be monitored continuously for any number of power conversion parameters including but not limited to the following: ? input voltage / output voltage ? output current ? internal junction temperature ? temperature of an external device ? switching frequency ? duty cycle the pmbus host should respond to salrt as follows: 1. zl device pulls salrt low 2. pmbus host detects that salrt is now low, performs transmission with alert response address to find which zl device is pulling salrt low. 3. pmbus host talks to the zl device that has pulled salrt low. the actions that the host performs are up to the system designer. if multiple devices are faulting, salrt will still be low after doing the above steps and will require transmission with the alert response address repeatedly until all faults are cleared. please refer to application note an33 for details on how to monitor specific parameters via the i 2 c/smbus interface. 6.18 snapshot? parameter capture the zl2006 offers a special mechanism that enables the user to capture parametric data during normal operation or following a fault. the snapshot functionality is enabled by setting bit 1 of misc_config to 1. the snapshot feature enabl es the user to read the parameters listed in table 30 via a block read transfer through the smbus. this can be done during normal operation, although it should be noted that reading the 22 bytes will occupy the smbus for some time. table 30. snapshot parameters byte description format 31:22 reserved linear 21:20 vin linear 19:18 vout vout linear 17:16 iout,avg linear 15:14 iout,peak linear 13:12 duty cycle linear 11:10 internal temp linear 9:8 external temp linear 7:6 fsw linear 5 vout status byte 4 iout status byte 3 input status byte 2 temp status byte 1 cml status byte 0 mfr specific status byte the snapshot_control command enables the user to store the snapshot parameters to flash memory in response to a pending fa ult as well as to read the stored data from flash memory after a fault has occurred. table 31 describes the usage of this command. automatic writes to flash memory following a fault are triggered when any fault threshold level is exceeded, provided that the specific fault?s response is to shut down (writing to flash memory is not allowed if the device is configured to re-try following the specific fault condition). it should also be noted that the device?s v dd voltage must be maintained during the time when the device is writing the data to flash memory; a process that requires between 700- 1400 s depending on whether the data is set up for a block write. undesirable results may be observed if the device?s v dd supply drops below 3.0 v during this process.
zl2006 40 fn6850.1 december 15, 2010 table 31. snapshot_control command data value description 1 copies current snapsh ot values from flash memory to ram for immediate access using snapshot command. 2 writes current snapshot values to flash memory. only available when device is disabled. in the event that the de vice experiences a fault and power is lost, the user can extract the last snapshot parameters stored during the fault by writing a 1 to snapshot_control (transfers data from flash memory to ram) and then issuing a snapshot command (reads data from ram via smbus). 6.19 non-volatile memory and device security features the zl2006 has internal non-volatile memory where user configurations are stored. integrated security measures ensure that the user can only restore the device to a level that has been made available to them. refer to section 5.4 ? start-up procedure ?, for details on how the device loads stored values from internal memory during start-up. during the initialization process, the zl2006 checks for stored values contained in its internal non-volatile memory. the zl2006 offers two internal memory storage units that are accessible by the user as follows: 1. default store : a power supply module manufacturer may want to protect the module from damage by preventing the user from being able to modify certain values that are related to the physical construction of the module. in this case, the module manufacturer would use the default store and would allow the user to restore the device to its default setting but would restrict the user from restoring the device to the factory settings. 2. user store : the manufacturer of a piece of equipment may want to provide the ability to modify certain power supply settings while still protecting the equipment from modifying values that can lead to a system level fault. the equipment manufacturer would use the user store to achieve this goal. please refer to application note an33 for details on how to set specific security measures via the i 2 c/smbus interface.
zl2006 41 fn6850.1 december 15, 2010 7. package dimensions notes: 1. dimensions and tolerances conform to asme y14.5m ? 1994. 2. all dim ensions are in m illim eters, is in degrees. 3. n is the total num ber of term inals. 4. dim ension b applies to m etalized term inal and is m easured between 0.15 and 0.33 m m from term inal tip. if the term inal has the optional radius on the other end of the term inal, the dim ension b should not be m easured in that radius area. 5. nd and ne refer to the num ber of term inals on each d and e side respectively. 6. max package warpage is 0.05 mm. 7. maximum allowable burrs is 0.076 mm in all directions. 8. pin # 1 id on top will be laser m arked. 9. bilateral coplanarity zone applies to the exposed heat sink slug as well as the terminals. 10. this drawing conform s to jedec registered outline mo- 220. 5 9 nd 4.20 4.10 4.00 e2 4.20 4.10 4.00 d2 4 0.30 0.25 0.18 b 0.65 0.60 0.55 l 5 9 ne 3 36 n 0.50 bsc e 6.0 bsc e 6.0 bsc d 0.20 min k 2 12 - 0 0.20 ref a3 0.05 0.02 0.00 a1 0.90 0.85 0.80 a max. nom. min. n o t e dimensions s y m b o l 5 9 nd 4.20 4.10 4.00 e2 4.20 4.10 4.00 d2 4 0.30 0.25 0.18 b 0.65 0.60 0.55 l 5 9 ne 3 36 n 0.50 bsc e 6.0 bsc e 6.0 bsc d 0.20 min k 2 12 - 0 0.20 ref a3 0.05 0.02 0.00 a1 0.90 0.85 0.80 a max. nom. min. n o t e dimensions s y m b o l
zl2006 42 fn6850.1 december 15, 2010 8. ordering information product designator shipping option t = tape & reel 100 pcs t1 = tape & reel 1000 pcs contact factory for other options lead finish f = lead-free matte tin firmware revision alpha character ambient temperature range l = -40 to +85 c package designator a = qfn package 9. related tools and documentation the following application support documents and tools are available to help simplify your design. item description zl2006evk2 evaluation kit ? zl2006ev2, usb adapter board, gui software an33 application note: pmbus command set an34 application note: current sharing an35 application note: digital-dc control loop compensation
zl2006 43 fn6850.1 december 15, 2010 10. revision history rev. # description date 1.0 initial release. march 2008 1.1 soft start delay setting changed from 1 ms to 2 ms on page 4. soft start duration accuracy changed fro m -0/+4ms to -0.25/+4ms on page 4. clarified frequency selection on page 20. added detail to r1, r2 selection on page 24. corrected number of allowed violations in table 19 on page 25. formatting changes on page 26. removed ddc address references in sections 6.10, 6.12, and 6.15. april 2008 1.2 updated ordering information. improved readability in curre nt sharing description. may 2008 1.3 added comment that a device set up for tracking must have both alternate ramp control and precise ramp-up delay disabled on page 33. clarified ddc pull-up requirement on page 35. june 2008 1.4 corrected ilim values in table 22. added note in table 3 and figure 17 that v out must be less than 4.0 v for dcr current sensing. corrected frequency values in table 16. updated adaptive frequency control description on page 30. august 2008 1.5 added v lim for dcr sensing to table 22. added equation for selecting v out in section 5.3. added procedure for determining sa0, sa1 resistor values in section 6.9. fn6850.0 assigned file number fn6850 to datasheet as th is will be the first release with an intersil file number. replaced header and footer with intersil header and footer. updated disclaimer information to read ?i ntersil and it?s subsidiaries including zilker labs, inc.? no changes to datasheet content february 2009 fn6850.1 stamped ?not recommended for new designs recommended replacement part zl6100? august 9, 2010 added footnote ?limits established by characterization and not production tested.? to parameters throughout spec table october 12, 2010 added following statement to disclaimer on page 45: ?this product is subject to a license from power one, inc. rela ted to digital power technology as set forth in u.s. patent no. 7,000,125 and other related patents owned by power one, inc. these license rights do not extend to stand-alone pol regulators unless a royalty is paid to power one, inc.? removed note ?limits established by characterization and not production tested.? from electrical specifications table and replaced with standard note in min max columns, ?compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.? november 30, 2010
zl2006 44 fn6850.1 december 15, 2010 notes:
zl2006 45 fn6850.1 december 15, 2010 zilker labs, inc. 4301 westbank drive building a-100 austin, tx 78746 tel: 512-382-8300 fax: 512-382-8329 ? 2008, zilker labs, inc. all rights reserved. zilker labs, digital-dc, snapshot, and the zilker labs logo are trademarks of zilker labs, inc. all other products or brand names mentioned herein are trademarks of their respective holders. this document contains information on a product under development. specifications are subject to change with- out notice. pricing, specifications and availability are su bject to change without notice. please see www.zilker- labs.com for updated information. this product is not intended for use in connection with any high-risk activity, including without limitation, air travel, life critical medi cal operations, nuclear facilitie s or equipment, or the like. the reference designs contained in this document ar e for reference and example purposes only. the refer- ence designs are provided "as is" and "with all faults" and intersil corporation and it?s subsidiaries including zilker labs, inc. disclaims all warranties, whether express or implied. zilker labs shall not be liable for any damages, whether direct, indirect, consequential (including loss of profits), or otherwise, resulting from the reference designs or any use thereof. any use of such reference designs is at your own risk and you agre e to indemnify intersil corporation and it?s subsidiaries including zilker labs, inc. for any damages resulting from such use. this product is subject to a license from power one, inc. related to digital power technology as set forth in u.s. patent no. 7,000,125 and other related patents owned by po wer one, inc. these license rights do not extend to stand-alone pol regulators unless a roya lty is paid to power one, inc.

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