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quad precision, high speed operational amplifier op467 rev. * information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 3C20 analog devices, inc. all rights reserved. features high slew rate: 170 v/s wide bandwidth: 28 mhz fast settling time: <200 ns to 0.01% low offset voltage: <500 v unity-gain stable low voltage operation: 5 v to 15 v low supply current: <10 ma drives capacitive loads applications high speed image display drivers high frequency active filters fast instrumentation amplifiers high speed detectors integrators photo diode preamps general description the op467 is a quad, high speed, precision operational amplifier. it offers the performance of a high speed op amp combined with the advantages of a precision op amp in a single package. the op467 is an ideal choice for applications where, traditionally, more than one op amp was used to achieve this level of speed and precision. the internal compensation of the op467 ensures stable unity- gain operation, and it can drive large capacitive loads without oscillation. with a gain bandwidth product of 28 mhz driving a 30 pf load, output slew rate is 170 v/s, and settling time to 0.01% in less than 200 ns, the op467 provides excellent dynamic accuracy in high speed data acquisition systems. the channel-to-channel separation is typically 60 db at 10 mhz. the dc performance of the op467 includes less than 0.5 mv of offset, a voltage noise density below 6 nv/hz, and a total supply current under 10 ma. the common-mode rejection ratio (cmrr) is typically 85 db. the power supply rejection ratio (psrr) is typically 107 db. psrr is maintained to better than 40 db with input frequencies as high as 1 mhz. the low offset and drift plus high speed and low noise make the op467 usable in applications such as high speed detectors and instrumentation. the op467 is specified for operation from 5 v to 15 v over the extended industrial temperature range (?40c to +85c) and is available in a 14-lead pdip, a 14-lead cerdip, a 16-lead soic, and a 20-terminal lcc. contact your local sales office for the mil-std-883 data sheet and availability. pin configurations out a 1 ?in a 2 +in a 3 v+ 4 out d 14 ?in d +in d v? +in c ?in c out c 13 12 11 +in b 5 10 ?in b 6 9 out b 7 8 op467 00302-001 + + + + figure 1. 14-lead cerdip (y suffix) and 14-lead pdip (p suffix) 00302-002 out a ?in a +in a v+ out d ?in d +in d v? +in c ?in c out c nc +in b ?in b out b nc op467 1 2 3 4 16 15 14 13 5 12 6 11 7 10 8 9 nc = no connect 00302-003 19 20 123 +in d v? +in c nc nc op467 4 5 6 7 8 18 17 16 15 14 13 12 11 10 9 (top view) nc = no connect out a out d ?in a ?i n d +in a v+ +in b nc nc nc out b out c ?in b ?in c nc figure 2. 16-lead soic (s suffix) figure 3. 20-terminal lcc (rc suffix) 00302-004 ?in +in v+ v? out figure 4. simplified schematic
op467 rev. i | page 2 of 20 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? pin configurations ........................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? electrical characteristics ............................................................. 3 ? wafer test limits .......................................................................... 5 ? absolute maximum ratings ............................................................ 6 ? thermal resistance ...................................................................... 6 ? dice characteristics ..................................................................... 6 ? esd caution .................................................................................. 6 ? typical performance characteristics ............................................. 7 ? applications information .............................................................. 13 ? output short-circuit performance .......................................... 13 ? unused amplifiers ..................................................................... 13 ? pcb layout considerations ...................................................... 13 ? grounding ................................................................................... 13 ? power supply considerations ................................................... 13 ? signal considerations ................................................................ 13 ? phase reversal ............................................................................ 14 ? saturation recovery time ......................................................... 14 ? high speed instrumentation amplifier .................................. 14 ? 2 mhz biquad band-pass filter ............................................... 15 ? fast i-to-v converter ................................................................ 16 ? op467 spice marco-model ..................................................... 17 ? outline dimensions ....................................................................... 19 ? ordering guide .......................................................................... 20 ? revision history 4/10rev. h to rev. i deleted endnote 2 from table 1 .................................................... 3 8/09rev. g to rev. h changes to table 4 ............................................................................ 6 4/09rev. f to rev. g changes to power supply considerations section ..................... 13 5/07rev. e to rev. f updated format .................................................................. universal changes to general description .................................................... 1 changes to table 1 ............................................................................ 3 changes to table 2 ............................................................................ 4 changes to table 3 ............................................................................ 5 updated outline dimensions ....................................................... 19 changes to ordering guide .......................................................... 20 3/04rev. d to rev. e changes to tpc 1 .............................................................................. 5 changes to ordering guide ............................................................. 4 updated outline dimensions ....................................................... 16 4/01rev. c to rev. d footnote added to power supply ..................................................... 2 footnote added to max ratings ...................................................... 4 edits to power supply considerations section ........................... 11
op467 rev. i | page 3 of 20 specifications electrical characteristics @ v s = 15.0 v, t a = 25c, unless otherwise noted. table 1. parameter symbol conditions min typ max unit input characteristics offset voltage v os 0.2 0.5 mv ?40c t a +85c 1 mv input bias current i b v cm = 0 v 150 600 na v cm = 0 v, ?40c t a +85c 150 700 na input offset current i os v cm = 0 v 10 100 na v cm = 0 v, ?40c t a +85c 10 150 na common-mode rejection cmr v cm = 12 v 80 90 db cmr v cm = 12 v, ?40c t a +85c 80 88 db large signal voltage gain a vo r l = 2 k 83 86 db r l = 2 k, ?40c t a +85c 77.5 db offset voltage drift v os /t 3.5 v/c bias current drift i b /t 0.2 pa/c long-term offset voltage drift 1 v os /t 750 v output characteristics output voltage swing v o r l = 2 k 13.0 13.5 v r l = 2 k, ?40c t a +85c 12.9 13.12 v power supply power supply rejection ratio psrr 4.5 v v s 18 v 96 120 db ?40c t a +85c 86 115 db supply current i sy v o = 0 v 8 10 ma v o = 0 v, ?40c t a +85c 13 ma supply voltage range v s 4.5 18 v dynamic performance gain bandwidth product gbp a v = +1, c l = 30 pf 28 mhz slew rate sr v in = 10 v step, r l = 2 k, c l = 30 pf a v = +1 125 170 v/s a v = ?1 350 v/s full-power bandwidth bw v in = 10 v step 2.7 mhz settling time t s to 0.01%, v in = 10 v step 200 ns phase margin 0 45 degrees input capacitance common mode 2.0 pf differential 1.0 pf noise performance voltage noise e n p-p f = 0.1 hz to 10 hz 0.15 v p-p voltage noise density e n f = 1 khz 6 nv/hz current noise density i n f = 1 khz 0.8 pa/hz 1 long-term offset voltage drift is guaranteed by 1000 hrs. life test performed on thr ee independent wafer lots at 125c, with a n ltpd of 1.3.
op467 rev. * | page 4 of 20 @ v s = 5.0 v, t a = 25c, unless otherwise noted. table 2. parameter symbol conditions min typ max unit input characteristics offset voltage v os 0.3 0.5 mv ?40c t a +85c 1 mv input bias current i b v cm = 0 v 125 600 na v cm = 0 v, ?40c t a +85c 150 700 na input offset current i os v cm = 0 v 20 100 na v cm = 0 v, ?40c t a +85c 150 na common-mode rejection cmr v cm = 2.0 v 76 85 db cmr v cm = 2.0 v, ?40c t a +85c 76 80 db large signal voltage gain a vo r l = 2 k 80 83 db r l = 2 k, ?40c t a +85c 74 db offset voltage drift v os /t 3.5 v/c bias current drift i b /t 0.2 pa/c output characteristics output voltage swing v o r l = 2 k 3.0 3.5 v r l = 2 k, ?40c t a +85c 3.0 3.20 v power supply power supply rejection ratio psrr 4.5 v v s 5.5 v 92 107 db ?40c t a +85c 83 105 db supply current i sy v o = 0 v 8 10 ma v o = 0 v, ?40c t a +85c 12 ma dynamic performance gain bandwidth product gbp a v = +1 22 mhz slew rate sr v in = 5 v step, r l = 2 k, c l = 39 pf a v = +1 90 v/s a v = ?1 90 v/s full-power bandwidth bw v in = 5 v step 2.5 mhz settling time t s to 0.01%, v in = 5 v step 280 ns phase margin 0 45 degrees noise performance voltage noise e n p-p f = 0.1 hz to 10 hz 0.15 v p-p voltage noise density e n f = 1 khz 7 nv/hz current noise density i n f = 1 khz 0.8 pa/hz
op467 rev. * | page 5 of 20 wafer test limits 1 @ v s = 15.0 v, t a = 25c, unless otherwise noted. table 3. parameter symbol conditions limit unit offset voltage v os 0.5 mv max input bias current i b v cm = 0 v 600 na max input offset current i os v cm = 0 v 100 na max input voltage range 2 12 v min/max common-mode rejection ratio cmrr v cm = 12 v 80 db min power supply rejection ratio psrr v = 4.5 v to 18 v 96 db min large signal voltage gain a vo r l = 2 k 83 db min output voltage range v o r l = 2 k 13.0 v min supply current i sy v o = 0 v, r l = 10 ma max 1 electrical tests and wafer probe to the limits shown. due to va riations in assembly methods an d normal yield loss, yield after packaging is not gua ranteed for standard product dice. consult sales to negotiate specifications based on dice lot qualifications through sample lot assembly and testin g. 2 guaranteed by cmr test.
op467 rev. * | page 6 o f 20 absolute maximum ratings table 4. parameter 1 rating supply voltage 18 v input voltage 2 18 v differential input voltage 2 26 v output short-circuit duration limited storage temperature range 14-lead cerdip and 20-terminal lcc ?65c to +175c 14-lead pdip and 16-lead soic ?65c to +150c operating temperature range op467a ?55c to +125c op467g ?40c to +85c junction temperature range 14-lead cerdip and 20-terminal lcc ?65c to +175c 14-lead pdip and 16-lead soic ?65c to +150c lead temperature (soldering, 60 sec) 300c 1 absolute maximum ratings apply to both dice and packaged parts, unless otherwise noted. 2 for supply voltages less than 18 v, the absolute maximum input voltage is equal to the supply voltage. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 5. package type ja 1 jc unit 14-lead cerdip (y) 94 10 c/w 14-lead pdip (p) 76 33 c/w 16-lead soic (s) 88 23 c/w 20-terminal lcc (rc) 78 33 c/w 1 ja is specified for the worst-case conditions, that is, ja is specified for device in socket for cerdip, pdip, and lcc packages, and ja is specified for device soldered in circuit board for the soic package. dice characteristics 00302-005 1 2 3 4 5 67 89 10 +in c ?in c +in d ?in d ? in a + in a + in b ? in b v+ out d out a t c t b v? 11 12 13 14 ou ou figure 5. 0.111 inch 0.100 inch die size, 11,100 sq. mils, substrate connected to v+, 165 transistors esd caution
op467 rev. * | page 7 of 20 ?20 1k 10k 100k 1m 10m 100m frequency (hz) 00 typical performance characteristics 20 30 40 50 60 70 80 ?10 ?90 ?135 ?180 0 10 open-loop gain (db) phase shift (degrees) 302-006 v s = 15v r l = 1m ? c l = 30pf gain phase figure 6. open-loop gain, phase vs. frequency 40 60 80 ?20 0 20 closed-loop gain (db) 00302-007 10k 100k 1m 10m 100m frequency (hz) v s = 15v t a = 25c figure 7. closed-loop gain vs. frequency 00302-008 25 10 0 5 15 20 open-loop gain (v/mv) t a = +25c 0 5 10 15 20 supply voltage (v) t a = +125c t a = ?55c figure 8. open-loop gain vs. supply voltage 60 80 100 20 0 40 100 1k 10k 100k 1m impedance ( ? ) frequency (hz) 00302-009 v s = 15v t a = 25c a vcl = +100 a vcl = +10 a vcl = +1 figure 9. closed-loop outp ut impedance vs. frequency ?0.3 3.4 5.8 ?0.2 ?0.1 0.0 0.1 0.2 0.3 0 100k 1m 10m gain error (db) frequency (hz) 00302-010 v s = 5v v s = 15v figure 10. gain error vs. frequency 15 20 25 30 0 5 10 1k 10k 100k 1m 10m maximum output swing (v) frequency (hz) 00302-011 a vcl = +1 a vcl = ?1 v s = 15v t a = 25c r l = 2k ? figure 11. maximum v out swing vs. frequency
op467 rev. * | page 8 of 20 0 2 1k 10k 100k 1m 10m 00302-012 6 8 10 12 4 maximum output swing (v) frequency (hz) a vcl = ?1 a vcl = +1 v s = 5v t a = 25c r l = 2k ? figure 12. maximum v out swing vs. frequency 60 80 100 120 20 40 common-mode rejection (v) 0 1k 10k 100k 1m 10m 00302-013 frequency (hz) v s = 15v t a = 25c figure 13. common-mode rejection vs. frequency 60 80 100 120 20 40 power supply rejection (db) 0 100 1k 10k 100k 1m frequency (hz) 00302-014 v s = 15v t a = 25c figure 14. power-supply rejection vs. frequency 30 40 50 60 0 10 20 0 200 400 600 overshoot (%) load capacitance (pf) 00302-015 800 1000 1200 1400 1600 v s = 15v r l = 2k ? v vin = 100mv p-p a vcl = +1 a vcl = ?1 figure 15. small signal overshoot vs. load capacitance 30 40 50 60 0 10 20 0 200 400 600 overshoot (%) load capacitance (pf) 00302-016 800 1000 1200 1400 1600 v s = 15v r l = 2k ? v vin = 100mv p-p a vcl = +1 a vcl = ?1 figure 16. small signal overshoot vs. load capacitance 10 20 30 40 50 60 ?40 ?30 ?20 ?10 0 10k 100k 1m gain (db) frequency (hz) 00302-017 10m 100m v s = 15v 10000pf 1000pf 500pf 200pf c in = network analyzer figure 17. noninverting ga in vs. capacitive loads
op467 rev. * | page 9 of 20 ?100 ?90 100 1k 10k 100k 00302-018 1m 10m 100m ?50 ?40 ?30 ?20 ?10 0 ?80 ?70 ?60 channel separation (db) frequency (hz) v s = 15v 0 1 10 100 inp 00302-019 1k figure 18. channel separation vs. frequency 10 12 2 4 6 8 ut current noise density (pa/ hz) frequency (hz) 5v v s 15v figure 19. input current noise density vs. frequency 10 100 tage noise density (nv/ hz) 1.0 0.1 1 10 100 1k 10k vol frequency (hz) 00302-020 figure 20. voltage noise density vs. frequency 0 1 2 3 4 ?4 ?3 ?2 ?1 0 100 200 300 400 500 v out error (mv) time (ns) 00302-021 v s = 15v v in = 5v c l = 50pf figure 21. settling time, negative edge 0 1 2 3 4 ?4 ?3 ?2 ?1 0 100 200 300 400 500 v out error (mv) time (ns) 00302-022 v s = 15v v in = 5v c l = 50pf figure 22. settling time, positive edge 0 5 10 15 20 ?20 ?15 ?10 ?5 0 5 10 15 20 input voltage range (v) supply voltage (v) 00302-023 t a = 25c figure 23. input voltage range vs. supply voltage
op467 rev. * | page 10 of 20 00302-024 10k 100k 1m 10m 100m gain (db) ?10 10 20 30 40 0 50 frequency (hz) v s1 = 15v ?50 ?40 ?30 ?20 v s2 = 5v v s1 = 15v v s2 = 5v r l = 10k ? c l = 50pf figure 24. noninverting gain vs. supply voltage 10 12 14 4 6 8 output swing (v) 0 2 10 100 1k 00302-025 10k load resistance ( ? ) v s = 15v t a = 25c positive swing negative swing figure 25. output swin g vs. load resistance 4 5 1 2 3 output swing (v) 0 10 100 1k load resistance ( ? ) 00302-026 10k negative swing positive swing v s = 15v t a = 25c figure 26. output swin g vs. load resistance units input offset voltage (v os v) 00302-027 500 0 100 200 300 400 ?100 ?50 0 50 100 150 200 250 300 350 400 v s = 15v t a = 25c 1252 op amps figure 27. input offset voltage distribution units input offset voltage (v os v) 00302-028 500 0 100 200 300 400 ?100 ?50 0 50 100 150 200 250 300 350 400 v s = 5v t a = 25c 1252 op amps figure 28. input offset voltage distribution units tc v os (v/c) 00302-029 500 0 100 200 300 400 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 v s = 15v t a = 25c 1252 op amps figure 29. tc v os distribution
op467 rev. * | page 11 of 20 units tc v os (v/c) 00302-030 500 0 100 200 300 400 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 v s = 5v t a = 25c 1252 op amps ga 00302-031 40 27.0 ?75 ?50 ?25 0 25 50 75 100 125 figure 30. tc v os distribution phase margin (degrees) in bandwidth product (mhz) 60 45 50 55 29.0 27.5 28.0 28.5 temperature (c) gbw m v s = 5v r l = 2k ? figure 31. phase margin and ga in bandwidth vs. temperature slew rate (v/s ) 400 50 100 150 200 250 300 350 ?sr +sr temperature (c) 00302-032 0 ?75 ?50 ?25 0 25 50 75 100 125 v s = 5v r l = 2k ? a vcl =?1 figure 32. slew rate vs. temperature slew rate (v/s) temperature (c) 00302-033 400 0 50 100 150 200 250 300 350 ?75 ?50 ?25 0 25 50 75 100 125 ?sr +sr v s = 5v r l = 2k ? a vcl =+1 figure 33. slew rate vs. temperature slew rate (v/s) temperature (c) 00302-034 650 250 300 350 400 450 500 550 600 ?75 ?50 ?25 0 25 50 75 100 125 ?sr +sr v s = 15v r l = 2k ? a vcl =?1 figure 34. slew rate vs. temperature slew rate (v/s) temperature (c) 00302-035 400 0 50 100 150 200 250 300 350 ?75 ?50 ?25 0 25 50 75 100 125 ?sr +sr v s = 15v r l = 2k ? a vcl =+1 figure 35. slew rate vs. temperature
op467 utput step for 15v supply (v) 10 ?6 ?4 ?2 0 2 4 6 8 0.1% 0.1% 0.1% rev. * | page 12 of 20 o 00302-036 ?10 ?8 0 100 200 300 400 0.1% settling time (ns) o ?1 ?2 utput step for 5v supply (v) ?3 ?4 ?5 0 1 2 3 4 5 r f = 5k ? t a =25c figure 36. output step vs. settling time supply curren t (ma) 10 4 6 8 supply voltage (v) 00302-037 0 2 0 5 10 15 20 t a = +125c t a = +25c t a = ?55c figure 37. supply current vs. supply voltage input bias current (na) temperature (c) 00302-038 200 0 40 90 120 160 ?75 ?50 ?25 0 25 50 75 100 125 v s =15v figure 38. input bias current vs. temperature input offset current (na) temperature (c) 00302-039 25 0 5 10 15 20 ?75 ?50 ?25 0 25 50 75 100 125 v s =15v figure 39. input offset current vs. temperature
op467 rev. * | page 13 of 20 applications information output short-circuit performance to achieve a wide bandwidth and high slew rate, the op467 output is not short-circuit protected. shorting the output to ground or to the supplies may destroy the device. for safe operation, the output load current should be limited so that the junction temperature does not exceed the absolute maximum junction temperature. the maximum internal power dissipation can be calculated by ja d p = a j tt ? max where: t j and t a are junction and ambient temperatures, respectively. p d is device internal power dissipation. ja is the packaged device thermal resistance given in the data sheet. unused amplifiers it is recommended that any unused amplifiers in the quad package be connected as a unity-gain follower with a 1 k feedback resistor with noninverting input tied to the ground plain. pcb layout considerations satisfactory performance of a high speed op amp largely depends on a good pcb layout. to achieve the best dynamic performance, follow the high frequency layout technique. grounding a good ground plain is essential to achieve the optimum performance in high speed applications. it can significantly reduce the undesirable effects of ground loops and ir drops by providing a low impedance reference point. best results are obtained with a multilayer board design with one layer assigned to the ground plain. to maintain a continuous and low impedance ground, avoid running any traces on this layer. power supply considerations in high frequency circuits, devi ce lead length introduces an inductance in series with the circuit. this inductance, combined with stray capacitance, forms a high frequency resonance circuit. poles generated by these circuits cause gain peaking and additional phase shift, reducing the phase margin of the op amp and leading to an unstable operation. a practical solution to this problem is to reduce the resonance frequency low enough to take advantage of the power supply rejection of the amplifier. this is easily done by placing capacitors across the supply line and the ground plane as close as possible to the device pin. because capacitors also have internal parasitic components, such as stray inductance, selecting the right capacitor is important. to be effective, they should have low impedance over the frequency range of interest. tantalum capacitors are an excellent choice for their high capacitance/size ratio, but their effective series resistance (esr) increases with frequency making them less effective. on the other hand, ceramic chip capacitors have excellent esr and effective series inductance (esl) performance at higher frequencies, and because of their small size, they can be placed very close to the device pin, further reducing the stray inductance. best results are achieved by using a combination of these two capacitors. a 5 f to 10 f tantalum parallel capacitor with a 0.1 f ceramic chip capacitor is recommended. if additional isolation from high frequency resonances of the power supply is needed, a ferrite bead should be placed in series with the supply lines between the bypass capacitors and the power supply. note that addition of the ferrite bead introduces a new pole and zero to the frequency response of the circuit and could cause unstable operation if it is not selected properly. 00302-040 + v s + 10f tantalum 0.1f ceramic chip ?v s 10f tantalum 0.1f ceramic chip figure 40. recommended power supply bypass signal considerations input and output traces need special attention to assure a minimum stray capacitance. input nodes are very sensitive to capacitive reactance, particularly when connected to a high impedance circuit. stray capacitance can inject undesirable signals from a noisy line into a high impedance input. protect high impedance input traces by providing guard traces around them, which also improves the channel separation significantly. additionally, any stray capacitance in parallel with the input capacitance of the op amp generates a pole in the frequency response of the circuit. the additional phase shift caused by this pole reduces the gain margin of the circuit. if this pole is within the gain range of the op amp, it causes unstable performance. to reduce these undesirable effects, use the lowest impedance where possible. lowering the impedance at this node places the poles at a higher frequency, far above the gain range of the amplifier. stray capacitance on the pcb can be reduced by making the traces narrow and as short as possible. further reduction can be realized by choosing a smaller pad size, increasing the spacing between the traces, and using pcb material with a low dielectric constant insulator (dielectric constant of some common insulators: air = 1, teflon? = 2.2, and fr4 = 4.7, with air being an ideal insulator). removing segments of the ground plane directly under the input and output pads is recommended.
op467 rev. * | page 14 of 20 outputs of high speed amplifiers are very sensitive to capacitive loads. a capacitive load introduces a pair of pole and zero to the frequency response of the circuit, reducing the phase margin, leading to unstable operation or oscillation. generally, it is good design practice to isolate the output of the amplifier from any capacitive load by placing a resistor between the output of the amplifier and the rest of the circuits. a series resistor of 10 to 100 is normally sufficient to isolate the output from a capacitive load. the op467 is internally compensated to provide stable operation and is capable of driving large capacitive loads without oscillation. sockets are not recommended because they increase the lead inductance/capacitance and reduce the power dissipation of the package by increasing the thermal resistance of the leads. if sockets must be used, use teflon or pin sockets with the shortest possible leads. phase reversal the op467 is immune to phase reversal; its inputs can exceed the supply rails by a diode drop without any phase reversal. 00302-041 intput output 15.8v v1 200s 10v 10v 100 90 10 0% figure 41. no phase reversal (a v = +1) saturation recovery time the op467 has a fast and symmetrical recovery time from either rail. this feature is very useful in applications such as high speed instrumentation and measurement circuits, where the amplifier is frequently exposed to large signals that overload the amplifier. 00302-042 dly 9.824s 20ns 5v 5v 100 90 10 0% figure 42. saturation recovery time, positive rail 00302-043 dly 4.806s 20ns 5v 5v 100 90 10 0% figure 43. saturation reco very time, negative rail high speed instrumentation amplifier the op467 performance lends itself to a variety of high speed applications, including high speed precision instrumentation amplifiers. figure 44 represents a circuit commonly used for data acquisition, ccd imaging, and other high speed applications. the circuit gain is set by r g . a 2 k resistor sets the circuit gain to 2; for unity gain, remove r g . for any other gain settings, use the following formula g = 2/ r g (resistor value is in k) r c is used for adjusting the dc common-mode rejection, and c c is used for ac common-mode rejection adjustments. 0 0302-044 +v in ?v in 1k ? 2k ? 2k ? 2k ? output 1k ? 10k ? 1.9k ? 200 ? 10t r c 5pf r g 10k ? c c figure 44. a high speed instrumentation amplifier
op467 rev. * | page 15 of 20 0 0302-04 5 2 mhz biquad band-pass filter 0.01% 10v step v s = 15v neg slope the circuit in figure 48 is commonly used in medical imaging ultrasound receivers. the 30 mhz bandwidth is sufficient to accurately produce the 2 mhz center frequency, as the measured response shows in figure 49 . when the bandwidth of the op amp is too close to the center frequency of the filter, the internal phase shift of the amplifier causes excess phase shift at 2 mhz, which alters the response of the filter. in fact, if the chosen op amp has a bandwidth close to 2 mhz, the combined phase shift of the three op amps causes the loop to oscillate. 2.5mv ?2.5mv careful consideration must be given to the layout of this circuit as with any other high speed circuit. figure 45. instrumentation amplifier settling time to 0.01% for a 10 v step input (negative slope) if the phase shift introduced by the layout is large enough, it can alter the circuit performance, or worse, cause oscillation. 0 0302-04 6 0.01% 10v step v s =15v pos slope 2.5mv ?2.5mv 00302-048 v in v out 1/4 op467 1/4 op467 1/4 op467 1/4 op467 r1 3k ? 2k ? r2 2k ? r6 1k ? c1 50pf c2 50pf r3 2k ? r4 2k ? r5 2k ? figure 46. instrumentation amplifier settling time to 0.01% for a 10 v step input (positive slope) figure 48. 2 mhz biquad filter 00302-047 + v s ad9617 gain (db) frequency (hz) 00302-049 ?30 ?20 ?10 0 10k 100k 1m 10m 100m ?40 + + ?v s 2k ? 1k ? to input to in-amp output error to scope 2k ? 61.9 ? 549 ? figure 47. settling time measurement circuit figure 49. biquad filter response
op467 rev. * | page 16 of 20 00302-050 15 v dd v ref av ref c r fb ar fb c r fb br fb d v ref bv ref d db0 (lsb) ds2 i out 1a i out 1c i out 2a/ i out 2c/ i out 2b i out 2d i out 1b i out 1d dgnd dac8408 out a out b out d out c c1 10pf c3 10pf c4 10pf c2 10pf 7 5 4 11 6 op467 op467 1 1 2 3 7 8 9 10 11 12 4 5 6 13 14 digital control signals db1 db2 db3 db4 db5 (msb) db7 db6 28 27 26 22 21 20 19 18 17 25 24 23 16 r/w a/b ds1 0.1f 0.1f +15v +10v +10v +5 v +10v + 10v ?15v 2 3 op467 14 12 13 op467 8 10 9 figure 50. quad dac unipolar operation fast i-to-v converter the fast slew rate and fast settling time of the op467 are well suited to the fast buffers and i-to-v converters used in a variety of applications. the circuit in figure 50 is a unipolar quad dac consisting of only two ics. the current output of the dac8408 is converted to a voltage by the op467 configured as an i-to-v converter. this circuit is capable of settling to 0.1% within 200 ns. figure 51 and figure 52 show the full-scale settling time of the outputs. to obtain reliable circuit performance, keep the traces from the i out of the dac to the inverting inputs of the op467 short to minimize parasitic capacitance. 00302-051 260.0ns 100ns 50mv 2v 100 90 10 0% figure 51. falling edge output settling time 00302-052 251.0ns 100ns 50mv 2v 100 90 10 0% figure 52. rising edge output settling time 00302-053 2k ? 2k ? 1k ? 60.4k ? 604 ? 50k ? 3pf dac8408 dc offset r fb i out i-v op467 ad847 figure 53. dac v out settling time circuit
op467 rev. * | page 17 of 20 op467 spice marco-model * node assignments noninverting input inverting input positive supply negative supply output * . subckt op467 1 2 99 50 27 * * input stage * i1 4 5 0 10eC3 cin 1 2 1eC12 ios 1 2 5eC9 q1 5 2 8 qn q2 6 7 9 qn r3 99 5 185 . 681 r4 99 6 185 . 681 r5 8 4 180 . 508 r6 9 4 180 . 508 eos 7 1 poly (1) (14,20) 50eC6 1 eref 98 0 (20,0) 1 * * gain stage and dominant pole at 1.5 khz * r7 10 98 3 . 714e6 c2 10 98 28 . 571eC12 g1 98 10 (5,6) 5 . 386eC3 v1 99 11 1 . 6 v2 12 50 1 . 6 d1 10 11 dx d2 12 10 dx rc 10 28 1 . 4e3 cc 28 27 12eC12 * * common-mode stage with zero at 1.26 khz * ecm 13 98 poly (2) (1, 20) (2,20) 0 0. 5 0 . 5 r8 13 14 1e6 r9 14 98 25 . 119 c3 13 14 126 . 721eC12 * *pole at 400e6 * r10 15 98 1e6 c4 15 98 0 . 398eC15 g2 98 15 (10,20) 1eC6 * * output stage * isy 99 50 C8 . 183eC3 rmp1 99 20 96 . 429e3 rmp2 20 50 96 . 429e3 ro1 99 26 200 ro2 26 50 200 l1 26 27 1eC7 go1 26 99 (99,15) 5eC3 go2 50 26 (15,50) 5eC3 g4 23 50 (15,26) 5eC3 g5 24 50 (26,15) 5eC3 v3 21 26 50 v4 26 22 50 d3 15 21 dx d4 22 15 dx d5 99 23 dx d6 99 24 dx d7 50 23 dy d8 50 24 dy * * models used * . model qn npn (bf=33.333e3) . model dx d . model dy d (bv=50) . ends op467
op467 g2 r10 c4 i sy rmp2 rmp1 20 15 d5 d3 d4 d6 23 24 22 21 v3 v4 g01 r02 r01 l1 99 26 15 99 27 rev. * | page 18 of 20 00302-054 e ref g4 d7 g5 d8 g02 50 50 ? + 98 ? + ? + figure 54. spice macro-model output stage 0 0302-05 5 i os c in i1 e os r3 5 g1 99 99 n+ 2 1 r4 6 r5 r6 4 89 7 c2 r7 10 98 12 e ref r c e cm c c 28 c3 r8 14 27 v1 11 13 d2 d1 r9 50 50 v2 ? + q1 q2 n? ? + ? + ? + ? + figure 55. spice macro-model input and gain stage
op467 rev. i | page 19 of 20 outline dimensions compliant to jedec standards ms-001 controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. corner leads may be configured as whole or half leads. 070606-a 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.130 (3.30) 0.110 (2.79) 0.070 (1.78) 0.050 (1.27) 0.045 (1.14) 14 1 7 8 0.100 (2.54) bsc 0.775 (19.69) 0.750 (19.05) 0.735 (18.67) 0.060 (1.52) max 0.430 (10.92) max 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.015 (0.38) gauge plane 0.210 (5.33) max seating plane 0.015 (0.38) min 0.005 (0.13) min 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) figure 56. 14-lead plastic dual in-line package [pdip] (n-14) p-suffix dimensions shown in inches and (millimeters) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 0.310 (7.87) 0.220 (5.59) 0.005 (0.13) min 0.098 (2.49) max 0.100 (2.54) bsc 15 0 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) seating plane 0.200 (5.08) max 0.785 (19.94) max 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) pin 1 1 7 8 14 figure 57. 14-lead ceramic dual in-line package [cerdip] (q-14) y-suffix dimensions shown in inches and (millimeters)
op467 rev. i | page 20 of 20 controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-013- aa 032707-b 10.50 (0.4134) 10.10 (0.3976) 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0 . 7 5 ( 0 . 0 2 9 5 ) 0 . 2 5 ( 0 . 0 0 9 8 ) 45 1.27 (0.0500) 0.40 (0.0157) c oplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) seating plane 8 0 16 9 8 1 1.27 (0.0500) bsc figure 58. 16-lead standard small outline package [soic_w] wide body (rw-16) s-suffix dimensions shown in millimeters and (inches) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 1 20 4 9 8 13 19 14 3 18 bottom view 0.028 (0.71) 0.022 (0.56) 45 typ 0.015 (0.38) min 0.055 (1.40) 0.045 (1.14) 0.050 (1.27) bsc 0.075 (1.91) ref 0.011 (0.28) 0.007 (0.18) r typ 0.095 (2.41) 0.075 (1.90) 0.100 (2.54) ref 0.200 (5.08) ref 0.150 (3.81) bsc 0.075 (1.91) ref 0.358 (9.09) 0.342 (8.69) sq 0.358 (9.09) max sq 0.100 (2.54) 0.064 (1.63) 0.088 (2.24) 0.054 (1.37) 022106-a figure 59. 20-terminal cerami c leadless chip carrier [lcc] (e-20-1) rc-suffix dimensions shown in inches and (millimeters) ordering guide model 1 temperature range package description package option op467gp ?40c to +85c 14-lead pdip n-14 op467gpz ?40c to +85c 14-lead pdip n-14 op467gs ?40c to +85c 16-lead soic_w rw-16 op467gs-reel ?40c to +85c 16-lead soic_w rw-16 op467gsz ?40c to +85c 16-lead soic_w rw-16 op467gsz-reel ?40c to +85c 16-lead soic_w rw-16 op467arc/883c ?55c to +125c 20-terminal lcc e-20-1 op467ay/883c ?55c to +125c 14-lead cerdip q-14 op467gbc die 1 z = rohs compliant part. ?1993C2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d00302-0-4/10(i)

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