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d a t a sh eet product speci?cation file under integrated circuits, ic19 1998 mar 10 integrated circuits oq2536hp sdh/sonet stm16/oc48 demultiplexer
1998 mar 10 2 philips semiconductors product speci?cation sdh/sonet stm16/oc48 demultiplexer oq2536hp features normal and loop (test) modes 1.2 v gtl (gunning transceiver logic) level compatible data and clock outputs (low speed interface) differential cml (current-mode logic) data and clock inputs high input sensitivity (100 mv for the high speed inputs) boundary scan test (bst) at low speed interface, in accordance with ieee std 1149.1-1990 low power dissipation (typically 1.45 w). description the oq2536hp is a 32-channel demultiplexer intended for use in stm16/oc48 applications. it demultiplexes a single 2.5 gbits/s input channel to 32 78 mbits/s output channels. the data and clock outputs on the low speed interface are gtl compatible, while the high speed data and clock inputs are cml compatible. ordering information block diagram type number package name description version oq2536hp hlqfp100 plastic heat-dissipating low pro?le quad ?at package; 100 leads; body 14 14 1.4 mm sot470-1 fig.1 block diagram. (1) see chapter pinning for d0 to d31 pin numbers. (2) pins 1, 8, 17, 22, 25, 29, 33, 35, 40 to 50, 52, 55, 58, 61, 64, 67, 78, 82, 91 and 96. handbook, full pagewidth 4 enl trst tms tck tdi tdo cdiv din dinq cin cinq dloop dloopq cloop cloopq dioa dioc 1 : 4 dmux divide by 4 622 mhz oq2536hp 78 mhz 2.5 ghz band gap reference 1 divide by 8 bst logic 4 1 : 8 dmux 622 mbits/s 2.5 gbits/s 78 mbits/s 75 70 72 69 68 71 12 26, 27, 28, 76, 77 13, 14, 36, 37, 63, 85, 86 11, 38, 39, 62, 88 v dd v cc1 v ee v cc2 bgcap1 29 5 7 5 (2) (1) gnd 74 51 band gap reference 2 bgcap2 34 73 refc 54 53 56 57 65 66 60 59 32 31 d0 to d31 mgk346
1998 mar 10 3 philips semiconductors product speci?cation sdh/sonet stm16/oc48 demultiplexer oq2536hp pinning symbol pin type (1) description gnd 1 s ground d29 2 o 78 mbits/s data output channel for d29 d25 3 o 78 mbits/s data output channel for d25 d21 4 o 78 mbits/s data output channel for d21 d17 5 o 78 mbits/s data output channel for d17 d13 6 o 78 mbits/s data output channel for d13 d9 7 o 78 mbits/s data output channel for d9 gnd 8 s ground d5 9 o 78 mbits/s data output channel for d5 d1 10 o 78 mbits/s data output channel for d1 v ee 11 s supply voltage ( - 4.5 v) cdiv 12 o 78 mhz clock output v cc2 13 s supply voltage (+1.5 v) v cc2 14 s supply voltage (+1.5 v) d28 15 o 78 mbits/s data output channel for d28 d24 16 o 78 mbits/s data output channel for d24 gnd 17 s ground d20 18 o 78 mbits/s data output channel for d20 d16 19 o 78 mbits/s data output channel for d16 d12 20 o 78 mbits/s data output channel for d12 d8 21 o 78 mbits/s data output channel for d8 gnd 22 s ground d4 23 o 78 mbits/s data output channel for d4 d0 24 o 78 mbits/s data output channel for d0 gnd 25 s ground v dd 26 i supply voltage (+3.3 v) v dd 27 i supply voltage (+3.3 v) v dd 28 i supply voltage (+3.3 v) gnd 29 s ground i.c. 30 - internally connected, to be left open-circuit dioc 31 a cathode of temperature diode array dioa 32 a anode of temperature diode array gnd 33 s ground bgcap2 34 a pin for connecting external band gap decoupling capacitor (4 1 : 8 dmux) gnd 35 s ground v cc2 36 s supply voltage (+1.5 v) v cc2 37 s supply voltage (+1.5 v) v ee 38 s supply voltage ( - 4.5 v) v ee 39 s supply voltage ( - 4.5 v) gnd 40 s ground
1998 mar 10 4 philips semiconductors product speci?cation sdh/sonet stm16/oc48 demultiplexer oq2536hp gnd 41 s ground gnd 42 s ground gnd 43 s ground gnd 44 s ground gnd 45 s ground gnd 46 s ground gnd 47 s ground gnd 48 s ground gnd 49 s ground gnd 50 s ground bgcap1 51 a pin for connecting external band gap decoupling capacitor (1 : 4 dmux) gnd 52 s ground dinq 53 i inverted data input in normal mode din 54 i data input in normal mode gnd 55 s ground cin 56 i clock input in normal mode cinq 57 i inverted clock input in normal mode gnd 58 s ground cloopq 59 i inverted clock input from multiplexer ic oq2535 (loop mode) cloop 60 i clock input from multiplexer ic oq2535 (loop mode) gnd 61 s ground v ee 62 s supply voltage ( - 4.5 v) v cc2 63 s supply voltage (+1.5 v) gnd 64 s ground dloop 65 i data input from multiplexer ic oq2535 (loop mode) dloopq 66 i inverted data input from multiplexer ic oq2535 (loop mode) gnd 67 s ground trst 68 i test reset input for bst mode (active low) tms 69 i test mode select input for bst tck 70 i test clock input for bst mode tdo 71 o serial test data output for bst mode tdi 72 i serial test data input for bst mode refc 73 a pin for connecting external reference decoupling capacitor (for standard ttl reference) v cc1 74 s supply voltage (+5.0 v) enl 75 i loop mode enable input (active low) v dd 76 i supply voltage (+3.3 v) v dd 77 i supply voltage (+3.3 v) gnd 78 s ground d31 79 o 78 mbits/s data output channel for d31 d27 80 o 78 mbits/s data output channel for d27 symbol pin type (1) description
1998 mar 10 5 philips semiconductors product speci?cation sdh/sonet stm16/oc48 demultiplexer oq2536hp note 1. pin type abbreviations: o = output, i = input, s = power supply, a = analog function. d23 81 o 78 mbits/s data output channel for d23 gnd 82 s ground d19 83 o 78 mbits/s data output channel for d19 d15 84 o 78 mbits/s data output channel for d15 v cc2 85 s supply voltage (+1.5 v) v cc2 86 s supply voltage (+1.5 v) d11 87 o 78 mbits/s data output channel for d11 v ee 88 s supply voltage ( - 4.5 v) d7 89 o 78 mbits/s data output channel for d7 d3 90 o 78 mbits/s data output channel for d3 gnd 91 s ground d30 92 o 78 mbits/s data output channel for d30 d26 93 o 78 mbits/s data output channel for d26 d22 94 o 78 mbits/s data output channel for d22 d18 95 o 78 mbits/s data output channel for d18 gnd 96 s ground d14 97 o 78 mbits/s data output channel for d14 d10 98 o 78 mbits/s data output channel for d10 d6 99 o 78 mbits/s data output channel for d6 d2 100 o 78 mbits/s data output channel for d2 symbol pin type (1) description
1998 mar 10 6 philips semiconductors product speci?cation sdh/sonet stm16/oc48 demultiplexer oq2536hp fig.2 pin configuration. handbook, full pagewidth 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 80 79 78 77 76 enl v cc1 refc tdi tdo tck tms trst gnd dloopq dloop gnd v cc2 v ee gnd cloop cloopq gnd cinq cin gnd din dinq gnd bgcap1 mgk345 gnd d29 d25 d21 d17 d13 d9 gnd d5 d1 v ee cdiv v cc2 v cc2 d28 d24 gnd d20 d16 d12 d8 gnd d4 d0 gnd d27 d31 gnd v dd v dd d2 d6 d10 d14 gnd d18 d22 d26 d30 gnd d3 d7 v ee d11 v cc2 v cc2 d15 d19 gnd d23 dioc dioa gnd bgcap2 gnd v cc2 v cc2 v ee v ee gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd v dd v dd v dd gnd i.c. 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 oq2536hp
1998 mar 10 7 philips semiconductors product speci?cation sdh/sonet stm16/oc48 demultiplexer oq2536hp functional description the oq2536hp is a 32-channel demultiplexer, intended for use in stm16/oc48 applications. it demultiplexes a single 2.5 gbits/s input channel to 32 78 mbits/s output channels. the demultiplexing is performed in two stages. the 2.5 gbits/s data channel is first demultiplexed to four 622 mbits/s data channels. each of these channels is then fed to a 1 : 8 demultiplexer to generate 32 78 mbits/s output channels. the enl control input is used for switching between normal and loop modes. when loop mode is enabled (enl = low), inputs dloop, dloopq, cloop and cloopq are selected. in normal mode (enl = high), inputs din, dinq, cin and cinq are selected. the signal applied to cin and cinq is a 2.5 ghz recovered clock signal, e.g. coming from the oq2541 data and clock recovery ic. the clock is divided down to 78 mhz, which is used for receive logic timing and is available as a gtl compatible output at pin cdiv. high bit rate stage: 1 : 4 dmux the 2.5 gbits/s data stream is fed into a 1 : 4 demultiplexer to generate four 622 mbits/s channels. the input pins din, dinq, dloop, dloopq, cin, cinq, cloop and cloopq are terminated internally with 50 w resistors to gnd. low bit rate part: 4 1 : 8 dmux the four 622 mbits/s output channels coming from the high bit rate stage are loaded into four 8-bit shift registers. the 622 mhz clock for these shift registers comes from the preceding stage. the 32 bits contained in the shift registers are loaded into latches and made available on outputs d0 to d31. these outputs are 1.2 v gtl compatible and have internal 100 w pull up resistors. the 78 mhz clock output, cdiv, has an internal 50 w pull up resistor. the first serial data bit coming in at din or dloop is given out at pin d31 (msb) and so on. the data outputs may not always represent four stm bytes. this is because the internal load pulse for the output latches is not synchronized to the stm16 frame. power supply connections the power supply pins need to be individually decoupled using chip capacitors mounted as close as possible to the ic. if multiple decoupling capacitors are used for a single supply node, large distance between the capacitances should be avoided in order to avoid resonance. to minimize low frequency switching noise in the vicinity of the oq2536hp, all power supply lines should be filtered once by an lc-circuit with a low cutoff frequency (as shown in the application diagram, fig.7). ground connection the ground connection on the pcb needs to be a large copper area fill connected to a common ground plane with low inductance. rf connections a coupled stripline or microstrip with an odd mode characteristic impedance of 50 w (nominal value) should be used for the rf connections on the pcb. the connections should be kept as short as possible. this applies to the cml differential line pairs cin and cinq, din and dinq, cloop and cloopq, and dloop and dloopq. in addition, the following lines should not vary in length by more than 5 mm: cin, cinq, din and dinq dloop, dloopq, cloop and cloopq. interface to receive logic the 78 mbits/s interface lines, cdiv and d0 to d31, should not exceed 50 mm in length. the parasitic capacitance of these lines should be as small as possible (less than 3 pf is desirable). esd protection all pads are protected by esd protection diodes, with the exception of the high frequency inputs din, dinq, dloop, dloopq, cin, cinq, cloop and cloopq. cooling in many cases it is necessary to mount a special cooling device on the package. the thermal resistance from junction to case, r th j-c and from junction to ambient, r th j-a , are given in chapter thermal characteristics. since the heat-slug in the package is connected to the die, the cooling device should be electrically isolated. to calculate if a heatsink is necessary, the maximum allowed total thermal resistance r is calculated as: (1) r th t j t amb C p tot ----------------------- - =
1998 mar 10 8 philips semiconductors product speci?cation sdh/sonet stm16/oc48 demultiplexer oq2536hp where: r th = total thermal resistance from junction to ambient in the application t j = junction temperature t amb = ambient temperature. as long as r th is greater than r th j-a of the oq2536hp including environmental conditions like air flow and board layout, no heatsink is necessary. for example if t j = 120 c, t amb =70 c and p tot = 1.45 w, then: (2) which is more than the worst case r th j-a = 33 k/w, so no heatsink is necessary. another example; if for safety reasons t j should stay as low as 110 c, while t amb =85 c and p tot = 2 w, then: (3) in this case extra cooling is needed. the thermal resistance of the heatsink is calculated as follows: (4) where: r th h-a = thermal resistance from heatsink to ambient r th c-h = thermal resistance from case to heatsink r th j-c = thermal resistance from junction to case, see chapter thermal characteristics. r th 120 70 C () 1.45 ----------------------------- 34.4 == kw [] r th 110 85 C () 2.0 ----------------------------- 12.5 == kw [] r thh a C 1 r th -------- 1 r thj a C ---------------- - C ? ?? 1 C r thj c C C r thc h C C if for instance r th c-h = 0.5 k/w and r th j -a = 33 k/w then: (5) built in temperature sensor three series-connected diodes have been integrated for measuring junction temperature. the diode array, accessed by means of the dioa (anode) and dioc (cathode) pins, has a temperature dependency of approximately - 6 mv/ c. with a diode current of 1 ma, the voltage will be somewhere in the range 1.7 to 2.5 v, depending on temperature. boundary scan test (bst) interface boundary scan test logic has been implemented for all digital inputs and outputs on the low frequency interface, in accordance with ieee std 1149.1-1990 . all scan tests other than sample mode are available. the boundary scan test logic consists of a tap controller, a bypass register, a 2-bit instruction register, a 32-bit identification register and a 36-bit boundary scan register (the last two are combined). the architecture of the tap controller and the bypass register is in accordance with ieee recommendations. the four command modes, selected be means of the instruction register, are: extest (00), preload (01), idcode (10) and bypass (11). all boundary scan test inputs, tdi, tms, tck and trst, have internal pull up resistors. the maximum test clock frequency at tck is 12 mhz. r thh a C 1 12.5 ----------- 1 33 ------ C ? ?? 1 C 3.1 C 17.0 kw [] table 1 bst identi?er code notes 1. lsb is shifted out first on the tdo pin. 2. the manufacturers code was implemented incorrectly. it should have been 0000 0010 101. version oq 2536 (binary) philips semiconductors lsb (1) 0001 01 00 1001 1110 1000 0000 0011 101 (2) 1
1998 mar 10 9 philips semiconductors product speci?cation sdh/sonet stm16/oc48 demultiplexer oq2536hp table 2 bst bit order note 1. lsb is shifted out first on the tdo pin. bit number symbol pin 33 (msb) d31 79 32 d27 80 31 d23 81 30 d19 83 29 d15 84 28 d11 87 27 d7 89 26 d3 90 25 d30 92 24 d26 93 23 d22 94 22 d18 95 21 d14 97 20 d10 98 19 d6 99 18 d2 100 17 d29 2 16 d25 3 15 d21 4 14 d17 5 13 d13 6 12 d9 7 11 d5 9 10 d1 10 9 cdiv 12 8 d28 15 7 d24 16 6 d20 18 5 d16 19 4 d12 20 3d8 21 2d4 23 1d0 24 0 (lsb) (1) enl 75
1998 mar 10 10 philips semiconductors product speci?cation sdh/sonet stm16/oc48 demultiplexer oq2536hp limiting values in accordance with the absolute maximum rating system (iec 134). thermal characteristics note 1. the thermal resistance from junction to ambient is strongly depending on the board design and air?ow. the values given in the table are typical values and are measured on a single sided test board with dimensions of 76 114 1.6 mm. better values can be obtained when mounted on multilayer boards with large ground planes. symbol parameter min. max. unit v cc1 supply voltage - 0.5 +6.0 v v ee supply voltage - 6.0 +0.5 v v dd supply voltage - 0.5 +5.0 v v cc2 supply voltage - 0.5 +2.0 v v n dc voltage pins 2 to 7, 9, 10, 15, 16, 18 to 21, 23, 24, 79, 80, 81, 83, 84, 87, 89, 90, 92 to 95 and 97 to 100 0.0 2.0 v pins 53, 54, 56, 57, 59, 60, 65 and 66 - 1.0 +0.5 v pins 68, 69, 70, 72, 73 and 75 - 0.5 v cc1 + 0.5 v pins 30, 34 and 51 v ee - 0.5 0.5 v pins 31and 32 v ee - 0.5 v cc1 + 0.5 v i n dc current pins 2 to 7, 9, 10, 15, 16, 18 to 21, 23, 24, 79, 80, 81, 83, 84, 87, 89, 90, 92 to 95, and 97 to 100 - 15 ma pin 12 - 30 ma pins 31 and 32 - 10 ma pin 71 - 50 ma p tot total power dissipation - 2.6 w t j junction temperature - 120 c t stg storage temperature - 65 +150 c symbol parameter conditions value unit r th j-c thermal resistance from junction to case 2.6 k/w r th j-a thermal resistance from junction to ambient see note 1 airflow = 0 ft/min 33 k/w airflow = 100 ft/min 28 k/w airflow = 200 ft/min 25 k/w airflow = 400 ft/min 22 k/w airflow = 600 ft/min 20 k/w
1998 mar 10 11 philips semiconductors product speci?cation sdh/sonet stm16/oc48 demultiplexer oq2536hp dc characteristics typical values at t amb =25 c and at typical supply voltages; minimum and maximum values are valid over the entire ambient temperature range and supply voltage range. symbol parameter conditions min. typ. max. unit general v cc1 supply voltage 4.75 5.0 5.25 v v ee supply voltage - 4.75 - 4.5 - 4.25 v v dd supply voltage 3.14 3.3 3.47 v v cc2 supply voltage 1.1 1.5 1.6 v i cc1 supply current - 14 22 ma i ee supply current - 170 215 ma i dd supply current - 100 185 ma i cc2 supply current note 1 - 190 525 ma p tot total power dissipation note 1 - 1.45 2.6 w t j junction temperature -- +120 c t amb ambient temperature - 40 - +85 c ttl input: enl v il low-level input voltage -- 0.8 v v ih high-level input voltage 2.0 -- v i il low-level input current - 90 - - m a i ih high-level input current - - 210 m a ttl inputs: tdi, tck, tms and trst; note 2 v il low-level input voltage -- 0.4 v v ih high-level input voltage 2.0 -- v cml inputs: cin, cinq, din, dinq, cloop, cloopq, dloop and dloopq; note 3 v i(p-p) input voltage (peak-to-peak value) 50 w measurement system 100 250 500 mv v io permitted input offset voltage - 25 - +25 mv v i,iq input voltages - 600 - +250 mv z i single ended input impedance for dc signal - 50 -w ttl output: tdo; note 4 v ol low-level output voltage i ol =4ma - 0.3 0.5 v
1998 mar 10 12 philips semiconductors product speci?cation sdh/sonet stm16/oc48 demultiplexer oq2536hp notes 1. maximum current i cc2 and maximum power dissipation p tot are worst case figures i.e. data outputs d0 to d31 remain in low state. 2. tdi, tck, tms and trst are connected via 90 k w to v dd . 3. see fig.3 for symbol definitions. 4. tdo is switched to high impedance state if bst is inactive. 5. output cdiv has an internal pull-up resistor of 50 w to v cc2 . outputs d0 to d31 have internal pull-up resistors of 100 w to v cc2 . 6. the first serial data bit coming in at din or dloop is given out at d31 (msb) and so on. 7. the high-level output voltage depends on the supply voltage v cc2 . 8. the temperature diode array can be used to measure the temperature of the die. the temperature dependency of this voltage is approximately - 6 mv/k. v oh high-level output voltage i oh = - 400 m a 2.4 4.0 - v i oz output current in high impedance state -- 1 m a outputs: cdiv and d0 to d31; notes 5 and 6 v ol low-level output voltage open outputs - 0.3 0.4 v v oh high-level output voltage; note 7 1.1 1.5 1.6 v temperature diode array d v dioa-dioc diode voltage range (8) i i(d) =1ma - 2.1 - v symbol parameter conditions min. typ. max. unit fig.3 logic level symbol definitions for cml. handbook, full pagewidth mgk144 v io v i(max) v iqh v ih v iql v il v i(min) v i (p-p) gnd cml input v oo v o(max) v oqh v oh v oql v ol v o(min) v o (p-p) gnd cml output
1998 mar 10 13 philips semiconductors product speci?cation sdh/sonet stm16/oc48 demultiplexer oq2536hp timing typical values at t amb =25 c and at typical supply voltages; minimum and maximum values are valid over the entire ambient temperature range and supply voltage range. notes 1. the speci?ed timing characteristics are applicable in both normal and loop modes. 2. a capacitive load of 15 pf was connected at all outputs. an input reference level of 1 v was used. symbol parameter conditions min. typ. max. unit cml input timing; note 1 ; fig.5 f clk(cin) input clock frequency 2.488 -- ghz t su input data set-up time 140 -- ps t h input data hold time 80 -- ps sr cin clock slew rate 1 -- v/ns ttl output timing; note 2 ; fig.6 f clk(cdiv) output clock frequency f clk(cdiv) = 2.488 ghz - 77.76 - mhz d cdiv output clock duty factor - 50 - % t r(cdiv) output clock rise time measured between 10% and 90% levels of full output swing -- 2700 ps t f(cdiv) output clock fall time -- 1000 ps t r(d0 to d31) data out rise time -- 5100 ps t f(d0 to d31) data out fall time -- 1000 ps t cdv clock edge to data valid time -- 2700 ps t di data invalid time -- 2850 ps fig.4 gtl output circuits. handbook, halfpage mbk756 v cc2 d0 to d31 gnd 100 w handbook, halfpage mbk757 v cc2 cdiv gnd 50 w
1998 mar 10 14 philips semiconductors product speci?cation sdh/sonet stm16/oc48 demultiplexer oq2536hp fig.5 cml input timing. handbook, full pagewidth t h t su 100 mv valid data 50% din cin t cy(cin) mgk347 fig.6 output timing. handbook, full pagewidth mgk348 t cdv t di t cy(cdiv) 1.0 v cdiv d0 to d31 1.1 v 0.9 v
1998 mar 10 15 philips semiconductors product speci?cation sdh/sonet stm16/oc48 demultiplexer oq2536hp application information fig.7 application diagram. (1) v cc2 pins 13, 14, 36, 37, 63, 85 and 86 should be connected together, and to the filter network. (2) v dd pins 26, 27, 28, 76 and 77 should be connected together, and to the filter network. (3) v ee pins 11, 38, 39, 62 and 8 should be connected together, and to the filter network. (4) all gnd pins (pins 1, 4, 8, 9, 11, 15, 17, 21, 25, 36, 40, 56, 64, 67, 70, 73, 76, 77, 79, 80, 81, 84, 89, 92 to 98 and 100) mus t be connected directly to the pcb ground plane. handbook, full pagewidth mgk349 ferrite bead ferrite bead ferrite bead ferrite bead 1 m f 100 nf tms tck tdo tdi din dinq cin cinq dioa dloop dloopq cloop v cc2 cloopq dloop dloopq cloop cloopq receive logic boundary scan test equipment micro- controller oq2535 mux oq2541 oq2536 68 75 69 70 72 71 v ee gnd 54 53 56 data and clock recovery 57 d dq cl clq 65 66 60 59 enl trst (3) 1 m f 100 nf v dd (2) 74 (1) 32 73 34 51 12 1 m f 100 nf 1 m f 100 nf dioc 31 refc bgcap2 33 nf 10 nf v cc1 v ee bgcap1 cdiv 10 nf d0 to d31 c78 d0 to d31 v ee (4)
1998 mar 10 16 philips semiconductors product speci?cation sdh/sonet stm16/oc48 demultiplexer oq2536hp package outline unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 1.6 0.20 0.05 1.5 1.3 0.25 0.28 0.16 0.18 0.12 14.1 13.9 0.5 16.25 15.75 1.15 0.85 7 0 o o 0.12 0.1 0.2 1.0 j (2) dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 2. heatsink intrusion 0.0127 maximum. 0.75 0.45 10.15 9.15 sot470-1 97-01-13 d (1) (1) (1) 14.1 13.9 h d 16.25 15.75 e z 1.15 0.85 d b p e e detail x j b 25 c d h b p e h a 1 a a 2 v m b d z d a z e e v m a x 1 100 76 75 51 50 26 q l p l (a ) 3 y w m w m 0 5 10 mm scale hlqfp100: plastic heat-dissipating low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm sot470-1 pin 1 index
1998 mar 10 17 philips semiconductors product speci?cation sdh/sonet stm16/oc48 demultiplexer oq2536hp soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). re?ow soldering reflow soldering techniques are suitable for all lqfp packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. wave soldering wave soldering is not recommended for lqfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. even with these conditions, do not consider wave soldering lqfp packages lqfp48 (sot313-2), lqfp64 (sot314-2) or lqfp80 (sot315-1). during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1998 mar 10 18 philips semiconductors product speci?cation sdh/sonet stm16/oc48 demultiplexer oq2536hp definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
1998 mar 10 19 philips semiconductors product speci?cation sdh/sonet stm16/oc48 demultiplexer oq2536hp notes
internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1998 sca57 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reli able and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 1231, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: al. vicente pinzon, 173, 6th floor, 04547-130 s?o paulo, sp, brazil, tel. +55 11 821 2333, fax. +55 11 821 2382 spain: balmes 22, 08007 barcelona, tel. +34 3 301 6312, fax. +34 3 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 632 2000, fax. +46 8 632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2686, fax. +41 1 488 3263 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2865, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. +90 212 279 2770, fax. +90 212 282 6707 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 181 730 5000, fax. +44 181 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 625 344, fax.+381 11 635 777 for all other countries apply to: philips semiconductors, international marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 160 1010, fax. +43 160 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 200 733, fax. +375 172 200 773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 689 211, fax. +359 2 689 102 canada: philips semiconductors/components, tel. +1 800 234 7381 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. +45 32 88 2636, fax. +45 31 57 0044 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615800, fax. +358 9 61580920 france: 51 rue carnot, bp317, 92156 suresnes cedex, tel. +33 1 40 99 6161, fax. +33 1 40 99 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 23 53 60, fax. +49 40 23 536 300 greece: no. 15, 25th march street, gr 17778 tavros/athens, tel. +30 1 4894 339/239, fax. +30 1 4814 240 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: see singapore ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381 middle east: see italy printed in the netherlands 425102/200/01/pp20 date of release: 1998 mar 10 document order number: 9397 750 01623

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