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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. mos integrated circuit pd434001al 4m-bit cmos fast sram 4m-word by 1-bit data sheet document no. m12223ej7v0ds00 (7th edition) date published december 2002 ns cp(k) printed in japan 1996 description the pd434001al is a high speed, low power, 4,194,304 bits (4,194,304 words by 1 bit) cmos static ram. operating supply voltage is 3.3 v 0.3 v. the pd434001al is packaged in 32-pin plastic soj and 32-pin plastic tsop (ii). features ? 4,194,304 words by 1 bit organization ? fast access time : 15, 17, 20 ns (max.) ? output enable input for easy application ? single +3.3 v power supply ordering information part number package access time supply current ma (max.) ns (max.) at operating at standby pd434001alle-a15 32-pin plastic soj 15 130 5 pd434001alle-a17 (10.16 mm (400)) 17 120 pd434001alle-a20 20 110 pd434001alg5-a15-7jd 32-pin plastic tsop (ii) 15 130 pd434001alg5-a17-7jd (10.16 mm (400)) 17 120 pd434001alg5-a20-7jd (normal bent) 20 110
2 pd434001al data sheet m12223ej7v0ds pin configuration /xxx indicates active low si gnal. 32-pin plastic soj (10.16 mm (400)) [ pd434001alle ] 32-pin plastic tsop (ii) (10.16 mm (400)) (normal bent) [ pd434001alg5-7jd ] marking side 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a0 a1 a2 a3 a4 a5 /cs v cc gnd d in /we a6 a7 a8 a9 a10 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a21 a20 a19 a18 a17 a16 /oe gnd v cc d out a15 a14 a13 a12 a11 nc a0 to a21 : address inputs d in : data input d out : data output /cs : chip select /we : write enable /oe : output enable v cc : power supply gnd : ground nc : no connection remark refer to package drawings for the 1-pin index mark.
3 pd434001al data sheet m12223ej7v0ds block diagram a0 | a21 address buffer row decoder memory cell array 4,194,304 bits gnd v cc /we /oe /cs input data controller sense amplifier / switching circuit column decoder address buffer output data controller d in d out truth table /cs /oe /we mode i/o supply current h not selected high-z i sb l l h read d out i cc l lwrite d in l h h output disable high-z remark : don?t care
4 pd434001al data sheet m12223ej7v0ds electrical specifications absolute maximum ratings parameter symbol condition rating unit supply voltage v cc ?0.5 note to +4.6 v input / output voltage v t ?0.5 note to +4.6 v operating ambient temperature t a 0 to 70 c storage temperature t stg ?55 to +125 c note ?2.0 v (min.) (pulse width : 2 ns) caution exposing the device to stress above those listed in absolute maximum rating could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter symbol condition min. typ. max. unit supply voltage v cc 3.0 3.3 3.6 v high level input voltage v ih 2.2 v cc +0.3 v low level input voltage v il ?0.3 note +0.8 v operating ambient temperature t a 070 c note ?2.0 v (min.) (pulse width : 2 ns)
5 pd434001al data sheet m12223ej7v0ds dc characteristics (recommended operating conditions unless otherwise noted) parameter symbol test condition min. typ. max. unit input leakage current i li v in = 0 v to v cc ?2 +2 a output leakage current i lo v out = 0 v to v cc ,?2+2 a /cs = v ih or /oe = v ih or /we = v il operating supply current i cc /cs = v il , cycle time : 15 ns 130 ma i out = 0 ma, cycle time : 17 ns 120 minimum cycle time cycle time : 20 ns 110 standby supply current i sb /cs = v ih , v in = v ih or v il 50 ma i sb1 /cs v cc ? 0.2 v, 5 v in 0.2 v or v in v cc ? 0.2 v high level output voltage v oh i oh = ?4.0 ma 2.4 v low level output voltage v ol i ol = +8.0 ma 0.4 v remarks 1. v in : input voltage v out : output voltage 2. these dc characteristics are in common regardless of package types. capacitance (t a = 25 c, f = 1 mhz) parameter symbol test condition min. typ. max. unit input capacitance c in v in = 0 v 6 pf output capacitance c out v out = 0 v 10 pf remarks 1. v in : input voltage v out : output voltage 2. these parameters are periodically sampled and not 100% tested.
6 pd434001al data sheet m12223ej7v0ds ac characteristics (recommended operating conditions unless otherwise noted) ac test conditions input waveform (rise and fall time 3 ns) test points gnd 3.0 v 1.5 v 1.5 v output waveform test points 1.5 v 1.5 v output load ac characteristics directed with the note should be measured with the output load shown in figure 1 or figure 2 . figure 1 figure 2 (for t aa , t acs , t oe , t oh )(for t clz , t olz , t chz , t ohz , t whz , t ow ) v tt = +1.5 v d out (output) 50 ? z o = 50 ? 30 pf c l +3.3 v d out (output) 317 ? 5 pf c l 351 ? remark c l includes capacitances of the probe and jig, and stray capacitances.
7 pd434001al data sheet m12223ej7v0ds read cycle parameter symbol -a15 -a17 -a20 unit notes min. max. min. max. min. max. read cycle time t rc 15 17 20 ns address access time t aa 15 17 20 ns 1 /cs access time t acs 15 17 20 ns /oe access time t oe 7 8 10 ns output hold from address change t oh 333ns /cs to output in low impedance t clz 3 3 3 ns 2, 3 /oe to output in low impedance t olz 000ns /cs to output in high impedance t chz 788ns /oe to output hold in high impedance t ohz 788ns notes 1. see the output load shown in figure 1 . 2. transition is measured at 200 mv from steady-state voltage with the output load shown in figure 2 . 3. these parameters are periodically sampled and not 100% tested. remark these ac characteristics are in common regardless of package types. read cycle timing chart 1 (address access) t oh t rc t aa address (input) d out (output) previous data out data out remarks 1. in read cycle, /we should be fixed to high level. 2. /cs = /oe = v il
8 pd434001al data sheet m12223ej7v0ds read cycle timing chart 2 (/cs access) address (input) t rc t aa t olz /cs (input) d out (output) data out t ohz high-z t acs /oe (input) t oe t clz t chz high-z caution address valid prior to or coincident with /cs low level input. remark in read cycle, /we should be fixed to high level.
9 pd434001al data sheet m12223ej7v0ds write cycle parameter symbol -a15 -a17 -a20 unit notes min. max. min. max. min. max. write cycle time t wc 15 17 20 ns /cs to end of write t cw 10 11 12 ns address valid to end of write t aw 10 11 12 ns write pulse width t wp 10 11 12 ns data valid to end of write t dw 789ns data hold time t dh 000ns address setup time t as 000ns write recovery time t wr 111ns /we to output in high impedance t whz 7 8 8 ns 1, 2 output active from end of write t ow 333ns notes 1. transition is measured at 200 mv from steady-state voltage with the output load shown in figure 2 . 2. these parameters are periodically sampled and not 100% tested. remark these ac characteristics are in common regardless of package types. write cycle timing chart 1 (/we controlled) t wc t cw t wp t as t wr t dw t dh data in address (input) /cs (input) /we (input) d in (input) d out (output) t acs t clz t oh t aa t ow t whz t aw high-z caution /cs or /we should be fixed to high level during address transition. remarks 1. write operation is done during the overlap time of a low level /cs and a low level /we. 2. during t whz , d out pin is in the output state, therefore the input signals must not be applied to the output. 3. when /we is at low level, the d out pin is always high impedance. when /we is at high level, read operation is executed. therefore /oe should be at high level to make the d out pin high impedance.
10 pd434001al data sheet m12223ej7v0ds write cycle timing chart 2 (/cs controlled) t wc t as t cw t aw t wp t wr t dw t dh data in address (input) /cs (input) /we (input) d in (input) d out (output) high-z caution /cs or /we should be fixed to high level during address transition. remark write operation is done during the overlap time of a low level /cs and a low level /we.
11 pd434001al data sheet m12223ej7v0ds package drawings item millimeters b c d e f g h i j k 21.26 0.2 11.18 0.2 3.5 0.2 2.545 0.2 0.8 min. 10.16 m n 9.4 0.20 0.12 1.27(t.p.) 2.6 0.40 0.10 p 1.005 0.1 0.74 p32le-400a-1 u 0.20 0.1 q t r0.85 + 0.10 ? 0.05 note each lead centerline is located within 0.12 mm of its true position (t.p.) at maximum material condition. 32-pin plastic soj (10.16mm (400)) 17 16 32 1 s n m q m g e f t u j i h k b cd p s
12 pd434001al data sheet m12223ej7v0ds note each lead centerline is located within 0.21 mm of its true position (t.p.) at maximum material condition. 32-pin plastic tsop ( ii ) (10.16mm (400)) item millimeters a b c e f g i 21.17 max. 1.27 (t.p.) 1.2 max. 0.97 1.075 max. m n 0.10 10.16 0.1 0.21 0.1 0.05 h 11.76 0.2 d 0.42 j 0.8 0.2 k 0.145 l 0.5 0.1 s32g5-50-7jd2-1 p3 + 7 ? 3 + 0.025 ? 0.015 + 0.08 ? 0.07 m s dm c 32 1 17 16 n b k l j p e f detail of lead end g s a h i
13 pd434001al data sheet m12223ej7v0ds recommended soldering conditions please consult with our sales offices for soldering conditions of the pd434001al. types of surface mount device pd434001alle : 32-pin plastic soj (10.16 mm (400)) pd434001alg5-7jd : 32-pin plastic tsop (ii) (10.16 mm (400)) (normal bent)
14 pd434001al data sheet m12223ej7v0ds [ memo ]
15 pd434001al data sheet m12223ej7v0ds notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 note: 3 status before initialization of mos devices handling of the applied waveform of input pins and the unused input pins for cmos note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. input levels of cmos devices must be fixed. cmos devices behave differently than bipolar or nmos devices. if the input of a cmos device stays in an area that is between v il (max.) and v ih (min.) due to the effects of noise or some other irregularity, malfunction may result. therefore, not only the input waveform is fixed, but also the waveform changes, it is important to use the cmos device under ac test conditions. for unused input pins in particular, cmos devices should not be operated in a state where nothing is connected, so input levels of cmos devices must be fixed to high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices.
pd434001al the information in this document is current as of december, 2002. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such pr oducts. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual pr operty rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third pa rties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a pa rticular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "special": tr ansportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) (1) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. (2) "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). ? ? ? ? ? ? m8e 02. 11-1

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