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latticexp2? family data sheet ds1009 version 01.6, august 2008
www.latticesemi.com 1-1 ds1009 introduction_01.2 february 2008 data sheet ds1009 ? 2008 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. features ? flexiflash? architecture ? instant-on ? infinitely reconfigurable ? single chip ? flashbak? technology ?serial tag memory ?design security ? live update technology ? transfr? technology ? secure updates with 128 bit aes encryption ? dual-boot with external spi ? sysdsp? block ? three to eight blocks for high performance ? multiply and accumulate ? 12 to 32 18x18 multipliers ? each block supports one 36x36 multiplier or four 18x18 or eight 9x9 multipliers ? embedded and distributed memory ? up to 885 kbits sysmem? ebr ? up to 83 kbits distributed ram ? sysclock? plls ? up to four analog plls per device ? clock multiply, divide and phase shifting ? flexible i/o buffer ? sysio? buffer supports: ? lvcmos 33/25/18/15/12; lvttl ? sstl 33/25/18 class i, ii ? hstl15 class i; hstl18 class i, ii ?pci ? lvds, bus-lvds, mlvds, lvpecl, rsds ? pre-engineered source synchronous interfaces ? ddr / ddr2 interfaces up to 200 mhz ? 7:1 lvds interfaces support display applications ?xgmii ? density and package options ? 5k to 40k lut4s, 86 to 540 i/os ? csbga, tqfp, pqfp, ftbga and fpbga packages ? density migration supported ? flexible device configuration ? spi (master and slave) boot flash interface ? dual boot image supported ? soft error detect (sed) macro embedded ? system level support ? ieee 1149.1 and ieee 1532 compliant ? on-chip oscillator for in itialization & general use ? devices operate with 1.2v power supply table 1-1. latticexp2 family selection guide device xp2-5 xp2-8 xp2-17 xp2-30 xp2-40 luts (k) 5 8 172940 distributed ram (kbits) 1018355683 ebr sram (kbits) 166 221 276 387 885 ebr sram blocks 9 12 15 21 48 sysdsp blocks 3 4 5 7 8 18 x 18 multipliers 1216202832 v cc voltage 1.2 1.2 1.2 1.2 1.2 gpll 22444 max available i/o 172 201 358 472 540 packages and i/o combinations 132-ball csbga (8 x 8 mm) 86 86 144-pin tqfp (20 x 20 mm) 100 100 208-pin pqfp (28 x 28 mm) 146 146 146 256-ball ftbga (17 x17 mm) 172 201 201 201 484-ball fpbga (23 x 23 mm) 358 363 363 672-ball fpbga (27 x 27 mm) 472 540 latticexp2 family data sheet introduction
1-2 introduction lattice semiconductor lattice xp2 family data sheet introduction latticexp2 devices combine a look-up table (lut) based fpga fabric with non-volatile flash cells in an architec- ture referred to as flexiflash. the flexiflash approach provides bene fits including instant-on , infinite reconfigurabilit y, on chip storage with flashbak embedded block memory and serial tag memory and design security. the parts also support live update technology wit h transfr, 128-bit aes encryption and dual-boot technologies. the latticexp2 fpga fabric was optimized for the new technology from the outset with high performance and low cost in mind. latticexp2 devices include lut-based logic, distributed and embedded memory, phase locked loops (plls), pre-engineered source synchronous i/o support and enhanced sysdsp blocks. the isplever ? design tool from lattice allows large and complex designs to be efficiently implemented using the latticexp2 family of fpga devices. synthesis library suppo rt for latticexp2 is availabl e for popular logic synthesis tools. the isplever tool uses the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the lattic exp2 device. the isplever tool extrac ts the timing from the routing and back-annotates it into the design for timing verification. lattice provides many pre-designed intellectual property (ip) isplevercore? modules for the latticexp2 family. by using these ips as standardized blocks, designers are free to concentrate on the unique aspects of their design, increasing their productivity.
www.latticesemi.com 2-1 ds1009 architecture_01.4 august 2008 data sheet ds1009 ? 2008 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. architecture overview each latticexp2 device contains an array of logic blocks surrounded by programmable i/o cells (pic). inter- spersed between the rows of logic blocks are rows of sysmem? embedded block ram (ebr) and a row of sys- dsp? digital signal processing blocks as shown in figure 2-1. on the left and right sides of the programmable functional unit (pfu) array, there are non-volatile memory blocks. in configuration mode the nonvolatile memory is programmed via the ieee 1149.1 tap port or the sysconfig? peripheral port. on power up, the configuration data is transferred from the non-volatile memory blocks to the con- figuration sram. with this technology, expensive external configuration memory is not required, and designs are secured from unauthorized read-back. this transfer of data from non-volatile memory to configuration sram via wide busses happens in microseconds, pr oviding an ?instant-on? capability that allows easy interfacing in many applications. latticexp2 devices can also transfer data from the sysmem ebr blocks to the non-volatile memory blocks at user request. there are two kinds of logic blocks, the pfu and the pfu without ram (pff). the pfu contains the building blocks for logic, arithmetic, ram and rom functions. the pff block contains building blocks for logic, arithmetic and rom functions. both pfu and pff blocks are optimized for flexibility allo wing complex designs to be imple- mented quickly and efficiently. logic blocks are arranged in a two-dimensional array. only one type of block is used per row. latticexp2 devices contain one or more rows of sysmem ebr blocks. sysmem ebrs are large dedicated 18kbit memory blocks. each sysmem block can be configured in a variety of depths and widths of ram or rom. in addi- tion, latticexp2 devices contain up to two rows of dsp blocks. each dsp block has multipliers and adder/accumu- lators, which are the buildin g blocks for complex signal processing capabilities. each pic block encompasses two pios (pio pairs) with their respective sysi o buffers. the sysio buffers of the latticexp2 devices are arranged into eight banks, allowing the implementation of a wide variety of i/o standards. pio pairs on the left and right edges of the device can be configured as lvds transmit/receive pairs. the pic logic also includes pre-engineered support to aid in the implementation of high speed source synchronous standards such as 7:1 lvds interfaces, found in many display app lications, and memory interfaces including ddr and ddr2. other blocks provided include plls and configuration functi ons. the latticexp2 architecture provides up to four general purpose plls (gpll) per device. the gpll blocks are located in the corners of the device. the configuration block that supports features such as configuration bit-stream de-encryption, transparent updates and dual boot support is located between banks two and three. every device in the latticexp2 family supports a sysconfig port, muxed with bank seven i/os, which supports serial device configuration. a jtag port is provided between banks two and three. this family also provides an on-chip oscillator and soft error detect (sed) ca pability. latticexp2 devices use 1.2v as their core voltage. latticexp2 family data sheet architecture
2-2 architecture lattice semiconductor lattice xp2 family data sheet figure 2-1. simplified block diagra m, latticexp2-17 device (top level) pfu blocks the core of the latticexp2 device is made up of logic blocks in two forms, pfus and pffs. pfus can be pro- grammed to perform logic, arithmetic, distributed ram and distributed rom functions. pff blocks can be pro- grammed to perform logic, arithmetic and rom functions. except where necessary, the remainder of this data sheet will use the term pfu to refer to both pfu and pff blocks. each pfu block consists of four interconnected slices, numbered slice 0 through slice 3, as shown in figure 2-2. all the interconnections to and from pfu blocks are from routing. there are 50 inputs and 23 outputs associated with each pfu block. on-chip oscillator programmable function units (pfus) spi port sysclock plls flexible routing flash jtag port sysio buffers, pre-engineered source synchronous support sysmem block ram dsp blocks
2-3 architecture lattice semiconductor lattice xp2 family data sheet figure 2-2. pfu diagram slice slice 0 through slice 2 contain two 4-input combinatorial look-up tables (lut4), which feed two registers. slice 3 contains two lut4s and no registers. for pfus, slice 0 and slice 2 can also be configured as distributed memory, a capability not available in pff blocks . table 2-1 shows the capability of th e slices in both pff and pfu blocks along with the operation modes they enable. in addition, each pfu contains logic that allows the luts to be com- bined to perform functions such as lut5, lut6, lut7 and lut8. there is control logic to perform set/reset func- tions (programmable as synchronous/asynchronous), clock select, chip-select and wider ram/rom functions. figure 2-3 shows an overview of the internal logic of the slice. the registers in the slice can be configured as posi- tive/negative edge triggered or level sensitive clocks. table 2-1. resources and modes available per slice slice 0 through slice 2 have 14 input signals: 13 signals from routing and one from the carry-chain (from the adja- cent slice or pfu). there are seven outputs: six to routing and one to carry-chain (to the adjacent pfu). slice 3 has 13 input signals from routing and four signals to routing. table 2-2 lists the signals associated with slice 0 to slice 2. slice pfu block pff block resources modes resources modes slice 0 2 lut4s and 2 registers logic, ripple, ram, rom 2 lut4s and 2 registers logic, ripple, rom slice 1 2 lut4s and 2 registers logic, ripple, rom 2 lut4s and 2 registers logic, ripple, rom slice 2 2 lut4s and 2 registers logic, ripple, ram, rom 2 lut4s and 2 registers logic, ripple, rom slice 3 2 lut4s logic, rom 2 lut4s logic, rom slice 0 lut4 & carry lut4 & carry d d slice 1 lut4 & carry lut4 & carry slice 2 lut4 & carry lut4 & carry from routing to routing slice 3 lut4 lut4 d d d d ff ff ff ff ff ff
2-4 architecture lattice semiconductor lattice xp2 family data sheet figure 2-3. slice diagram table 2-2. slice signal descriptions function type signal names description input data signal a0, b0, c0, d0 inputs to lut4 input data signal a1, b1, c1, d1 inputs to lut4 input multi-purpose m0 multipurpose input input multi-purpose m1 multipurpose input input control signal ce clock enable input control signal lsr local set/reset input control signal clk system clock input inter-pfu signal fci fast carry-in 1 input inter-slice signal fxa intermediate signal to generate lut6 and lut7 input inter-slice signal fxb intermediate signal to generate lut6 and lut7 output data signals f0, f1 lut4 output register bypass signals output data signals q0, q1 register outputs output data signals ofx0 output of a lut5 mux output data signals ofx1 output of a lut6, lut7, lut8 2 mux depending on the slice output inter-pfu signal fco slice 2 of each pfu is the fast carry chain output 1 1. see figure 2-3 for connection details. 2. requires two pfus. lut4 & carry* lut4 & carry* slice a0 c0 d0 ff* ofx0 f0 q0 a1 b1 c1 d1 ci ci co co ce clk lsr ff* ofx1 f1 q1 f/sum f/sum d d m1 fci into slice/pfu, fco from different slice/pfu fco from slice/pfu, fci into different slice/pfu lut5 mux m0 from routing to routing fxb fxa b0 for slices 0 and 2, memory control signals are generated from slice 1 as follows: wck is clk wre is from lsr di[3:2] for slice 2 and di[1:0] for slice 0 data wad [a:d] is a 4bit address from slice 1 lut input * not in slice 3
2-5 architecture lattice semiconductor lattice xp2 family data sheet modes of operation each slice has up to four potential modes of operation: logic, ripple, ram and rom. logic mode in this mode, the luts in each slice are configured as lut4s. a lut4 has 16 possible input combinations. four- input logic functions are generated by programming the lut4. since there are two lut4s per slice, a lut5 can be constructed within one slice. larger luts such as lu t6, lut7 and lut8, can be constructed by concatenating two or more slices. note that a lut8 requires more than four slices. ripple mode ripple mode allows efficient implementation of small arithmetic functions. in ripple mode, the following functions can be implemented by each slice: ? addition 2-bit ? subtraction 2-bit ? add/subtract 2-bit using dynamic control ? up counter 2-bit ? down counter 2-bit ? up/down counter with async clear ? up/down counter with preload (sync) ? ripple mode multiplier building block ? multiplier support ? comparator functions of a and b inputs ? a greater-than-or-equal-to b ? a not-equal-to b ? a less-than-or-equal-to b two carry signals, fci and fco, are generated per slice in this mode, allowing fast arit hmetic functions to be con- structed by concatenating slices. ram mode in this mode, a 16x4-bit distributed single port ram (spr) can be constructed using each lut block in slice 0 and slice 2 as a 16x1-bit memory. slice 1 is used to provide memory address and control signals. a 16x2-bit pseudo dual port ram (pdpr) memory is created by using one slice as the read-write port and the other companion slice as the read-only port. the lattice design tools support the creation of a variety of different size memories. where appropriate, the soft- ware will construct these using distribute d memory primitives that represent th e capabilities of the pfu. table 2-3 shows the number of slices required to implement different distributed ram primitives. for more information on using ram in latticexp2 devices, please see tn1137, latticexp2 memory usage guide . table 2-3. number of slices required for implementing distributed ram rom mode rom mode uses the lut logic; hence, slices 0 through 3 can be used in the rom mode. preloading is accom- plished through the programming interface during pfu configuration. spr 16x4 pdpr 16x4 number of slices 3 3 note: spr = single port ram, pdpr = pseudo dual port ram
2-6 architecture lattice semiconductor lattice xp2 family data sheet routing there are many resources provided in the latticexp2 devices to route signals individually or as busses with related control signals. the routing resources consist of switching circuitry, buffers and metal interconnect (routing) seg- ments. the inter-pfu connections are made with x1 (spans two pfu), x2 (spans three pfu) or x6 (spans seven pfu) connections. the x1 and x2 connections provide fast and ef ficient connections in horizontal and vertical directions. the x2 and x6 resources are buffered to allow both short and long connections routing between pfus. the latticexp2 family has an enhanced routing architec ture to produce a compact design. the isplever design tool takes the output of the synthesis tool and places an d routes the design. generally, the place and route tool is completely automatic, although an interactive routing editor is available to optimize the design. sysclock phase locked loops (pll) the sysclock plls provide the ability to synthesize clock frequencies. the latticexp2 family supports between two and four full featured general purpose plls (gpll). the architecture of the gpll is shown in figure 2-4. clki, the pll reference frequency, is provided either from the pin or from routing; it feeds into the input clock divider block. clkfb, the feedback signal, is generated from clkop (the primary clock output) or from a user clock pin/logic. clkfb feeds into the feedback divider and is used to multiply the reference frequency. both the input path and feedback sign als enter the voltage controlled oscilla tor (vco) block. the phase and fre- quency of the vco are determined from the input path and feedback signals. a lock signal is generated by the vco to indicate that the vco is locked with the input clock signal. the output of the vco feeds into the clkop divider, a po st-scalar divider. the duty cycle of the clkop divider output can be fine tuned using the duty trim block, which creates the clkop signal. by allowing the vco to oper- ate at higher frequencies than clkop, the frequency range of the gpll is expanded. the output of the clkop divider is passed through the clkok divider, a secondary clock divider, to generate lower frequencies for the clkok output. for applications that require even lower frequencies, the clkop signal is passed through a divide- by-three divider to produce the clkok2 output. the clko k2 output is provided for applications that use source synchronous logic. the phase/duty cycle/duty trim block is used to adjust the phase and duty cycle of the clkop divider output to generate the clkos signal. the phase/ duty cycle setting can be pre-programmed or dynamically adjusted. the clock outputs from the gpll; clkop, clkok, clkok2 and clkos, are fed to the clock distribution network. for further information on the gpll please see tn1126, latticexp2 sysclock pll design and usage guide .
2-7 architecture lattice semiconductor lattice xp2 family data sheet figure 2-4. general purpose pll (gpll) diagram table 2-4 provides a description of the signals in the gpll blocks. table 2-4. gpll block signal descriptions clock dividers latticexp2 devices have two clock dividers, one on the left side and one on the right side of the device. these are intended to generate a slower-speed system clock from a high-speed edge clock. the block operates in a 2, 4 or 8 mode and maintains a known phase relationship between the divided down clock and the high-speed clock based on the release of its reset signal. the clock divide rs can be fed from the clkop output from the gplls or from the edge clocks (eclk). the clock divider outputs serv e as primary clock sources and feed into the clock dis- tribution network. the reset (rst) control signal resets the input and forces all outputs to low. the release sig- nal releases outputs to the input clock. for furthe r information on clock dividers, please see tn1126, latticexp2 sysclock pll design and usage guide . figure 2-5 shows the clock divider connections. signal i/o description clki i clock input from external pin or routing clkfb i pll feedback input from clkop (pll internal), from clock net (clkop) or from a user clock (pin or logic) rst i ?1? to reset pll counters, vco, charge pumps and m-dividers rstk i ?1? to reset k-divider dphase [3:0] i dpa phase adjust input ddduty [3:0] i dpa duty cycle select input wrdel i dpa fine delay adjust input clkos o pll output clock to clock tree (phase shifted/duty cycle changed) clkop o pll output clock to clock tree (no phase shift) clkok o pll output to clock tree through secondary clock divider clkok2 o pll output to clock tree (clkop divided by 3) lock o ?1? indicates pll lock to clki clkfb divider rst clkfb clki lock clkop clkos rstk dphase internal feedback dduty wrdel clkok2 clkok clki divider pfd vco/ loop filter clkop divider phase/ duty cycle/ duty trim duty trim clkok divider lock detect 3
2-8 architecture lattice semiconductor lattice xp2 family data sheet figure 2-5. clock divider connections clock distribution network latticexp2 devices have eight quadrant-based primary cloc ks and between six and eight flexible region-based sec- ondary clocks/control signals. two high performance edge clocks are available on each edge of the device to sup- port high speed interfaces. the clock inputs are selected from external i/os, the sysclock plls, or routing. clock inputs are fed throughout the chip via the primary, secondary and edge clock networks. primary clock sources latticexp2 devices derive primary clocks from four sources: pll outputs, clkdiv outputs, dedicated clock inputs and routing. latticexp2 devices have two to four sysclock plls, located in the four corners of the device. there are eight dedicated clock inputs, two on each side of the device. figure 2-6 shows the primary clock sources. rst release 1 2 4 8 clkop (gpll) eclk clkdiv
2-9 architecture lattice semiconductor lattice xp2 family data sheet figure 2-6. primary clock sources for xp2-17 primary clock sources to eight quadrant clock selection from routing from routing gpll gpll pll input pll input note: this diagram shows sources for the xp2-17 device. smaller latticexp2 devices have two gplls. clk div clock input clock input pll input pll input clock input clock input clock input clock input clock input clock input gpll gpll clk div
2-10 architecture lattice semiconductor lattice xp2 family data sheet secondary clock/control sources latticexp2 devices derive secondary clocks (sc0 through sc7) from eight dedicated clock input pads and the rest from routing. figure 2-7 shows the secondary clock sources. figure 2-7. secondary clock sources secondary clock sources from routing from routing from routing from routing from routing from routing from routing from routing from routing from routing clock input clock input clock input clock input clock input clock input from routing from routing from routing from routing clock input clock input from routing from routing
2-11 architecture lattice semiconductor lattice xp2 family data sheet edge clock sources edge clock resources can be driven from a variety of sources at the same edge. edge clock resources can be driven from adjacent edge clock pios, primary clock pios, plls and clock dividers as shown in figure 2-8. figure 2-8. edge clock sources eight edge clocks (eclk) two clocks per edge sources for bottom edge clocks sources for right edge clocks clock input clock input from routing from routing from routing from routing from routing clock input clock input clock input clock input from routing from routing clock input clock input from routing sources for left edge clocks sources for top edge clocks pll input pll input gpll clkop clkos pll input gpll clkop clkos clkop clkos gpll pll input clkop clkos gpll note: this diagram shows sources for the xp2-17 device. smaller latticexp2 devices have two gplls.
2-12 architecture lattice semiconductor lattice xp2 family data sheet primary clock routing the clock routing structure in latticexp2 devices consists of a network of eight primary clock lines (clk0 through clk7) per quadrant. the primary clocks of each quadrant are generated from muxes located in the center of the device. all the clock sources are connected to these muxes. figure 2-9 shows the clock routing for one quadrant. each quadrant mux is identical. if desired, any clock can be routed globally. figure 2-9. per quadrant primary clock selection dynamic clock select (dcs) the dcs is a smart multiplexer function available in the primary clock routing. it switches between two independent input clock sources without any glitches or runt pulses. this is achieved irrespective of when the select signal is toggled. there are two dcs blocks per quadrant; in total, eight dcs blocks per device. the inputs to the dcs block come from the center muxes. the output of the dcs is connected to primary clocks clk6 and clk7 (see figure 2- 9). figure 2-10 shows the timing waveforms of the default dcs operating mode. the dcs block can be programmed to other modes. for more information on the dcs, please see tn1126, latticexp2 sysclock pll design and usage guide . figure 2-10. dcs waveforms secondary clock/control routing secondary clocks in the latticexp2 devices are region-bas ed resources. the benefit of region-based resources is the relatively low injection delay and skew within the region, as compared to primary clocks. ebr rows, dsp rows and a special vertical routing channel bound the secondary clock regions. this special vertical routing channel aligns with either the left edge of the center dsp block in the dsp row or the center of the dsp row. figure 2-11 shows this special vertical routing channel and the eight secondary clock regions for the latticexp2-40. clk0 clk1 clk2 clk3 clk4 clk5 clk6 clk7 30:1 30:1 30:1 30:1 29:1 29:1 29:1 29:1 30:1 30:1 8 primary clocks (clk0 to clk7) per quadrant dcs dcs primary clock sources: plls + clkdivs + pios + routing clk0 sel dcsout clk1
2-13 architecture lattice semiconductor lattice xp2 family data sheet latticexp2-30 and smaller devices have six secondary clock regions. all devices in the latticexp2 family have four secondary clocks (sc0 to sc3) which are distributed to every region. the secondary clock muxes are located in the center of the device. figure 2-12 shows the mux structure of the secondary clock routing. secondary clocks sc0 to sc3 are used for clock and control and sc4 to sc7 are used for high fan-out signals. figure 2-11. secondary clock regions xp2-40 i/o bank 0 i/o bank 7 i/o bank 2 i/o bank 3 i/o bank 6 i/o bank 1 i/o bank 5 i/o bank 4 secondary clock region 1 secondary clock region 2 secondary clock region 3 secondary clock region 4 secondary clock region 5 secondary clock region 6 secondary clock region 7 secondary clock region 8 vertical routing channel regional boundary dsp row regional boundary ebr row regional boundary ebr row regional boundary
2-14 architecture lattice semiconductor lattice xp2 family data sheet figure 2-12. secondary clock selection slice clock selection figure 2-13 shows the clock selections and figure 2-14 shows the control selections for slice0 through slice2. all the primary clocks and the four secondary clocks are routed to this clock selection mux. other signals, via routing, can be used as clock inputs to the slices. slice controls are generated from the secondary clocks or other signals connected via routing. if none of the signals are selected for both clock and control, then the default value of the mux output is 1. slice 3 does not have any registers; therefore it does not have the clock or control muxes. figure 2-13. slice0 through slice2 clock selection sc0 sc1 sc2 sc3 sc4 sc5 24:1 24:1 24:1 sc6 sc7 24:1 24:1 24:1 24:1 24:1 4 secondary clocks/ce/lsr (sc0 to sc3) per region clock/control secondary clock feedlines: 8 pios + 16 routing high fan-out data 4 high fan-out data signals (sc4 to sc7) per region clock to slice primary clock secondary clock routing vcc 8 4 12 1 25:1
2-15 architecture lattice semiconductor lattice xp2 family data sheet figure 2-14. slice0 through slice2 control selection edge clock routing latticexp2 devices have eight high-speed edge clocks th at are intended for use with the pios in the implementa- tion of high-speed interfaces. each device has two edge clocks per edge. figure 2-15 shows the selection muxes for these clocks. figure 2-15. edge clock mux connections slice control secondary clock routing vcc 3 12 1 16:1 left and right edge clocks eclk1 top and bottom edge clocks eclk1/ eclk2 clock input pad routing routing input pad gpll input pad gpll output clkop left and right edge clocks eclk2 routing input pad gpll input pad gpll output clkos (both muxes)
2-16 architecture lattice semiconductor lattice xp2 family data sheet sysmem memory latticexp2 devices contains a number of sysmem embe dded block ram (ebr). the ebr consists of 18 kbit ram with dedicated input and output registers. sysmem memory block the sysmem block can implement single port, dual port or pseudo dual port memories. each block can be used in a variety of depths and widths as shown in table 2-5. fifos can be implemented in sysmem ebr blocks by using support logic with pfus. the ebr block supports an optional pa rity bit for each data byte to facilitate parity check- ing. ebr blocks provide byte-enable support for configurations with18-bit and 36-bit data widths. table 2-5. sysmem block con? gurations bus size matching all of the multi-port memory modes support different widths on each of the ports. the ram bits are mapped lsb word 0 to msb word 0, lsb word 1 to msb word 1, and so on. although the word size and number of words for each port varies, this mapping scheme applies to each port. flashbak ebr content storage all the ebr memory in the latticexp2 is shadowed by fl ash memory. optionally, initia lization values for the mem- ory blocks can be defined using the la ttice isplever tools. the initialization values ar e loaded into the flash memory during device programming and into the sram at power up or whenever the device is reconfigured. this feature is ideal for the storage of a variety of information such as look-up tables and microprocessor code. it is also possible to write the curren t contents of the ebr memory back to flash memory. this capability is useful for the storage of data such as error codes and calibration information. for additional information on the flashbak capa- bility see tn1137, latticexp2 memory usage guide . memory mode configurations single port 16,384 x 1 8,192 x 2 4,096 x 4 2,048 x 9 1,024 x 18 512 x 36 true dual port 16,384 x 1 8,192 x 2 4,096 x 4 2,048 x 9 1,024 x 18 pseudo dual port 16,384 x 1 8,192 x 2 4,096 x 4 2,048 x 9 1,024 x 18 512 x 36
2-17 architecture lattice semiconductor lattice xp2 family data sheet figure 2-16. flashbak technology memory cascading larger and deeper blocks of rams can be created usin g ebr sysmem blocks. typically, the lattice design tools cascade memory transparently, based on speci? c design inputs. single, dual and pseudo-dual port modes in all the sysmem ram modes the input data and address for the ports are registered at the input of the memory array. the output data of the memory is optionally registered at the output. ebr memory supports two forms of write behavior for single port or dual port operation: 1. normal ? data on the output appears only during a read cycle. during a write cycle, the data (at the current address) does not appear on the output. this mode is supported for all data widths. 2. write through ? a copy of the input data appears at the output of the same port during a write cycle. this mode is supported for all data widths. memory core reset the memory array in the ebr utilizes la tches at the a and b out put ports. these latches can be reset asynchro- nously or synchronously. rsta and rstb are local signal s, which reset the output latches associated with port a and port b respectively. gsrn, the global reset signal, resets both ports. the output data latches and associated resets for both ports are as shown in figure 2-17. figure 2-17. memory core reset flash ebr jtag / spi port fpga logic write from flash to ebr during configuration / write from ebr to flash on user command make infinite reads and writes to ebr write to flash during programming q set d l clr output data latches memory core port a[17:0] q set d port b[17:0] rstb gsrn pro g rammable disable rsta l clr
2-18 architecture lattice semiconductor lattice xp2 family data sheet for further information on the sysmem ebr block, please see tn1137, latticexp2 memory usage guide . ebr asynchronous reset ebr asynchronous reset or gsr (if used) can only be applied if all clock enables are low for a clock cycle before the reset is applied and released a clock cycle after the low-to-hi gh transition of the reset signal, as shown in figure 2-18. the gsr input to the ebr is always asynchronous. figure 2-18. ebr asynchronous reset (including gsr) timing diagram if all clock enables remain enabled, the ebr asynchronous reset or gsr may only be applied and released after the ebr read and write clock inputs are in a steady state condition for a minimum of 1/f max (ebr clock). the reset release must adhere to the ebr synchronous reset setup time before the next active read or write clock edge. if an ebr is pre-loaded during configuration, the gsr input must be disabled or the release of the gsr during device wake up must occur before the release of the device i/os becoming active. these instructions apply to all ebr ram and rom implementations. note that there are no reset restrictions if the ebr syn chronous reset is used and the ebr gsr input is disabled. sysdsp? block the latticexp2 family provides a sysdsp block making it id eally suited for low cost, high performance digital sig- nal processing (dsp) applications. typical functions used in these applications include bit correlators, fast fourier transform (fft) functions, finite impulse response (fir ) filter, reed-solomon encoder/decoder, turbo encoder/ decoder and convolutional encoder/decoder. these complex signal processing functions use similar building blocks such as multiply-adders and multiply-accumulators. sysdsp block approach comp are to general dsp conventional general-purpose dsp chips typically contain one to four (multiply and accumulate) mac units with ? xed data-width multipliers; this leads to limited parallelism and limited throughput. their throughput is increased by higher clock speeds. the latticexp2 family, on the other hand, has many dsp blocks that support different data- widths. this allows the designer to us e highly parallel implementations of dsp functions. the designer can opti- mize the dsp performance vs. area by choosing appropriate levels of parallelism. figure 2-19 compares the fully serial and the mixed parallel and serial implementations. reset clock clock enable
2-19 architecture lattice semiconductor lattice xp2 family data sheet figure 2-19. comparison of general dsp and latticexp2 approaches sysdsp block capabilities the sysdsp block in the latticexp2 family supports four functional elements in three 9, 18 and 36 data path widths. the user selects a function element for a dsp block and then selects the width and type (signed/unsigned) of its operands. the operands in the latticexp2 family sysdsp blocks can be either signed or unsigned but not mixed within a function element. similarly, the operand widths cannot be mixed within a block. dsp elements can be concatenated. the resources in each sysdsp block can be con? gured to support the following four elements: ? mult (multiply) ? mac (multiply, accumulate) ? multaddsub (multiply, addition/subtraction) ? multaddsubsum (multiply, addition/subtraction, accumulate) the number of elements available in each block depends on the width selected from the three available options: x9, x18, and x36. a number of these elements are concatenat ed for highly parallel implementations of dsp functions. table 2-6 shows the capabilities of the block. table 2-6. maximum number of elements in a block some options are available in four elements. the input regist er in all the elements can be directly loaded or can be loaded as shift register from previous operand registers. by selecting ?dynamic operation? the following operations are possible: width of multiply x9 x18 x36 mult 841 mac 2 2 ? multaddsub 4 2 ? multaddsubsum 2 1 ? multiplier 0 x operand a operand b x operand a operand b x operand a operand b multiplier 1 multiplier k (k adds) output m/k loops single multiplier x operand a accumulator operand b m loops function implemented in general purpose dsp function implemented in latticexp2 m/k accumulate + +
2-20 architecture lattice semiconductor lattice xp2 family data sheet ? in the ?signed/unsigned? options the operands can be switched between signed and unsigned on every cycle. ? in the ?add/sub? option the accumulator can be switched between addition and subtraction on every cycle. ? the loading of operands can switch between parallel and serial operations. mult sysdsp element this multiplier element implements a multiply with no addition or accumulator nodes. the two operands, a and b, are multiplied and the result is available at the output. the user can enable the input/output and pipeline registers. figure 2-20 shows the mult sysdsp element. figure 2-20. mult sysdsp element multiplier x n m m n m n m n n m m+n m+n (default) clk (clk0,clk1,clk2,clk3) ce (ce0,ce1,ce2,ce3) rst(rst0,rst1,rst2,rst3) pipeline register input register multiplier multiplicand signed a shift register a in shift register b in shift register a out shift register b out output input data register a input data register b output register to multiplier input register signed b to multiplier
2-21 architecture lattice semiconductor lattice xp2 family data sheet mac sysdsp element in this case, the two operands, a and b, are multiplied and the result is added with the previous accumulated value. this accumulated value is available at the output. the user can enable the input and pipeline registers but the out- put register is always enabled. the output register is used to store the accumulated value. the accumulators in the dsp blocks in latticexp2 family can be initialized dynamically. a registered over flow signal is also available. the over? ow conditions are provided later in this document. figure 2-21 shows the mac sysdsp element. figure 2-21. mac sysdsp multiplier x input data register a n m input data register b m n n n m n n m output register output register accumulator multiplier multiplicand signed a serial register b in serial register a in srob sroa output addn accumsload pipeline clk (clk0,clk1,clk2,clk3) ce (ce0,ce1,ce2,ce3) rst(rst0,rst1,rst2,rst3) input pipeline register input register pipeline register input register pipeline register to accumulator signed b pipeline input to accumulator to accumulator to accumulator overflow signal m+n (default) m+n+16 (default) m+n+16 (default) preload register register register register
2-22 architecture lattice semiconductor lattice xp2 family data sheet multaddsub sysdsp element in this case, the operands a0 and b0 are multiplied and the result is added/subtracted with the result of the multi- plier operation of operands a1 and b1. the user can enable the input, output and pipeline registers. figure 2-22 shows the multaddsub sysdsp element. figure 2-22. multaddsub multiplier multiplier add/sub pipe reg pipe reg n m m n m n m n n m m+n (default) m+n+1 (default) m+n+1 (default) m+n (default) x x n m m n m n n m multiplier b0 multiplicand a0 multiplier b1 multiplicand a1 signed a shift register a in shift register b in shift register a out shift register b out output addn pipeline register clk (clk0,clk1,clk2,clk3) ce (ce0,ce1,ce2,ce3) rst (rst0,rst1,rst2,rst3) input register pipeline register input register pipeline register pipeline register pipe reg signed b pipeline register input register input data register a input data register a input data register b input data register b output register to add/sub to add/sub to add/sub
2-23 architecture lattice semiconductor lattice xp2 family data sheet multaddsubsum sysdsp element in this case, the operands a0 and b0 are multiplied and the result is added/subtracted with the result of the multi- plier operation of operands a1 and b1. additionally the operands a2 and b2 are multiplied and the result is added/ subtracted with the result of the multiplier operation of operands a3 and b3. the result of both addition/subtraction are added in a summation block. the user can enable the input, output and pipeline registers. figure 2-23 shows the multaddsubsum sysdsp element. figure 2-23. multaddsubsum clock, clock enable and reset resources global clock, clock enable (ce) and reset (rst) signals from routing are available to every dsp block. from four clock sources (clk0, clk1, clk2, clk3) one clock is selected for each input register, pipeline register and output multiplier add/sub0 x n m m+n (default) m+n (default) m+n+1 m+n+2 m+n+2 m+n+1 m+n (default) m+n (default) m n m n m n n m x n n m n n m multiplier multiplier multiplier add/sub1 x n m m n m n m n n m x n m m n m n n m sum multiplier b0 multiplicand a0 multiplier b1 multiplicand a1 multiplier b2 multiplicand a2 multiplier b3 multiplicand a3 signed a shift register b in output addn0 pipeline register clk (clk0,clk1,clk2,clk3) ce (ce0,ce1,ce2,ce3) rst(rst0,rst1,rst2,rst3) input register pipeline register input register to add/sub0 to add/sub0, add/sub1 pipeline register signed b pipeline register input register to add/sub0, add/sub1 pipeline register input register to add/sub1 addn1 pipeline register pipeline register pipeline register shift register a in shift register b out shift register a out input data register a input data register a input data register a input data register a input data register b input data register b input data register b input data register b output register
2-24 architecture lattice semiconductor lattice xp2 family data sheet register. similarly, ce and rst are selected from their four respective sources (ce0, ce1, ce2, ce3 and rst0, rst1, rst2, rst3) at each input register, pipeline register and output register. signed and unsigned with different widths the dsp block supports other widths, in addition to x9, x18 and x36 widths, of signed and unsigned multipliers. for unsigned operands, unused upper data bits should be ? lled to create a valid x9, x18 or x36 operand. for signed two?s complement operands, sign extension of the most signi? cant bit should be performed until x9, x18 or x36 width is reached. table 2-7 provides an example of this. table 2-7. sign extension example overflow flag from mac the sysdsp block provides an overflow output to indicate that the accumulator has overflowed. ?roll-over? occurs and an overflow signal is indicated when any of the following is true: two unsigned numbers are added and the result is a smaller number than the accumulator, two positive numbers are added with a negative sum or two nega- tive numbers are added with a positive sum. note that when overflow occurs the overflow flag is present for only one cycle. by counting these overflow pulses in fpga logic, larger accumulators can be constructed. the condi- tions for the overflow signal for signed and unsigned operands are listed in figure 2-24. figure 2-24. accumulator over? ow/under? ow number unsigned unsigned 9-bit unsigned 18-bit signed two?s complement signed 9 bits two?s complement signed 18 bits +5 0101 000000101 000000000000000101 0101 000000101 000000000000000101 -6 n/a n/a n/a 1010 111111010 111111111111111010 000000000 000000001 000000010 000000011 111111101 111111110 111111111 overflow signal is generated for one cycle when this boundary is crossed 0 +1 +2 +3 -3 -2 -1 unsigned operation signed operation 255 254 253 252 -254 -255 -256 000000000 000000001 000000010 000000011 111111101 111111110 111111111 carry signal is generated for one cycle when this boundary is crossed 0 1 2 3 509 510 511 255 254 253 252 258 257 256 011111100 011111101 011111110 011111111 100000000 100000001 100000010 011111100 011111101 011111110 011111111 100000000 100000001 100000010
2-25 architecture lattice semiconductor lattice xp2 family data sheet ipexpress? the user can access the sysdsp block via the isplever ipex press tool, which provides the option to configure each dsp module (or group of modules), or by direct hdl instantiation. in addition, lattice has partnered with the mathworks ? to support instanti ation in the simulink ? tool, a graphical simulation environment. simulink works with isplever to dramatically shorten the dsp design cycle in lattice fpgas. optimized dsp functions lattice provides a library of optimized dsp ip function s. some of the ip cores planned for the latticexp2 dsp include the bit correlator, fft functions, fir filter, re ed-solomon encoder/decoder, turbo encoder/decoder and convolutional encoder/decoder. please contact lattice to obtain the latest list of available dsp ip cores. resources available in the latticexp2 family table 2-8 shows the maximum number of multipliers for each member of the latticexp2 family. table 2-9 shows the maximum available ebr ram blocks and serial tag me mory bits in each latticexp2 device. ebr blocks, together with distributed ram can be used to store variables locally for fast dsp operations. table 2-8. maximum number of dsp blocks in the latticexp2 family table 2-9. embedded sram/tag memory in the latticexp2 family latticexp2 dsp performance table 2-10 lists the maximum performanc e in millions of mac (mmac) operatio ns per second for each member of the latticexp2 family. table 2-10. dsp performance for further information on the sysdsp block, please see tn1140, latticexp2 sysdsp usage guide . device dsp block 9x9 multiplier 18 x18 multiplier 36x36 multiplier xp2-5 3 24 12 3 xp2-8 4 32 16 4 xp2-17 5 40 20 5 xp2-30 7 56 28 7 xp2-40 8 64 32 8 device ebr sram block total ebr sram (kbits) tag memor y (bits) xp2-5 9 166 632 xp2-8 12 221 768 xp2-17 15 276 2184 xp2-30 21 387 2640 xp2-40 48 885 3384 device dsp block dsp performance mmac xp2-5 3 3,900 xp2-8 4 5,200 xp2-17 5 6,500 xp2-30 7 9,100 xp2-40 8 10,400
2-26 architecture lattice semiconductor lattice xp2 family data sheet programmable i/o cells (pic) each pic contains two pios connected to their respecti ve sysio buffers as shown in figure 2-25. the pio block supplies the output data (do) and the tri-state control signal (to) to the sysio buffer and receives input from the buffer. table 2-11 provides the pio signal list. figure 2-25. pic diagram two adjacent pios can be joined to provide a differential i/o pair (labeled as ?t? and ?c?) as shown in figure 2-25. the pad labels ?t? and ?c? distinguish the two pios. approximately 50% of the pio pairs on the left and right edges of the device can be configured as true lvds outputs. all i/o pairs can operate as inputs. opos1 oneg1 td inck 2 indd inff ipos0 ipos1 clk ce lsr gsrn clk1 clk0 ceo cei sysio buffer pada ?t? pad b ?c? lsr gsr eclk1 ddrclkpol 1 1. signals are available on left/right/bottom edges only. 2. selected blocks. iold0 di tristate register block output register block input register block control muxes piob pioa opos0 opos2 1 oneg0 oneg2 1 dqsxfer 1 dqs del qpos1 1 qneg1 1 qneg0 1 qpos0 1 iolt0 eclk2
2-27 architecture lattice semiconductor lattice xp2 family data sheet table 2-11. pio signal list pio the pio contains four blocks: an input register block, output register block, tristate register block and a control logic block. these blocks contain registers for operating in a variety of modes along with necessary clock and selection logic. input register block the input register blocks for pios contain delay elements and registers that can be used to condition high-speed interface signals, such as ddr memory interfaces and source sy nchronous interfaces, befo re they are passed to the device core. figure 2-26 shows the diagram of the input register block. input signals are fed from the sysio buffer to the input register block (as signal di). if desired, the input signal can bypass the register and delay elements and be used directly as a combinatorial signal (indd), a clock (inck) and, in selected blocks, the input to the dqs delay block. if an input delay is desired, designers can select either a fixed delay or a dynamic delay del[3:0]. the delay, if selected, reduces input register hold time requirements when using a global clock. the input block allows three modes of operation. in the single data rate (sdr) mode, the data is registered, by one of the registers in the sdr sync register block, with the system clock. in ddr mode two registers are used to sample the data on the positive and negative edges of the dqs signal which creates two data streams, d0 and d2. d0 and d2 are synchronized with the system clock before en tering the core. further information on this topic can be found in the ddr memory support section of this data sheet. by combining input blocks of the complementary pios and sharing registers from output blocks, a gearbox function can be implemented, that takes a double data rate signal applied to pioa and converts it as four data streams, ipos0a, ipos1a, ipos0b and ipos1b. figure 2-26 shows the diagram using this gearbox function. for more information on this topic, please see tn1138, latticexp2 high speed i/o interface . name type description ce control from the core clock enables for input and output block flip-flops clk control from the core system clocks for input and output blocks eclk1, eclk2 control from the core fast edge clocks lsr control from the core local set/reset gsrn control from routing global set/reset (active low) inck 2 input to the core input to primary clock network or pll reference inputs dqs input to pio dqs signal from logic (routing) to pio indd input to the core unregistered data input to core inff input to the core registered input on positive edge of the clock (clk0) ipos0, ipos1 input to the core double data rate registered inputs to the core qpos0 1 , qpos1 1 input to the core gearbox pipelined inputs to the core qneg0 1 , qneg1 1 input to the core gearbox pipelined inputs to the core opos0, oneg0, opos2, oneg2 output data from the core output signal s from the core for sdr and ddr operation opos1 oneg1 tristate control from the core signal s to tristate register block for ddr operation del[3:0] control from the core dy namic input delay control bits td tristate control from the core tristate signal from the core used in sdr operation ddrclkpol control from clock polarity bus controls the pola rity of the clock (clk0) that feed the ddr input block dqsxfer control from core controls signal to the output block 1. signals available on left/right/bottom only. 2. selected i/o.
2-28 architecture lattice semiconductor lattice xp2 family data sheet the signal ddrclkpol controls the pola rity of the clock used in the synchr onization registers. it ensures ade- quate timing when data is transferred from the dqs to system clock domain. for further discussion on this topic, see the ddr memory section of this data sheet. figure 2-26. input register block output register block the output regist er block provides the ability to register signals from the core of the device before they are passed to the sysio buffers. the blocks on the pios on the left, right and bottom contain regist ers for sdr operation that are combined with an additional latch for ddr operation. figure 2-27 shows the diagram of the output register block for pios. in sdr mode, oneg0 feeds one of the flip-flops that then feeds the output. the flip-flop can be configured as a d- type or latch. in ddr mode, oneg0 and opos0 are fed into registers on the positive edge of the clock. at the next clock cycle the registered opos0 is latched. a multiplexer running off the same clock cycle selects the correct reg- ister to feed the output (d0). by combining output blocks of the complementary pios and sharing some registers from input blocks, a gearbox function can be implemented, to take four data streams oneg0a, oneg1a, oneg1b and oneg1b. figure 2-27 clock transfer registers clock transfer registers sdr & sync registers d1 d2 d0 ddr registers d q d-type d q d-type d q d-type d q d-type /latch d q d-type 0 1 d q d q 0 1 fixed delay dynamic delay di (from sysio buffer) di (from sysio buffer) inck 2 indd ipos0a qpos0a ipos1a qpos1a del [3:0] clk0 (of pio a) delayed dqs 0 1 clka dq d q d q 0 1 0 1 d q d q 0 1 d q d q 0 1 fixed delay dynamic delay inck 2 indd ipos0b qpos0b ipos1b qpos1b del [3:0] clk0 (of pio b) delayed dqs clkb /latch true pio (a) in lvds i/o pair comp pio (b) in lvds i/o pair d-type 1 d-type 1 d-type /latch d-type /latch d-type 1 d-type 1 from routing to routing d1 d2 d0 ddr registers sdr & sync registers 0 1 ddrsrc gearbox configuration bit ddrclkpol ddrclkpol 1. shared with output register 2. selected pio. note: simplified version does not show ce and set/reset details from routing to routing to dqs delay block 2 to dqs delay block 2 d-type d-type d-type
2-29 architecture lattice semiconductor lattice xp2 family data sheet shows the diagram using this gearbox function. for more information on this topic, see tn1138, latticexp2 high speed i/o interface . figure 2-27. output and tristate block clock transfer registers oneg1 clka to opos1 from routing td dq dq dq 0 1 0 1 0 1 dq dq dq 0 1 0 1 d q d-type * d q latch d q 0 1 0 1 0 1 0 1 oneg0 opos0 do programmable control programmable control 0 1 eclk1 eclk2 clk1 tristate logic tristate logic output logic true pio (a) in lvds i/o pair to sysio buf fer oneg1 clkb to opos1 from routing td d q d q d q 0 1 0 1 0 1 d q d-type /latch d-type /latch d-type /latch d-type /latch dq dq 0 1 0 1 d q dq latch d-type d-type latch latch d-type latch d-type latch dq oneg0 opos0 do eclk1 eclk2 clk1 output logic to sysio buff er comp pio (b) in lvds i/o pair (clkb) (clka) d-type * d-type* d-type* clock transfer registers ddr output registers ddr output registers * shared with input register note: simplified version does not show ce and set/reset details 0 1 dqsxfer dqsxfer 0 1 0 1
2-30 architecture lattice semiconductor lattice xp2 family data sheet tristate register block the tristate register block prov ides the ability to register tr i-state control signals from t he core of the device before they are passed to the sysio buffers. the block contains a register for sdr operation and an additional latch for ddr operation. figure 2-27 shows the tristate register block with the output block in sdr mode, oneg1 feeds one of the flip-flops that then feeds the output. the flip-flop can be configured as d- type or latch. in ddr mode, oneg1 and opos1 are fed into registers on the positive edge of the clock. then in the next clock the registered opos1 is latched. a multiplexer running off the same clock cycle selects the correct register for feeding to the output (d0). control logic block the control logic block allows the selection and modification of control signals for use in the pio block. a clock sig- nal is selected from general purpose routing, eclk1, eclk2 or a dqs signal (from the programmable dqs pin) and is provided to the input register block. the clock can optionally be inverted. ddr memory support pics have additional circuitry to allow implementation of high speed source synchronous and ddr memory inter- faces. pics have registered element s that support ddr memory interfaces. inte rfaces on the left and right edges are designed for ddr memories that support 16 bits of data, whereas interfaces on the top and bottom are designed for memories that support 18 bits of data. one of every 16 pios on the left and right and one of every 18 pios on the top and bottom contain delay elem ents to facilitate the gene ration of dqs signals. the dqs signals feed the dqs buses which span the set of 16 or 18 pios. figure 2-28 and figure 2-29 show the dqs pin assignments in each set of pios. the exact dqs pins are shown in a dual function in the lo gic signal connections table in this data sheet. addi- tional detail is provided in the signal descriptions table. the dqs signal from the bus is used to strobe the ddr data from the memory into input register blocks. for additional information on using ddr memory support please see tn1138, latticexp2 high speed i/o interface .
2-31 architecture lattice semiconductor lattice xp2 family data sheet figure 2-28. dqs input routing (left and right) figure 2-29. dqs input routing (top and bottom) pio b pio a pio b pio a assigned dqs pin dqs delay sysio buffer pada "t" padb "c" lvds pair pada "t" padb "c" lvds pair pio a pio b pada "t" padb "c" lvds pair pio a pio b pada "t" padb "c" lvds pair pio a pio b pada "t" padb "c" lvds pair pio a pio b pada "t" padb "c" lvds pair pio a pio b pada "t" padb "c" lvds pair pio a pio b pada "t" padb "c" lvds pair pio b pio a pio b pio a assigned dqs pin dqs delay sysio buffer pada "t" padb "c" lvds pair pada "t" padb "c" lvds pair pio a pio b pada "t" padb "c" lvds pair pio a pio b pada "t" padb "c" lvds pair pio a pio b pada "t" padb "c" lvds pair pio a pio b pada "t" padb "c" lvds pair pio a pio b pada "t" padb "c" lvds pair pio b pio a pada "t" padb "c" lvds pair pio a pio b pada "t" padb "c" lvds pair
2-32 architecture lattice semiconductor lattice xp2 family data sheet dll calibrated dqs delay block source synchronous interfaces generally require the input clock to be adjusted in order to correctly capture data at the input register. for most interfaces a pll is used for this adjustment. however, in ddr memories the clock, referred to as dqs, is not free-running, and this approach cannot be used. the dqs delay block provides the required clock alignment fo r ddr memory interfaces. the dqs signal (selected pios only, as shown in figure 2-30) feeds from the pad through a dqs delay element to a dedicated dqs routing resource. the dqs signal also feeds polarity control logic which controls the polarity of the clock to the sync registers in the input register blocks. figure 2-30 and figure 2-31 show how the dqs transi- tion signals are routed to the pios. the temperature, voltage and process variations of the dqs delay block are compensated by a set of 6-bit bus cal- ibration signals from two dedicated dlls (ddr_dll) on opposite sides of the device. each dll compensates dqs delays in its half of the device as shown in figure 2-30. the dll loop is compensated for temperature, volt- age and process variations by the system clock and feedback loop. figure 2-30. edge clock, dll calibr ation and dqs local bus distribution i/o bank 5 i/o bank 6 i/o bank 7 i/o bank 2 i/o bank 3 i/o bank 4 i/o bank 0 i/o bank 1 ddr_dll (right) ddr_dll (left) eclk1 eclk2 delayed dqs polarity control dqsxfer dqs delay control bus dqs input spans 18 pios top & bottom sides spans 16 pios left & right sides
2-33 architecture lattice semiconductor lattice xp2 family data sheet figure 2-31. dqs local bus polarity control logic in a typical ddr memory interface design, the phase relationship between the incoming delayed dqs strobe and the internal system clock (during the read cycle) is unknown. the latticexp2 family contains dedicated circuits to transfer data between these domains. to prevent set-up and hold violations, at the domain transfer between dqs (delayed) and the system clock, a clock polarity selector is used. this changes the edge on which the data is regis- tered in the synchronizing registers in the input register block and requires evaluation at the start of each read cycle for the correct clock polarity. prior to the read operation in ddr me mories, dqs is in tristate (pulled by termination). the ddr memory device drives dqs low at the start of the preamble state. a dedicated circuit detects this transition. this signal is used to control the polarity of the clock to the synchronizing registers. sysio buffer ddr datain pad di clk1 cei pio sysio buffer gsr dqs to sync reg. dqs to ddr reg. dqs strobe pad pio dqsdel polarity control logic dqs calibration bus from dll dqsxfer output register block input register block dqsxfer dcntl[6:0] polarit y control dqs di dqsxferdel* dqsxfer dcntl[6:0] *dqsxferdel shifts eclk1 by 90% and is not associated with a particular pio. dcntl[6:0] eclk1 clk1 eclk2 eclk1
2-34 architecture lattice semiconductor lattice xp2 family data sheet dqsxfer latticexp2 devices provide a dqsxfer signal to the output buffer to assist it in data transfer to ddr memories that require dqs strobe be shifted 90 o . this shifted dqs strobe is generated by the dqsdel block. the dqsxfer signal runs the span of the data bus. sysio buffer each i/o is associated with a ? exible buffer referred to as a sysio buffer. these buffers are arranged around the periphery of the device in groups referred to as banks. the sysio buffers allow users to implement the wide variety of standards that are found in today?s systems including lvcm os, sstl, hstl, lvds and lvpecl. sysio buffer banks latticexp2 devices have eight sysio buffer banks for user i/os arranged two per side. each bank is capable of sup- porting multiple i/o standards. each sysio bank has its own i/o supply voltage (v ccio ). in addition, each bank has voltage references, v ref1 and v ref2 , that allow it to be completely independent from the others. figure 2-32 shows the eight banks and their associated supplies. in latticexp2 devices, single-ended output buffers and ratioed input buffers (lvttl, lvcmos and pci) are pow- ered using v ccio . lvttl, lvcmos33, lvcmos25 and lvcmos12 can also be set as fixed threshold inputs inde- pendent of v ccio . each bank can support up to two separate v ref voltages, v ref1 and v ref2 , that set the threshold for the refer- enced input buffers. some dedicated i/o pins in a bank c an be configured to be a reference voltage supply pin. each i/o is individually configurable based on the bank?s supply and reference voltages. figure 2-32. latticexp2 banks v ref1(2) gnd b ank 2 v ccio2 v ref2(2) v ref1(3) gnd ban k 3 v ccio3 v ref2(3) v ref1(7) gnd ban k 7 v ccio7 v ref2(7) v ref1(6) gnd ban k 6 v ccio6 v ref2(6) bank 5 bank 4 v ref 1 (0 ) g nd bank 0 v cci o0 v ref2(0) v re f1 (1 ) gnd bank 1 v cc io1 v ref2(1 ) lef t right top v ref1(5 ) gnd v ccio5 v ref 2(5 ) v ref1(4) gnd v ccio4 v ref 2(4) bottom
2-35 architecture lattice semiconductor lattice xp2 family data sheet latticexp2 devices contain two types of sysio buffer pairs. 1. top and bottom (banks 0, 1, 4 and 5) sysio buffer pairs (single-ended outputs only) ? the sysio buffer pairs in the top banks of the device consist of two single-ended output drivers and two sets of single-ended input buffers (both ratioed and referenced). one of the referenced input buffers can also be con - figured as a differential input. ? ? the two pads in the pair are described as ?true? and ?c omp?, where the true pad is associated with the positive side of the differential input buffer and the comp (complementary) pad is associated with the negative side of the differential input buffer. ? ? only the i/os on the top and bottom banks have programmable pci clamps. 2. left and right (banks 2, 3, 6 and 7) sysio buffer pairs (50% differential and 100% single-ended outputs) ? the sysio buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two sets of single-ended input buffers (both ratioed and referenced) and one differential output driver. one of the ref- erenced input buffers can also be configured as a differential input. ? ? the two pads in the pair are described as ?true? and ?c omp?, where the true pad is associated with the positive side of the differential i/o, and the comp pad is associated with the negative side of the differential i/o. ? ? lvds differential output drivers are available on 50% of the buffer pairs on the left and right banks. typical sysio i/o beha vior during power-up the internal power-on-reset (por) signal is deactivated when v cc and v ccaux have reached satisfactory levels. after the por signal is deacti vated, the fpga core logic becomes active. it is the user?s resp onsibility to ensure that all other v ccio banks are active with valid input logic levels to properly control the output logic states of all the i/o banks that are critical to the application. for more information on controlling the output logic state with valid input logic levels during power-up in latticexp2 devices, please see tn1136, latticexp2 sysio usage guide . the v cc and v ccaux supply the power to the fpga core fabric, whereas the v ccio supplies power to the i/o buf- fers. in order to simplify system design while providing consistent and predictable i/o behavior, it is recommended that the i/o buffers be powered-up prior to the fpga core fabric. v ccio supplies should be powered-up before or together with the v cc and v ccaux supplies. supported sysio standards the latticexp2 sysio buffer supports both single-ended and differential standards. single-ended standards can be further subdivided into lvcmos, lvttl and other standards. the buffers support the lvttl, lvcmos 1.2v, 1.5v, 1.8v, 2.5v and 3.3v standards. in the lvcmos and lvttl modes, the buffer has individual configuration options for drive strength, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper latch) and open drain. other single-ended standards supported include sstl and hstl. differential standards supported include lvds, mlvds, blvds, lvpecl, rsds, differential sstl and diff erential hstl. tables 2-12 and 2-13 show the i/o stan- dards (together with their supply and reference voltages) supported by latticexp2 devices. for further information on utilizing the sysio buffer to support a variety of standards please see tn1136, latticexp2 sysio usage guide .
2-36 architecture lattice semiconductor lattice xp2 family data sheet table 2-12. supported input standards input standard v ref (nom.) v ccio 1 (nom.) single ended interfaces lv t t l ? ? lv c m o s 3 3 ? ? lv c m o s 2 5 ? ? lv c m o s 1 8 ? 1 . 8 lv c m o s 1 5 ? 1 . 5 lv c m o s 1 2 ? ? pci33 ? ? hstl18 class i, ii 0.9 ? hstl15 class i 0.75 ? sstl33 class i, ii 1.5 ? sstl25 class i, ii 1.25 ? sstl18 class i, ii 0.9 ? differential interfaces differential sstl18 class i, ii ? ? differential sstl25 class i, ii ? ? differential sstl33 class i, ii ? ? differential hstl15 class i ? ? differential hstl18 class i, ii ? ? lvds, mlvds, lvpecl, blvds, rsds ? ? 1. when not specified, v ccio can be set anywhere in the valid operating range (page 3-1).
2-37 architecture lattice semiconductor lattice xp2 family data sheet table 2-13. supported output standards hot socketing latticexp2 devices have been carefully designed to ensure predictable behavior during power-up and power- down. power supplies can be sequenced in any order. during power-up and power-down sequences, the i/os remain in tri-state until the power supply voltage is high enough to ensure reliable operation. in addition, leakage into i/o pins is controlled to within specified limits. this allows for ea sy integration with the rest of the system. these capabilities make the lattice xp2 ideal for many multiple powe r supply and hot-swap applications. ieee 1149.1-compliant boundary scan testability all latticexp2 devices have boundary scan cells that are accessed through an ieee 1149.1 compliant test access port (tap). this allows functional testing of the circuit board, on which the device is mounted, through a serial scan path that can access all critical logic nodes. internal registers are linked internally, allowing test data to be shifted in output standard drive v ccio (nom.) single-ended interfaces lvttl 4ma, 8ma, 12ma, 16ma, 20ma 3.3 lvcmos33 4ma, 8ma, 12ma 16ma, 20ma 3.3 lvcmos25 4ma, 8ma, 12ma, 16ma, 20ma 2.5 lvcmos18 4ma, 8ma, 12ma, 16ma 1.8 lvcmos15 4ma, 8ma 1.5 lvcmos12 2ma, 6ma 1.2 lvcmos33, open drain 4ma, 8ma, 12ma 16ma, 20ma ? lvcmos25, open drain 4ma, 8ma, 12ma 16ma, 20ma ? lvcmos18, open drain 4ma, 8ma, 12ma 16ma ? lvcmos15, open drain 4ma, 8ma ? lvcmos12, open drain 2ma, 6ma ? pci33 n/a 3.3 hstl18 class i, ii n/a 1.8 hstl15 class i n/a 1.5 sstl33 class i, ii n/a 3.3 sstl25 class i, ii n/a 2.5 sstl18 class i, ii n/a 1.8 differential interfaces differential sstl33, class i, ii n/a 3.3 differential sstl25, class i, ii n/a 2.5 differential sstl18, class i, ii n/a 1.8 differential hstl18, class i, ii n/a 1.8 differential hstl15, class i n/a 1.5 lv d s 1, 2 n/a 2.5 mlvds 1 n/a 2.5 blvds 1 n/a 2.5 lvpecl 1 n/a 3.3 rsds 1 n/a 2.5 lvcmos33d 1 4ma, 8ma, 12ma, 16ma, 20ma 3.3 1. emulated with external resistors. for more detail, please see tn1138, latticexp2 high speed i/o interface . 2. on the left and right edges, lvds outputs are supported with a dedi cated differential output driver on 50% of the i/os. this solution does not require external resistors at the driver.
2-38 architecture lattice semiconductor lattice xp2 family data sheet and loaded directly onto test nodes, or test data to be captured and shifted out for veri? cation. the test access port consists of dedicated i/os: tdi, tdo, tck and tms. the test access port has its own supply voltage v ccj and can operate with lvcmos3.3, 2.5, 1.8, 1.5 and 1.2 standards. for more information, please see tn1141, latticexp2 sysconfig usage guide . flexiflash device configuration the latticexp2 devices combine flash and sram on a single chip to provide users wit h flexibility in device pro- gramming and configuration. figure 2-33 provides an overview of the arrangement of flash and sram configura- tion cells within the device. the remain der of this section provides an overvi ew of these capabilities. see tn1141, latticexp2 sysconfig usage guide for a more detailed description. figure 2-33. overview of flash and sram co nfiguration cells within latticexp2 devices at power-up, or on user command, data is transferred from the on-chip flash memory to the sram configuration cells that control the operation of th e device. this is done with massively parallel buses enabling the parts to oper- ate within microseconds of the power supplies reaching valid levels; this capability is referred to as instant-on. the on-chip flash enables a single-chip solution eliminatin g the need for external boot memory. this flash can be programmed through either the jtag or slave spi ports of the device. the sram configuration space can also be infinitely reconfigured thro ugh the jtag and master spi ports. the jtag port is ieee 1149.1 and ieee 1532 com- pliant. as described in the ebr section of the data sheet, the flashbak ca pability of the par ts enables the co ntents of the ebr blocks to be written back into the flash storage area without erasing or reprogramming other aspects of the device configuration. serial tag memory is also available to allow the storage of small amounts of data such as calibration coefficients and error codes. for applications where security is important, the lack of an external bitstream provides a solution that is inherently more secure than sram only fpgas. this is further enhanc ed by device locking. the device can be in one of three modes: ebr blocks flash memory ebr blocks sram configuration bits massively parallel data transfer instant-on flash for single-chip solution flashbak for ebr storage decryption and device lock spi and jtag tag memory device lock for design security
2-39 architecture lattice semiconductor lattice xp2 family data sheet 1. unlocked 2. key locked ? presenting the key through the programming interface allows the device to be unlocked. 3. permanently locked ? the device is permanently locked. to further complement the security of the device a one time programmable (otp) mode is available. once the device is set in this mode it is not possible to erase or re-program the flash portion of the device. serial tag memory latticexp2 devices offer 0.6 to 3.3kbits of flash memory in the form of serial tag memory. the tag memory is an area of the on-chip flash that can be used for non-volatile storage including electronic id codes, version codes, date stamps, asset ids and calibration settings. a block diagram of the tag memory is shown in figure 2-34. the tag memory is accessed in the same way as external spi flash and it can be read or programmed either through jtag, an external slave spi port, or directly from fpga logic. to read the tag memory, a start address is speci- fied and the entire tag memory contents are read sequentially in a first-in-first-out manner. the tag memory is independent of the flash used for device configuration an d given its use for general-purpose storage functions is always accessible regardless of the device security settings. for more information, see tn1137, latticexp2 mem- ory usage guide and tn1141, latticexp2 sysconfig usage guide . figure 2-34. serial tag memory diagram live update technology many applications require field updates of the fpga. latticexp2 devices provide three features that enable this configuration to be done in a secure and failsafe manner while minimizing impact on system operation. 1. decryption support ? latticexp2 devices provide on-chip, non-volatile key storage to support decryption of a 128-bit aes encrypted bitstream, securing designs and deterring design piracy. 2. transfr (transparent field reconfiguration) ? transfr i/o (tfr) is a unique lattice technology that allows users to update their logic in the field without interrupting system operation using a single ispvm command. transfr i/o allows i/o states to be frozen dur- ing device configuration. this allows the device to be field updated with a mini mum of system disruption and downtime. for more information please see tn1087, minimizing system interruption during configuration using transfr technology . 3. dual boot image support ? dual boot images are supported for applications requiring reliable remote updates of configuration data for the system fpga. after the system is running with a basic configuration, a new boot image can be downloaded remotely and stored in a separate location in the configuration storage device. any time after the update the latticexp2 can be re-booted from this new configuration file. if there is a problem such as corrupt data during download or incorrect version number with this new boot image, the latticexp2 device can revert back to the flash jtag fpga logic external slave spi port jtag fpga logic external slave spi port tdi tdo data shift register flash memory array sequential address counter
2-40 architecture lattice semiconductor lattice xp2 family data sheet original backup configuration and tr y again. this all can be done without power cycling the system. for more information please see tn1144, latticexp2 dual boot usage guide . for more information on device configuration, please see tn1141, latticexp2 sysconfig usage guide . soft error detect (sed) support latticexp2 devices have dedicated logic to perform cyclic redundancy code (crc) checks. during configuration, the configuration data bitstream can be checked with the crc logic block. in addition, latticexp2 devices can be programmed for checking soft errors in sram. the sed operation can run in the background during user mode (normal operation). in the event a soft error occurs, the device can be programmed to either reload from a known good boot image (from internal flash or external spi memory) or generate an error signal. for further information on sed support, please see tn1130, latticexp2 soft error dete ction (sed) usage guide . on-chip oscillator every latticexp2 device has an internal cmos oscillator that is used to derive a mast er clock (cclk) for configu- ration. the oscillator and cclk run continuously and are ava ilable to user logic after co nfiguration is complete. the available cclk frequencies are listed in table 2-14. when a different cclk frequency is selected during the design process, the following sequence takes place: 1. device powers up with the default cclk frequency. 2. during configuration, users select a different cclk frequency. 3. cclk frequency changes to the selected frequency after clock configuration bits are received. this internal cmos oscillator is availabl e to the user by routing it as an in put clock to the clock tree. for further information on the use of this oscillator for configuration or user mode, please see tn1141, latticexp2 syscon- fig usage guide . table 2-14. selectable cclks and oscillator frequencies during configuration and user mode cclk/oscillator (mhz) 2.5 1 3.1 2 4.3 5.4 6.9 8.1 9.2 10 13 15 20 26 32 40 54 80 3 163 3 1. software default oscillator frequency. 2. software default cclk frequency. 3. frequency not valid for cclk.
2-41 architecture lattice semiconductor lattice xp2 family data sheet density shifting the latticexp2 family is designed to ensure that different density devices in the same family and in the same pack- age have the same pinout. furthermore, the architecture ensures a high success rate when performing design migration from lower density devices to higher density devices. in many cases, it is also possible to shift a lower uti- lization design targeted for a high-density device to a lowe r density device. however, the exact details of the final resource utilization will impact t he likely success in each case.
www.latticesemi.com 3-1 ds1009 dc and switching_01.6 august 2008 data sheet ds1009 ? 2008 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. absolute maximum ratings 1, 2, 3 recommended operating conditions on-chip flash memory specifications supply voltage v cc . . . . . . . . . . . . . . . . . . . -0.5 to 1.32v supply voltage v ccaux . . . . . . . . . . . . . . . . -0.5 to 3.75v supply voltage v ccj . . . . . . . . . . . . . . . . . . -0.5 to 3.75v supply voltage v ccpll 4 . . . . . . . . . . . . . . . . -0.5 to 3.75v output supply voltage v ccio . . . . . . . . . . . -0.5 to 3.75v input or i/o tristate voltage applied 5 . . . . . . -0.5 to 3.75v storage temperature (ambient) . . . . . . . . . -65 to 150c junction temperature under bias (tj) . . . . . . . . . +125c 1. stress above those listed under the ?absol ute maximum ratings? may cause permanent damage to the device. functional operation of the device at these or any other conditions abov e those indicated in the operational sectio ns of this specification is not implied. 2. compliance with the lattice thermal management document is required. 3. all voltages referenced to gnd. 4. v ccpll only available on csbga, pqfp and tqfp packages. 5. overshoot and undershoot of -2v to (v ihmax + 2) volts is permitted for a duration of <20 ns. symbol parameter min. max. units v cc core supply voltage 1.14 1.26 v v ccaux 4 auxiliary supply voltage 3.135 3.465 v v ccpll 1 pll supply voltage 3.135 3.465 v v ccio 2, 3, 4 i/o driver supply voltage 1.14 3.465 v v ccj 2 supply voltage for ieee 1149.1 test access port 1.14 3.465 v t jcom junction temperature, commercial operation 0 85 c t jind junction temperature, industrial operation -40 100 c 1. v ccpll only available on csbga, pqfp and tqfp packages. 2. if v ccio or v ccj is set to 1.2v, they must be connected to the same power supply as v cc. if v ccio or v ccj is set to 3.3v, they must be con- nected to the same power supply as v ccaux . 3. see recommended voltages by i/o standard in subsequent table. 4. to ensure proper i/o behavior, v ccio must be turned off at the same time or earlier than v ccaux. symbol parameter max. units n progcyc flash programming cycles per t retention 10,000 cycles flash functional programming cycles 100,000 t retention data retention 20 years latticexp2 family data sheet dc and switching characteristics
3-2 dc and switching characteristics lattice semiconductor lattice xp2 family data sheet hot socketing specifications 1, 2, 3, 4 dc electrical characteristics over recommended operating conditions symbol parameter condition min. typ. max. units i dk input or i/o leakage current 0 ? v in ? v ih (max.) ? ? +/-1 ma 1. insensitive to sequence of v cc , v ccaux and v ccio . however, assumes monotonic rise/fall rates for v cc , v ccaux and v ccio . 2. 0 ? v cc ? v cc (max), 0 ? v ccio ? v ccio (max) or 0 ? v ccaux ? v ccaux (max). 3. i dk is additive to i pu , i pw or i bh . 4. lvcmos and lvttl only. symbol parameter condition min. typ. max. units i il , i ih 1 input or i/o low leakage 0 ? v in ? v ccio ??10a v ccio ? v in ? v ih (max) ? ? 150 a i pu i/o active pull-up current 0 ? v in ? 0.7 v ccio -30 ? -150 a i pd i/o active pull-down current v il (max) ? v in ? v ccio 30 ? 210 a i bhls bus hold low sustaining current v in = v il (max) 30 ? ? a i bhhs bus hold high sustaining current v in = 0.7 v ccio -30 ? ? a i bhlo bus hold low overdrive current 0 ? v in ? v ccio ??210a i bhho bus hold high overdrive current 0 ? v in ? v ccio ??-150a v bht bus hold trip points v il (max) ? v ih (min) v c1 i/o capacitance 2 v ccio = 3.3v, 2.5v, 1.8v, 1.5v, 1.2v, v cc = 1.2v, v io = 0 to v ih (max) ?8?pf c2 dedicated input capacitance v ccio = 3.3v, 2.5v, 1.8v, 1.5v, 1.2v, v cc = 1.2v, v io = 0 to v ih (max) ?6?pf 1. input or i/o leakage current is measured wi th the pin con? gured as an input or as an i/o with the output driver tri-stated. i t is not measured with the output driver active. bus maintenance circuits are disabled. 2. t a 25 o c, f = 1.0 mhz.
3-3 dc and switching characteristics lattice semiconductor lattice xp2 family data sheet supply current (standby) 1, 2, 3, 4 over recommended operating conditions symbol parameter device typical 5 units i cc core power supply current xp2-5 14 ma xp2-8 18 ma xp2-17 24 ma xp2-30 35 ma xp2-40 45 ma i ccaux auxiliary power supply current 6 xp2-5 15 ma xp2-8 15 ma xp2-17 15 ma xp2-30 16 ma xp2-40 16 ma i ccpll pll power supply current (per pll) 0.1 ma i ccio bank power supply current (per bank) 2 ma i ccj v ccj power supply current 0.25 ma 1. for further information on s upply current, please see tn1139, power estimation and management for latticexp2 devices . 2. assumes all outputs are tristated, all inputs are con? gured as lvcmos and held at the v ccio or gnd. 3. frequency 0 mhz. 4. pattern represents a ?bl ank? con? guration data ? le. 5. t j = 25 o c, power supplies at nominal voltage. 6. in fpbga and ftbga packages the plls are connected to and powe red from the auxiliary power supply. for these packages, the actual auxiliary supply current is the sum of i ccaux and i ccpll. for csbga, pqfp and tq fp packages the plls are powered independent of the auxiliary power supply.
3-4 dc and switching characteristics lattice semiconductor lattice xp2 family data sheet initialization supply current 1, 2, 3, 4, 5 over recommended operating conditions symbol parameter device typical (25c, max. supply) 6 units i cc core power supply current xp2-5 20 ma xp2-8 21 ma xp2-17 44 ma xp2-30 58 ma xp2-40 62 ma i ccaux auxiliary power supply current 7 xp2-5 67 ma xp2-8 74 ma xp2-17 112 ma xp2-30 124 ma xp2-40 130 ma i ccpll pll power supply current (per pll) 1.8 ma i ccio bank power supply current (per bank) 6.4 ma i ccj vccj power supply current 1.2 ma 1. for further information on supply current, please see tn1139, power estimation and management for latticexp2 devices . 2. assumes all outputs are tristated, all input s are con? gured as lvcmos and held at the v ccio or gnd. 3. frequency 0 mhz. 4. does not include additional current from by pass or decoupling capacit or across the supply. 5. a specific configuration pattern is used that scales with the size of the device; consists of 75% pfu ut ilization, 50% ebr, a nd 25% i/o con- figuration. 6. t j = 25c, power supplies at nominal voltage. 7. in fpbga and ftbga packages the plls are connected to and powe red from the auxiliary power s upply. for these packages, the ac tual auxiliary supply current is the sum of i ccaux and i ccpll. for csbga, pqfp and tqfp packages t he plls are powered independent of the auxiliary power supply.
3-5 dc and switching characteristics lattice semiconductor lattice xp2 family data sheet programming and erase flash supply current 1, 2, 3, 4, 5 over recommended operating conditions symbol parameter device typical (25c, max. supply) 6 units i cc core power supply current xp2-5 17 ma xp2-8 21 ma xp2-17 28 ma xp2-30 36 ma xp2-40 50 ma i ccaux auxiliary power supply current 7 xp2-5 64 ma xp2-8 66 ma xp2-17 83 ma xp2-30 87 ma xp2-40 88 ma i ccpll pll power supply current (per pll) 0.1 ma i ccio bank power supply current (per bank) 5 ma i ccj v ccj power supply current 8 14 ma 1. for further information on s upply current, please see tn1139, power estimation and management for latticexp2 devices . 2. assumes all outputs are tristated, all i nputs are con? gured as lvcmos and held at the v ccio or gnd. 3. frequency 0 mhz (excludes dynamic power from fpga operation). 4. a specific configuration pattern is used t hat scales with the size of the device; c onsists of 75% pfu utilization, 50% ebr, a nd 25% i/o con- figuration. 5. bypass or decoupling c apacitor across the supply. 6. t j = 25c, power supplies at nominal voltage. 7. in fpbga and ftbga packages the plls are connected to and powe red from the auxiliary power supply. for these packages, the ac tual auxiliary supply current is the sum of i ccaux and i ccpll . for csbga, pqfp and tqfp packages the plls are powered independent of the auxiliary power supply. 8. when programming via jtag.
3-6 dc and switching characteristics lattice semiconductor lattice xp2 family data sheet sysio recommended operating conditions over recommended operating conditions standard v ccio v ref (v) min. typ. max. min. typ. max. lv c m o s 3 3 2 3.135 3.3 3.465 ? ? ? lv c m o s 2 5 2 2.375 2.5 2.625 ? ? ? lvcmos18 1.71 1.8 1.89 ? ? ? lvcmos15 1.425 1.5 1.575 ? ? ? lv c m o s 1 2 2 1.14 1.2 1.26 ? ? ? lv t t l 3 3 2 3.135 3.3 3.465 ? ? ? pci33 3.135 3.3 3.465 ? ? ? sstl18_i 2 , sstl18_ii 2 1.71 1.8 1.89 0.833 0.9 0.969 sstl25_i 2 , sstl25_ii 2 2.375 2.5 2.625 1.15 1.25 1.35 sstl33_i 2 , sstl33_ii 2 3.135 3.3 3.465 1.3 1.5 1.7 hstl15_i 2 1.425 1.5 1.575 0.68 0.75 0.9 hstl18_i 2 , hstl18_ii 2 1.71 1.8 1.89 0.816 0.9 1.08 lv d s 2 5 2 2.375 2.5 2.625 ? ? ? mlvds25 1 2.375 2.5 2.625 ? ? ? lvpecl33 1, 2 3.135 3.3 3.465 ? ? ? blvds25 1, 2 2.375 2.5 2.625 ? ? ? rsds 1, 2 2.375 2.5 2.625 ? ? ? sstl18d_i 2 , sstl18d_ii 2 1.71 1.8 1.89 ? ? ? sstl25d_ i 2 , sstl25d_ii 2 2.375 2.5 2.625 ? ? ? sstl33d_ i 2 , sstl33d_ ii 2 3.135 3.3 3.465 ? ? ? hstl15d_ i 2 1.425 1.5 1.575 ? ? ? hstl18d_ i 2 , hstl18d_ ii 2 1.71 1.8 1.89 ? ? ? 1. inputs on chip. outputs are implemented with the addition of external resistors. 2. input on this standard does not depend on the value of v ccio .
3-7 dc and switching characteristics lattice semiconductor lattice xp2 family data sheet sysio single-ended dc el ectrical characteristics over recommended operating conditions input/output standard v il v ih v ol v oh i ol 1 (ma) i oh 1 (ma) min. (v) max. (v) min. (v) max. (v) max. (v) min. (v) lvcmos33 -0.3 0.8 2.0 3.6 0.4 v ccio - 0.4 20, 16, 12, 8, 4 -20, -16, -12, -8, -4 0.2 v ccio - 0.2 0.1 -0.1 lvttl33 -0.3 0.8 2.0 3.6 0.4 v ccio - 0.4 20, 16, 12, 8, 4 -20, -16, -12, -8, -4 0.2 v ccio - 0.2 0.1 -0.1 lvcmos25 -0.3 0.7 1.7 3.6 0.4 v ccio - 0.4 20, 16, 12, 8, 4 -20, -16, -12, -8, -4 0.2 v ccio - 0.2 0.1 -0.1 lvcmos18 -0.3 0.35 v ccio 0.65 v ccio 3.6 0.4 v ccio - 0.4 16, 12, 8, 4 -16, -12, -8, -4 0.2 v ccio - 0.2 0.1 -0.1 lvcmos15 -0.3 0.35 v ccio 0.65 v ccio 3.6 0.4 v ccio - 0.4 8, 4 -8, -4 0.2 v ccio - 0.2 0.1 -0.1 lvcmos12 -0.3 0.35 v cc 0.65 v cc 3.6 0.4 v ccio - 0.4 6, 2 -6, -2 0.2 v ccio - 0.2 0.1 -0.1 pci33 -0.3 0.3 v ccio 0.5 v ccio 3.6 0.1 v ccio 0.9 v ccio 1.5 -0.5 sstl33_i -0.3 v ref - 0.2 v ref + 0.2 3.6 0.7 v ccio - 1.1 8 -8 sstl33_ii -0.3 v ref - 0.2 v ref + 0.2 3.6 0.5 v ccio - 0.9 16 -16 sstl25_i -0.3 v ref - 0.18 v ref + 0.18 3.6 0.54 v ccio - 0.62 7.6 -7.6 12 -12 sstl25_ii -0.3 v ref - 0.18 v ref + 0.18 3.6 0.35 v ccio - 0.43 15.2 -15.2 20 -20 sstl18_i -0.3 v ref - 0.125 v ref + 0.125 3.6 0.4 v ccio - 0.4 6.7 -6.7 sstl18_ii -0.3 v ref - 0.125 v ref + 0.125 3.6 0.28 v ccio - 0.28 8-8 11 -11 hstl15_i -0.3 v ref - 0.1 v ref + 0.1 3.6 0.4 v ccio - 0.4 4-4 8-8 hstl18_i -0.3 v ref - 0.1 v ref + 0.1 3.6 0.4 v ccio - 0.4 8-8 12 -12 hstl18_ii -0.3 v ref - 0.1 v ref + 0.1 3.6 0.4 v ccio - 0.4 16 -16 1. the average dc current drawn by i/os between gnd connections, or between the last gnd in an i/o bank and the end of an i/o ba nk, as shown in the logic signal connections table shall not exceed n * 8ma, where n is the number of i/os between bank gnd connection s or between the last gnd in a bank and the end of a bank.
3-8 dc and switching characteristics lattice semiconductor lattice xp2 family data sheet sysio differential elec trical characteristics lv d s over recommended operating conditions differential hstl and sstl differential hstl and sstl outputs are implemented as a pair of complementary single-ended outputs. all allow- able single-ended output cl asses (class i and class ii) are supported in this mode. for further information on lvpecl, rsds, mlvds, blvds and other differential interfaces please see details in additional technical notes listed at the end of this data sheet. lvds25e the top and bottom sides of latticexp2 devices support lvds outputs via emulated complementary lvcmos out- puts in conjunction with a parallel resistor across the driver outputs. the scheme shown in figure 3-1 is one possi- ble solution for point-to-point signals. figure 3-1. lvds25e output termination example parameter description test conditions min. typ. max. units v inp , v inm input voltage 0 ? 2.4 v v cm input common mode voltage half the sum of the two inputs 0.05 ? 2.35 v v thd differential input threshold differ ence between the two inputs +/-100 ? ? mv i in input current power on or power off ? ? +/-10 a v oh output high voltage for v op or v om r t = 100 ohm ? 1.38 1.60 v v ol output low voltage for v op or v om r t = 100 ohm 0.9v 1.03 ? v v od output voltage differential (v op - v om ), r t = 100 ohm 250 350 450 mv ? v od change in v od between high and low ??50mv v os output voltage offset (v op + v om )/2, r t = 100 ohm 1.125 1.20 1.375 v ? v os change in v os between h and l ? ? 50 mv i sa output short circuit current v od = 0v driver outputs shorted to ground ??24ma i sab output short circuit current v od = 0v driver outputs shorted to each other ??12ma + - rs=158 ohms (1%) rs=158 ohms (1%) rp = 140 ohms (1%) rt = 100 ohms (1%) off-chip transmission line, zo = 100 ohm differential vccio = 2.5v (5%) 8 ma vccio = 2.5v (5%) on-chip off-chip on-chip 8 ma
3-9 dc and switching characteristics lattice semiconductor lattice xp2 family data sheet table 3-1. lvds25e dc conditions lvcmos33d all i/o banks support emulated differential i/o using the lvcmos33d i/o type. this option, along with the external resistor network, provides the system designer the flexibility to place differential outputs on an i/o bank with 3.3v vccio. the default drive current for lvcmos33d output is 12ma with the option to change the device strength to 4ma, 8ma, 16ma or 20ma. follow the lvcmos33 specifications for the dc characteristics of the lvcmos33d. parameter description typical units v ccio output driver supply (+/-5%) 2.50 v z out driver impedance 20 ? r s driver series resistor (+/-1%) 158 ? r p driver parallel resistor (+/-1%) 140 ? r t receiver termination (+/-1%) 100 ? v oh output high voltage (after r p )1.43v v ol output low voltage (after r p )1.07v v od output differential voltage (after r p )0.35 v v cm output common mode voltage 1.25 v z back back impedance 100.5 ? i dc dc output current 6.03 ma
3-10 dc and switching characteristics lattice semiconductor lattice xp2 family data sheet blvds the latticexp2 devices support the blvds standard. this standard is emulated using complementary lvcmos outputs in conjunction with a parallel external resistor across the driver outputs. blvds is intended for use when multi-drop and bi-directional multi-point differential signaling is required. the scheme shown in figure 3-2 is one possible solution for bi-directional multi-point differential signals. figure 3-2. blvds multi-point output example table 3-2. blvds dc conditions 1 over recommended operating conditions parameter description typical units zo = 45 ? zo = 45 ? v ccio output driver supply (+/- 5%) 2.50 2.50 v z out driver impedance 10.00 10.00 ? r s driver series resistor (+/- 1%) 90.00 90.00 ? r tl driver parallel resistor (+/- 1%) 45.00 90.00 ? r tr receiver termination (+/- 1%) 45.00 90.00 ? v oh output high voltage (after r tl ) 1.38 1.48 v v ol output low voltage (after r tl ) 1.12 1.02 v v od output differentia l voltage (after r tl ) 0.25 0.46 v v cm output common mode voltage 1.25 1.25 v i dc dc output current 11.24 10.20 ma 1. for input buffer, see lvds table. heavily loaded backplane, effective zo ~ 45 to 90 ohms differential 2.5v r tl r tr r s = 90 ohms r s = 90 ohms r s = 90 ohms r s = 90 ohms r s = 90 ohms r s = 90 ohms r s = 90 ohms r s = 90 ohms 45-90 ohms 45-90 ohms 2.5v 2.5v 2.5v 2.5v 2.5v 2.5v 2.5v + - . . . + - . . . + - + - 16ma 16ma 16ma 16ma 16ma 16ma 16ma 16ma
3-11 dc and switching characteristics lattice semiconductor lattice xp2 family data sheet lvpecl the latticexp2 devices support the diff erential lvpecl standard. this standard is emulat ed using complementary lvcmos outputs in conjunct ion with a parallel resistor across the driv er outputs. the lvpecl input standard is supported by the lvds differential input buffer. the scheme shown in figure 3-3 is one possible solution for point- to-point signals. figure 3-3. diff erential lvpecl table 3-3. lvpecl dc conditions 1 over recommended operating conditions parameter description typical units v ccio output driver supply (+/-5%) 3.30 v z out driver impedance 10 ? r s driver series resistor (+/-1%) 93 ? r p driver parallel resistor (+/-1%) 196 ? r t receiver termination (+/-1%) 100 ? v oh output high voltage (after r p )2.05v v ol output low voltage (after r p )1.25v v od output differential voltage (after r p )0.80 v v cm output common mode voltage 1.65 v z back back impedance 100.5 ? i dc dc output current 12.11 ma 1. for input buffer, see lvds table. transmission line, zo = 100 ohm differential off-chip on-chip v ccio = 3.3v (+/-5%) v ccio = 3.3v (+/-5%) r p = 196 ohms (+/-1%) r t = 100 ohms (+/-1%) r s = 93.1 ohms (+/-1%) r s = 93.1 ohms (+/-1%) 16ma 16ma + - off-chip on-chip
3-12 dc and switching characteristics lattice semiconductor lattice xp2 family data sheet rsds the latticexp2 devices support differential rsds standard. this standard is emulated using complementary lvc- mos outputs in conjunction with a parallel resistor across the driver outputs. the rsds input standard is sup- ported by the lvds differential input buffer. the scheme shown in figure 3-4 is one possible solution for rsds standard implementation. resistor values in figure 3-4 are industry standard values for 1% resistors. figure 3-4. rsds (reduced swing differential standard) table 3-4. rsds dc conditions 1 over recommended operating conditions parameter description typical units v ccio output driver supply (+/-5%) 2.50 v z out driver impedance 20 ? r s driver series resistor (+/-1%) 294 ? r p driver parallel resistor (+/-1%) 121 ? r t receiver termination (+/-1%) 100 ? v oh output high voltage (after r p )1.35v v ol output low voltage (after r p )1.15v v od output differential voltage (after r p )0.20v v cm output common mode voltage 1.25 v z back back impedance 101.5 ? i dc dc output current 3.66 ma 1. for input buffer, see lvds table. r s = 294 ohms (+/-1%) r s = 294 ohms (+/-1%) r p = 121 ohms (+/-1%) r t = 100 ohms (+/-1%) on-chip on-chip 8ma 8ma v ccio = 2.5v (+/-5%) v ccio = 2.5v (+/-5%) transmission line, zo = 100 ohm differential + - off-chip off-chip
3-13 dc and switching characteristics lattice semiconductor lattice xp2 family data sheet mlvds the latticexp2 devices support the differential mlvds standard. this standard is emulated using complementary lvcmos outputs in conjunction with a parallel resistor across the driver outputs. the mlvds input standard is supported by the lvds differential input buffer. the scheme shown in figure 3-5 is one possible solution for mlvds standard implementation. resistor values in figure 3-5 are industry standard values for 1% resistors. figure 3-5. mlvds (reduced swing differential standard) table 3-5. mlvds dc conditions 1 for further information on lvpecl, rsds, mlvds, blvds and other differential interfaces please see details of additional technical information at the end of this data sheet. parameter description typical units zo=50 ? zo=70 ? v ccio output driver supply (+/-5%) 2.50 2.50 v z out driver impedance 10.00 10.00 ? r s driver series resistor (+/-1%) 35.00 35.00 ? r tl driver parallel resistor (+/-1%) 50.00 70.00 ? r tr receiver termination (+/-1%) 50.00 70.00 ? v oh output high voltage (after r tl )1.521.60v v ol output low voltage (after r tl )0.980.90v v od output differential voltage (after r tl )0.54 0.70 v v cm output common mode voltage 1.25 1.25 v i dc dc output current 21.74 20.00 ma 1. for input buffer, see lvds table. 16ma 2.5v 2.5v + - 2.5v 2.5v + - 2.5v 2.5v + - . . . . . . a m 6 1 heavily loaded backplace, effective zo~50 to 70 ohms differential 50 to 70 ohms +/-1% 50 to 70 ohms +/-1% r s = 35ohms r s = 35ohms r s = 35ohms r s = 35ohms r s = 35ohms r s = 35ohms r s = 35ohms r s = 35ohms r tr r tl 16ma 2.5v a m 6 1 2.5v + - a m 6 1 2.5v a m 6 1 2.5v + - 16ma 16ma
3-14 dc and switching characteristics lattice semiconductor lattice xp2 family data sheet typical building block function performance 1 pin-to-pin performance (lvcmos25 12ma drive) function -7 timing units basic functions 16-bit decoder 4.4 ns 32-bit decoder 5.2 ns 64-bit decoder 5.6 ns 4:1 mux 3.7 ns 8:1 mux 3.9 ns 16:1 mux 4.3 ns 32:1 mux 4.5 ns register-to-register performance function -7 timing units basic functions 16-bit decoder 521 mhz 32-bit decoder 537 mhz 64-bit decoder 484 mhz 4:1 mux 744 mhz 8:1 mux 678 mhz 16:1 mux 616 mhz 32:1 mux 529 mhz 8-bit adder 570 mhz 16-bit adder 507 mhz 64-bit adder 293 mhz 16-bit counter 541 mhz 32-bit counter 440 mhz 64-bit counter 321 mhz 64-bit accumulator 261 mhz embedded memory functions 512x36 single port ram, eb r output registers 315 mhz 1024x18 true-dual port ram (write through or normal, ebr output registers) 315 mhz 1024x18 true-dual port ram (write through or normal, plc output registers) 231 mhz distributed memory functions 16x4 pseudo-dual port ram (one pfu) 760 mhz 32x2 pseudo-dual port ram 455 mhz 64x1 pseudo-dual port ram 351 mhz dsp functions 18x18 multiplier (all registers) 342 mhz 9x9 multiplier (all registers) 342 mhz 36x36 multiply (all registers) 330 mhz 18x18 multiply/accumulate (input and output registers) 218 mhz 18x18 multiply-add/sub-sum (all registers) 292 mhz
3-15 dc and switching characteristics lattice semiconductor lattice xp2 family data sheet derating timing tables logic timing provided in the following sections of this data sheet and the isplever design tools are worst case numbers in the operating range. actual delays at nominal temperature and voltage for best case process, can be much better than the values given in the tables. the isplever design tool can provide logic timing numbers at a particular temperature and voltage. dsp ip functions 16-tap fully-parallel fir filter 198 mhz 1024-pt fft 221 mhz 8x8 matrix multiplication 196 mhz 1. these timing numbers were generated using the isplever design to ol. exact performance may vary wi th device, design and tool v ersion. the tool uses internal parameters that have been characterized but are not tested on every device. timing v. a 0.12 register-to-register performance (continued) function -7 timing units
3-16 dc and switching characteristics lattice semiconductor lattice xp2 family data sheet latticexp2 external sw itching characteristics over recommended operating conditions parameter description device -7 -6 -5 units min. max. min. max. min. max. general i/o pin parameters (using primary clock without pll) 1 t co clock to output - pio output register xp2-5 ? 3.80 ? 4.20 ? 4.60 ns xp2-8 ? 3.80 ? 4.20 ? 4.60 ns xp2-17 ? 3.80 ? 4.20 ? 4.60 ns xp2-30 ? 4.00 ? 4.40 ? 4.90 ns xp2-40 ? 4.00 ? 4.40 ? 4.90 ns t su clock to data setup - pio input register xp2-5 0.00 ? 0.00 ? 0.00 ? ns xp2-8 0.00 ? 0.00 ? 0.00 ? ns xp2-17 0.00 ? 0.00 ? 0.00 ? ns xp2-30 0.00 ? 0.00 ? 0.00 ? ns xp2-40 0.00 ? 0.00 ? 0.00 ? ns t h clock to data hold - pio input register xp2-5 1.40 ? 1.70 ? 1.90 ? ns xp2-8 1.40 ? 1.70 ? 1.90 ? ns xp2-17 1.40 ? 1.70 ? 1.90 ? ns xp2-30 1.40 ? 1.70 ? 1.90 ? ns xp2-40 1.40 ? 1.70 ? 1.90 ? ns t su_del clock to data setup - pio input register with data input delay xp2-5 1.40 ? 1.70 ? 1.90 ? ns xp2-8 1.40 ? 1.70 ? 1.90 ? ns xp2-17 1.40 ? 1.70 ? 1.90 ? ns xp2-30 1.40 ? 1.70 ? 1.90 ? ns xp2-40 1.40 ? 1.70 ? 1.90 ? ns t h_del clock to data hold - pio input register with input data delay xp2-5 0.00 ? 0.00 ? 0.00 ? ns xp2-8 0.00 ? 0.00 ? 0.00 ? ns xp2-17 0.00 ? 0.00 ? 0.00 ? ns xp2-30 0.00 ? 0.00 ? 0.00 ? ns xp2-40 0.00 ? 0.00 ? 0.00 ? ns f max_io clock frequency of i/o and pfu register xp2 ?420?357?311mhz general i/o pin parameters (using edge clock without pll) 1 t coe clock to output - pio output register xp2-5 ? 3.20 ? 3.60 ? 3.90 ns xp2-8 ? 3.20 ? 3.60 ? 3.90 ns xp2-17 ? 3.20 ? 3.60 ? 3.90 ns xp2-30 ? 3.20 ? 3.60 ? 3.90 ns xp2-40 ? 3.20 ? 3.60 ? 3.90 ns t sue clock to data setup - pio input register xp2-5 0.00 ? 0.00 ? 0.00 ? ns xp2-8 0.00 ? 0.00 ? 0.00 ? ns xp2-17 0.00 ? 0.00 ? 0.00 ? ns xp2-30 0.00 ? 0.00 ? 0.00 ? ns xp2-40 0.00 ? 0.00 ? 0.00 ? ns
3-17 dc and switching characteristics lattice semiconductor lattice xp2 family data sheet t he clock to data hold - pio input register xp2-5 1.00 ? 1.30 ? 1.60 ? ns xp2-8 1.00 ? 1.30 ? 1.60 ? ns xp2-17 1.00 ? 1.30 ? 1.60 ? ns xp2-30 1.20 ? 1.60 ? 1.90 ? ns xp2-40 1.20 ? 1.60 ? 1.90 ? ns t su_dele clock to data setup - pio input register with data input delay xp2-5 1.00 ? 1.30 ? 1.60 ? ns xp2-8 1.00 ? 1.30 ? 1.60 ? ns xp2-17 1.00 ? 1.30 ? 1.60 ? ns xp2-30 1.20 ? 1.60 ? 1.90 ? ns xp2-40 1.20 ? 1.60 ? 1.90 ? ns t h_dele clock to data hold - pio input register with input data delay xp2-5 0.00 ? 0.00 ? 0.00 ? ns xp2-8 0.00 ? 0.00 ? 0.00 ? ns xp2-17 0.00 ? 0.00 ? 0.00 ? ns xp2-30 0.00 ? 0.00 ? 0.00 ? ns xp2-40 0.00 ? 0.00 ? 0.00 ? ns f max_ioe clock frequency of i/o and pfu register xp2 ?420?357?311mhz general i/o pin parameters (using primary clock with pll) 1 t copll clock to output - pio output register xp2-5 ? 3.00 ? 3.30 ? 3.70 ns xp2-8 ? 3.00 ? 3.30 ? 3.70 ns xp2-17 ? 3.00 ? 3.30 ? 3.70 ns xp2-30 ? 3.00 ? 3.30 ? 3.70 ns xp2-40 ? 3.00 ? 3.30 ? 3.70 ns t supll clock to data setup - pio input register xp2-5 1.00 ? 1.20 ? 1.40 ? ns xp2-8 1.00 ? 1.20 ? 1.40 ? ns xp2-17 1.00 ? 1.20 ? 1.40 ? ns xp2-30 1.00 ? 1.20 ? 1.40 ? ns xp2-40 1.00 ? 1.20 ? 1.40 ? ns t hpll clock to data hold - pio input register xp2-5 0.90 ? 1.10 ? 1.30 ? ns xp2-8 0.90 ? 1.10 ? 1.30 ? ns xp2-17 0.90 ? 1.10 ? 1.30 ? ns xp2-30 1.00 ? 1.20 ? 1.40 ? ns xp2-40 1.00 ? 1.20 ? 1.40 ? ns t su_delpll clock to data setup - pio input register with data input delay xp2-5 1.90 ? 2.10 ? 2.30 ? ns xp2-8 1.90 ? 2.10 ? 2.30 ? ns xp2-17 1.90 ? 2.10 ? 2.30 ? ns xp2-30 2.00 ? 2.20 ? 2.40 ? ns xp2-40 2.00 ? 2.20 ? 2.40 ? ns latticexp2 external switchin g characteristics (continued) over recommended operating conditions parameter description device -7 -6 -5 units min. max. min. max. min. max.
3-18 dc and switching characteristics lattice semiconductor lattice xp2 family data sheet t h_delpll clock to data hold - pio input register with input data delay xp2-5 0.00 ? 0.00 ? 0.00 ? ns xp2-8 0.00 ? 0.00 ? 0.00 ? ns xp2-17 0.00 ? 0.00 ? 0.00 ? ns xp2-30 0.00 ? 0.00 ? 0.00 ? ns xp2-40 0.00 ? 0.00 ? 0.00 ? ns ddr 2 and ddr2 3 i/o pin parameters t dvadq data valid after dqs ? (ddr read) xp2 ? 0.29 ? 0.29 ? 0.29 ui t dvedq data hold after dqs ? (ddr read) xp2 0.71 ? 0.71 ? 0.71 ? ui t dqvbs data valid before dqs xp2 0.25 ? 0.25 ? 0.25 ? ui t dqvas data valid after dqs xp2 0.25 ? 0.25 ? 0.25 ? ui f max_ddr ddr clock frequency xp2 95 200 95 166 95 133 mhz f max_ddr2 ddr clock frequency xp2 133 200 133 200 133 166 mhz primary clock f max_pri frequency for primary clock tr e e xp2 ?420?357?311mhz t w_pri clock pulse width for primary clock xp2 1?1?1?ns t skew_pri primary clock skew within a bank xp2 ?160?160?160ps edge clock (eclk1 and eclk2) f max_eclk frequency for edge clock xp2 ? 420 ? 357 ? 311 mhz t w_eclk clock pulse width for edge clock xp2 1?1?1?ns t skew_eclk edge clock skew within an edge of the device xp2 ?130?130?130ps 1. general timing numbers based on lvcmos 2.5, 12ma, 0pf load. 2. ddr timing numbers based on sstl25. 3. ddr2 timing numbers based on sstl18. timing v. a 0.12 latticexp2 external switchin g characteristics (continued) over recommended operating conditions parameter description device -7 -6 -5 units min. max. min. max. min. max.
3-19 dc and switching characteristics lattice semiconductor lattice xp2 family data sheet latticexp2 internal sw itching characteristics 1 over recommended operating conditions parameter description -7 -6 -5 units min. max. min. max. min. max. pfu/pff logic mode timing t lut4_pfu lut4 delay (a to d inputs to f o u t p u t ) ? 0.216 ? 0.238 ? 0.260 ns t lut6_pfu lut6 delay (a to d inputs to ofx output) ? 0.304 ? 0.399 ? 0.494 ns t lsr_pfu set/reset to output of pfu (asyn- chronous) ? 0.720 ? 0.769 ? 0.818 ns t sum_pfu clock to mux (m0,m1) input setup time 0.154 ? 0.151 ? 0.148 ? ns t hm_pfu clock to mux (m0,m1) input hold time -0.061 ? -0.057 ? -0.053 ? ns t sud_pfu clock to d input setup time 0.061 ? 0.077 ? 0.093 ? ns t hd_pfu clock to d input hold time 0.002 ? 0.003 ? 0.003 ? ns t ck2q_pfu clock to q delay, (d-type register configuration) ? 0.342 ? 0.363 ? 0.383 ns t rstrec_pfu asynchronous reset recovery time for pfu logic ? 0.520 ? 0.634 ? 0.748 ns t rst_pfu asynchronous reset time for pfu logic ? 0.720 ? 0.769 ? 0.818 ns pfu dual port memory mode timing t coram_pfu clock to output (f port) ? 1.082 ? 1.267 ? 1.452 ns t sudata_pfu data setup time -0.206 ? -0.240 ? -0.274 ? ns t hdata_pfu data hold time 0.239 ? 0.275 ? 0.312 ? ns t suaddr_pfu address setup time -0.294 ? -0.333 ? -0.371 ? ns t haddr_pfu address hold time 0.295 ? 0.333 ? 0.371 ? ns t suwren_pfu write/read enable setup time -0.146 ? -0.169 ? -0.193 ? ns t hwren_pfu write/read enable hold time 0.158 ? 0.182 ? 0.207 ? ns pio input/output buffer timing t in_pio input buffer delay (lvcmos25) ? 0.858 ? 0.766 ? 0.674 ns t out_pio output buffer delay (lvcmos25) ? 1.561 ? 1.403 ? 1.246 ns iologic input/output timing t sui_pio input register setup time (data before clock) 0.583 ? 0.893 ? 1.201 ? ns t hi_pio input register hold time (data after clock) 0.062 ? 0.322 ? 0.482 ? ns t coo_pio output register clock to output delay ? 0.608 ? 0.661 ? 0.715 ns t suce_pio input register clock enable setup time 0.032 ? 0.037 ? 0.041 ? ns t hce_pio input register clock enable hold time -0.022 ? -0.025 ? -0.028 ? ns t sulsr_pio set/reset setup time 0.184 ? 0.201 ? 0.217 ? ns t hlsr_pio set/reset hold time -0.080 ? -0.086 ? -0.093 ? ns t rstrec_pio asynchronous reset recovery time for io logic 0.228 ? 0.247 ? 0.266 ? ns
3-20 dc and switching characteristics lattice semiconductor lattice xp2 family data sheet t rst_pio asynchronous reset time for pfu logic ? 0.386 ? 0.419 ? 0.452 ns t del dynamic delay step size 0.035 0.035 0.035 0.035 0.035 0.035 ns ebr timing t co_ebr clock (read) to output from address or data ? 2.774 ? 3.142 ? 3.510 ns t coo_ebr clock (write) to output from ebr output register ? 0.360 ? 0.408 ? 0.456 ns t sudata_ebr setup data to ebr memory (write clk) -0.167 ? -0.198 ? -0.229 ? ns t hdata_ebr hold data to ebr memory (write clk) 0.194 ? 0.231 ? 0.267 ? ns t suaddr_ebr setup address to ebr memory (write clk) -0.117 ? -0.137 ? -0.157 ? ns t haddr_ebr hold address to ebr memory (write clk) 0.157 ? 0.182 ? 0.207 ? ns t suwren_ebr setup write/read enable to ebr memory (write/read clk) -0.135 ? -0.159 ? -0.182 ? ns t hwren_ebr hold write/read enable to ebr memory (write/read clk) 0.158 ? 0.186 ? 0.214 ? ns t suce_ebr clock enable setup time to ebr output register (read clk) 0.144 ? 0.160 ? 0.176 ? ns t hce_ebr clock enable hold time to ebr output register (read clk) -0.097 ? -0.113 ? -0.129 ? ns t rsto_ebr reset to output delay time from ebr output regi ster (asynchro- nous) ? 1.156 ? 1.341 ? 1.526 ns t sube_ebr byte enable set-up time to ebr output register -0.117 ? -0.137 ? -0.157 ? ns t hbe_ebr byte enable hold time to ebr output register dynamic delay on each pio 0.157 ? 0.182 ? 0.207 ? ns t rstrec_ebr asynchronous reset recovery time for ebr 0.233 ? 0.291 ? 0.347 ? ns t rst_ebr asynchronous reset time for ebr ? 1.156 ? 1.341 ? 1.526 ns pll parameters t rstkrec_pll after rstk de-assert, recovery time before next clock edge can toggle k-divider counter 1.000 ? 1.000 ? 1.000 ? ns t rstrec_pll after rst de-assert, recovery time before next clock edge can toggle m-divider counter (applies to m-divider portion of rst only 2 ) 1.000 ? 1.000 ? 1.000 ? ns dsp block timing t sui_dsp input register setup time 0.135 ? 0.151 ? 0.166 ? ns t hi_dsp input register hold ti me 0.021 ? -0.006 ? -0.031 ? ns t sup_dsp pipeline register setup time 2.505 ? 2.784 ? 3.064 ? ns latticexp2 internal sw itching characteristics 1 (continued) over recommended operating conditions parameter description -7 -6 -5 units min. max. min. max. min. max.
3-21 dc and switching characteristics lattice semiconductor lattice xp2 family data sheet t hp_dsp pipeline register hold time -0.787 ? -0.890 ? -0.994 ? ns t suo_dsp output register setup time 4.896 ? 5.413 ? 5.931 ? ns t ho_dsp output register hold ti me -1.439 ? -1.604 ? -1.770 ? ns t coi_dsp 3 input register clock to output time ? 4.513 ? 4.947 ? 5.382 ns t cop_dsp 3 pipeline register clock to output time ? 2.153 ? 2.272 ? 2.391 ns t coo_dsp 3 output register clock to output time ? 0.569 ? 0.600 ? 0.631 ns t suadsub adsub input register setup time -0.270 ? -0.298 ? -0.327 ? ns t hadsub adsub input register hold time 0.306 ? 0.338 ? 0.371 ? ns 1. internal parameters are characterized, but not tested on every device. 2. rst resets vco and all counters in pll. 3. these parameters include the adder subtractor block in the path. timing v. a 0.12 latticexp2 internal sw itching characteristics 1 (continued) over recommended operating conditions parameter description -7 -6 -5 units min. max. min. max. min. max.
3-22 dc and switching characteristics lattice semiconductor lattice xp2 family data sheet ebr timing diagrams figure 3-6. read/write mode (normal) note: input data and address are registered at the positive edge of the clock and output data appears after the positive edge o f the clock. figure 3-7. read/write mode with input and output registers a0 a1 a0 a1 d0 d1 doa a0 t co_ebr t co_ebr invalid data t co_ebr t su t h d0 d1 d0 dia ada wea csa clka a0 a1 a0 a0 d0 d1 output is only updated during a read cycle a1 d0 d1 mem(n) data from previous read dia ada wea csa clka doa (regs) t su t h t coo_ebr t coo_ebr
3-23 dc and switching characteristics lattice semiconductor lattice xp2 family data sheet figure 3-8. write through (sp read/write on port a, input registers only) note: input data and address are registered at the positive edge of the clock and output data appears after the positive edge o f the clock. a0 a1 a0 d0 d1 d4 t su t access t access t access t h d2 d3 d4 d0 d1 d2 data from prev read or write three consecutive writes to a0 d3 doa dia ada wea csa clka t access
3-24 dc and switching characteristics lattice semiconductor lattice xp2 family data sheet latticexp2 family timing adders 1, 2, 3 over recommended operating conditions buffer type description -7 -6 -5 units input adjusters lvds25 lvds -0.26 -0.11 0.04 ns blvds25 blvds -0.26 -0.11 0.04 ns mlvds lvds -0.26 -0.11 0.04 ns rsds rsds -0.26 -0.11 0.04 ns lvpecl33 lvpecl -0.26 -0.11 0.04 ns hstl18_i hstl_18 class i -0.23 -0.08 0.07 ns hstl18_ii hstl_18 class ii -0.23 -0.08 0.07 ns hstl18d_i differential hstl 18 class i -0.28 -0.13 0.02 ns hstl18d_ii differential hstl 18 class ii -0.28 -0.13 0.02 ns hstl15_i hstl_15 class i -0.23 -0.09 0.06 ns hstl15d_i differential hstl 15 class i -0.28 -0.13 0.01 ns sstl33_i sstl_3 class i -0.20 -0.04 0.12 ns sstl33_ii sstl_3 class ii -0.20 -0.04 0.12 ns sstl33d_i differential sstl_3 class i -0.27 -0.11 0.04 ns sstl33d_ii differential sstl_3 class ii -0.27 -0.11 0.04 ns sstl25_i sstl_2 class i -0.21 -0.06 0.10 ns sstl25_ii sstl_2 class ii -0.21 -0.06 0.10 ns sstl25d_i differential sstl_2 class i -0.27 -0.12 0.03 ns sstl25d_ii differential sstl_2 class ii -0.27 -0.12 0.03 ns sstl18_i sstl_18 class i -0.23 -0.08 0.07 ns sstl18_ii sstl_18 class ii -0.23 -0.08 0.07 ns sstl18d_i differential sstl_18 class i -0.28 -0.13 0.02 ns sstl18d_ii differential sstl_18 class ii -0.28 -0.13 0.02 ns lvttl33 lvttl -0.09 0.05 0.18 ns lvcmos33 lvcmos 3.3 -0.09 0.05 0.18 ns lvcmos25 lvcmos 2.5 0.00 0.00 0.00 ns lvcmos18 lvcmos 1.8 -0.23 -0.07 0.09 ns lvcmos15 lvcmos 1.5 -0.20 -0.02 0.16 ns lvcmos12 lvcmos 1.2 -0.35 -0.20 -0.04 ns pci33 3.3v pci -0.09 0.05 0.18 ns output adjusters lv d s 2 5 e lv d s 2 . 5 e 4 -0.25 0.02 0.30 ns lvds25 lvds 2.5 -0.25 0.02 0.30 ns blvds25 blvds 2.5 -0.28 0.00 0.28 ns mlvds mlvds 2.5 4 -0.28 0.00 0.28 ns rsds rsds 2.5 4 -0.25 0.02 0.30 ns lvpecl33 lvpecl 3.3 4 -0.37 -0.10 0.18 ns hstl18_i hstl_18 class i 8ma drive -0.17 0.13 0.43 ns hstl18_ii hstl_18 class ii -0.29 0.00 0.29 ns hstl18d_i differential hstl 18 class i 8ma drive -0.17 0.13 0.43 ns hstl18d_ii differential hstl 18 class ii -0.29 0.00 0.29 ns
3-25 dc and switching characteristics lattice semiconductor lattice xp2 family data sheet hstl15_i hstl_15 class i 4ma drive 0.32 0.69 1.06 ns hstl15d_i differential hstl 15 class i 4ma drive 0.32 0.69 1.06 ns sstl33_i sstl_3 class i -0.25 0.05 0.35 ns sstl33_ii sstl_3 class ii -0.31 -0.02 0.27 ns sstl33d_i differential sstl_3 class i -0.25 0.05 0.35 ns sstl33d_ii differential sstl_3 class ii -0.31 -0.02 0.27 ns sstl25_i sstl_2 class i 8ma drive -0.25 0.02 0.30 ns sstl25_ii sstl_2 class ii 16ma drive -0.28 0.00 0.28 ns sstl25d_i differential sstl_2 class i 8ma drive -0.25 0.02 0.30 ns sstl25d_ii differential sstl_2 class ii 16ma drive -0.28 0.00 0.28 ns sstl18_i sstl_1.8 class i -0.17 0.13 0.43 ns sstl18_ii sstl_1.8 class ii 8ma drive -0.18 0.12 0.42 ns sstl18d_i differential sstl_1.8 class i -0.17 0.13 0.43 ns sstl18d_ii differential sstl_1.8 class ii 8ma drive -0.18 0.12 0.42 ns lvttl33_4ma lvttl 4ma drive -0.37 -0.05 0.26 ns lvttl33_8ma lvttl 8ma drive -0.45 -0.18 0.10 ns lvttl33_12ma lvttl 12ma drive -0.52 -0.24 0.04 ns lvttl33_16ma lvttl 16ma drive -0.43 -0.14 0.14 ns lvttl33_20ma lvttl 20ma drive -0.46 -0.18 0.09 ns lvcmos33_4ma lvcmos 3.3 4ma drive, fast slew rate -0.37 -0.05 0.26 ns lvcmos33_8ma lvcmos 3.3 8ma drive, fast slew rate -0.45 -0.18 0.10 ns lvcmos33_12ma lvcmos 3.3 12ma drive, fast slew rate -0.52 -0.24 0.04 ns lvcmos33_16ma lvcmos 3.3 16ma drive, fast slew rate -0.43 -0.14 0.14 ns lvcmos33_20ma lvcmos 3.3 20ma drive, fast slew rate -0.46 -0.18 0.09 ns lvcmos25_4ma lvcmos 2.5 4ma drive, fast slew rate -0.42 -0.15 0.13 ns lvcmos25_8ma lvcmos 2.5 8ma drive, fast slew rate -0.48 -0.21 0.05 ns lvcmos25_12ma lvcmos 2.5 12ma drive, fast slew rate 0.00 0.00 0.00 ns lvcmos25_16ma lvcmos 2.5 16ma drive, fast slew rate -0.45 -0.18 0.08 ns lvcmos25_20ma lvcmos 2.5 20ma drive, fast slew rate -0.49 -0.22 0.04 ns lvcmos18_4ma lvcmos 1.8 4ma drive, fast slew rate -0.46 -0.18 0.10 ns lvcmos18_8ma lvcmos 1.8 8ma drive, fast slew rate -0.52 -0.25 0.02 ns lvcmos18_12ma lvcmos 1.8 12ma drive, fast slew rate -0.56 -0.30 -0.03 ns lvcmos18_16ma lvcmos 1.8 16ma drive, fast slew rate -0.50 -0.24 0.03 ns lvcmos15_4ma lvcmos 1.5 4ma drive, fast slew rate -0.45 -0.17 0.11 ns lvcmos15_8ma lvcmos 1.5 8ma drive, fast slew rate -0.53 -0.26 0.00 ns lvcmos12_2ma lvcmos 1.2 2ma drive, fast slew rate -0.46 -0.19 0.08 ns lvcmos12_6ma lvcmos 1.2 6ma drive, fast slew rate -0.55 -0.29 -0.02 ns lvcmos33_4ma lvcmos 3.3 4ma drive, slow slew rate 0.98 1.41 1.84 ns lvcmos33_8ma lvcmos 3.3 8ma drive, slow slew rate 0.74 1.16 1.58 ns lvcmos33_12ma lvcmos 3.3 12ma drive, slow slew rate 0.56 0.97 1.38 ns lvcmos33_16ma lvcmos 3.3 16ma drive, slow slew rate 0.77 1.19 1.61 ns lvcmos33_20ma lvcmos 3.3 20ma drive, slow slew rate 0.57 0.98 1.40 ns latticexp2 family timing adders 1, 2, 3 (continued) over recommended operating conditions buffer type description -7 -6 -5 units
3-26 dc and switching characteristics lattice semiconductor lattice xp2 family data sheet lvcmos25_4ma lvcmos 2.5 4ma drive, slow slew rate 1.05 1.43 1.81 ns lvcmos25_8ma lvcmos 2.5 8ma drive, slow slew rate 0.78 1.15 1.52 ns lvcmos25_12ma lvcmos 2.5 12ma drive, slow slew rate 0.59 0.96 1.33 ns lvcmos25_16ma lvcmos 2.5 16ma drive, slow slew rate 0.81 1.18 1.55 ns lvcmos25_20ma lvcmos 2.5 20ma drive, slow slew rate 0.61 0.98 1.35 ns lvcmos18_4ma lvcmos 1.8 4ma drive, slow slew rate 1.01 1.38 1.75 ns lvcmos18_8ma lvcmos 1.8 8ma drive, slow slew rate 0.72 1.08 1.45 ns lvcmos18_12ma lvcmos 1.8 12ma drive, slow slew rate 0.53 0.90 1.26 ns lvcmos18_16ma lvcmos 1.8 16ma drive, slow slew rate 0.74 1.11 1.48 ns lvcmos15_4ma lvcmos 1.5 4ma drive, slow slew rate 0.96 1.33 1.71 ns lvcmos15_8ma lvcmos 1.5 8ma drive, slow slew rate -0.53 -0.26 0.00 ns lvcmos12_2ma lvcmos 1.2 2ma drive, slow slew rate 0.90 1.27 1.65 ns lvcmos12_6ma lvcmos 1.2 6ma drive, slow slew rate -0.55 -0.29 -0.02 ns pci33 3.3v pci -0.29 -0.01 0.26 ns 1. timing adders are characterized but not tested on every device. 2. lvcmos timing measured with the load s pecified in switching test condition table. 3. all other standards tested according to the appropriate specifications. 4. these timing adders are measured with the recommended resistor values. timing v. a 0.12 latticexp2 family timing adders 1, 2, 3 (continued) over recommended operating conditions buffer type description -7 -6 -5 units
3-27 dc and switching characteristics lattice semiconductor lattice xp2 family data sheet sysclock pll timing over recommended operating conditions parameter description conditions min. typ. max. units f in input clock frequency (clki, clkfb) 10 ? 435 mhz f out output clock frequency (clkop, clkos) 10 ? 435 mhz f out2 k-divider output frequency clkok 0.078 ? 217.5 mhz clkok2 3.3 ? 145 mhz f vco pll vco frequency 435 ? 870 mhz f pfd phase detector input frequency 10 ? 435 mhz ac characteristics t dt output clock duty cycle def ault duty cycle selected 3 45 50 55 % t cpa coarse phase adjust -5 0 5 % t ph 4 output phase accuracy -5 0 5 % t opjit 1 output clock period jitter f out > 400 mhz ? ? 50 ps 100 mhz < f out < 400 mhz ? ? 125 ps f out < 100 mhz ? ? 0.025 uipp t sk input clock to output clock skew n/m = integer ? ? 240 ps t opw output clock pulse width at 90% or 10% 1 ? ? ns t lock 2 pll lock-in time 25 to 435 mhz ? ? 50 s 10 to 25 mhz ? ? 100 s t ipjit input clock period jitter ? ? 200 ps t fbkdly external feedback delay ? ? 10 ns t hi input clock high time 90% to 90% 0.5 ? ? ns t lo input clock low time 10% to 10% 0.5 ? ? ns t r / t f input clock rise/fall time 10% to 90% ? ? 1 ns t rstkw reset signal pulse width (rstk) 10 ? ? ns t rstw reset signal pulse width (rst) 500 ? ? ns 1. jitter sample is taken over 10,000 samples of the primary pll output with clean reference clock. 2. output clock is valid after t lock for pll reset and dynamic delay adjustment. 3. using lvds output buffers. 4. relative to clkop. timing v. a 0.12
3-28 dc and switching characteristics lattice semiconductor lattice xp2 family data sheet latticexp2 sysconfig port timing specifications over recommended operating conditions parameter description min max units sysconfig por, initialization and wake up t icfg minimum vcc to initn high ? 50 ms t vmc time from ticfg to valid master cclk ? 2 s t prgmrj programn pin pulse rejection ? 12 ns t prgm programn low time to start con? guration 50 ? ns t dinit programn high to initn high delay ? 1 ms t dppinit delay time from programn low to initn low ? 50 ns t dppdone delay time from programn low to done low ? 50 ns t iodiss user i/o disable from programn low ? 35 ns t ioenss user i/o enabled time from ccl k edge during wake-up sequence ? 25 ns t mwc additional wake master clock signals after done pin high 0 ? cycles sysconfig spi port (master) t cfgx initn high to cclk low ? 1 s t csspi initn high to csspin low ? 2 s t cscclk cclk low before csspin low 0 ? ns t socdo cclk low to output valid ? 15 ns t cspid csspin[0:1] low to first cclk edge setup time 2cyc 600+6cyc ns f maxspi max cclk frequency ? 20 mhz t suspi sospi data setup time before cclk 7 ? ns t hspi sospi data hold ti me after cclk 10 ? ns sysconfig spi port (slave) f maxspis slave cclk frequency ? 25 mhz t rf rise and fall time 50 ? mv/ns t stco falling edge of cclk to sospi active ? 20 ns t stoz falling edge of cclk to sospi disable ? 20 ns t stsu data setup time (sispi) 8 ? ns t sth data hold time (sispi) 10 ? ns t stckh cclk clock pulse width, high 0.02 200 s t stckl cclk clock pulse width, low 0.02 200 s t stvo falling edge of cclk to valid sospi output ? 20 ns t scs csspisn high time 25 ? ns t scss csspisn setup time 25 ? ns t scsh csspisn hold time 25 ? ns
3-29 dc and switching characteristics lattice semiconductor lattice xp2 family data sheet on-chip oscillator and configuratio n master clock characteristics over recommended operating conditions figure 3-9. master spi configuration waveforms parameter min. max. units master clock frequency selected value -30% selected value +30% mhz duty cycle 40 60 % timing v. a 0.12 opcode address 0 1 2 3 ? 7 8 9 10 ? 31 32 33 34 ? 127 128 vcc programn done initn csspin cclk sispi sospi capture cfgx capture cr0 ignore valid bitstream
3-30 dc and switching characteristics lattice semiconductor lattice xp2 family data sheet flash download time (from on-chip flash to sram) over recommended operating conditions flash program time over recommended operating conditions flash erase time over recommended operating conditions symbol parameter min. typ. max. units t refresh programn low-to- high. transition to done high. xp2-5 ? 1.8 2.1 ms xp2-8 ? 1.9 2.3 ms xp2-17 ? 1.7 2.0 ms xp2-30 ? 2.0 2.1 ms xp2-40 ? 2.0 2.3 ms power-up refresh when programn is pulled up to v cc ? (v cc =v cc min) xp2-5 ? 1.8 2.1 ms xp2-8 ? 1.9 2.3 ms xp2-17 ? 1.7 2.0 ms xp2-30 ? 2.0 2.1 ms xp2-40 ? 2.0 2.3 ms device flash density program time units typ. xp2-5 1.2m tag 1 . 0 m s main array 1.1 s xp2-8 2.0m tag 1 . 0 m s main array 1.4 s xp2-17 3.6m tag 1 . 0 m s main array 1.8 s xp2-30 6.0m tag 2 . 0 m s main array 3.0 s xp2-40 8.0m tag 2 . 0 m s main array 4.0 s device flash density erase time units typ. xp2-5 1.2m tag 1 . 0 s main array 3.0 s xp2-8 2.0m tag 1 . 0 s main array 4.0 s xp2-17 3.6m tag 1 . 0 s main array 5.0 s xp2-30 6.0m tag 2 . 0 s main array 7.0 s xp2-40 8.0m tag 2 . 0 s main array 9.0 s
3-31 dc and switching characteristics lattice semiconductor lattice xp2 family data sheet flashbak time (from ebr to flash) over recommended operating conditions jtag port timing specifications over recommended operating conditions device ebr density (bits) time (typ.) units xp2-5 166k 1.5 s xp2-8 221k 1.5 s xp2-17 276k 1.5 s xp2-30 387k 2.0 s xp2-40 885k 3.0 s symbol parameter min. max. units f max tck clock frequency ? 25 mhz t btcp tck [bscan] clock pulse width 40 ? ns t btcph tck [bscan] clock pulse width high 20 ? ns t btcpl tck [bscan] clock pulse width low 20 ? ns t bts tck [bscan] setup time 8 ? ns t bth tck [bscan] hold time 10 ? ns t btrf tck [bscan] rise/fall time 50 ? mv/ns t btco tap controller falling edge of clock to valid output ? 10 ns t btcodis tap controller falling edge of clock to valid disable ? 10 ns t btcoen tap controller falling edge of clock to valid enable ? 10 ns t btcrs bscan test capture register setup time 8 ? ns t btcrh bscan test capture register hold time 25 ? ns t butco bscan test update register, falling edge of clock to valid output ? 25 ns t btuodis bscan test update register, falling edge of clock to valid disable ? 25 ns t btupoen bscan test update register, falling edge of clock to valid enable ? 25 ns timing v. a 0.12
3-32 dc and switching characteristics lattice semiconductor lattice xp2 family data sheet figure 3-10. jtag port timing waveforms tms tdi tck tdo data to be captured from i/o data to be driven out to i/o a t a d d i l a v a t a d d i l a v a t a d d i l a v a t a d d i l a v data captured t btcph t btcpl t btcoen t btcrs t btupoen t butco t btuodis t btcrh t btco t btcodis t bts t bth t btcp
3-33 dc and switching characteristics lattice semiconductor lattice xp2 family data sheet switching test conditions figure 3-11 shows the output test load that is used for ac testing. the speci? c values for resistance, capacitance, voltage, and other test conditions are shown in table 3-6. figure 3-11. output test load, lvttl and lvcmos standards table 3-6. test fixture required components, non-terminated interfaces test condition r 1 r 2 c l timing ref. v t lvttl and other lvcmos settings (l -> h, h -> l) ?? 0pf lvcmos 3.3 = 1.5v ? lvcmos 2.5 = v ccio /2 ? lvcmos 1.8 = v ccio /2 ? lvcmos 1.5 = v ccio /2 ? lvcmos 1.2 = v ccio /2 ? lvcmos 2.5 i/o (z -> h) ? 1m ? v ccio /2 ? lvcmos 2.5 i/o (z -> l) 1m ? ? v ccio /2 v ccio lvcmos 2.5 i/o (h -> z) ? 100 v oh - 0.10 ? lvcmos 2.5 i/o (l -> z) 100 ? v ol + 0.10 v ccio note: output test conditions for all other inte rfaces are determined by the respective standards. dut v t r1 r2 cl* test poi nt *cl includes test fixture and probe capacitance
www.latticesemi.com 4-1 pinout information_01.5 june 2008 data sheet ds1009 ? 2008 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. signal descriptions signal name i/o description general purpose p[edge] [row/column number*]_[a/b] i/o [edge] indicates the edge of the device on which the pad is located. valid edge designations are l (left), b (bottom), r (right), t (top). [row/column number] indicates the pfu row or the column of the device on which the pic exists. when edge is t (top) or b (bottom), only need to spec- ify row number. when edge is l (left) or r (right), only need to specify col- umn number. [a/b] indicates the pio within the pic to which the pad is connected. some of these user-programmable pins are shared with special function pins. these pins, when not used as special purpose pins, can be programmed as i/os for user logic. during configuration the user-programmable i/os are tri-stated with an internal pull-up resistor enabl ed. if any pin is not used (or not bonded to a package pin), it is also tri-stat ed with an internal pull-up resistor enabled after configuration. gsrn i global reset signal (activ e low). any i/o pin can be gsrn. nc ? no connect. gnd ? ground. dedicated pins. v cc ? power supply pins for core logic. dedicated pins. v ccaux ? auxiliary power supply pin. this dedicated pin powers all the differential and referenced input buffers. v ccpll ? pll supply pins. csbga, pqfp and tqfp packages only. v cciox ? dedicated power supply pins for i/o bank x. v ref1_x , v ref2_x ? reference supply pins for i/o bank x. pre-determined pins in each bank are assigned as v ref inputs. when not used, they may be used as i/o pins. pll and clock functions (used as user programmable i/o pins when not in use for pll or clock pins) [loc][num]_v ccpll ? power supply pin for pll: llc, lrc, urc, ulc, num = row from center. [loc][num]_gpll[t, c]_in_a i general purpose pll (gpll) input pads: llc, lrc, urc, ulc, num = row from center, t = true and c = complement, index a,b,c...at each side. [loc][num]_gpll[t, c]_fb_a i optional feedback gpll input pads: llc, lrc, urc, ulc, num = row from center, t = true and c = complement, index a,b,c...at each side. pclk[t, c]_[n:0]_[3:0] i primary clock pads, t = true and c = complement, n per side, indexed by bank and 0,1,2,3 within bank. [loc]dqs[num] i dqs input pads: t (top), r (right), b (bottom), l (left), dqs, num = ball function number. any pad can be configured to be output. test and programmin g (dedicated pins) tms i test mode select input, used to control the 1149.1 state machine. pull-up is enabled during configuration. tck i test clock input pin, used to clock the 1149.1 state machine. no pull-up enabled. tdi i test data in pin. used to load data into device using 1149.1 state machine. after power-up, this tap port can be activated for configuration by sending appropriate command. (note: once a co nfiguration port is selected it is locked. another configuration port cannot be selected until the power-up sequence). pull-up is enabled during configuration. latticexp2 family data sheet pinout information
4-2 pinout information lattice semiconductor lattice xp2 family data sheet tdo o output pin. test data out pin used to shift data out of a device using 1149.1. vccj ? power supply pin for jtag test access port. configuration pads (used during sysconfig) cfg[1:0] i mode pins used to specify configuratio n mode values latched on rising edge of initn. during configuration, an internal pull-up is enabled. initn 1 i/o open drain pin. indicates the fpga is re ady to be configured. during config- uration, a pull-up is enabled. programn i initiates configuration sequence when asserted low. this pin always has an active pull-up. done i/o open drain pin. indicates that the c onfiguration sequence is complete, and the startup sequence is in progress. cclk i/o configuration clock for configuring an fpga in sysconfig mode. sispi 2 i/o input data pin in slave spi mode and output data pin in master spi mode. sospi 2 i/o output data pin in slave spi mode and input data pin in master spi mode. csspin 2 o chip select for external spi flash memory in master spi mode. this pin has a weak internal pull-up. csspisn i chip select in slave spi mode. this pin has a weak internal pull-up. toe i test output enable tristates all i/o pins when driven low. this pin has a weak internal pull-up, but when not used an external pull-up to v cc is recom- mended. 1. if not actively driven, the internal pull-up may not be su fficient. an external pull- up resistor of 4.7k to 10k ? is recommended. 2. when using the device in master spi mode, it must be mutually exclusive from jtag operations (i.e. tck tied to gnd) or the jt ag tck must be free-running when used in a system jtag test environment. if master spi mode is used in conjunction with a jtag downloa d cable, the device power cycle is required after the cable is unplugged. signal descriptions (cont.) signal name i/o description
4-3 pinout information lattice semiconductor lattice xp2 family data sheet pics and ddr data (dq) pins associ ated with the ddr strobe (dqs) pin pics associated with dqs strobe pio within pic ddr strobe (dqs) and data (dq) pins for left and right edges of the device p[edge] [n-4] adq bdq p[edge] [n-3] adq bdq p[edge] [n-2] adq bdq p[edge] [n-1] adq bdq p[edge] [n] a[edge]dqsn bdq p[edge] [n+1] adq bdq p[edge] [n+2] adq bdq p[edge] [n+3] adq bdq for top and bottom edges of the device p[edge] [n-4] adq bdq p[edge] [n-3] adq bdq p[edge] [n-2] adq bdq p[edge] [n-1] adq bdq p[edge] [n] a [edge]dqsn bdq p[edge] [n+1] adq bdq p[edge] [n+2] adq bdq p[edge] [n+3] adq bdq p[edge] [n+4] adq bdq notes: 1. ?n? is a row pic number. 2. the ddr interface is designed for memori es that support one dqs strobe up to 16 bits of data for the left and right edges and up to 18 bits of data for the top and bottom edges. in some packages, all the potential ddr data (dq) pins may not be available. pic numbering definitions are provided in the ?signal names? column of the signal descriptions table.
4-4 pinout information lattice semiconductor lattice xp2 family data sheet pin information summary pin type xp2-5 xp2-8 xp2-17 xp2-30 xp2-40 132 csbga 144 tqfp 208 pqfp 256 ftbga 132 csbga 144 tqfp 208 pqfp 256 ftbga 208 pqfp 256 ftbga 484 fpbga 256 ftbga 484 fpbga 672 fpbga 484 fpbga 672 fpbga single ended user i/o 86 100 146 172 86 100 146 201 146 201 358 201 363 472 363 540 differential pair user i/o normal 35 39 57 66 35 39 57 77 57 77 135 77 137 180 137 204 highspeed 8 11 16 20 8 11 16 23 16 23 44 23 44 56 44 66 configuration tap 5555555555555555 muxed 9999999999999999 dedicated1111111111111111 non configura- tion muxed 5 57 7 7 79 9111121 7 11131113 dedicated1111111111111111 vcc 6 49 6 6 49 6 9 6 16 6 16201620 vccaux 4444444444848888 vccpll 222-222-4------- vccio bank0 2222222222424444 bank1 1122112222424444 bank2 2222222222424444 bank3 1122112222424444 bank4 1122112222424444 bank5 2222222222424444 bank6 1122112222424444 bank7 2222222222424444 gnd, gnd0-gnd7 15 15 20 20 15 15 22 20 22 20 56 20 56 64 56 64 nc - -431- -22-2722692 1 single ended/ differential i/o per bank bank0 18/9 20/10 20/10 26/13 18/9 20/10 20/10 28/14 20/10 28/14 52/26 28/14 52/26 70/35 52/26 70/35 bank1 4/2 6/3 18/9 18/9 4/2 6/3 18/9 22/11 18/9 22/11 36/18 22/11 36/18 54/27 36/18 70/35 bank2 16/8 18/9 18/9 22/11 16/8 18/9 18/9 26/13 18/9 26/13 46/23 26/13 46/23 56/28 46/23 64/32 bank3 4/2 4/2 16/8 20/10 4/2 4/2 16/8 24/12 16/8 24/12 44/22 24/12 46/23 56/28 46/23 66/33 bank4 8/4 8/4 18/9 18/9 8/4 8/4 18/9 26/13 18/9 26/13 36/18 26/13 38/19 54/27 38/19 70/35 bank5 14/7 18/9 20/10 24/12 14/7 18/9 20/10 24/12 20/10 24/12 52/26 24/12 53/26 70/35 53/26 70/35 bank6 6/3 8/4 18/9 22/11 6/3 8/4 18/9 27/13 18/9 27/13 46/23 27/13 46/23 56/28 46/23 66/33 bank7 16/8 18/9 18/9 22/11 16/8 18/9 18/9 24/12 18/9 24/12 46/23 24/12 46/23 56/28 46/23 64/32 true lvds pairs ? bonding out per bank bank0 0000000000000000 bank1 0000000000000000 bank2 3 44 5 3 44 6 4 6 11 6 11141116 bank3 1 14 5 1 14 6 4 6 11 6 11141117 bank4 0000000000000000 bank5 0000000000000000 bank6 1 24 5 1 24 6 4 6 11 6 11141117 bank7 3 44 5 3 44 5 4 5 11 5 11141116 ddr banks bonding out per i/o bank 1 bank0 1111111111312424 bank1 0011001111212324 bank2 1111111111213334 bank3 0011001111213334 bank4 0011001111212324 bank5 1111111111312424 bank6 0011001111213334 bank7 1111111111213334
4-5 pinout information lattice semiconductor lattice xp2 family data sheet logic signal connections package pinout information can be found under ?data sheets? on the latticexp2 product page of the lattice web- site a www.latticesemi.com/products/fpga/xp2 and in the lattice isplever software. thermal management thermal management is recommended as part of any sound fpga design methodology. to assess the thermal characteristics of a system, lattice sp ecifies a maximum allowable junction temperature in all device data sheets. designers must complete a thermal analysis of their specific design to ensure that the device and package do not exceed the junction temperature limits. refer to the lattice thermal management document to find the device/ package specific thermal values. for further information ? tn1139, power estimation and management for latticexp2 devices ? power calculator tool included wit h lattice?s isplever design tool, or as a standalone download from ? www.latticesemi.com/products/designsoftware pci capable i/os ? bonding out per bank bank0 18202026182020282028522852705270 bank1 4 61818 4 618221822362236543670 bank2 0000000000000000 bank3 0000000000000000 bank4 8 81818 8 818261826362638543870 bank5 14182024141820242024522453705370 bank6 0000000000000000 bank7 0000000000000000 1. minimum requirement to implement a full y functional 8-bit wide ddr bus. available ddr interface consists of at least 12 i/os (1 dqs + 1 dqsb + 8 dqs + 1 dm + bank vref1). pin information summary (cont.) pin type xp2-5 xp2-8 xp2-17 xp2-30 xp2-40 132 csbga 144 tqfp 208 pqfp 256 ftbga 132 csbga 144 tqfp 208 pqfp 256 ftbga 208 pqfp 256 ftbga 484 fpbga 256 ftbga 484 fpbga 672 fpbga 484 fpbga 672 fpbga
www.latticesemi.com 5-1 order info_01.2 august 2008 data sheet ds1009 ? 2008 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. part number description lfxp2 ? xx e ? x xxxxx x grade c = commercial i = industrial logic capacity 5 = 5k luts 8 = 8k luts 17 = 17k luts 30 = 30k luts 40 = 40k luts supply voltage e = 1.2v speed 5 = slowest 6 7 = fastest package m132 = 132-ball csbga ft256 = 256-ball ftbga f484 = 484-ball fpbga f672 = 672-ball fpbga mn132 = 132-ball lead-free csbga tn144 = 144-pin lead-free tqfp qn208 = 208-pin lead-free pqfp ftn256 = 256-ball lead-free ftbga fn484 = 484-ball lead-free fpbga fn672 = 672-ball lead-free fpbga device family xp2 ordering information the latticexp2 devices are marked with a single temperat ure grade, either commercial or industrial, as shown below. lfxp2-17e 7ft256c datecode xp2 lfxp2-17e 6ft256i datecode xp2 latticexp2 family data sheet ordering information
5-2 ordering information lattice semiconductor lattice xp2 family data sheet lead-free packaging commercial part number voltage grade package pins temp. luts (k) lfxp2-5e-5mn132c 1.2v -5 lead-free csbga 132 com 5 lfxp2-5e-6mn132c 1.2v -6 lead-free csbga 132 com 5 lfxp2-5e-7mn132c 1.2v -7 lead-free csbga 132 com 5 LFXP2-5E-5TN144C 1.2v -5 lead-free tqfp 144 com 5 lfxp2-5e-6tn144c 1.2v -6 lead-free tqfp 144 com 5 lfxp2-5e-7tn144c 1.2v -7 lead-free tqfp 144 com 5 lfxp2-5e-5qn208c 1.2v -5 lead-free pqfp 208 com 5 lfxp2-5e-6qn208c 1.2v -6 lead-free pqfp 208 com 5 lfxp2-5e-7qn208c 1.2v -7 lead-free pqfp 208 com 5 lfxp2-5e-5ftn256c 1.2v -5 lead-free ftbga 256 com 5 lfxp2-5e-6ftn256c 1.2v -6 lead-free ftbga 256 com 5 lfxp2-5e-7ftn256c 1.2v -7 lead-free ftbga 256 com 5 part number voltage grade package pins temp. luts (k) lfxp2-8e-5mn132c 1.2v -5 lead-free csbga 132 com 8 lfxp2-8e-6mn132c 1.2v -6 lead-free csbga 132 com 8 lfxp2-8e-7mn132c 1.2v -7 lead-free csbga 132 com 8 lfxp2-8e-5tn144c 1.2v -5 lead-free tqfp 144 com 8 lfxp2-8e-6tn144c 1.2v -6 lead-free tqfp 144 com 8 lfxp2-8e-7tn144c 1.2v -7 lead-free tqfp 144 com 8 lfxp2-8e-5qn208c 1.2v -5 lead-free pqfp 208 com 8 lfxp2-8e-6qn208c 1.2v -6 lead-free pqfp 208 com 8 lfxp2-8e-7qn208c 1.2v -7 lead-free pqfp 208 com 8 lfxp2-8e-5ftn256c 1.2v -5 lead-free ftbga 256 com 8 lfxp2-8e-6ftn256c 1.2v -6 lead-free ftbga 256 com 8 lfxp2-8e-7ftn256c 1.2v -7 lead-free ftbga 256 com 8 part number voltage grade package pins temp. luts (k) lfxp2-17e-5qn208c 1.2v -5 lead-free pqfp 208 com 17 lfxp2-17e-6qn208c 1.2v -6 lead-free pqfp 208 com 17 lfxp2-17e-7qn208c 1.2v -7 lead-free pqfp 208 com 17 lfxp2-17e-5ftn256c 1.2v -5 lead-free ftbga 256 com 17 lfxp2-17e-6ftn256c 1.2v -6 lead-free ftbga 256 com 17 lfxp2-17e-7ftn256c 1.2v -7 lead-free ftbga 256 com 17 lfxp2-17e-5fn484c 1.2v -5 lead-free fpbga 484 com 17 lfxp2-17e-6fn484c 1.2v -6 lead-free fpbga 484 com 17 lfxp2-17e-7fn484c 1.2v -7 lead-free fpbga 484 com 17
5-3 ordering information lattice semiconductor lattice xp2 family data sheet industrial part number voltage grade package pins temp. luts (k) lfxp2-30e-5ftn256c 1.2v -5 lead-free ftbga 256 com 30 lfxp2-30e-6ftn256c 1.2v -6 lead-free ftbga 256 com 30 lfxp2-30e-7ftn256c 1.2v -7 lead-free ftbga 256 com 30 lfxp2-30e-5fn484c 1.2v -5 lead-free fpbga 484 com 30 lfxp2-30e-6fn484c 1.2v -6 lead-free fpbga 484 com 30 lfxp2-30e-7fn484c 1.2v -7 lead-free fpbga 484 com 30 lfxp2-30e-5fn672c 1.2v -5 lead-free fpbga 672 com 30 lfxp2-30e-6fn672c 1.2v -6 lead-free fpbga 672 com 30 lfxp2-30e-7fn672c 1.2v -7 lead-free fpbga 672 com 30 part number voltage grade package pins temp. luts (k) lfxp2-40e-5fn484c 1.2v -5 lead-free fpbga 484 com 40 lfxp2-40e-6fn484c 1.2v -6 lead-free fpbga 484 com 40 lfxp2-40e-7fn484c 1.2v -7 lead-free fpbga 484 com 40 lfxp2-40e-5fn672c 1.2v -5 lead-free fpbga 672 com 40 lfxp2-40e-6fn672c 1.2v -6 lead-free fpbga 672 com 40 lfxp2-40e-7fn672c 1.2v -7 lead-free fpbga 672 com 40 part number voltage grade package pins temp. luts (k) lfxp2-5e-5mn132i 1.2v -5 lead-free csbga 132 ind 5 lfxp2-5e-6mn132i 1.2v -6 lead-free csbga 132 ind 5 lfxp2-5e-5tn144i 1.2v -5 lead-free tqfp 144 ind 5 lfxp2-5e-6tn144i 1.2v -6 lead-free tqfp 144 ind 5 lfxp2-5e-5qn208i 1.2v -5 lead-free pqfp 208 ind 5 lfxp2-5e-6qn208i 1.2v -6 lead-free pqfp 208 ind 5 lfxp2-5e-5ftn256i 1.2v -5 lead-free ftbga 256 ind 5 lfxp2-5e-6ftn256i 1.2v -6 lead-free ftbga 256 ind 5 part number voltage grade package pins temp. luts (k) lfxp2-8e-5mn132i 1.2v -5 lead-free csbga 132 ind 8 lfxp2-8e-6mn132i 1.2v -6 lead-free csbga 132 ind 8 lfxp2-8e-5tn144i 1.2v -5 lead-free tqfp 144 ind 8 lfxp2-8e-6tn144i 1.2v -6 lead-free tqfp 144 ind 8 lfxp2-8e-5qn208i 1.2v -5 lead-free pqfp 208 ind 8 lfxp2-8e-6qn208i 1.2v -6 lead-free pqfp 208 ind 8 lfxp2-8e-5ftn256i 1.2v -5 lead-free ftbga 256 ind 8 lfxp2-8e-6ftn256i 1.2v -6 lead-free ftbga 256 ind 8
5-4 ordering information lattice semiconductor lattice xp2 family data sheet part number voltage grade package pins temp. luts (k) lfxp2-17e-5qn208i 1.2v -5 lead-free pqfp 208 ind 17 lfxp2-17e-6qn208i 1.2v -6 lead-free pqfp 208 ind 17 lfxp2-17e-5ftn256i 1.2v -5 lead-free ftbga 256 ind 17 lfxp2-17e-6ftn256i 1.2v -6 lead-free ftbga 256 ind 17 lfxp2-17e-5fn484i 1.2v -5 lead-free fpbga 484 ind 17 lfxp2-17e-6fn484i 1.2v -6 lead-free fpbga 484 ind 17 part number voltage grade package pins temp. luts (k) lfxp2-30e-5ftn256i 1.2v -5 lead-free ftbga 256 ind 30 lfxp2-30e-6ftn256i 1.2v -6 lead-free ftbga 256 ind 30 lfxp2-30e-5fn484i 1.2v -5 lead-free fpbga 484 ind 30 lfxp2-30e-6fn484i 1.2v -6 lead-free fpbga 484 ind 30 lfxp2-30e-5fn672i 1.2v -5 lead-free fpbga 672 ind 30 lfxp2-30e-6fn672i 1.2v -6 lead-free fpbga 672 ind 30 part number voltage grade package pins temp. luts (k) lfxp2-40e-5fn484i 1.2v -5 lead-free fpbga 484 ind 40 lfxp2-40e-6fn484i 1.2v -6 lead-free fpbga 484 ind 40 lfxp2-40e-5fn672i 1.2v -5 lead-free fpbga 672 ind 40 lfxp2-40e-6fn672i 1.2v -6 lead-free fpbga 672 ind 40
5-5 ordering information lattice semiconductor lattice xp2 family data sheet conventional packaging commercial part number voltage grade package pins temp. luts (k) lfxp2-5e-5m132c 1.2v -5 csbga 132 com 5 lfxp2-5e-6m132c 1.2v -6 csbga 132 com 5 lfxp2-5e-7m132c 1.2v -7 csbga 132 com 5 lfxp2-5e-5ft256c 1.2v -5 ftbga 256 com 5 lfxp2-5e-6ft256c 1.2v -6 ftbga 256 com 5 lfxp2-5e-7ft256c 1.2v -7 ftbga 256 com 5 part number voltage grade package pins temp. luts (k) lfxp2-8e-5m132c 1.2v -5 csbga 132 com 8 lfxp2-8e-6m132c 1.2v -6 csbga 132 com 8 lfxp2-8e-7m132c 1.2v -7 csbga 132 com 8 lfxp2-8e-5ft256c 1.2v -5 ftbga 256 com 8 lfxp2-8e-6ft256c 1.2v -6 ftbga 256 com 8 lfxp2-8e-7ft256c 1.2v -7 ftbga 256 com 8 part number voltage grade package pins temp. luts (k) lfxp2-17e-5ft256c 1.2v -5 ftbga 256 com 17 lfxp2-17e-6ft256c 1.2v -6 ftbga 256 com 17 lfxp2-17e-7ft256c 1.2v -7 ftbga 256 com 17 lfxp2-17e-5f484c 1.2v -5 fpbga 484 com 17 lfxp2-17e-6f484c 1.2v -6 fpbga 484 com 17 lfxp2-17e-7f484c 1.2v -7 fpbga 484 com 17 part number voltage grade package pins temp. luts (k) lfxp2-30e-5ft256c 1.2v -5 ftbga 256 com 30 lfxp2-30e-6ft256c 1.2v -6 ftbga 256 com 30 lfxp2-30e-7ft256c 1.2v -7 ftbga 256 com 30 lfxp2-30e-5f484c 1.2v -5 fpbga 484 com 30 lfxp2-30e-6f484c 1.2v -6 fpbga 484 com 30 lfxp2-30e-7f484c 1.2v -7 fpbga 484 com 30 lfxp2-30e-5f672c 1.2v -5 fpbga 672 com 30 lfxp2-30e-6f672c 1.2v -6 fpbga 672 com 30 lfxp2-30e-7f672c 1.2v -7 fpbga 672 com 30
5-6 ordering information lattice semiconductor lattice xp2 family data sheet industrial part number voltage grade package pins temp. luts (k) lfxp2-40e-5f484c 1.2v -5 fpbga 484 com 40 lfxp2-40e-6f484c 1.2v -6 fpbga 484 com 40 lfxp2-40e-7f484c 1.2v -7 fpbga 484 com 40 lfxp2-40e-5f672c 1.2v -5 fpbga 672 com 40 lfxp2-40e-6f672c 1.2v -6 fpbga 672 com 40 lfxp2-40e-7f672c 1.2v -7 fpbga 672 com 40 part number voltage grade package pins temp. luts (k) lfxp2-5e-5m132i 1.2v -5 csbga 132 ind 5 lfxp2-5e-6m132i 1.2v -6 csbga 132 ind 5 lfxp2-5e-6ft256i 1.2v -6 ftbga 256 ind 5 part number voltage grade package pins temp. luts (k) lfxp2-8e-5m132i 1.2v -5 csbga 132 ind 8 lfxp2-8e-6m132i 1.2v -6 csbga 132 ind 8 lfxp2-5e-5ft256i 1.2v -5 ftbga 256 ind 5 lfxp2-8e-5ft256i 1.2v -5 ftbga 256 ind 8 lfxp2-8e-6ft256i 1.2v -6 ftbga 256 ind 8 part number voltage grade package pins temp. luts (k) lfxp2-17e-5ft256i 1.2v -5 ftbga 256 ind 17 lfxp2-17e-6ft256i 1.2v -6 ftbga 256 ind 17 lfxp2-17e-5f484i 1.2v -5 fpbga 484 ind 17 lfxp2-17e-6f484i 1.2v -6 fpbga 484 ind 17 part number voltage grade package pins temp. luts (k) lfxp2-30e-5ft256i 1.2v -5 ftbga 256 ind 30 lfxp2-30e-6ft256i 1.2v -6 ftbga 256 ind 30 lfxp2-30e-5f484i 1.2v -5 fpbga 484 ind 30 lfxp2-30e-6f484i 1.2v -6 fpbga 484 ind 30 lfxp2-30e-5f672i 1.2v -5 fpbga 672 ind 30 lfxp2-30e-6f672i 1.2v -6 fpbga 672 ind 30
5-7 ordering information lattice semiconductor lattice xp2 family data sheet part number voltage grade package pins temp. luts (k) lfxp2-40e-5f484i 1.2v -5 fpbga 484 ind 40 lfxp2-40e-6f484i 1.2v -6 fpbga 484 ind 40 lfxp2-40e-5f672i 1.2v -5 fpbga 672 ind 40 lfxp2-40e-6f672i 1.2v -6 fpbga 672 ind 40
may 2007 data sheet ds1009 ? 2007 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. www.latticesemi.com 6-1 further info_01.1 for further information a variety of technical notes for the latticexp2 fpga family are available on the lattice semiconductor web site at ? www.latticesemi.com . ? tn1136, latticexp2 sysio usage guide ? tn1137, latticexp2 memory usage guide ? tn1138, latticexp2 high speed i/o interface ? tn1126, latticexp2 sysclock pll design and usage guide ? tn1139, power estimation and management for latticexp2 devices ? tn1140, latticexp2 sysdsp usage guide ? tn1141, latticexp2 sysconfig usage guide ? tn1142, latticexp2 configuration encryption and security usage guide ? tn1087, minimizing system interruption during configuration using transfr technology ? tn1144, latticexp2 dual boot usage guide ? tn1130, latticexp2 soft error detection (sed) usage guide ? tn1143, latticexp2 hardware checklist for further information on interface standards refer to the following websites: ? jedec standards (lvttl, lvcm os, sstl, hstl): www.jedec.org ? pci: www.pcisig.com latticexp2 family data sheet supplemental information
august 2008 data sheet ds1009 ? 2008 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the specifications and information herein are subject to change without notice. www.latticesemi.com 7-1 revision history date version section change summary may 2007 01.1 ? initial release. september 2007 01.2 dc and switching characteristics added jtag port timing waveforms diagram. updated sysclock pll timing table. pinout information added therma l management text section. february 2008 01.3 architecture added lvcmos33 d to supported output standards table. clarified: ?this flash can be programmed through either the jtag or slave spi ports of the device. the sram configuration space can also be infinitely reconfigured through the jtag and master spi ports.? added external slave spi port to serial tag memory section. updated serial tag memory diagram. dc and switching characteristics updated flash programming specifications table. added ?8w? specification to hot socketing specifications table. updated timing tables clarifications for iih in dc electrical characteristics table. added lvcmos33d section updated doa and doa (regs) to ebr timing diagrams. removed master clock frequency and duty cycle sections from the latticexp2 sysconfig port timing specificati ons table. these are listed on the on-chip oscillator and configuration master clock charac- teristics table. changed csspin to csspisn in description of t scs , t scss , and t scsh parameters. removed t soe parameter. clarified on-chip oscillator documentation added switching test conditions pinout information added ?true lvds pairs bonding out per bank,? ?ddr banks bonding out per i/o bank,? and ?pci capable i/os bonding out per bank? to pin information summary in place of previous blank table ?pci and ddr capabilities of the device-package combinations? removed pinout listing. this information is available on the latticexp2 product web pages ordering information added xp2-17 ?8w? and all other family opns. april 2008 01.4 dc and switching characteristics updated absolute maximum ratings footnotes. updated recommended operating conditions table footnotes. updated supply current (standby) table updated initialization supply current table updated programming and erase flash supply current table updated register to register performance table updated latticexp2 external switching characteristics table updated latticexp2 internal switching characteristics table updated sysclock pll timing table latticexp2 family data sheet revision history
7-2 revision history lattice semiconductor lattice xp2 family data sheet april 2008 (cont.) 01.4 (cont.) dc and switching characteristics (cont.) updated flash download time (from on-chip flash to sram) table updated flash program time table updated flash erase time table updated flashbak (from ebr to flash) table updated hot socketing spec ifications table footnotes pinout information updated signal descriptions table june 2008 01.5 architecture removed re ad-before-write sysmem ebr mode. clarification of the operation of the secondary clock regions. dc and switching characteristics removed read-before-write sysmem ebr mode. pinout information updated ddr banks bonding out per i/o bank section of pin informa- tion summary table. august 2008 01.6 ? data sheet status changed from preliminary to final. architecture clarification of the operation of the secondary clock regions. dc and switching characteristics removed ?8w? specification from hot socketing specifications table. removed "8w" footnote from dc electrical characteristics table. updated register-to-register performance table. ordering information removed ?8w? option from part number description. removed xp2-17 ?8w? opns. date version section change summary

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