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rene s a s 1 6 -bit s in g le- c hip mi c r oco mp u te r m16 c family / m16 c /tin y s erie s m16c/26a group(m16c/26a,m16c/26t) 16 rev. 1.00 revision date: mar.15, 2005 hardware manual www.renesas.com before using this material, please visit our website to verify that this is the most current document available. rej09b0202-0100
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how to use this manual 1. introduction this hardware manual provides detailed information on the m16c/26 group (m16c/26a, m16c/26t) microcom- puters. users are expected to have basic knowledge of electric circuits, logical circuits and microcomputers. 2. register diagram the symbols, and descriptions, used for bit function in each register are shown below. function xxx register bit name bit symbol symbol address after reset xxx xxx 00h rw rw rw wo ro xxx0 xxx1 (b2) (b4 - b3) xxx bit reserved bit xxx7 set to "0" 0: xxx 1: xxx nothing is assigned. when write, set to "0". when read, its content is indeterminate. xxx bit 0 0: xxx 0 1: xxx 1 0: do not set a value 1 1: xxx b1 b0 xxx bit function varies depending on mode of operation xxx5 xxx6 0 rw rw b7 b6 b5 b4 b3 b2 b1 b0 *1 *2 *4 *3 0 *5 *1 blank:set to "0" or "1" according to the application 0: set to "0" 1: set to "1" x: nothing is assigned *2 rw: read and write ro: read only wo: write only ? nothing is assigned *3 ?reserved bit reserved bit. set to specified value. *4 ?nothing is assigned nothing is assigned to the bit concerned. as the bit may be use for future functions, set to "0" when writing to this bit. ?do not set a value the operation is not guaranteed when a value is set. ?function varies depending on mode of operation bit function varies depending on peripheral function mode. refer to respective register for each mode.
3. m16c family documents the following documents were prepared for the m16c family. (1) document contents short sheet hardware overview data sheet hardware overview and electrical characteristics hardware manual hardware specifications (pin assignments, memory maps, peripheral specifications, electrical characteristics, timing charts) software manual detailed description of assembly instructions and microcomputer perfor- mance of each instruction application note ?application examples of peripheral functions ?sample programs ?introduction to the basic functions in the m16c family ?programming method with assembly and c languages renesas technical update preliminary report about the specification of a product, a document, etc. notes : 1. before using this material, please visit the our website to verify that this is the most current document available.
a-1 table of contents quick reference by address _____________________ b-1 1. overview _____________________________________ 1 1.1 applications ............................................................................................................... .. 1 1.2 performance outline ................................................................................................... 2 1.3 block diagram ............................................................................................................. 4 1.4 product list ............................................................................................................... .. 6 1.5 pin configuration ........................................................................................................ 9 1.6 pin description .......................................................................................................... 11 2. central processing unit (cpu)___________________ 13 2.1 data registers (r0, r1, r2 and r3) ......................................................................... 13 2.2 address registers (a0 and a1) ................................................................................ 13 2.3 frame base register (fb) ........................................................................................ 14 2.4 interrupt table register (intb) ................................................................................ 14 2.5 program counter (pc) .............................................................................................. 14 2.6 user stack pointer (usp) and interrupt stack pointer (isp) ................................. 14 2.7 static base register (sb) ......................................................................................... 14 2.8 flag register (flg) ................................................................................................... 14 2.8.1 carry flag (c flag) ............................................................................................. 14 2.8.2 debug flag (d flag) ........................................................................................... 14 2.8.3 zero flag (z flag) .............................................................................................. 14 2.8.4 sign flag (s flag) ............................................................................................... 14 2.8.5 register bank select flag (b flag) .................................................................. 14 2.8.6 overflow flag (o flag) ....................................................................................... 14 2.8.7 interrupt enable flag (i flag) ............................................................................ 14 2.8.8 stack pointer select flag (u flag) .................................................................... 14 2.8.9 processor interrupt priority level (ipl) ........................................................... 14 2.8.10 reserved area .................................................................................................. 14 3. memory______________________________________ 15 4. special function register (sfr) _________________ 16 5. reset________________________________________ 22 5.1 hardware reset ......................................................................................................... 22 5.1.1 hardware reset 1 ............................................................................................... 22 5.1.2 hardware reset 2 ............................................................................................... 22
a-2 5.2 software reset .......................................................................................................... 23 5.3 watchdog timer reset ............................................................................................. 23 5.4 oscillation stop detection reset ............................................................................. 23 5.5 voltage detection circuit .......................................................................................... 25 6. processor mode ______________________________ 31 7. clock generation circuit ................................................ 32 7.1 main clock ................................................................................................................. 39 7.2 sub clock .................................................................................................................. .40 7.3 on-chip oscillator clock .......................................................................................... 41 7.4 pll clock .................................................................................................................. .41 7.5 cpu clock and peripheral function clock ............................................................. 43 7.5.1 cpu clock ........................................................................................................... 43 7.5.2 peripheral function clock(f 1 , f 2 , f 8 , f 32 , f 1sio , f 2sio , f 8sio , f 32sio , f ad, f c32 ) ........ 43 7.5.3 clockoutput function ....................................................................................... 43 7.6 power control ............................................................................................................ 44 7.6.1 normal operation mode .................................................................................... 44 7.6.2 wait mode ........................................................................................................... 45 7.6.3 stop mode .......................................................................................................... 47 7.7 system clock protective function .......................................................................... 51 7.8 oscillation stop and re-oscillation detect function ............................................. 51 7.8.1 operation when the cm27 bit is set to "0" (oscillation stop detection reset) ...... 52 7.8.2 operation when the cm27 bit is set to "1" (oscillation stop and re-oscillation detect interrupt) ... 52 7.8.3 how to use oscillation stop and re-oscillation detect function ................. 53 8. protection____________________________________ 54 9. interrupt _____________________________________ 55 9.1 type of interrupts ...................................................................................................... 55 9.1.1 software interrupts ............................................................................................ 56 9.1.2 hardware interrupts ........................................................................................... 57 9.2 interrupts and interrupt vector ................................................................................ 58 9.2.1 fixed vector tables ........................................................................................... 58 9.2.2 relocatable vector tables ................................................................................. 59 9.3 interrupt control ........................................................................................................ 60 9.3.1 i flag ................................................................................................................... .63 9.3.2 ir bit ................................................................................................................... .63 9.3.3 ilvl2 to ilvl0 bits and ipl ............................................................................... 63
a-3 9.4 interrupt sequence ................................................................................................... 64 9.4.1 interrupt response time ................................................................................... 65 9.4.2 variation of ipl when interrupt request is accepted ..................................... 65 9.4.3 saving registers ................................................................................................ 66 9.4.4 returning from an interrupt routine ................................................................ 68 9.5 interrupt priority ........................................................................................................ 6 8 9.5.1 interrupt priority resolution circuit ................................................................. 68 ______ 9.6 int interrupt .............................................................................................................. .70 ______ 9.7 nmi interrupt .............................................................................................................. 71 9.8 key input interrupt .................................................................................................... 71 9.9 address match interrupt ........................................................................................... 72 10. watchdog timer _____________________________ 74 10.1 count source protective mode .............................................................................. 75 10.2 cold start / warm start ............................................................................................ 76 11. dmac ______________________________________ 77 11.1 transfer cycles ....................................................................................................... 82 11.2. dma transfer cycles .............................................................................................. 84 11.3 dma enable .............................................................................................................. 85 11.4 dma request ........................................................................................................... 85 11.5 channel priority and dma transfer timing ......................................................... 86 12. timer_______________________________________ 87 12.1 timer a .................................................................................................................. .. 89 12.1.1. timer mode ...................................................................................................... 92 12.1.2. event counter mode ....................................................................................... 93 12.1.3. one-shot timer mode ..................................................................................... 98 12.1.4. pulse width modulation (pwm) mode ......................................................... 100 12.2 timer b .................................................................................................................. 103 12.2.1 timer mode .................................................................................................... 106 12.2.2 event counter mode ...................................................................................... 107 12.2.3 pulse period and pulse width measurement mode ................................... 108 12.2.4 a/d trigger mode .......................................................................................... 110 12.3 three-phase motor control timer function ....................................................... 112 12.3.1 position-data-retain function ....................................................................... 123 12.3.2 three-phase/port output switch function .................................................. 125
a-4 13. serial i/o ___________________________________ 127 13.1. uarti (i=0 to 2) .................................................................................................... 127 13.1.1. clock synchronous serial i/o mode ............................................................ 137 13.1.2. clock asynchronous serial i/o (uart) mode ............................................ 145 13.1.3 special mode 1 (i 2 c bus mode)(uart2) ...................................................... 153 13.1.4 special mode 2 (uart2) ................................................................................ 163 13.1.5 special mode 3 (ie bus mode )(uart2) ..................................................... 168 13.1.6 special mode 4 (sim mode) (uart2) .......................................................... 170 14. a/d converter ______________________________ 175 14.1 operation modes ................................................................................................... 181 14.1.1 one-shot mode .............................................................................................. 181 14.1.2 repeat mode .................................................................................................. 183 14.1.3 single sweep mode ...................................................................................... 185 14.1.4 repeat sweep mode 0 ................................................................................... 187 14.1.5 repeat sweep mode 1 ................................................................................... 189 14.1.6 simultaneous sample sweep mode ............................................................. 191 14.1.7 delayed trigger mode 0 ................................................................................. 194 14.1.8 delayed trigger mode 1 ................................................................................. 200 14.2 resolution select function .................................................................................. 206 14.3 sample and hold ................................................................................................... 206 14.4 power consumption reducing function ............................................................ 206 14.5 output impedance of sensor under a/d conversion ........................................ 207 15. crc calculation circuit ______________________ 208 15.1. crc snoop ........................................................................................................... 208 16. programmable i/o ports ______________________ 211 16.1 port pi direction register (pdi register, i = 1, 6 to 10)...................................... 211 16.2 port pi register (pi register, i = 1, 6 to 10) ......................................................... 211 16.3 pull-up control register 0 to pull-up control register 2 (pur0 to pur2 registers) ........ 211 16.4 port control register ............................................................................................ 212 16.5 pin assignment control register (pacr) ............................................................ 212 16.6 digital debounce function .................................................................................... 212 17. flash memory version _______________________ 225 17.1 flash memory performance ................................................................................. 225 17.2 memory map .......................................................................................................... 227
a-5 17.3 functions to prevent flash memory from rewriting ........................................ 230 17.3.1 rom code protect function ......................................................................... 230 17.3.2 id code check function ............................................................................... 230 17.4 cpu rewrite mode ................................................................................................ 232 17.4.1 ew0 mode ....................................................................................................... 233 17.4.2 ew1 mode ....................................................................................................... 233 17.5 register description ............................................................................................. 234 17.5.1 flash memory control register 0 (fmr0) ..................................................... 234 17.5.2 flash memory control register 1 (fmr1) ..................................................... 235 17.5.3 flash memory control register 4 (fmr4) ..................................................... 235 17.6 precautions in cpu rewrite mode ...................................................................... 240 17.6.1 operation speed ............................................................................................ 240 17.6.2 prohibited instructions .................................................................................. 240 17.6.3 interrupts ........................................................................................................ 240 17.6.4 how to access................................................................................................ 240 17.6.5 writing in the user rom space .................................................................... 240 17.6.6 dma transfer .................................................................................................. 241 17.6.7 writing command and data .......................................................................... 241 17.6.8 wait mode ....................................................................................................... 241 17.6.9 stop mode ....................................................................................................... 241 17.6.10 low power consumption mode and on-chip oscillator-low power consumption mode .......................................................................... 241 17.7 software commands ............................................................................................ 242 17.7.1 read array command (ff16)........................................................................ 242 17.7.2 read status register command (7016) ....................................................... 242 17.7.3 clear status register command (5016) ....................................................... 243 17.7.4 program command (4016) ............................................................................ 243 17.7.5 block erase .................................................................................................... 244 17.8 status register ...................................................................................................... 246 17.8.1 sequence status (sr7 and fmr00 bits ) ..................................................... 246 17.8.2 erase status (sr5 and fmr07 bits) ............................................................. 246 17.8.3 program status (sr4 and fmr06 bits) ........................................................ 246 17.8.4 full status check ........................................................................................... 247 17.9 standard serial i/o mode ...................................................................................... 249 17.9.1 id code check function ............................................................................... 249 17.9.2 example of circuit application in standard serial i/o mode ..................... 253 17.10 parallel i/o mode ................................................................................................. 255 17.10.1 rom code protect function ....................................................................... 255
a-6 18. electrical characteristics _____________________ 256 18.1. normal version ..................................................................................................... 256 18.2. t version ............................................................................................................... 2 75 19. usage precaution ___________________________ 294 19.1 sfr ....................................................................................................................... .. 294 19.1.1 precaution for 48 pin version ....................................................................... 294 19.1.2 precaution for 42 pin version ....................................................................... 294 19.2 pll frequency synthesizer ................................................................................. 295 19.3 power control ........................................................................................................ 296 19.4 protect ................................................................................................................... . 298 19.5 interrupts ............................................................................................................... 2 99 19.5.1 reading address 0000016 ............................................................................. 299 19.5.2 setting the sp ................................................................................................. 299 _______ 19.5.3 the nmi interrupt ........................................................................................... 299 19.5.4 changing the interrupt generation factor .................................................. 300 19.5.6 rewrite the interrupt control register ......................................................... 301 19.5.7 watchdog timer interrupt ............................................................................. 302 19.6 dmac ..................................................................................................................... 3 03 19.6.1 write to dmae bit in dmicon register ....................................................... 303 19.7 timer..................................................................................................................... .. 304 19.7.1 timer a ............................................................................................................ 304 19.7.2 timer b ............................................................................................................ 308 19.8 serial i/o (clock-synchronous serial i/o) ........................................................... 311 19.8.1 transmission/reception................................................................................. 311 19.8.2 transmission .................................................................................................. 312 19.8.3 reception ........................................................................................................ 313 19.9 serial i/o (uart mode) ......................................................................................... 314 19.9.1 special mode 1 (i 2 c bus mode) ..................................................................... 314 19.9.2 special mode 2 ............................................................................................... 314 19.9.3 special mode 4 (sim mode) ........................................................................... 314 19.10 a/d converter ...................................................................................................... 315 19.11 programmable i/o ports ..................................................................................... 317 19.12 electric characteristic differences between mask rom and flash memory version microcomputers ..................................................................... 318 19.13 mask rom version .............................................................................................. 318 19.13.1 internal rom area ........................................................................................ 318 19.13.2 reserve bit .................................................................................................... 318
a-7 19.14 flash memory version ........................................................................................ 319 19.14.1 functions to inhibit rewriting flash memory ........................................... 319 19.14.2 stop mode .................................................................................................... 319 19.14.3 wait mode ..................................................................................................... 319 19.14.4 low power dissipation mode, on-chip oscillator low power dissipation mode ...... 319 19.14.5 writing command and data ......................................................................... 319 19.14.6 program command ...................................................................................... 319 19.14.7 operation speed ........................................................................................... 319 19.14.8 instructions prohibited in ew0 mode ........................................................ 320 19.14.9 interrupts ...................................................................................................... 320 19.14.10 how to access ............................................................................................ 320 19.14.11 writing in the user rom area .................................................................... 320 19.14.12 dma transfer............................................................................................... 320 19.14.13 regarding programming/erasure times and execution time .............. 321 19.14.14 definition of programming/erasure times .............................................. 321 19.14.15 flash memory version electrical characteristics 10,000 e/w cycle products (u7, u9) ............................................................................. 321 19.14.16 boot mode .................................................................................................. 321 19.15 noise .................................................................................................................... 322 19.16 instruction for a device use ............................................................................... 323 appendix 1. package dimensions _________________ 324 appendix 2. functional difference ________________ 325 appendix 2.1 differences between m16c/26a and m16c/26t................................... 325 appendix 2.2 differences between m16c/26a and m16c/26 ..................................... 326 register index _________________________________ 327
b-1 quick reference by address 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 address note: the blank areas are reserved and cannot be accessed by users. register symbol page 0040 16 0041 16 0042 16 0043 16 0044 16 0045 16 0046 16 0047 16 0048 16 0049 16 004a 16 004b 16 004c 16 004d 16 004e 16 004f 16 0050 16 0051 16 0052 16 0053 16 0054 16 0055 16 0056 16 0057 16 0058 16 0059 16 005a 16 005b 16 005c 16 005d 16 005e 16 005f 16 0060 16 0061 16 0062 16 0063 16 0064 16 0065 16 0066 16 0067 16 0068 16 0069 16 006a 16 006b 16 006c 16 006d 16 006e 16 006f 16 0070 16 0071 16 0072 16 0073 16 0074 16 0075 16 0076 16 0077 16 0078 16 0079 16 007a 16 007b 16 007c 16 007d 16 007e 16 007f 16 watchdog timer start register wdts watchdog timer control register wdc processor mode register 0 pm0 system clock control register 0 cm0 system clock control register 1 cm1 address match interrupt enable register aier protect register prcr processor mode register 1 pm1 oscillation stop detection register cm2 pll control register 0 plc0 processor mode register 2 pm2 address match interrupt register 0 rmad0 address match interrupt register 1 rmad1 dma0 control register dm0con dma0 transfer counter tcr0 dma1 control register dm1con dma1 source pointer sar1 dma1 destination pointer dar1 dma0 destination pointer dar0 dma0 source pointer sar0 voltage detection register 1 vcr1 voltage detection register 2 vcr2 voltage down detection interrupt register d4int uart0 transmit interrupt control register s0tic uart0 receive interrupt control register s0ric uart1 transmit interrupt control register s1tic uart1 receive interrupt control register s1ric dma1 transfer counter tcr1 int3 interrupt control register int3ic int5 interrupt control register int5ic int4 interrupt control register int4ic uart2 bus collision detection interrupt control register bcnic dma0 interrupt control register dm0ic dma1 interrupt control register dm1ic key input interrupt control register kupic a/d conversion interrupt control register adic uart2 transmit interrupt control register s2tic uart2 receive interrupt control register s2ric timer a0 interrupt control register ta0ic timer a1 interrupt control register ta1ic timer a2 interrupt control register ta2ic timer a3 interrupt control register ta3ic timer a4 interrupt control register ta4ic timer b0 interrupt control register tb0ic timer b2 interrupt control register tb2ic int0 interrupt control register int0ic int1 interrupt control register int1ic int2 interrupt control register int2ic timer b1 interrupt control register tb1ic 31 31 34 35 73 54 36 75 75 73 73 26 26 38 37 26 81 81 81 80 81 81 81 80 61 61 61 61 61 61 61 61 61 61 61 61 61 61 61 61 61 61 61 61 61 61 61 61 61 address register symbol page
b-2 quick reference by address note 1: the blank areas are reserved and cannot be accessed by users. note 2: this register is included in the flash memory version. 0080 16 0081 16 0082 16 0083 16 0084 16 0085 16 0086 16 01b0 16 01b1 16 01b2 16 01b3 16 01b4 16 01b5 16 01b6 16 01b7 16 01b8 16 01b9 16 01ba 16 01bb 16 01bc 16 01bd 16 01be 16 01bf 16 0250 16 0251 16 0252 16 0253 16 0254 16 0255 16 0256 16 0257 16 0258 16 0259 16 025a 16 025b 16 025c 16 025d 16 025e 16 025f 16 02e0 16 02e1 16 02e2 16 02e3 16 02e4 16 02e5 16 02e6 16 02e7 16 02e8 16 02e9 16 033d 16 033e 16 033f 16 peripheral clock select register pclkr flash memory control register 0 fmr0 flash memory control register 1 fmr1 236 236 37 (note 2) (note 2) address register symbol page (note 2) flash memory control register 4 fmr4 237 pin assignment control register pacr on-chip oscillator control register rocr 134, 221 35 p1 7 digital debounce register p17ddr nmi digital debounce register nddr 222 222 three phase protect control register tprc 0340 16 0341 16 0342 16 0343 16 0344 16 0345 16 0346 16 0347 16 0348 16 0349 16 034a 16 034b 16 034c 16 034d 16 034e 16 034f 16 0350 16 0351 16 0352 16 0353 16 0354 16 0355 16 0356 16 0357 16 0358 16 0359 16 035a 16 035b 16 035c 16 035d 16 035e 16 035f 16 0360 16 0361 16 0362 16 0363 16 0364 16 0365 16 0366 16 0367 16 0368 16 0369 16 036a 16 036b 16 036c 16 036d 16 036e 16 036f 16 0370 16 0371 16 0372 16 0373 16 0374 16 0375 16 0376 16 0377 16 0378 16 0379 16 037a 16 037b 16 037c 16 037d 16 037e 16 037f 16 timer a1-1 register ta11 timer a2-1 register ta21 dead time timer dtt timer b2 interrupt occurrence frequency set counter ictb2 three-phase pwm control register 0 invc0 three-phase pwm control register 1 invc1 three-phase output buffer register 0 idb0 three-phase output buffer register 1 idb1 interrupt request cause select register ifsr uart2 special mode register u2smr uart2 receive buffer register u2rb uart2 transmit buffer register u2tb uart2 transmit/receive control register 0 u2c0 uart2 transmit/receive mode register u2mr uart2 transmit/receive control register 1 u2c1 uart2 bit rate generator u2brg timer a4-1 register ta41 uart2 special mode register 2 u2smr2 uart2 special mode register 3 u2smr3 uart2 special mode register 4 u2smr4 117 117 117 114 115 116 116 116 116 136 136 135 135 132 131 131 133 134 131 62, 70 address register symbol page position-data-retain function contol register pdrf 124 port function contol register pfcr interrupt request cause select register 2 ifsr2a 62 126 126
b-3 quick reference by address note : the blank areas are reserved and cannot be accessed by users. 0380 16 0381 16 0382 16 0383 16 0384 16 0385 16 0386 16 0387 16 0388 16 0389 16 038a 16 038b 16 038c 16 038d 16 038e 16 038f 16 0390 16 0391 16 0392 16 0393 16 0394 16 0395 16 0396 16 0397 16 0398 16 0399 16 039a 16 039b 16 039c 16 039d 16 039e 16 039f 16 03a0 16 03a1 16 03a2 16 03a3 16 03a4 16 03a5 16 03a6 16 03a7 16 03a8 16 03a9 16 03aa 16 03ab 16 03ac 16 03ad 16 03ae 16 03af 16 03b0 16 03b1 16 03b2 16 03b3 16 03b4 16 03b5 16 03b6 16 03b7 16 03b8 16 03b9 16 03ba 16 03bb 16 03bc 16 03bd 16 03be 16 03bf 16 count start flag tabsr trigger select register trgsr timer a0 register ta0 timer a1 register ta1 timer a2 register ta2 timer b0 register tb0 timer b1 register tb1 timer b2 register tb2 one-shot start flag onsf timer a0 mode register ta0mr timer a1 mode register ta1mr timer a2 mode register ta2mr timer b0 mode register tb0mr timer b1 mode register tb1mr timer b2 mode register tb2mr up-down flag udf timer a3 register ta3 timer a4 register ta4 timer a3 mode register ta3mr timer a4 mode register ta4mr clock prescaler reset flag cpsrf uart0 transmit/receive mode register u0mr uart0 transmit buffer register u0tb uart0 receive buffer register u0rb uart1 transmit/receive mode register u1mr uart1 transmit buffer register u1tb uart1 receive buffer register u1rb uart0 bit rate generator u0brg uart0 transmit/receive control register 0 u0c0 uart0 transmit/receive control register 1 u0c1 uart1 bit rate generator u1brg uart1 transmit/receive control register 0 u1c0 uart1 transmit/receive control register 1 u1c1 dma1 request cause select register dm1sl dma0 request cause select register dm0sl uart transmit/receive control register 2 ucon timer b2 special mode register tb2sc 90, 105, 119 91 91, 105 91, 119 90 105 105 105, 119 89 89, 120 89 104 104 111, 118 132 131 131 133 134 131 132 131 131 133 134 131 133 79 80 90 90, 117 90, 117 90 90, 117 89, 120 89, 120 104, 120 address register symbol page crc snoop address register crcsar crc mode register crcmr crc data register crcd crc input register crcin 03c0 16 03c1 16 03c2 16 03c3 16 03c4 16 03c5 16 03c6 16 03c7 16 03c8 16 03c9 16 03ca 16 03cb 16 03cc 16 03cd 16 03ce 16 03cf 16 03d0 16 03d1 16 03d2 16 03d3 16 03d4 16 03d5 16 03d6 16 03d7 16 03d8 16 03d9 16 03da 16 03db 16 03dc 16 03dd 16 03de 16 03df 16 03e0 16 03e1 16 03e2 16 03e3 16 03e4 16 03e5 16 03e6 16 03e7 16 03e8 16 03e9 16 03ea 16 03eb 16 03ec 16 03ed 16 03ee 16 03ef 16 03f0 16 03f1 16 03f2 16 03f3 16 03f4 16 03f5 16 03f6 16 03f7 16 03f8 16 03f9 16 03fa 16 03fb 16 03fc 16 03fd 16 03fe 16 03ff 16 a/d control register 1 adcon1 port p9 register p9 pull-up control register 0 pur0 port control register pcr a/d register 7 ad7 a/d register 0 ad0 a/d register 1 ad1 a/d register 2 ad2 a/d register 3 ad3 a/d register 4 ad4 a/d register 5 ad5 a/d register 6 ad6 a/d control register 0 adcon0 a/d control register 2 adcon2 port p1 register p1 port p1 direction register pd1 port p6 register p6 port p6 direction register pd6 port p7 register p7 port p7 direction register pd7 port p8 register p8 port p8 direction register pd8 port p9 direction register pd9 port p10 register p10 port p10 direction register pd10 pull-up control register 1 pur1 pull-up control register 2 pur2 179 179 179 179 179 179 179 179 177 177 177 219 218 219 219 218 218 219 219 218 218 219 218 220 220 220 221 address register symbol page a/d convert status register 0 adstat0 179 a/d trigger control register adtrgcon 178 209 209 209 209
m16c/26a group(m16c/26a, m16c/26t) single-chip 16-bit cmos microcomputer rej09b0202-0100 rev.1.00 mar. 15, 2005 page 1 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r 1. overview the m16c/26a group(m16c/26a, m16c/26t) of single-chip microcomputers is built using the high-perfor- mance silicon gate cmos process using a m16c/60 series cpu core and is packaged in a 42-pin and 48- pin plastic molded qfp. these single-chip microcomputers operate using sophisticated instructions featur- ing a high level of instruction efficiency. with 1m bytes of address space, they are capable of executing instructions at high speed. in addition, this microcomputer contains a multiplier and a dmac which com- bined with fast instruction processing capability, makes it suitable for control of various oa, communication, and industrial equipment which requires high-speed arithmetic/logic operations. there is a normal-ver. for m16c/26a and t-ver. and v-ver. for m16c/26t. 1.1 applications audio, cameras, office equipment, communications equipment, portable equipment, home appliances (inverter solution), auotmotives, motor control, etc
1. overview page 2 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m item performance cpu number of basic instructions 91 instructions minimun instruction execution 50 ns (f(bclk)= 20mh z , v cc = 3.0v to 5.5v) (m16c/26a, m16c/26t(t-ver.)) time 100 ns (f(bclk)= 10mh z , v cc = 2.7v to 5.5v) (m16c/26a) 50 ns (f(bclk)= 20mh z , v cc = 4.2v to 5.5v -40 to 105 c) (m16c/26t(v-ver.)) 62.5 ns (f(bclk)= 16mh z , v cc = 4.2v to 5.5v -40 to 125 c) (m16c/26t(v-ver.)) operation mode single chip mode address space 1m byte memory capacity rom/ram : see the product list peripheral port input/output : 39 lines function multifunction timer timera:16 bits x 5 channels, timerb:16 bits x 3 channels three-phase motor control timer serial i/o 2 channels (uart, clock synchronous serial i/o) 1 channel (uart, clock synchronous, i 2 c bus (1) , or iebus (2) ) a/d converter 10 bit a/d converter : 1 circuit, 12 channels dmac 2 channels crc calcuration circuit 2 polynomial (crc-ccitt and crc-16) with msb/lsb selectable watchdog timer 15 bits x 1 channel (with prescaler) interrupt 20 internal and 8 external sources, 4 software sources, 7 levels clock generation circuit 4 circuits main clock(*), sub-clock(*) on-chip oscillator, pll frequency synthesizer (*)these circuit contain a built-in feedback resister. oscillation stop detection main clock oscillation stop, re-oscillation detection function voltage detection circuit available(m16c/26a, option (4) ), absent(m16c/26t) electrical power supply voltage v cc =3.0v to 5.5v ( f(bclk)=20mh z ) (m16c/26a) characteristics v cc = 2.7v to 5.5v ( f(bclk)=10mh z ) v cc =3.0v to 5.5v (m16c/26t(t-ver.)) v cc =4.2v to 5.5v (m16c/26t(v-ver.)) power consumption 16ma (vcc=5v, f(bclk)=20mhz) 25 a (vcc=3v, f(bclk)=f(x cin )=32khz on ram) 1.8 a (vcc=3v, f(bclk)=f(x cin )=32khz, in wait mode) 0.7 a (vcc=3v, in stop mode) flash memory program/erase supply voltage 2.7v to 5.5v (m16c/26a) version 3.0v to 5.5v (m16c/26t(t-ver.)) 4.2v to 5.5v (m16c/26t(v-ver.)) program and erase endurance 100 times (all area) or 1,000 times (block 0 to 3) / 10,000 times (block a, block b) (3) operating ambient temperature -20 to 85 c / -40 to 85 c (3) (m16c/26a) -40 to 85 c (m16c/26t(t-ver.)) -40 to 105 c / -40 to 125 c (m16c/26t(v-ver.)) package 48-pin plastic molded qfp notes: 1. i 2 c bus is a trademark of koninklijke philips electronics n. v. 2. iebus is a trademark of nec electronics corporation. 3. see table 1.6 product code for the program and erase endurance, and operating ambient temperature. 4. the option is on a request basis. table 1.1. performance outline of m16c/26a group(m16c/26a, m16c/26t) (48-pin device) 1.2 performance outline table 1.1 lists performance outline of m16c/26a group 48-pin device. table 1.2 lists performance outline of m16c/26a group 42-pin device.
1. overview page 3 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m table 1.2. performance outline of m16c/26a group (m16c/26a) (42-pin device) item performance cpu number of basic instructions 91 instructions minimun instruction execution 50 ns (f(bclk)= 20mh z , v cc = 3.0v to 5.5v) time 100 ns (f(bclk)= 10mh z , v cc = 2.7v to 5.5v) operation mode single chip mode address space 1m byte memory capacity rom/ram : see the product list peripheral port input/output : 33 lines function multifunction timer timera:16 bits x 5 channels, timerb:16 bits x 3 channels three-phase motor control timer serial i/o 1 channel (uart, clock synchronous serial i/o) 1 channel (uart, clock synchronous, i 2 c bus (1) , or iebus (2) ) a/d converter 10 bit a/d converter : 1 circuit, 10 channels dmac 2 channels crc calcuration circuit 2 polynomial (crc-ccitt and crc-16) with msb/lsb selectable watchdog timer 15 bits x 1 channel (with prescaler) interrupt 18 internal and 8 external sources, 4 software sources, 7 levels clock generation circuit 4 circuits main clock(*), sub-clock(*) on-chip oscillator, pll frequency synthesizer (*)these circuit contain a built-in feedback resister. oscillation stop detection main clock oscillation stop, re-oscillation detection function voltage detection circuit available (option (4) ) electrical power supply voltage v cc =3.0v to 5.5v ( f(bclk)=20mh z ) characteristics v cc = 2.7v to 5.5v ( f(bclk)=10mh z ) power consumption 16ma (vcc=5v, f(bclk)=20mhz) 25 a (vcc=3v, f(bclk)=f(x cin )=32khz on ram) 1.8 a (vcc=3v, f(bclk)=f(x cin )=32khz, in wait mode) 0.7 a (vcc=3v, in stop mode) flash memory program/erase supply voltage 2.7v to 5.5v program and erase endurance 100 times (all area) or 1,000 times (block 0 to 3) / 10,000 times (block a, block b) (3) operating ambient temperature -20 to 85 c / -40 to 85 c (3) package 42-pin plastic molded ssop notes: 1. i 2 c bus is a trademark of koninklijke philips electronics n. v. 2. iebus is a trademark of nec electronics corporation. 3. see table 1.6 product code for the program and erase endurance, and operating ambient temperature. 4. the option is on a request basis.
1. overview page 4 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m i/o ports internal peripheral functions timer timer a0 (16 bits) timer a1 (16 bits) timer a2 (16 bits) timer a3 (16 bits) timer a4 (16 bits) timer b0 (16 bits) timer b1 (16 bits) timer b2 (16 bits) watchdog timer (15bits) a/d converter (10bits x 12 channels) u(s)art/sio (channel 0) serial ports system clock generator x in -x out x cin -x cout on-chip oscillator m16c/60 series 16-bit cpu core r0l r0h r1l r1h r2 r3 a0 a1 fr r0l r0h r1l r1h r2 r3 a0 a1 fb registers sb pc isp usp program counter stack pointers intb vector table flg flag register memory multiplier flash rom ram u(s)art/sio (channel 1) u(s)art/sio/i 2 c bus/iebus (channel 2) 3-phase pwm port p1 3 port p6 8 port p7 8 port p8 8 port p9 4 port p10 8 flash rom (data flash) dmac (2 channels) pll frequency synthesizer crc calculation circuit (ccitt, crc-16) 1.3 block diagram figure 1.1 is a block diagram of the m16c/26a group, 48-pin device. figure 1.1. m16c/26a group(m16c/26a, m16c/26t), 48-pin version block diagram
1. overview page 5 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 1.2 is a block diagram of the m16c/26a group, 42-pin device. figure 1.2. m16c/26a group(m16c/26a), 42-pin version block diagram i/o ports internal peripheral functions timer timer a0 (16 bits) timer a1 (16 bits) timer a2 (16 bits) timer a3 (16 bits) timer a4 (16 bits) timer b0 (16 bits) timer b1 (16 bits) timer b2 (16 bits) watchdog timer (15bits) a/d converter (10bits x 10 channels) u(s)art/sio (channel 0) serial ports system clock generator x in -x out x cin -x cout on-chip oscillator m16c/60 series 16-bit cpu core r0l r0h r1l r1h r2 r3 a0 a1 fr r0l r0h r1l r1h r2 r3 a0 a1 fb registers sb pc isp usp program counter stack pointers intb vector table flg flag register memory multiplier flash rom ram u(s)art/sio/i 2 c bus/iebus (channel 2) 3-phase pwm port p1 3 port p6 4 port p7 8 port p8 8 port p9 2 port p10 8 flash rom (data flash) dmac (2 channels) pll frequency synthesizer crc calculation circuit (ccitt, crc-16)
1. overview page 6 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 1.4 product list tables 1.3 to 1.5 list the m16c/26a group products and figure 1.3 shows the type numbers, memory sizes and packages. table 1.6 lists the product code of flash memory version and masked rom version for m16c/26a, and figure 1.4 shows the marking diagram of flash memory version and masked rom version. please contact renesas technology corp. or an authorized renesas technology corp. product distributor for the product code and the marking diagram of m16c/26t table 1.3. product list (1) -m16c/26a as of march 2005 type no. rom capacity ram capacity package type remarks m30260m3a-xxxgp (d) 24k byte 1k byte m30260m6a-xxxgp (d) 48k byte 2k byte 48p6q m30260m8a-xxxgp (d) 64k byte 2k byte m30263m3a-xxxfp (d) 24k byte 1k byte m30263m6a-xxxfp (d) 48k byte 2k byte 42p2r m30263m8a-xxxfp (d) 64k byte 2k byte m30260f3agp (d) 24k + 4k byte 1k byte m30260f6agp (d) 48k + 4k byte 2k byte 48p6q m30260f8agp (d) 64k + 4k byte 2k byte m30263f3afp (d) 24k + 4k byte 1k byte m30263f6afp (d) 48k + 4k byte 2k byte 42p2r m30263f8afp (d) 64k + 4k byte 2k byte (p) : under planning (d) : under development table 1.4. product list (2) -m16c/26t t-ver. as of march 2005 (p) : under planning (d) : under development notes. the specification of m16c/26t varies from the one of m16c/26a. table 1.5. product list (3) -m16c/26t v-ver. as of march 2005 (p) : under planning (d) : under development notes. the specification of m16c/26t varies from the one of m16c/26a. mask rom version flash rom version type no. rom capacity ram capacity package type remarks m30260m3t-xxxgp (p) 24k byte 1k byte m30260m6t-xxxgp (p) 48k byte 2k byte 48p6q mask rom version m30260m8t-xxxgp (p) 64k byte 2k byte m30260f3tgp (d) 24k + 4k byte 1k byte m30260f6tgp (d) 48k + 4k byte 2k byte 48p6q flash rom version m30260f8tgp (d) 64k + 4k byte 2k byte type no. rom capacity ram capacity package type remarks m30260m3v-xxxgp (p) 24k byte 1k byte m30260m6v-xxxgp (p) 48k byte 2k byte 48p6q mask rom version m30260m8v-xxxgp (p) 64k byte 2k byte m30260f3vgp (d) 24k + 4k byte 1k byte m30260f6vgp (d) 48k + 4k byte 2k byte 48p6q flash rom version m30260f8vgp (d) 64k + 4k byte 2k byte
1. overview page 7 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m package type: gp : package 48p6q (m16c/26a, m16c/26at) fp : package 42p2r (m16c/26a) version: a : m16c/26a t : m16c/26at t-ver. v : m16c/26at v-ver. rom / ram capacity: 3: (24k+4k) bytes (note 1) / 1k bytes 6: (48k+4k) bytes (note 1) / 2k bytes 8: (64k+4k) bytes (note 1) / 2k bytes note 1: only flash memory version exists in "+4k bytes" memory type: m: mask rom version f: flash memory version type no. m 3 0 2 6 0 m 8 a - xxx g p - 6 3 m16c/26a group m16c family shows pin count, (the value itself has no specific meaning) product code: see table 1.6 product code rom number: rom number is omitted in flash memory version figure 1.3. type no., memory size, and package product code package internal rom (program area) program and erase endurance temperature range internal rom (data area) operating ambient temperature temperature range lead-free u3 u5 u7 u9 100 1,000 0 c to 60 c 100 10,000 0 c to 60 c -40 c to 85 c -20 c to 85 c -40 c to 85 c -20 c to 85 c -40 c to 85 c -20 c to 85 c program and erase endurance product code package operating ambient temperature lead-free u3 u5 -40 c to 85 c -20 c to 85 c table 1.6 product code (flash memory version, m16c/26a) (mask rom version, m16c/26a) note 1: the lead contained products, d3, d5, d7 and d9, are put together with u3, u5, u7 and u9 respectively. lead-free (sn-cu plating) products can be mounted by both conventional sn-pb paste and lead-free paste.
1. overview page 8 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 0260f8a a u3 xxxxx (1) flash memory version, 48p6q, m16c/26a m30263f8afp a u3 xxxxxxx (2) flash memory version, 42p2r, m16c/26a 0260m8a 001a u3 xxxxx (3) mask rom version, 48p6q, m16c/26a m30263m8a-001fp a u3 xxxxxxx (4) mask rom version, 42p2r, m16c/26a product name : indicates m30260f8agp chip version and product code: a : indicates chip version the first edition is shown to be blank and continues with a and b. u3 : indicates product code (see table 1.6 product code ) date code (5 digits) ? indicates manufacturing management code product name : indicates m30260m8agp rom number, chip version and product code: 001: indicates rom number a : indicates chip version the first edition is shown to be blank and continues with a and b. u3 : indicates product code (see table 1.6 product code ) date code (5 digits) ? indicates manufacturing management code product name : indicates m30263f8afp chip version and product code: a : indicates chip version the first edition is shown to be blank and continues with a and b. u3 : indicates product code (see table 1.6 product code ) date code (7 digits) ? indicates manufacturing management code product name and rom number m30263m8a and fp are indicated of produnct name 001 is indicated of rom number chip version and product code: a : indicates chip version the first edition is shown to be blank and continues with a and b. u3 : indicates product code (see table 1.6 product code ) date code (7 digits) ? indicates manufacturing management code figure 1.4 marking diagram (top vier, m16c/26a)
1. overview page 9 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 p9 2 /tb2 in /an 32 p9 1 /tb1 in /an 31 cnv ss p1 7 /int 5 /idu p1 6 /int 4 /idw p1 5 /int 3 /ad trg /idv p10 7 /an 7 /ki 3 p7 0 /txd 2 /ta 0out /sda 2 /cts 1 /rts 1 /cts 0 /clks 1 x out v ss x in p8 5 /nmi/sd v cc p6 7 /txd 1 p6 6 /rxd 1 p6 5 /clk 1 reset p7 1 /rxd 2 /ta0 in /scl 2 /clk 1 p7 2 /clk 2 /ta1 out /v/rxd 1 p7 3 /cts 2 /rts 2 /ta1 in /v/txd 1 p7 4 /ta2 out /w p7 5 /ta2 in /w p7 6 /ta3 out p7 7 /ta3 in p8 0 /ta4 out /u p8 1 /ta4 in /u p8 2 /int 0 p8 3 /int 1 p6 4 /cts 1 /rts 1 /cts 0 /clks 1 p6 3 /txd 0 p6 2 /rxd 0 p6 1 /clk 0 p6 0 /cts 0 /rts 0 p9 0 /tb0 in /an 30 /clk out p8 7 /x cin p8 6 /x cout p10 6 /an 6 /ki 2 p10 5 /an 5 /ki 1 p10 4 /an 4 /ki 0 p10 3 /an 3 p10 2 /an 2 p10 1 /an 1 av ss p10 0 /an 0 v ref av cc p9 3 /an 24 p8 4 /int 2 /zp note. set pacr2 to pacr0 bit in the pacr register to "100 2 " before you input and output it after resetting to each pin. when the pacr register isn't set up, the input and output function of some of the p ins are disabled. package: 48p6q figure 1.5. pin configuration (top view) of m16c/26a group, 48-pin package pin configuration (top view)(note) 1.5 pin configuration figures 1.5 and 1.6 show the pin configurations (top view).
1. overview page 10 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 1.6. pin configuration (top view) of m16c/26a group, 42-pin package pin configuration (top view)(note) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 reset av ss p10 0 /an 0 v ref x in x out v ss v cc p8 6 /x cout p6 5 /clk 1 p8 3 /int 1 p8 2 /int 0 p8 1 /ta4 in /u p8 0 /ta4 out /u p7 7 /ta3 in p7 6 /ta3 out p7 5 /ta2 in /w p7 4 /ta2 out /w p6 4 /cts 1 /rts 1 /cts 0 /clks 1 p7 0 /txd 2 /sda 2 /ta0 out /cts 1 /rts 1 /cts 0 /clks 1 p7 1 /rxd 2 /scl 2 /ta0 in /clk 1 p7 2 /clk 2 /ta1 out /v/rxd 1 p7 3 /cts 2 /rts 2 /ta1 in /v/txd 1 av cc p9 1 /tb1 in /an 31 p9 0 /tb0 in /an 30 /clk out cnv ss p8 7 /x cin p6 6 /rxd 1 p6 7 /txd 1 p8 5 /nmi/sd p8 4 /int 2 /zp p1 7 /int 5 /idu p1 6 /int 4 /idw p1 5 /int 3 /ad trg /idv p10 7 /an 7 /ki 3 p10 6 /an 6 /ki 2 p10 5 /an 5 /ki 1 p10 4 /an 4 /ki 0 p10 3 /an 3 p10 2 /an 2 p10 1 /an 1 note. set pacr2 to pacr0 bit in the pacr register to "001 2 " before you input and output it after resetting to each pin. when the pacr register isn't set up, the input and output function of some of the p ins are disabled. package: 42p2r
1. overview page 11 ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r table 1.7. pin description(1) 1.6 pin description table 1.7 and 1.8 describes the available pins. pin name signal name i/o type function v cc ,v ss power supply apply 0v to the vss pin, and the following voltage to the vcc pin. input 2.7 to 5.5v (m16c/26a) 3.0 to 5.5v (m16c/26t t-ver.) 4.2 to 5.5v (m16c/26t v-ver.) cnv ss cnv ss input connect this pin to vss. ____________ reset reset input input "l" on this input resets the microcomputer. x in clock input input these pins are provided for the main clock generating circuit input/output. x out clock output output connect a ceramic resonator or crystal between the x in and the x out pins. to use an externally derived clock, input it to the x in pin and leave the x out pin open. if x in is not used (for external oscillator or external clock) connect x in pin to v cc and leave x out pin open. av cc analog power this pin is a power supply input for the a/d converter. connect this supply input pin to v cc . av ss analog power this pin is a power supply input for the a/d converter. connect this supply input pin to v ss . v ref reference input this pin is a reference voltage input for the a/d converter. voltage input p1 5 ~p1 7 i/o port p1 input/ this is an 3-bit cmos i/o port. it has an input/output port direction output register that allows the user to set each pin for input or output individually. when used for input, a pull-up resister option can be selected for the entire group of three pins. additional software selectable secondary ______ functions are: 1) p1 5 to p1 7 can be configured as external int interrupt pins; 2) p1 5 to p1 7 can be configured as position-data-retain function input pins,and; 3) p1 5 can input a trigger for the a/d converter. p6 0 ~p6 7 i/o port p6 input/ this is an 8-bit cmos i/o port. it has an input/output port direction output register that allows the user to set each pin for input or output individually. when used for input, a pull-up resister option can be selected for the entire group of four pins. pins in this port also function as uart0 and uart1 i/o, as selected by software. p6 0 to p6 3 are not available in the 42 pin version. p7 0 ~p7 7 i/o port p7 input/ this is an 8-bit i/o port equivalent to p6. p7 can also function as i/o for output timer a0 to a3, as selected by software. additional programming options are: p7 0 to p7 3 can assume uart1 i/o or uart2 i/o capabilities, and p7 2 to p7 5 can function as output pins for the three-phase motor control timer.
1. overview page 12 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m table 1.8. pin description(2) pin name signal name i/o type function p8 0 ~p8 7 i/o port p8 input/ this is an 8-bit i/o port equivalent to p6. additional software-selectable output secondary functions are: 1) p8 0 and p8 1 can act as either i/o for timer a4, or as output pins for the three-phase motor control timer; 2) p8 2 to ______ p8 4 can be configured as external int interrupt pins. p8 4 can be used for _______ _____ timer a zphase function; 3) p8 5 can be used as nmi/sd. p8 5 can not be used as i/o port while the three-phase motor control is enabled. apply a stable "h" to p8 5 after setting the direction register for p8 5 to "0" when the three-phase motor control is enabled, and; 4) p8 6 and p8 7 can serve as i/o pins for the sub-clock generation circuit. in this latter case, a quartz oscillator must be connented between p8 6 (x cout pin) and p8 7 (x cin pin). p9 0 ~p9 3 i/o port p9 input/ this is an 4-bit i/o port equivalent to p6. additional software-selectable output secondary functions are: 1) p9 0 to p9 2 can act as timer b0 to b2 input pins, and; 2) p9 0 to p9 3 can act as a/d converter input pins. p9 0 outputs a no-divide, divide-by-8 or divide-by-32 clock of x in or a clock of the same frequency as x cin as selected by program. p9 2 to p9 3 are not available in the 42 pin version. p10 0 ~p10 7 i/o port p10 input/ this is an 8-bit i/o port equivalent to p6. this port can also function as output a/d converter input pins, as selected by software. furthermore, p10 4 to p10 7 can also function as input pins for the key input interrupt function.
2. central processing unit(cpu) page 13 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 2. central processing unit (cpu) figure 2.1 shows the cpu registers. the cpu has 13 registers. of these, r0, r1, r2, r3, a0, a1 and fb comprise a register bank. there are two register banks. figure 2.1. central processing unit register 2.1 data registers (r0, r1, r2 and r3) the r0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. r1 to r3 are the same as r0. the r0 register can be separated between high (r0h) and low (r0l) for use as two 8-bit data registers. r1h and r1l are the same as r0h and r0l. conversely, r2 and r0 can be combined for use as a 32- bit data register (r2r0). r3r1 is the same as r2r0. 2.2 address registers (a0 and a1) the register a0 consists of 16 bits, and is used for address register indirect addressing and address register relative addressing. they also are used for transfers and arithmetic/logic operations. a1 is the same as a0. in some instructions, registers a1 and a0 can be combined for use as a 32-bit address register (a1a0). data registers (note) address registers (note) frame base registers (note) program counter interrupt table register user stack pointer interrupt stack pointer static base register flag register note: these registers comprise a register bank. there are two register banks. r0h(r0's high bits) b15 b8 b7 b0 r3 intbh usp isp sb aa aa a a aa aa aa aa aaaaaa aaaaaa aa aa aa aa aa aa a a aa aa c d z s b o i u ipl r0l(r0's low bits) r1h(r1's high bits) r1l(r1's low bits) r2 b31 r3 r2 a1 a0 fb b19 intbl b15 b0 pc b19 b0 b15 b0 flg b15 b0 b15 b0 b7 b8 reserved area carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved area processor interrupt priority level the upper 4 bits pg intb are intbh and the lower 16 bits of intb are intbl.
2. central processing unit(cpu) page 14 ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r 2.3 frame base register (fb) fb is configured with 16 bits, and is used for fb relative addressing. 2.4 interrupt table register (intb) intb is configured with 20 bits, indicating the start address of an interrupt vector table. 2.5 program counter (pc) pc is configured with 20 bits, indicating the address of an instruction to be executed. 2.6 user stack pointer (usp) and interrupt stack pointer (isp) stack pointer (sp) comes in two types: usp and isp, each configured with 16 bits. your desired type of stack pointer (usp or isp) can be selected by the u flag of flg. 2.7 static base register (sb) sb is configured with 16 bits, and is used for sb relative addressing. 2.8 flag register (flg) flg consists of 11 bits, indicating the cpu status. 2.8.1 carry flag (c flag) this flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. 2.8.2 debug flag (d flag) the d flag is used exclusively for debugging purpose. during normal use, it must be set to 0 . 2.8.3 zero flag (z flag) this flag is set to 1 when an arithmetic operation resulted in 0; otherwise, it is 0 . 2.8.4 sign flag (s flag) this flag is set to 1 when an arithmetic operation resulted in a negative value; otherwise, it is 0 . 2.8.5 register bank select flag (b flag) register bank 0 is selected when this flag is 0 ; register bank 1 is selected when this flag is 1 . 2.8.6 overflow flag (o flag) this flag is set to 1 when the operation resulted in an overflow; otherwise, it is 0 . 2.8.7 interrupt enable flag (i flag) this flag enables a maskable interrupt. maskable interrupts are disabled when the i flag is 0 , and are enabled when the i flag is 1 . the i flag is cleared to 0 when the interrupt request is accepted. 2.8.8 stack pointer select flag (u flag) isp is selected when the u flag is 0 ; usp is selected when the u flag is 1 . the u flag is cleared to 0 when a hardware interrupt request is accepted or an int instruction for software interrupt nos. 0 to 31 is executed. 2.8.9 processor interrupt priority level (ipl) ipl is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. if a requested interrupt has priority greater than ipl, the interrupt is enabled. 2.8.10 reserved area when write to this bit, write "0". when read, its content is indeterminate.
3. memory page 15 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 3. memory figure 3.1 is a memory map. the linear address space of 1m bytes extends from address 00000 16 to fffff 16 . the internal rom is allocated in a lower address direction beginning with address fffff 16 . for example, a 64-kbyte internal rom is allocated to the address from f0000 16 to fffff 16 . in the flash memory version, internal rom area (data area) contain two blocks of flash rom as data area to store data. these two blocks of 2k bytes are located from 0f000 16 to 0ffff 16 . the fixed interrupt vector table is allocated to the address from fffdc 16 to fffff 16 . therefore store the start address of each interrupt routine here. for details, refer to the "interrupt". the internal ram is allocated in an upper address direction beginning with address 00400 16 . for example, a 1-kbyte internal ram is allocated to the address from 00400 16 to 007ff 16 . in addition to storing data, the internal ram also stores the stack used when calling subroutines and when interrupts are generated. the sfr is allocated to the address from 00000 16 to 003ff 16 . peripheral function control registers are located here. of the sfr, any area which has no functions allocated is reserved for future use and cannot be used by users. the special page vector table is allocated to the addresses from ffe00 16 to fffdb 16 . this vector is used by the jmps or jsrs instruction. for details, refer to the "m16c/60 and m16c/20 series software manual". figure 3.1. memory map sfr internal ram reserved area internal rom (program area) (note 2) reset watchdog timer single step address match brk instruction overflow undefined instruction special page vector table 00000 16 00400 16 xxxxx 16 yyyyy 16 fffff 16 fffff 16 fffdc 16 ffe00 16 dbc nmi internal rom (data area) (note 1) 0f000 16 0ffff 16 reserved area note 1: shown here is a block a (2k bytes) and block b (2k bytes). (in the flash memory version) note 2: when using the masked rom version, write nothing to internal rom area. size address yyyyy 16 size address xxxxx 16 internal ram intrnal rom 2k byte 00bff 16 48k byte f4000 16 64k byte f0000 16 1k byte 007ff 16 24k byte fa000 16
4. special function register (sfr) page 16 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 4. special function register (sfr) sfr(special function register) is the control register of peripheral functions. table 4.1 to 4.6 list the sfr information. table 4.1 sfr information (1) processor mode register 0 pm0 00 16 processor mode register 1 pm1 00001000 2 system clock control register 0 cm0 01001000 2 (m16c/26a) 01101000 2 (m16c/26t) system clock control register 1 cm1 00100000 2 address match interrupt enable register aier xxxxxx00 2 protect register pbcr xx000000 2 oscillation stop detection register (note 2) cm2 0x000010 2 watchdog timer start register wdts xx 16 watchdog timer control register wdc 00xxxxxx 2 (note3) address match interrupt register 0 rmad0 00 16 00 16 x0 16 address match interrupt register 1 rmad1 00 16 00 16 x0 16 voltage detection register 1 (note 4,5) vcr1 00001000 2 voltage detection register 2 (note 4,5) vcr2 00 16 pll control register 0 plc0 0001x010 2 processor mode register 2 pm2 xxx00000 2 voltage down detection interrupt register (note 5) d4int 00 16 dma0 source pointer sar0 xx 16 xx 16 xx 16 dma0 destination pointer dar0 xx 16 xx 16 xx 16 dma0 transfer counter tcr0 xx 16 xx 16 dma0 control register dm0con 00000x00 2 dma1 source pointer sar1 xx 16 xx 16 xx 16 dma1 destination pointer dar1 xx 16 xx 16 xx 16 dma1 transfer counter tcr1 xx 16 xx 16 dma1 control register dm1con 00000x00 2 note 1: blank spaces are reserved. no access is allowed. note 2: the cm20, cm21 and cm27 bits do not change at oscillation stop detection reset.. note 3: the wdc5 bit is "0" (cold start) immediately after power-on. it can only be set to "1" in a program. the wdc5 bit is not supported for m16c/26t. note 4: this register does not change at software reset, watchdog timer reset and oscillation stop detection reset. note 5: this register is not supported for m16c/26t. x : indeterminate 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 address register symbol after reset
4. special function register (sfr) page 17 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m note 1: blank spaces are reserved. no access is allowed. x : indeterminate 0040 16 0041 16 0042 16 0043 16 0044 16 0045 16 0046 16 0047 16 0048 16 0049 16 004a 16 004b 16 004c 16 004d 16 004e 16 004f 16 0050 16 0051 16 0052 16 0053 16 0054 16 0055 16 0056 16 0057 16 0058 16 0059 16 005a 16 005b 16 005c 16 005d 16 005e 16 005f 16 0060 16 0061 16 0062 16 0063 16 0064 16 0065 16 0066 16 0067 16 0068 16 0069 16 006a 16 006b 16 006c 16 006d 16 006e 16 006f 16 0070 16 0071 16 0072 16 0073 16 0074 16 0075 16 0076 16 0077 16 0078 16 0079 16 007a 16 007b 16 007c 16 007d 16 007e 16 007f 16 address register symbol after reset int3 interrupt control register int3ic xx00x000 2 int5 interrupt control register int5ic xx00x000 2 int4 interrupt control register int4ic xx00x000 2 uart2 bus collision detection interrupt control register bcnic xxxxx000 2 dma0 interrupt control register dm0ic xxxxx000 2 dma1 interrupt control register dm1ic xxxxx000 2 key input interrupt control register kupic xxxxx000 2 a/d conversion interrupt control register adic xxxxx000 2 uart2 transmit interrupt control register s2tic xxxxx000 2 uart2 receive interrupt control register s2ric xxxxx000 2 uart0 transmit interrupt control register s0tic xxxxx000 2 uart0 receive interrupt control register s0ric xxxxx000 2 uart1 transmit interrupt control register s1tic xxxxx000 2 uart1 receive interrupt control register s1ric xxxxx000 2 timera0 interrupt control register ta0ic xxxxx000 2 timera1 interrupt control register ta1ic xxxxx000 2 timera2 interrupt control register ta2ic xxxxx000 2 timera3 interrupt control register ta3ic xxxxx000 2 timera4 interrupt control register ta4ic xxxxx000 2 timerb0 interrupt control register tb0ic xxxxx000 2 timerb1 interrupt control register tb1ic xxxxx000 2 timerb2 interrupt control register tb2ic xxxxx000 2 int0 interrupt control register int0ic xx00x000 2 int1 interrupt control register int1ic xx00x000 2 int2 interrupt control register int2ic xx00x000 2 table 4.2 sfr information (2) (1)
4. special function register (sfr) page 18 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 0080 16 0081 16 0082 16 0083 16 0084 16 0085 16 0086 16 01b0 16 01b1 16 01b2 16 01b3 16 01b4 16 01b5 16 01b6 16 01b7 16 01b8 16 01b9 16 01ba 16 01bb 16 01bc 16 01bd 16 01be 16 01bf 16 0250 16 0251 16 0252 16 0253 16 0254 16 0255 16 0256 16 0257 16 0258 16 0259 16 025a 16 025b 16 025c 16 025d 16 025e 16 025f 16 0330 16 0331 16 0332 16 0333 16 0334 16 0335 16 0336 16 0337 16 0338 16 0339 16 033a 16 033b 16 033c 16 033d 16 033e 16 033f 16 note 1: blank spaces are reserved. no access is allowed. note 2: this register is included in the flash memory version. x : indeterminate address register symbol after reset flash memory control register 4 (note 2) fmr4 01000000 2 flash memory control register 1 (note 2) fmr1 000xxx0x 2 flash memory control register 0 (note 2) fmr0 01 16 three phase protect control register tprc 00 16 on-chip oscillator control register rocr 00000101 2 pin assignment control register pacr 00 16 peripheral clock select register pclkr 00000011 2 nmi digital debounce register nddr ff 16 port1 7 digital debounce register p17ddr ff 16 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ table 4.3 sfr information (3) (1)
4. special function register (sfr) page 19 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m address register symbol after reset 0340 16 0341 16 0342 16 0343 16 0344 16 0345 16 0346 16 0347 16 0348 16 0349 16 034a 16 034b 16 034c 16 034d 16 034e 16 034f 16 0350 16 0351 16 0352 16 0353 16 0354 16 0355 16 0356 16 0357 16 0358 16 0359 16 035a 16 035b 16 035c 16 035d 16 035e 16 035f 16 0360 16 0361 16 0362 16 0363 16 0364 16 0365 16 0366 16 0367 16 0368 16 0369 16 036a 16 036b 16 036c 16 036d 16 036e 16 036f 16 0370 16 0371 16 0372 16 0373 16 0374 16 0375 16 0376 16 0377 16 0378 16 0379 16 037a 16 037b 16 037c 16 037d 16 037e 16 037f 16 note 1 : blank spaces are reserved. no access is allowed. x : indeterminate timer a1-1 register ta11 xx 16 xx 16 timer a2-1 register ta21 xx 16 xx 16 timer a4-1 register ta41 xx 16 xx 16 three phase pwm control register 0 invc0 00 16 three phase pwm control register 1 invc1 00 16 three phase output buffer register 0 idb0 3f 16 three phase output buffer register 1 idb1 3f 16 dead time timer dtt xx 16 timer b2 interrupt occurrence frequency set counter ictb2 xx 16 position-data-retain function control register pdrf xxxx0000 2 port function control register pfcr 00111111 2 interrupt request cause select register 2 ifsr2a xxxxxxx0 2 interrupt request cause select register ifsr 00 16 uart2 special mode register 4 u2smr4 00 16 uart2 special mode register 3 u2smr3 000x0x0x 2 uart2 special mode register 2 u2smr2 x0000000 2 uart2 special mode register u2smr x0000000 2 uart2 transmit/receive mode register u2mr 00 16 uart2 bit rate register u2brg xx 16 uart2 transmit buffer register u2tb xxxxxxxx 2 xxxxxxxx 2 uart2 transmit/receive control register 0 u2c0 00001000 2 uart2 transmit/receive control register 1 u2c1 00000010 2 uart2 receive buffer register u2rb xxxxxxxx 2 xxxxxxxx 2 table 4.3 sfr information (4) (1)
4. special function register (sfr) page 20 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 0380 16 0381 16 0382 16 0383 16 0384 16 0385 16 0386 16 0387 16 0388 16 0389 16 038a 16 038b 16 038c 16 038d 16 038e 16 038f 16 0390 16 0391 16 0392 16 0393 16 0394 16 0395 16 0396 16 0397 16 0398 16 0399 16 039a 16 039b 16 039c 16 039d 16 039e 16 039f 16 03a0 16 03a1 16 03a2 16 03a3 16 03a4 16 03a5 16 03a6 16 03a7 16 03a8 16 03a9 16 03aa 16 03ab 16 03ac 16 03ad 16 03ae 16 03af 16 03b0 16 03b1 16 03b2 16 03b3 16 03b4 16 03b5 16 03b6 16 03b7 16 03b8 16 03b9 16 03ba 16 03bb 16 03bc 16 03bd 16 03be 16 03bf 16 note 1 : blank spaces are reserved. no access is allowed. x : indeterminate address register symbol after reset count start flag tabsr 00 16 clock prescaler reset flag cpsrf 0xxxxxxx 2 one-shot start flag onsf 00 16 trigger select register trgsr 00 16 up-dowm flag udf 00 16 timer a0 register ta0 xx 16 xx 16 timer a1 register ta1 xx 16 xx 16 timer a2 register ta2 xx 16 xx 16 timer a3 register ta3 xx 16 xx 16 timer a4 register ta4 xx 16 xx 16 timer b0 register tb0 xx 16 xx 16 timer b1 register tb1 xx 16 xx 16 timer b2 register tb2 xx 16 xx 16 timer a0 mode register ta0mr 00 16 timer a1 mode register ta1mr 00 16 timer a2 mode register ta2mr 00 16 timer a3 mode register ta3mr 00 16 timer a4 mode register ta4mr 00 16 timer b0 mode register tb0mr 00xx0000 2 timer b1 mode register tb1mr 00xx0000 2 timer b2 mode register tb2mr 00xx0000 2 timer b2 special mode register tb2sc x0000000 2 uart0 transmit/receive mode register u0mr 00 16 uart0 bit rate register u0brg xx 16 uart0 transmit buffer register u0tb xxxxxxxx 2 xxxxxxxx 2 uart0 transmit/receive control register 0 u0c0 00001000 2 uart0 transmit/receive control register 1 u0c1 00000010 2 uart0 receive buffer register u0rb xxxxxxxx 2 xxxxxxxx 2 uart1 transmit/receive mode register u1mr 00 16 uart1 bit rate register u1brg xx 16 uart1 transmit buffer register u1tb xxxxxxxx 2 xxxxxxxx 2 uart1 transmit/receive control register 0 u1c0 00001000 2 uart1 transmit/receive control register 1 u1c1 00000010 2 uart1 receive buffer register u1rb xxxxxxxx 2 xxxxxxxx 2 uart transmit/receive control register 2 ucon x0000000 2 crc snoop address register crcsar xx 16 00xxxxxx 2 crc mode register crcmr 0xxxxxx0 2 dma0 request cause select register dm0sl 00 16 dma1 request cause select register dm1sl 00 16 crc data register crcd xx 16 xx 16 crc input register crcin xx 16 table 4.3 sfr information (5) (1)
4. special function register (sfr) page 21 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 03c0 16 03c1 16 03c2 16 03c3 16 03c4 16 03c5 16 03c6 16 03c7 16 03c8 16 03c9 16 03ca 16 03cb 16 03cc 16 03cd 16 03ce 16 03cf 16 03d0 16 03d1 16 03d2 16 03d3 16 03d4 16 03d5 16 03d6 16 03d7 16 03d8 16 03d9 16 03da 16 03db 16 03dc 16 03dd 16 03de 16 03df 16 03e0 16 03e1 16 03e2 16 03e3 16 03e4 16 03e5 16 03e6 16 03e7 16 03e8 16 03e9 16 03ea 16 03eb 16 03ec 16 03ed 16 03ee 16 03ef 16 03f0 16 03f1 16 03f2 16 03f3 16 03f4 16 03f5 16 03f6 16 03f7 16 03f8 16 03f9 16 03fa 16 03fb 16 03fc 16 03fd 16 03fe 16 03ff 16 note 1 : blank spaces are reserved. no access is allowed. x : indeterminate register symbol after reset a/d register 0 ad0 xxxxxxxx 2 xxxxxxxx 2 a/d register 1 ad1 xxxxxxxx2 xxxxxxxx 2 a/d register 2 ad2 xxxxxxxx 2 xxxxxxxx 2 a/d register 3 ad3 xxxxxxxx 2 xxxxxxxx 2 a/d register 4 ad4 xxxxxxxx 2 xxxxxxxx 2 a/d register 5 ad5 xxxxxxxx 2 xxxxxxxx 2 a/d register 6 ad6 xxxxxxxx 2 xxxxxxxx 2 a/d register 7 ad7 xxxxxxxx 2 xxxxxxxx 2 a/d trigger control register adtrgcon 00 16 a/d status register 0 adstat0 00000x00 2 a/d control register 2 adcon2 00 16 a/d control register 0 adcon0 00000xxx 2 a/d control register 1 adcon1 00 16 port p1 register p1 xx 16 port p1 direction register pd1 00 16 port p6 register p6 xx 16 port p7 register p7 xx 16 port p6 direction register pd6 00 16 port p7 direction register pd7 00 16 port p8 register p8 xx 16 port p9 register p9 xxxxxxxx 2 port p8 direction register pd8 00 16 port p9 direction register pd9 xxxx0000 2 port p10 register p10 xx 16 port p10 direction register pd10 00 16 pull-up control register 0 pur0 00 16 pull-up control register 1 pur1 00 16 pull-up control register 2 pur2 00 16 port control register pcr 00 16 address table 4.3 sfr information (6) (1)
5. reset page 22 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 5. reset there are four types of resets: a hardware reset, a software reset, an watchdog timer reset, and an oscilla- tion stop detection reset. 5.1 hardware reset there are two types of hardware resets: a hardware reset 1 and a hardware reset 2. 5.1.1 hardware reset 1 ____________ ____________ a reset is applied using the reset pin. when an ??signal is applied to the reset pin while the power supply voltage is within the recommended operating condition, the pins are initialized (see ____________ table 5.1.1.1 pin status when reset pin level is ??. the internal on-chip oscillator is initialized and used as sysem clock. ____________ when the input level at the reset pin is released from ??to ?? the cpu and sfr are initialized, and the program is executed starting from the address indicated by the reset vector. the internal ram ____________ is not initialized. if the reset pin is pulled ??while writing to the internal ram, the internal ram becomes indeterminate. figure 5.1.1.1 shows the example reset circuit. figure 5.1.1.2 shows the reset sequence. table ____________ 5.1.1.1 shows the status of the other pins while the reset pin is ?? figure 5.1.1.3 shows the cpu register status after reset. refer to ?fr map?for sfr status after reset. 1. when the power supply is stable ____________ (1) apply an ??signal to the reset pin. (2) wait td(roc) or more. ____________ (3) apply an ??signal to the reset pin. 2. power on ____________ (1) apply an ??signal to the reset pin. (2) let the power supply voltage increase until it meets the recommended operating condition. (3) wait td(p-r) or more until the internal power supply stabilizes. (4) wait td(roc) or more. ____________ (5) apply an ??signal to the reset pin. 5.1.2 hardware reset 2 note m16c/26t does not use this function. this reset is generated by the microcomputer? internal voltage detection circuit. the voltage detec- tion circuit monitors the voltage supplied to the v cc pin. if the vc26 bit in the vcr2 register is set to ??(reset level detection circuit enabled), the microcom- puter is reset when the voltage at the v cc input pin drops below vdet3. conversely, when the input voltage at the v cc pin rises to vdet3r or more, the pins and the cpu and sfr are initialized, and the program is executed starting from the address indicated by the reset vector. it takes about td(s-r) before the program starts running after vdet3r is detected. the initialized pins and registers and the status thereof are the same as in hardware reset 1. the microcomputer cannot exit stop mode by voltage down detection reset (hardware reset 2).
5. reset page 23 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 5.2 software reset when the pm03 bit in the pm0 register is set to 1 (microcomputer reset), the microcomputer has its pins, cpu, and sfr initialized. then the program is executed starting from the address indicated by the reset vector. the device will reset using on-chip oscillator as the system clock. at software reset, some sfr s are not initialized. refer to sfr . 5.3 watchdog timer reset when the pm12 bit in the pm1 register is 1 (reset when watchdog timer underflows), the microcomputer initializes its pins, cpu and sfr if the watchdog timer underflows. the device will reset using on-chip oscillator as the system clock. then the program is executed starting from the address indicated by the reset vector. at watchdog timer reset, some sfr s are not initialized. refer to sfr . 5.4 oscillation stop detection reset when the cm20 bit in the cm2 register is set to 1 (oscillation stop, re-oscillation detection function enabled) and the cm27 bit is set to 0 (reset at oscillation stop detection), the microcomputer initializes its pins, cpu and sfr, coming to a halt if it detects main clock oscillation circuit stop. refer to the section oscillation stop, re-oscillation detection function . at oscillation stop detection reset, some sfr s are not initialized. refer to the section sfr . figure 5.1.1.1. example reset circuit reset v cc reset v cc 0v 0v more than td(roc) + td(p-r) equal to or less than 0.2v cc equal to or less than 0.2v cc recommended operating voltage
5. reset page 24 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m ____________ table 5.1.1.1. pin status when reset pin level is ? status pin name p1, p6 to p10 input port (high impedance) figure 5.1.1.3. cpu register status after reset b15 b0 data register(r0) address register(a0) frame base register(fb) program counter(pc) interrupt table register(intb) user stack pointer(usp) interrupt stack pointer(isp) static base register(sb) flag register(flg) 0000 16 0000 16 0000 16 aa aa a a aa aa aa aa aaaaaa aaaaaa aa aa aa aa aa aa a a aa aa c d z s b o i u ipl 0000 16 0000 16 0000 16 0000 16 0000 16 b19 b0 content of addresses ffffe 16 to ffffc 16 b15 b0 b15 b0 b15 b0 b7 b8 00000 16 data register(r1) data register(r2) data register(r3) address register(a1) 0000 16 0000 16 0000 16 figure 5.1.1.2. reset sequence td(p-r) more than td(roc) cpu clock address roc reset content of reset vector cpu clock 28cycles ffffe 16 ffffc 16 v cc
5. reset page 25 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 5.5.1. voltage detection circuit block b 7 b 6 v c r 2 r e g i s t e r r e s e t cm10 bit=1 (stop mode) + v d e t 3 + vdet4 e noise rejection v o l t a g e d o w n d e t e c t s i g n a l b3 v c r 1 r e g i s t e r v c 1 3 b i t write to wdc register s r q w a r m / c o l d >t q 1 s h o t internal reset signal ( l active) w d c 5 b i t e ( c o l d s t a r t , w a r m s t a r t ) v c c internal power on reset t d ( s - r ) voltage down detect reset (hardware reset 2 release wait time) 5.5 voltage detection circuit note using the voltage detection circuit with v cc =5v is assumed. the m16c/26t do not use this function. the voltage detection circuit has circuits to monitor the input voltage at the v cc pin, each checking the input voltage with respect to vdet3, and vdet4, respectively. use the vc26 to vc27 bits in the vcr2 register to select whether or not to enable these circuits. use the reset level detection circuit for hardware reset 2. the voltage down detection circuit can be set to detect whether the input voltage is equal to or greater than vdet4 or less than vdet4 by monitoring the vc13 bit in the vcr1 register. furthermore, a voltage down detection interrupt can be generated.
5. reset page 26 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 5.5.2. vcr1 register, vcr2 register, and d4int register v c 1 3 v o l t a g e d e t e c t i o n r e g i s t e r 1 symbol address after reset (note 2) vcr1 0019 16 00001000 2 v o l t a g e d o w n m o n i t o r f l a g ( n o t e 1 ) bit name function b i t s y m b o l rw b 7b 6b 5b 4b 3b2b 1b 0 note 1: the vc13 bit is useful when the vc27 bit of vcr2 register is set to 1 (voltage down detection circuit enable). the vc13 bit is always 1 (v cc vdet4) when the vc27 bit in the vcr2 register is set to 0 (voltage down detection circuit disable). note 2: this register does not change at software reset, watchdog timer reset and oscillation stop detection reset. 0 : v c c < v d e t 4 1 : v c c v d e t 4 ro 0000 000 rw rw reserved bit reserved bit m u s t se t t o 0 m u s t s e t t o 0 v o l t a g e d e t e c t i o n r e g i s t e r 2 ( n o t e 1 ) symbol address after reset (note 5) vcr2 001a 16 00 16 bit name b i t s y m b o l b 7b 6b 5b 4b 3b2b 1b 0 note 1: write to this register after setting the prc3 bit in the prcr register to 1 (write enable). note 2: when not in stop mode, to use hardware reset 2, set the vc26 bit to 1 (reset level detection circuit enable). note 3: vc26 bit is disabled in stop mode. (the microcomputer is not reset even if the voltage input to vcc pin becomes lower than vdet3.) note 4: when the vc13 bit in the vcr1 register and d42 bit in the d4int register are used or the d40 bit is set to 1 (voltage down detection interrupt enable), set the vc27 bit to 1 (voltage down detection circuit enable). note 5: this register does not change at software reset, watchdog timer reset and oscillation stop detection reset. note 6: the detection circuit does not start operation until td(e-a) elapses after the vc26 bit, or vc27 bit are set to 1 . v c 2 6 v c 2 7 rw rw rw rw 00000 function reserved bit m u s t s e t t o 0 re s e t l e v e l m o n i t o r b i t ( n o t e s 2 , 3 , 6 ) 0: disable reset level detection circuit 1: enable reset level detection circuit v o l t a g e d o w n m o n i t o r b i t ( n o t e 4 , 6 ) 0: disable voltage down detection circuit 1: enable voltage down detection circuit ( b 2 - b 0 ) ( b 7 - b 4 ) ( b 5 - b 0 ) 0 d40 v o l t a g e d o w n d e t e c t i o n i n t e r r u p t r e g i s t e r ( n o t e 1 ) symbol address after reset d4int 001f 16 00 16 v o l t a g e d o w n d e t e c t i o n i n t e r r u p t e n a b l e b i t ( n o t e 5 ) bit name b i t s y m b o l b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 : disable 1 : enable d41 s t o p m o d e d e a c t i v a t i o n c o n t r o l b i t ( n o t e 4 ) 0 : d i s a b l e ( d o n o t u s e t h e v o l t a g e d o w n d e t e c t i o n i n t e r r u p t t o g e t o u t o f s t o p m o d e ) 1 : e n a b l e ( u s e t h e v o l t a g e d o w n d e t e c t i o n i n t e r r u p t t o g e t o u t o f s t o p m o d e ) d42 v o l t a g e c h a n g e d e t e c t i o n f l a g ( n o t e 2 ) 0: not detected 1: vdet4 passing detection d43 w d t o v e r f l o w d e t e c t f l a g 0: not detected 1: detected df0 s a m p l i n g c l o c k s e l e c t b i t 00 : cpu clock divided by 8 01 : cpu clock divided by 16 10 : cpu clock divided by 32 11 : cpu clock divided by 64 df1 note 1: write to this register after setting the prc3 bit in the prcr register to 1 (write enable). note 2: useful when the vc27 bit in the vcr2 register is set to 1 (voltage down detection circuit enabled). if the vc27 bit is set to 0 (voltage down detection circuit disable), the d42 bit is set to 0 (not detect). note 3: this bit is set to 0 by writing a 0 in a program. (writing a 1 has no effect.) note 4: if the voltage down detection interrupt needs to be used to get out of stop mode again after once used for that purpose, reset the d41 bit by writing a 0 and then a 1 . note 5: the d40 bit is effective when the vc27 bit in the vcr2 register is set to 1 . to set the d40 bit to 1 , follow the procedure described below. (1) set the vc27 bit to 1 . (2) wait for td(e-a) until the detection circuit is actuated. (3) wait for the sampling time (refer to table 5.5.1.2 sampling clock periods ). (4) set the d40 bit to 1 . b 5 b 4 rw rw rw rw ( n o t e 3 ) rw r w r w (b7-b6) function ( n o t e 3 ) n o t h i n g i s a s s i g n e d . w h e n w r i t e , s e t t o 0 . w h e n r e a d , i t s c o n t e n t i s 0 .
5. reset page 27 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 5.5.3. typical operation of hardware reset 2 vdet4 vdet3 5.0v 5.0v vcc internal reset signal vc13 bit in vcr1 register vc26 bit in vcr2 register (1) vc27 bit in vcr2 register set to 1 by program (reset level detect circuit enable) set to 1 by program (voltage down detect circuit enable) vss indefinite indefinite indefinite reset vdet3s vdet3r notes : 1. vc26 bit is invalid (the microcomputer is not reset even if input voltage of vcc pin becomes lower than vdet3).
5. reset page 28 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 5.5.1 voltage down detection interrupt if the d40 bit in the d4int register is set to ??(voltage down detection interrupt enabled), the voltage down detection interrupt request is generated when the voltage applied to the vcc pin crosses the vdet4 voltage level. the voltage down detection interrupt shares the same interrupt vector with the watchdog timer interrupt and oscillation stop, re-oscillation detection interrupt. set the d41 bit in the d4int register to ??(enabled) to use the voltage down detection interrupt to exit stop mode. the d42 bit in the d4int register is set to ??as soon as the voltage applied to the vcc pin reaches vdet4 due to the voltage rise and voltage drop. when the d42 bit changes ??to ?? the voltage down detection interrupt request is generated. set the d42 bit to ??by program. however, when the d41 bit is set to ??and the microcomputer is in stop mode, the voltage down detection interrupt request is generated regardless of the d42 bit state if the voltage applied to the vcc pin is detected to be above vdet4. the microcomputer then exits stop mode. table 5.5.1.1 shows how the voltage down detection interrupt request is generated. the df1 to df0 bits in the d4int register determine the sampling period that detects the voltage applied to the vcc pin reaches vdet4. table 5.5.1.2 shows the sampling periods. cpu clock (mhz) df1 to df0=00 (cpu clock divided by 8) sampling period ( s) 16 3.0 6.0 12.0 24.0 df1 to df0=01 (cpu clock divided by 16) df1 to df0=10 (cpu clock divided by 32) df1 to df0=11 (cpu clock divided by 64) table 5.5.1.1 voltage down detection interrupt request generation conditions d41 bit vc27 bit operation mode d40 bit d42 bit cm02 bit vc13 bit normal operation mode (1) wait mode (2) stop mode (2) notes: 1. the status except the wait mode and stop mode is handled as the normal mode.(refer to 7. clock generating circuit ) 2. refer to 5.5.2 limitations on stop mode , 5.5.3 limitations on wait mode . 3. an interrupt request for voltage reduction is generated a sampling time after the value of the vc13 bit has changed. see the figure 5.5.1.2 voltage down detection interrupt generation circuit operation example for details. 0 to 1 (3) 1 0 1 1 0 1 to 0 (3) 0 to 1 (3) 1 to 0 (3) 0 to 1 0 to 1 0 to 1 0 to 1 1 : 0 or 1 table 5.5.1.2 sampling periods
5. reset page 29 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 5.5.1.1 power supply down detection interrupt generation block figure 5.5.1.2 power supply down detection interrupt generation circuit operation example output of the digital filter (2) d42 bit in d4int register notes : 1. d40 bit in the d4int register is set to 1 (voltage down detection interrupt enabled). 2. output of the digital filter is shown in figure 5.5.1.1. voltage down detection interrupt signal no voltage down detection interrupt signals are generated when the d42 bit is h . sampling vc13 bit in vcr1 register vcc sampling sampling sampling set to 0 by program (not detected) voltage down detection interrupt generation circuit watchdog timer interrupt signal vc27 vc13 voltage down detection circuit d4int clock(the clock with which it operates also in wait mode) d42 df1, df0 1/2 00b 01b 10b 11b 1/2 1/2 1/8 non-maskable interrupt signal oscillation stop, re-oscillation detection interrupt signal voltage down detection interrupt signal watchdog timer block this bit is set to 0 (not detected) by program. watchdog timer underflow signal d43 d41 cm02 wait instruction(wait mode) d40 vcc vref + - noise rejection (rejection range:200 ns) voltage down detection signal the voltage down detection signal becomes h when the vc27 bit is set to 0 (disabled) noise rejection circuit digital filter cm10 the d42 bit is set to 0 (not detected) by program. the vc27 bit is set to 0 (voltage down detect circuit disabled), the d42 bit is set to 0 .
5. reset page 30 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 5.5.2 limitations on exiting stop mode the voltage down detection interrupt is immediately generated and the microcomputer exits stop mode if the cm10 bit in the cm1 register is set to 1 under the conditions below. ? the vc27 bit in the vcr2 register is set to 1 (voltage down detection circuit enabled), ? the d40 bit in the d4int register is set to 1 (voltage down detection interrupt enabled), ? the d41 bit in the d4int register is set to 1 (voltage down detection interrupt is used to exit stop mode), and ? the voltage applied to the vcc pin is higher than vdet4 (the vc13 bit in the vcr1 register is 1 ) if the microcomputer is set to enter stop mode when the voltage applied to the vcc pin drops below vdet4 and to exit stop mode when the voltage applied rises to vdet4 or above, set the cm10 bit to 1 when vc13 bit is 0 (vcc < vdet4). 5.5.3 limitations on exiting wait mode the voltage down detection interrupt is immediately generated and the microcomputer exits wait mode if wait instruction is executed under the conditions below. ? the cm02 bit in the cm0 register is set to 1 (stop peripheral function clock), ? the vc27 bit in the vcr2 register is set to 1 (voltage down detection circuit enabled), ? the d40 bit in the d4int register is set to 1 (voltage down detection interrupt enabled), ? the d41 bit in the d4int register is set to 1 (voltage down detection interrupt is used to exit wait mode), and ? the voltage applied to the vcc pin is higher than vdet4 (the vc13 bit in the vcr1 register is 1 ) if the microcomputer is set to enter wait mode when the voltage applied to the vcc pin drops below vdet4 and to exit wait mode when the voltage applied rises to vdet4 or above, perform wait instruc- tion when vc13 bit is 0 (vcc < vdet4).
6. processor mode page 31 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 6. processor mode this device functions in single-chip mode only. figures 6.1 and 6.2 detail the associated registers. figure 6.2. pm1 register processor mode register 1 (note 1) symbol address after reset pm1 0005 16 0000100 0 2 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 flash data block access bit (note 2) 0: disabled 1: enabled (note 3) pm10 rw pm17 wait bit (note 5) 0 : no wait state 1 : with wait state (1 wait) 0 : watchdog timer interrupt 1 : watchdog timer reset (note 4) watchdog timer function select bit pm12 rw rw rw rw rw note 1: write to this register after setting the prc1 bit in the prcr register to "1" (write enable). note 2: to access the two 2k-byte data areas in data block a and data block b, this bit must be set to "1". note 3: when cpu rewrite mode (fmr01="1"), this bit is automatically set to "1" during that time. note 4: pm12 bit is set to 1 by writing a 1 in a program. (writing a 0 has no effect.) note 5: when pm17 bit is set to "1" (with wait state), one wait state is inserted when accessing the internal ram or the internal rom. should be set to "0". (b1) reserved bit should be set to "1". reserved bit should be set to "0". (b6-b4) reserved bit (b3) 0 10 00 figure 6.1. pm0 register processor mode register 0 (note) symbol address after reset pm0 0004 16 0000000 0 2 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 setting this bit to "1" resets the microcomputer. when read, its content is "0". software reset bit pm03 rw rw rw note: write to this register after setting the prc1 bit in the prcr register to "1" (write enable). should be set to "0". (b2-b0) reserved bit should be set to "0". (b7-b4) reserved bit 000 0 000
7. clock generation circuit page 32 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m ? cpu clock source ? peripheral function clock source use of clock main clock oscillation circuit sub clock oscillation circuit item ? cpu clock source ? timer a, b s clock source clock frequency 0 to 20 mhz 32.768 khz ? ceramic oscillator ? crystal oscillator usable oscillator ? crystal oscillator x in , x out pins to connect oscillator x cin , x cout presence oscillation stop, restart function presence oscillating(m16c/26a) stopped(m16c/26t) oscillator status after reset stopped externally derived clock can be input other pll frequency synthesizer 10 to 20 mhz presence stopped on-chip oscillator ? cpu clock source ? peripheral function clock source ? cpu and peripheral function clock sources when the main clock stops oscillating ? selectable source frequency: f 1(roc) , f 2(roc) , f 3(roc) ? selectable divider: by 2, by 4, by 8 presence oscillating ? cpu clock source ? peripheral function clock source (cpu clock source) 7. clock generation circuit the clock generation circuit contains four oscillator circuits as follows: (1) main clock oscillation circuit (2) sub clock oscillation circuit (3) on-chip oscillator (available at reset, oscillation stop detect function) (4) pll frequency synthesizer table 7.1 lists the clock generation circuit specifications. figure 7.1 shows the clock generation circuit. figures 7.2 to 7.6 show the clock-related registers. table 7.1. clock generation circuit specifications
7. clock generation circuit page 33 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m f c3 2 cm00, cm01, cm02, cm04, cm05, cm06, cm07: cm0 register bits cm10, cm11, cm16, cm17: cm1 register bits pclk0, pclk1, pclk5: pclkr register bits cm21, cm27 : cm2 register bits 1/32 main clock generating circuit f c cm02 cm04 cm10=1(stop mode) q s r wait instruction cm05 q s r nmi interrupt request level judgment output reset software reset f c cpu clock cm07 = 0 cm07 = 1 a d 1/2 1/2 1/2 1/2 cm06=0 cm17-cm16=00 2 cm06=0 cm17-cm16=01 2 cm06=0 cm17-cm16=10 2 cm06=1 cm06=0 cm17-cm16=11 2 d a details of divider sub-clock generating circuit x cin x cout x out x in f 8 f 32 c b b 1/2 c f 32sio f 8s i o f ad f 1 e e 1/2 1/4 1/8 1/16 1/32 p c lk 0 = 1 pll frequency s y nt h es i z e r 0 1 c m21= 1 c m11 c m21= 0 pl l cloc k sub-clock o n-chi p oscillato r cloc k p c lk 0 = 0 f 2 f 1 s i o p c lk1=1 p c lk1= 0 f 2 s i o main clock oscillation stop, re- oscillation detection circuit d4int clock clk out i/o ports pclk5=0,cm01-cm00=00 2 pclk5=0,cm01-cm00=01 2 pclk5=1, cm01-cm00=00 2 pclk5=0, cm01-cm00=10 2 pclk5=0, cm01-cm00=11 2 cm21 figure 7.1. clock generation circuit phase comparator charge pump voltage control oscillator (vco) pll clock main clock 1/2 programmable counter internal low- pass filter pll frequency synthesizer pulse generation circuit for clock edge detection and charge, discharge control charge, discharge circuit reset generating circuit oscillation stop, re-oscillation detection interrupt generating circuit main clock oscillation stop detection reset cm27=0 cm21 switch signal oscillation stop, re-oscillation detection signal oscillation stop, re-oscillation detection circuit cm27=1 1/2 1/2 1/2 rocr3-rocr2=11 2 on-chip oscillator clock 1/8 1/4 1/2 rocr3-rocr2=10 2 rocr3-rocr2=01 2 rocr1-rocr0=00 2 f 1(roc) f 2(roc) f 3(roc) rocr1-rocr0=01 2 rocr1-rocr0=11 2 on-chip oscillator
7. clock generation circuit page 34 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m system clock control register 0 (note 1) symbol address after reset cm0 0006 16 01001000 2 (m16c/26a) bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 cm07 cm05 cm04 cm03 cm02 cm06 wait peripheral function clock stop bit (note 10) 1 : stop peripheral function clock in wait mode (note 8) x cin -x cout drive capacity select bit (note 2) 1 : high main clock stop bit (notes 3, 10, 12, 13) 0 : on 1 : off (note 4, note5) main clock division select bit 0 (notes 7, 13, 14) 0 : cm16 and cm17 valid 1 : division by 8 mode system clock select bit (notes 6, 10, 11, 12) 0 : main clock, pll clock, or ring oscillator clock 1 : sub-clock note 1: write to this register after setting the prc0 bit in the prcr register to "1" (write enable). note 2: the cm03 bit is set to "1" (high) when the cm04 bit is set to "0" (i/o port) or the microcomputer goes to a stop mode. note 3: this bit is provided to stop the main clock when the low power dissipation mode or ring oscillator low power dissipatio n mode is selected. this bit cannot be used for detection as to whether the main clock stopped or not. to stop the main clock, the following setting is required: (1) set the cm07 bit to "1" (sub-clock select) or the cm21 bit in the cm2 register to "1" (ring oscillator select) with the sub-clock stably oscillating. (2) set the cm20 bit in cm2 register to "0" (oscillation stop, re-oscillation detection function disabled). (3) set the cm05 bit to "1" (stop). note 4: during external clock input, only the clock oscillation buffer is turned off and clock input is accepted. note 5: when cm05 bit is set to "1", the x out pin goes h ? . furthermore, because the internal feedback resistor remains connected, the x in pin is pulled "h" to the same level as x out via the feedback resistor. note 6: after setting the cm04 bit to "1" (x cin -x cout oscillator function), wait until the sub-clock oscillates stably before switching the cm07 bit from "0" to "1" (sub-clock). note 7: when entering stop mode from high or middle speed mode, ring oscillator mode or ring oscillator low power mode, the cm0 6 bit is set to "1" (divide-by-8 mode). note 8: the f c32 clock does not stop. during low speed or low power dissipation mode, do not set this bit to "1" (peripheral clock turned off when in wait mode). note 9: to use a sub-clock, set this bit to "1". also make sure ports p8 6 and p8 7 are directed for input, with no pull-ups. note 10: when the pm21 bit of pm2 register is set to "1" (clock modification disable), writing to the cm02, cm05, and cm07 bits has no effect. note 11: if the pm21 bit needs to be set to "1", set the cm07 bit to "0"(main clock) before setting it. note 12: to use the main clock as the clock source for the cpu clock, follow the procedure below. (1) set the cm05 bit to "0" (oscillate). (2) wait until td(m-l) elapses or the main clock oscillation stabilizes, whichever is longer. (3) set the cm11, cm21 and cm07 bits all to "0". note 13: when the cm21 bit is set to "0" (ring oscillaor turned off) and the cm05 bit is set to "1" (main clock turned off), th e cm06 bit is fixed to "1" (divide-by-8 mode) and the cm15 bit is fixed to "1" (drive capability high). note 14: to return from ring oscillator mode to high-speed or middle-speed mode set the cm06 and cm15 bits both to "1". rw port x c select bit (note 2) rw rw rw rw rw rw rw refer to table 7.5.3.1 function of the clkout pin 01101000 2 (m16c/26t) cm00 cm01 clock output function select bit 0 : do not stop peripheral function clock in wait mode 0 : low 0 : i/o port p8 6 , p8 7 1 : x cin -x cout generation function (note 9) rw figure 7.2. cm0 register
7. clock generation circuit page 35 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m system clock control register 1 (note 1) symbol address after reset cm1 0007 16 00100000 2 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 cm10 all clock stop control bit (notes 4, 6) 0 : clock on 1 : all clocks off (stop mode) note 1: write to this register after setting the prc0 bit in the prcr register to 1 (write enable). note 2: when entering stop mode from high or middle speed mode, or when the cm05 bit is set to 1 (main clock turned off) in low speed mode, the cm15 bit is set to 1 (drive capability high). note 3: effective when the cm06 bit is 0 (cm16 and cm17 bits enable). note 4: if the cm10 bit is 1 (stop mode), x out goes h and the internal feedback resistor is disconnected. the x cin and x cout pins are placed in the high-impedance state. when the cm11 bit is set to 1 (pll clock), or the cm20 bit in the cm2 register is set to 1 (oscillation stop, re-oscillation detection function enabled), do not set the cm10 bit to 1 . note 5: after setting the plc07 bit in the plc0 register to 1 (pll operation), wait until tsu (pll) elapses before setting the cm11 bit to 1 (pll clock). note 6: when the pm21 bit in the pm2 register is set to 1 (clock modification disable), writing to the cm10, cm011 bits has no effect. when the pm22 bit in the pm2 register is set to 1 (watchdog timer count source is on-chip oscillator clock), writing to the cm10 bit has no effect. note 7: effective when cm07 bit is 0 and cm21 bit is 0 . cm15 x in -x out drive capacity select bit (note 2) 0 : low 1 : high rw cm16 cm17 reserved bit must set to 0 main clock division select bits (note 3) 0 0 : no division mode 0 1 : division by 2 mode 1 0 : division by 4 mode 1 1 : division by 16 mode b7 b6 0 00 cm11 system clock select bit 1 (notes 6, 7) 0 : main clock 1 : pll clock (note 5) rw rw rw rw rw rw (b4-b2) figure 7.3. cm1 register figure 7.4. rocr register b7 b6 b5 b4 b3 b2 b1 b0 rw rocr0 rocr1 on-chip oscillator control register (note 1) symbol address after reset rocr 025c 16 00000101 2 bit name function bit symbol frequency select bits rw rw reserved bit when write, set to 0 . when read, its content is 0 . ro 00 00 0 0 : f 1 (roc) 0 1 : f 2 (roc) 1 0 : not supported 1 1 : f 3 (roc) b1 b0 rocr2 rocr3 divider select bits rw rw 0 0 : not supported 0 1 : divide by 2 1 0 : divide by 4 1 1 : divide by 8 b3 b2 note 1 : write to this register after setting the prc0 bit in the prcr register to "1" (write enable). (b5-b4) reserved bit set to 0 . rw (b6) reserved bit when write, set to 0 . when read, its content is indeterminate. ro (b7)
7. clock generation circuit page 36 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m b7 b6 b5 b4 b3 b2 b1 b0 rw cm20 cm21 oscillation stop detection register (note 1) symbol address after reset cm2 000c 16 0x000010 2 (note 11) bit name function bit symbol system clock select bit 2 (notes 2, 3, 6, 8, 11, 12 ) 0: oscillation stop, re-oscillation detection function disabled 1: oscillation stop, re-oscillation detection function enabled 0: main clock or pll clock 1: on-chip oscillator clock (on-chip oscillator oscillating) oscillation stop, re- oscillation detection bit (notes 7, 9, 10, 11) note 1: write to this register after setting the prc0 bit in the prcr register to 1 (write enable). note 2: when the cm20 bit is set to 1 (oscillation stop, re-oscillation detection function enabled), the cm27 bit is set to 1 (oscillation stop, re-oscillation detection interrupt), and the cpu clock source is the main clock, the cm21 bit is automatically set to 1 (on-chip oscillator clock) if the main clock stop is detected. note 3: if the cm20 bit is set to 1 and the cm23 bit is set to 1 (main clock not oscillating), do not set the cm21 bit to 0 . note 4: this flag is set to 1 when the main clock is detected to have stopped or when the main clock is detected to have restarted oscillating. when this flag changes state from 0 to 1 , an oscillation stop, reoscillation detection interrupt is generated. use this flag in an interrupt routine to discriminate the causes of interrupts between the oscillation stop, reoscillation detection interrupts and the watchdog timer interrupt. the flag is cleared to 0 by writing a 0 in a program. (writing a 1 has no effect. nor is it cleared to 0 by an oscillation stop or an oscillation restart detection interrupt request acknowledged.) if when the cm22 bit is set to "1" an oscillation stop or an oscillation restart is detected, no oscillation stop, reoscillatio n detection interrupts are generated. note 5: read the cm23 bit in an oscillation stop, re-oscillation detection interrupt handling routine to determine the main clo ck status. note 6: effective when the cm07 bit in the cm0 register is set to 0 . note 7: when the pm21 bit in the pm2 register is 1 (clock modification disabled), writing to the cm20 bit has no effect. note 8: when the cm20 bit is set to 1 (oscillation stop, re-oscillation detection function enabled), the cm27 bit is set to 1 (oscillation stop, re-oscillation detection interrupt), and the cm11 bit is set to 1 (the cpu clock source is pll clock), the cm21 bit remains unchanged even when main clock stop is detected. if the cm22 bit is set to 0 under these conditions, oscillation stop, re-oscillation detection interrupt occur at main clock stop detection; it is, therefore, necessary to set the cm21 bit to 1 (on-chip oscillator clock) inside the interrupt routine. note 9: set the cm20 bit to 0 (disable) before entering stop mode. after exiting stop mode, set the cm20 bit back to 1 (enable). note 10: set the cm20 bit to 0 (disable) before setting the cm05 bit in the cm0 register. note 11: the cm20, cm21 and cm27 bits do not change at oscillation stop detection reset. note 12: when the cm21 bit is set to "0" (on-chip oscillator turned off) and the cm05 bit is set to "1" (main clock turned off) , the cm06 bit is fixed to 1 (divide-by-8 mode) and the cm15 bit is fixed to 1 (drive capability high). cm22 cm23 oscillation stop, re- oscillation detection flag 0: main clock stop or re-oscillation not detected 1: main clock stop or re-oscillation detected 0: main clock oscillating 1: main clock not oscillating x in monitor flag (note 4) cm27 0: oscillation stop detection reset 1: oscillation stop, re-oscillation detection interrupt nothing is assigned. when write, set to 0 . when read, its content is indeterminate. operation select bit (when an oscillation stop, re-oscillation is detected) (note 11) rw rw rw rw ro (b6) (note 5) reserved bit (b5-b4) must set to 0 rw 00 figure 7.5. cm2 register
7. clock generation circuit page 37 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 7.6. pclkr register and pm2 register function bit symbol bit name peripheral clock select register (note) symbol address when reset pclkr 025e 16 00000011 2 rw b7 b6 b5 b4 b3 b2 b1 b0 pclk0 timers a, b clock select bit (clock source for the timers a, b, and the dead timer) 0 : f 2 1 : f 1 000 reserved bit must set to ? note: write to this register after setting the prc0 bit in the prcr register to ??(write enable). 00 pclk1 si/o clock select bit (clock source for uart0 to uart2) 0 : f 2sio 1 : f 1sio rw rw rw (b4-b2) reserved bit must set to ? rw (b7-b6) rw pclk5 clock output function expansion select bit refer to table 7.5.3.1 function of clkout pin function bit symbol bit name processeor mode register 2 (note 1) symbol address when reset pm2 001e 16 xxx00000 2 rw b7 b6 b5 b4 b3 b2 b1 b0 pm20 specifying wait when accessing sfr at pll operation 0 : 2 wait 1 : 1 wait 0 nothing is assigned. when write, set to 0 . when read, its content is indeterminate. pm21 system clock protective bit 0 : clock is protected by prcr register 1 : clock modification disabled rw rw rw (b7-b5) pm22 pm24 (b3) wdt count source protective bit reserved bit 0 : cpu clock is used for the watchdog timer count source 1 : on-chip oscillator clock is used for the watchdog timer count source must set to 0 p8 5 /nmi configuration bit rw rw (note 2) (note 3,4) (note 3,5) (note 6,7) note 1: write to this register after setting the prc1 bit in the prcr register to 1 (write enable). note 2: this bit can only be rewritten while the plc07 bit is 0 (pll turned off). also, set the pm20 bit to 0 (2 wait) when pll clock > 16mhz. note that if the clock source for the cpu clock is to be changed from pll clock to another, the plc07 bit must be set to "0" before setting the pm20 bit. note 3: once this bit is set to 1 , it cannot be cleared to 0 in a program. note 4: if the pm21 bit is set to 1 , writing to the following bits has no efftect: cm02 bit in the cm0 register cm05 bit in the cm0 register (main clock is not halted) cm07 bit in the cm0 register (cpu clock source does not change) cm10 bit in the cm1 register (stop mode is not entered) cm11 bit in the cm1 register (cpu clock source does not change) cm20 bit in the cm2 register (oscillation stop, re-oscillation detection function settings do not change) all bits in the plc0 register (pll frequency synthesizer setting do not change) be aware that the wait instruction cannot be executed when the pm21 bit is set to "1". note 5: setting the pm22 bit to 1 results in the following conditions: the on-chip oscillator starts oscillating, and the on-chip oscillator clock becomes the watchdog timer count source. the cm10 bit in the cm1 register is disabled against write. (writing a 1 has no effect, nor is stop mode entered.) the watchdog timer does not stop when in wait mode. note 6: for nmi function, the pm24 bit must be set to 1 (nmi function) in first instruction after rest. once this bit is set to 1 , it cannot be cleared to 0 in a program. when the pm24 bit is set to 1 , the p85 direction register must be 0 (input mode). note 7: sd input is valid regardless of the pm24 setting. 0 : p8 5 function (nmi disable) 1 : nmi function
7. clock generation circuit page 38 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 7.7. plc0 register plc00 plc01 plc02 plc07 (note 3) (note 4) function note 1: write to this register after setting the prc0 bit in the prcr register to "1" (write enable). note 2: when the pm21 bit in the pm2 register is "1" (clock modification disable), writing to this register has no effect. note 3: these three bits can only be modified when the plc07 bit is set to "0" (pll turned off). the value once written to this bit cannot be modified. note 4: before setting this bit to "1" , set the cm07 bit to "0" (main clock), set the cm17 and cm16 bits to "00 2 " (main clock undivided mode), and set the cm06 bit to "0" (cm16 and cm17 bits enable). pll control register 0 (note 1, note 2) pll multiplying factor select bit nothing is assigned. when write, set to "0". when read, its content is indeterminate. reserved bit operation enable bit 0 0 0: 0 0 1: multiply by 2 0 1 0: multiply by 4 0 1 1: 1 0 0: 1 0 1: 1 1 0: 1 1 1: 0: pll off 1: pll on must set to "1" bit name bit symbol symbol address after reset plc0 001c 16 0001 x010 2 rw b1b0 b2 reserved bit must set to "0" do not set rw rw rw rw rw rw do not set (b4) (b6-b5) (b3) b7 b6 b5 b4 b3 b2 b1 b0 0 1 0
7. clock generation circuit page 39 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m microcomputer (built-in feedback resistor) x in x out externally derived clock open v cc vss microcomputer (built-in feedback resistor) x in x out r d c in c out (note) note: insert a damping resistor if required. the resistance will vary depending on the oscillator and the oscillation drive capacity setting. use the value recommended by the maker of the oscillator. when the oscillation drive capacity is set to low, check that oscillation is stable. also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between x in and x out following the instruction. figure 7.1.1. examples of main clock connection circuit the following describes the clocks generated by the clock generation circuit. 7.1 main clock the main clock is generated by the main clock oscillation circuit. this clock is used as the clock source for the cpu and peripheral function clocks. the main clock oscillator circuit is configured by connecting a resonator between the x in and x out pins. the main clock oscillator circuit contains a feedback resistor, which is disconnected from the oscillator circuit during stop mode in order to reduce the amount of power consumed in the chip. the main clock oscillator circuit may also be configured by feeding an externally generated clock to the x in pin. figure 7.1.1 shows the examples of main clock connection circuit. the main clock after reset oscillates in the m16c/26a, but stop in the m16c/26t. the power consumption in the chip can be reduced by setting the cm05 bit in the cm0 register to 1 (main clock oscillator circuit turned off) after switching the clock source for the cpu clock to a sub clock or on-chip oscillator clock. in this case, x out goes h . furthermore, because the internal feedback resistor remains on, x in is pulled h to x out via the feedback resistor. during stop mode, all clocks including the main clock are turned off. refer to 7.6 power control . if the main clock is not used, it is recommended to connect the xin pin to vcc to reduce power consump- tion during reset.
7. clock generation circuit page 40 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m microcomputer (built-in feedback resistor) x cin x cout externally derived clock open vss note: insert a damping resistor if required. the resistance will vary depending on the oscillator and the oscillation drive capacity setting. use the value recommended by the maker of the oscillator. when the oscillation drive capacity is set to low, check that oscillation is stable. also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between x cin and x cout following the instruction. microcomputer (built-in feedback resistor) x cin x cout (note) c cin c cout r cd v cc figure 7.2.1. examples of sub clock connection circuit 7.2 sub clock the sub clock is generated by the sub clock oscillation circuit. this clock is used as the clock source for the cpu clock, as well as the timer a and timer b count sources. the sub clock oscillator circuit is configured by connecting a crystal resonator between the x cin and x cout pins. the sub clock oscillator circuit contains a feedback resistor, which is disconnected from the oscillator circuit during stop mode in order to reduce the amount of power consumed in the chip. the sub clock oscillator circuit may also be configured by feeding an externally generated clock to the x cin pin. figure 7.2.1 shows the examples of sub clock connection circuit. after reset, the sub clock is turned off. at this time, the feedback resistor is disconnected from the oscillator circuit. to use the sub clock for the cpu clock, set the cm07 bit in the cm0 register to 1 (sub clock) after the sub clock becomes oscillating stably. during stop mode, all clocks including the sub clock are turned off. refer to 7.6 power control .
7. clock generation circuit page 41 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 7.3 on-chip oscillator clock this clock is supplied by a on-chip oscillator. this clock is used as the clock source for the cpu and peripheral function clocks. in addition, if the pm22 bit in the pm2 register is 1 (on-chip oscillator clock for the watchdog timer count source), this clock is used as the count source for the watchdog timer (refer to 10.1 count source protective mode ). the on-chip oscillator clock after reset oscillates. the on-chip oscillator clock f 2(roc) divided by 16 is used for the cpu clock. it can also be turned off by setting the cm21 bit in the cm2 register to 0 (main clock or pll clock). if the main clock stops oscillating when the cm20 bit in the cm2 register is 1 (oscillation stop, re-oscillation detection function enabled) and the cm27 bit is 1 (oscillation stop, re-oscillation detection interrupt), the on-chip oscillator automatically starts operating, supplying the necessary clock for the micro- computer. 7.4 pll clock the pll clock is generated from the main clock by a pll frequency synthesizer. this clock is used as the clock source for the cpu and peripheral function clocks. after reset, the pll clock is turned off. the pll frequency synthesizer is activated by setting the plc07 bit to 1 (pll operation). when the pll clock is used as the clock source for the cpu clock, wait t su (pll) for the pll clock to be stable, and then set the cm11 bit in the cm1 register to 1 . before entering wait mode or stop mode, be sure to set the cm11 bit to 0 (cpu clock source is the main clock). furthermore, before entering stop mode, be sure to set the plc07 bit in the plc0 register to 0 (pll stops). figure 7.4.1 shows the procedure for using the pll clock as the clock source for the cpu. the pll clock frequency is determined by the equation below. pll clock frequency=f(x in ) x (multiplying factor set by the plc02 to plc00 bits in the plc0 register (however, 10 mhz pll clock frequency 20 mhz) the plc02 to plc00 bits can be set only once after reset. table 7.4.1 shows the example for setting pll clock frequencies. x in (mhz) plc02 plc01 plc00 multiplying factor pll clock (mhz)(note) 10 0 0 1 2 20 50 1 0 4 note: 10mhz pll clock frequency 20mhz. table 7.4.1. example for setting pll clock frequencies
7. clock generation circuit page 42 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 7.4.1. procedure to use pll clock as cpu clock source start set the cm07 bit to 0 (main clock), the cm17 to cm16 bits to 00 2 (main clock undivided), and the cm06 bit to 0 (cm16 and cm17 bits enabled). (note) set the plc02 to plc00 bits (multiplying factor). (to select a 16 mhz < pll clock) set the pm20 bit to 0 (2-wait states). set the plc07 bit to 1 (pll operation). wait until the pll clock becomes stable (t su (pll)). set the cm11 bit to 1 (pll clock for the cpu clock source). end note : pll operation mode can be entered from high speed mode.
7. clock generation circuit page 43 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 7.5 cpu clock and peripheral function clock the cpu clock is used to operate the cpu and peripheral function clocks are used to operate the periph- eral functions. 7.5.1 cpu clock this is the operating clock for the cpu and watchdog timer. the clock source for the cpu clock can be chosen to be the main clock, sub clock, on-chip oscillator clock or the pll clock. if the main clock or on-chip oscillator clock is selected as the clock source for the cpu clock, the selected clock source can be divided by 1 (undivided), 2, 4, 8 or 16 to produce the cpu clock. use the cm06 bit in cm0 register and the cm17 to cm16 bits in cm1 register to select the divide-by-n value. when the pll clock is selected as the clock source for the cpu clock, the cm06 bit should be set to 0 and the cm17 and cm16 bits to 00 2 (undivided). after reset, the on-chip oscillator clock divided by 16 provides the cpu clock. note that when entering stop mode from high or middle speed mode, on-chip oscillator mode or on-chip oscillator low power dissipation mode, or when the cm05 bit in the cm0 register is set to 1 (main clock turned off) in low-speed mode, the cm06 bit in the cm0 register is set to 1 (divide-by-8 mode). 7.5.2 peripheral function clock(f 1 , f 2 , f 8 , f 32 , f 1sio , f 2sio , f 8sio , f 32sio , f ad , f c32 ) these are operating clocks for the peripheral functions. of these, fi (i = 1, 2, 8, 32) and fi sio are derived from the main clock, pll clock or on-chip oscillator clock by dividing them by i. the clock fi is used for timers a and b, and fi sio is used for serial i/o. the f ad clock is produced from the main clock, pll clock or on-chip oscillator clock, and is used for the a/ d converter. when the wait instruction is executed after setting the cm02 bit in the cm0 register to 1 (peripheral function clock turned off during wait mode), or when the microcomputer is in low power dissipation mode, the fi, fi sio and f ad clocks are turned off. the f c32 clock is produced from the sub clock, and is used for timers a and b. this clock can only be used when the sub clock is on. 7.5.3 clockoutput function the f 1 , f 8 , f 32 or f c clock can be output from the clk out pin. use the pclk5 bit in the pclkr register and cm01 to cm00 bits in the cm0 register to select. table 7.5.3.1 shows the function of the clk out pin. table 7.5.3.1 the function of the clk out pin pc lk5 cm01 cm00 the function of the clk out pin 0 0 0 i/o port p9 0 001f c 010f 8 011f 32 100f 1 1 0 1 do not set 1 1 0 do not set 1 1 1 do not set
7. clock generation circuit page 44 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 7.6 power control there are three power control modes. for convenience sake, all modes other than wait and stop modes are referred to as normal operation mode here. 7.6.1 normal operation mode normal operation mode is further classified into seven modes. in normal operation mode, because the cpu clock and the peripheral function clocks both are on, the cpu and the peripheral functions are operating. power control is exercised by controlling the cpu clock frequency. the higher the cpu clock frequency, the greater the processing capability. the lower the cpu clock frequency, the smaller the power consumption in the chip. if the unnecessary oscillator circuits are turned off, the power consumption is further reduced. before the clock sources for the cpu clock can be switched over, the new clock source to which switched must be oscillating stably. if the new clock source is the main clock, sub clock or pll clock, allow a sufficient wait time in a program until it becomes oscillating stably. note that operation modes cannot be changed directly from low speed or low power dissipation mode to on-chip oscillator or on-chip oscillator low power dissipation mode. nor can operation modes be changed directly from on-chip oscillator or on-chip oscillator low power dissipation mode to low speed or low power dissipation mode. when the cpu clock source is changed from the on-chip oscillator to the main clock, change the operation mode to the medium speed mode (divided by 8 mode) after the clock was divided by 8 (the cm06 bit in the cm0 register was set to 1 ) in the on-chip oscillator mode. 7.6.1.1 high-speed mode the main clock divided by 1 provides the cpu clock. if the sub clock is on, f c32 can be used as the count source for timers a and b. 7.6.1.2 pll operation mode the main clock multiplied by 2 or 4 provides the pll clock, and this pll clock serves as the cpu clock. if the sub clock is on, f c32 can be used as the count source for timers a and b. pll operation mode can be entered from high speed mode. if pll operation mode is to be changed to wait or stop mode, first go to high speed mode before changing. 7.6.1.3 medium-speed mode the main clock divided by 2, 4, 8 or 16 provides the cpu clock. if the sub clock is on, f c32 can be used as the count source for timers a and b. 7.6.1.4 low-speed mode the sub clock provides the cpu clock. the main clock is used as the clock source for the peripheral function clock when the cm21 bit is set to 0 (on-chip oscillator turned off), and the on-chip oscillator clock is used when the cm21 bit is set to 1 (on-chip oscillator oscillating). the f c32 clock can be used as the count source for timers a and b. 7.6.1.5 low power dissipation mode in this mode, the main clock is turned off after being placed in low speed mode. the sub clock provides the cpu clock. the f c32 clock can be used as the count source for timers a and b. peripheral function clock can use only f c32 . simultaneously when this mode is selected, the cm06 bit in the cm0 register becomes 1 (divided by 8 mode). in the low power dissipation mode, do not change the cm06 bit. consequently, the medium speed (divided by 8) mode is to be selected when the main clock is operated next.
7. clock generation circuit page 45 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 7.6.1.6 on-chip oscillator mode the selected on-chip oscillator clock divided by 1 (undivided), 2, 4, 8 or 16 provides the cpu clock. the on-chip oscillator clock is also the clock source for the peripheral function clocks. if the sub clock is on, f c32 can be used as the count source for timers a and b. the on-chip oscillator frequency can be selected rocr3 to rocr0 bits in rocr register. when the operation mode is returned to the high and medium speed modes, set the cm06 bit to 1 (divided by 8 mode). 7.6.1.7 on-chip oscillator low power dissipation mode the main clock is turned off after being placed in on-chip oscillator mode. the cpu clock can be selected as in the on-chip oscillator mode. the on-chip oscillator clock is the clock source for the peripheral function clocks. if the sub clock is on, f c32 can be used as the count source for timers a and b. 1(note 1) modes cm2 register cm21 cm1 register cm11 cm17, cm16 cm0 register cm07 cm06 cm05 cm04 pll operation mode 0100 2 00 high-speed mode 0 0 00 2 00 0 medium- speed mode 0001 2 00 0 0010 2 00 0 divided by 2 00 01 0 0011 2 00 0 low-speed mode 1 0 1 low power dissipation mode 11 on-chip oscillator mode (note 3) 1 divided by 4 divided by 8 divided by 16 on-chip oscillator low power dissipation mode note 1: when the cm05 bit is set to 1 (main clock turned off) in low-speed mode, the mode goes to low power dissipation mode and cm06 bit is set to 1 (divided by 8 mode) simultaneously. note 2: the divide-by-n value can be selected the same way as in on-chip oscillator mode. 0 0 101 2 000 110 2 000 110 111 2 00 0 100 2 00 0 (note 2) divided by 2 divided by 4 divided by 8 divided by 16 divided by 1 1(note 1) (note 2) 1 note 3: on-chip oscillator frequency can be any of those described in the section 7.6.1.6 on-chip oscillator mode . 0 0 7.6.2 wait mode in wait mode, the cpu clock is turned off, so are the cpu (because operated by the cpu clock) and the watchdog timer. however, if the pm22 bit in the pm2 register is 1 (on-chip oscillator clock for the watch- dog timer count source), the watchdog timer remains active. because the main clock, sub clock, on-chip oscillator clock and pll clock all are on, the peripheral functions using these clocks keep operating. 7.6.2.1 peripheral function clock stop function if the cm02 bit is 1 (peripheral function clocks turned off during wait mode), the f 1 , f 2 , f 8 , f 32 , f 1sio , f 8sio , f 32sio and f ad clocks are turned off when in wait mode, with the power consumption reduced that much. however, f c32 remains on. 7.6.2.2 entering wait mode the microcomputer is placed into wait mode by executing the wait instruction. when the cm11 bit is set to 1 (cpu clock source is the pll clock), be sure to clear the cm11 bit to 0 (cpu clock source is the main clock) before going to wait mode. the power consumption of the chip can be reduced by clearing the plc07 bit to 0 (pll stops). table 7.6.1.1. setting clock related bit and modes
7. clock generation circuit page 46 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m interrupt cm02=0 cm02=1 nmi interrupt can be used serial i/o interrupt can be used when operating with internal or external clock can be used when operating with external clock key input interrupt can be used can be used a/d conversion interrupt can be used in one-shot mode or single sweep mode timer a interrupt can be used in all modes can be used in event counter mode or when the count source is fc32 timer b interrupt int interrupt can be used can be used (do not use) can be used table 7.6.2.4.1. interrupts to exit wait mode 7.6.2.3 pin status during wait mode table 7.6.2.3.1 lists pin status during wait mode. table 7.6.2.3.1 pin status in wait mode pin status i/o ports retains status before wait mode when fc selected does not stop clk out when f1, f8, f32 selected does not stop when the cm02 bit is set to 0 . retains status before wait mode when the cm02 bit is set to 1 . 7.6.2.4 exiting wait mode ______ the microcomputer is moved out of wait mode by a hardware reset, nmi interrupt or peripheral func- tion interrupt. ______ if the microcomputer is to be moved out of exit wait mode by a hardware reset or nmi interrupt, set the peripheral function interrupt priority ilvl2 to ilvl0 bits to 000 2 (interrupts disabled) before execut- ing the wait instruction. the peripheral function interrupts are affected by the cm02 bit. if the cm02 bit is set to 0 (peripheral function clocks not turned off during wait mode), all peripheral function interrupts can be used to exit wait mode. if the cm02 bit is set to 1 (peripheral function clocks turned off during wait mode), the peripheral functions using the peripheral function clocks stop operating, so that only the peripheral functions clocked by external signals can be used to exit wait mode. table 7.6.2.4.1 lists the interrupts to exit wait mode. if the microcomputer is to be moved out of wait mode by a peripheral function interrupt, set up the following before executing the wait instruction. 1. in the ilvl2 to ilvl0 bits in the interrupt control register, set the interrupt priority level of the periph eral function interrupt to be used to exit wait mode. also, for all of the peripheral function interrupts not used to exit wait mode, set the ilvl2 to ilvl0 bits to 000 2 (interrupt disable). 2. set the i flag to 1 . 3. enable the peripheral function whose interrupt is to be used to exit wait mode. in this case, when an interrupt request is generated and the cpu clock is thereby turned on, an interrupt routine is executed. the cpu clock turned on when exiting wait mode by a peripheral function interrupt is the same cpu clock that was on when the wait instruction was executed.
7. clock generation circuit page 47 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 7.6.3 stop mode in stop mode, all oscillator circuits are turned off, so are the cpu clock and the peripheral function clocks. therefore, the cpu and the peripheral functions clocked by these clocks stop operating. the least amount of power is consumed in this mode. if the voltage applied to vcc pin is v ram or more, the internal ram is retained. when applying 2.7 or less voltage to vcc pin, make sure vcc v ram . however, the peripheral functions clocked by external signals keep operating. the following interrupts can be used to exit stop mode. ______ ? nmi interrupt ? key interrupt ______ ? int interrupt ? timer a, timer b interrupt (when counting external pulses in event counter mode) ? serial i/o interrupt (when external clock is selected) ? voltage down detection interrupt (refer to 5.5.1 voltage down detection interrupt for an operating condition) 7.6.3.1 entering stop mode the microcomputer is placed into stop mode by setting the cm10 bit in the cm1 register to 1 (all clocks turned off). at the same time, the cm06 bit in the cm0 register is set to 1 (divide-by-8 mode) and the cm15 bit in the cm10 register is set to 1 (main clock oscillator circuit drive capability high). before entering stop mode, set the cm20 bit to 0 (oscillation stop, re-oscillation detection function disable). also, if the cm11 bit is 1 (pll clock for the cpu clock source), set the cm11 bit to 0 (main clock for the cpu clock source) and the plc07 bit to 0 (pll turned off) before entering stop mode. 7.6.3.2 pin status during stop mode the i/o pins retain their status held just prior to entering stop mode. 7.6.3.3 exiting stop mode ______ the microcomputer is moved out of stop mode by a hardware reset, nmi interrupt or peripheral func- tion interrupt. ______ if the microcomputer is to be moved out of stop mode by a hardware reset or nmi interrupt, set the peripheral function interrupt priority ilvl2 to ilvl0 bits to 000 2 (interrupts disable) before setting the cm10 bit to 1 . if the microcomputer is to be moved out of stop mode by a peripheral function interrupt, set up the following before setting the cm10 bit to 1 . 1. in the ilvl2 to ilvl0 bits in the interrupt control register, set the interrupt priority level of the peripheral function interrupt to be used to exit stop mode. also, for all of the peripheral function interrupts not used to exit stop mode, set the ilvl2 to ilvl0 bits to 000 2 . 2. set the i flag to 1 . 3. enable the peripheral function whose interrupt is to be used to exit stop mode. in this case, when an interrupt request is generated and the cpu clock is thereby turned on, an interrupt service routine is executed. ______ which cpu clock will be used after exiting stop mode by a peripheral function or nmi interrupt is determined by the cpu clock that was on when the microcomputer was placed into stop mode as follows: if the cpu clock before entering stop mode was derived from the sub clock : sub clock if the cpu clock before entering stop mode was derived from the main clock : main clock divide-by-8 if the cpu clock before entering stop mode was derived from the on-chip oscillator clock: on-chip oscillator clock divide-by-8
7. clock generation circuit page 48 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 7.6.1. state transition to stop mode and wait mode reset medium-speed mode (divided-by-8 mode) high-speed, medium- speed mode stop mode wait mode interrupt cm10=1 interrupt low-speed, low power dissipation mode cm10=1 stop mode interrupt wait mode interrupt cm10=1 stop mode all oscillators stopped interrupt wait mode wait instruction interrupt cpu operation stopped when low- speed mode when low power dissipation mode pll operation mode notes 1, 2 : arrow shows mode can be changed. do not change mode to another mode when no arrow is shown. note 1: do not go directly from pll operation mode to wait or stop mode. note 2: pll operation mode can be entered from high speed mode. similarly, pll operation mode can be changed back to high speed mode. note 3: when the pm21 bit is set to "0" (system clock protective function unused). note 4: the on-chip oscillator clock divided by 8 provides the cpu clock. note 5: write to the cm0 register and cm1 register simultaneously by accessing in word units while cm21 bit is set to "1" (on- chip oscillator turned off). when the clock generated externally is input to the x cin pin, transit to stop mode with this process. note 6: before entering stop mode, be sure to clear the cm20 bit in the cm2 register to "0" (oscillation stop and oscillation r estart detection function disabled). wait mode interrupt cm10=1 interrupt (note 4) stop mode wait instruction wait instruction wait instruction on-chip oscillator mode (selectable frequency) on-chip oscillator mode (f 2 (roc) /16) normal operation mode cm21=1 cm21=0 cm07=0 cm06=1 cm05=0 cm11=0 cm10=1 (note 5) on-chip oscillator low power dissipation mode cm10=1 stop mode interrupt wait mode interrupt wait instruction figure 7.6.1 shows the state transition from normal operation mode to stop mode and wait mode. figure 7.6.1.1 shows the state transition in normal operation mode. table 7.6.1 shows a state transition matrix describing allowed transition and setting. the vertical line shows current state and horizontal line shows state after transition.
7. clock generation circuit page 49 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 7.6.1.1. state transition in normal mode cm04=0 cpu clock: f(pll) cm07=0 cm06=0 cm17=0 cm16=0 pll operation mode cm07=0 cm06=0 cm17=0 cm16=0 cm07=0 cm17=0 cm06=0 cm16=0 cm07=0 cm17=0 cm06=0 cm16=1 cm07=0 cm17=1 cm06=0 cm16=0 cm07=0 cm06=1 cm07=0 cm17=1 cm06=0 cm16=1 high-speed mode cm07=0 cm17=0 cm06=0 cm16=0 cm07=0 cm17=0 cm06=0 cm16=1 cm07=0 cm17=1 cm06=0 cm16=0 cm07=0 cm06=1 cm07=0 cm17=1 cm06=0 cm16=1 cm07=0 low-speed mode cm07=0 low power dissipation mode cm06=1 cm15=1 on-chip oscillator mode cpu clock on-chip oscillator mode cpu clock cpu clock on-chip oscillator low power dissipation mode cpu clock cm07=0 low-speed mode plc07=1 cm11=1 (note 6) plc07=0 cm11=0 (note 7) cm04=0 plc07=1 cm11=1 plc07=0 cm11=0 cm04=0 cm04=1 cm04=1 cm04=1 cm04=0 cm04=1 cm07=0 (note 2, note 4) cm07=1 (note 3) cm05=1 (note 1, note 9) cm05=0 cm21=0 (note 8) cm21=1 cm21=0 (note 8) cm21=1 cm21=0 cm21=1 main clock oscillation on-chip oscillator clock oscillation sub clock oscillation f(ring) f(ring)/2 f(ring)/4 f(ring)/8 f(ring)/16 f(ring) f(ring)/2 f(ring)/4 f(ring)/8 f(ring)/16 f(ring) f(ring)/2 f(ring)/4 f(ring)/8 f(ring)/16 f(ring) f(ring)/2 f(ring)/4 f(ring)/8 f(ring)/16 pll operation mode cpu clock: f(pll) cpu clock: f(x in ) high-speed mode middle-speed mode (divide by 2) cpu clock: f(x in )/2 cpu clock: f(x in )/4 cpu clock: f(x in )/8 cpu clock: f(x in )/16 cpu clock: f(x cin ) cpu clock: f(x cin ) cpu clock: f(x cin ) cm05=0 m0 m cm05=1 (note 1) cm05=1 (note 1) cm05=0 (note 6) (note 7) middle-speed mode (divide by 4) middle-speed mode (divide by 8) middle-speed mode (divide by 16) middle-speed mode (divide by 2) middle-speed mode (divide by 4) middle-speed mode (divide by 8) middle-speed mode (divide by 16) cpu clock: f(x in ) cpu clock: f(x in )/2 cpu clock: f(x in )/4 cpu clock: f(x in )/8 cpu clock: f(x in )/16 on-chip oscillator low power dissipation mode notes: : arrow shows mode can be changed. do not change mode to another mode when no arrow is shown. 1: avoid making a transition when the cm20 bit is set to 1 (oscillation stop, re-oscillation detection function enabled). set the cm20 bit to 0 (oscillation stop, re-oscillation detection function disabled) before transiting. 2: wait for the main clock oscillation stabilization time before switching over. 3: switch clock after oscillation of sub-clock is sufficiently stable. 4: change cm17 and cm16 before changing cm06. 5: transit in accordance with arrow. 6: pll operation mode can only be entered from high speed mode. also, wait until the pll clock is sufficiently stable before c hanging operation modes. to select pll clock > 16mhz, set the pm20 bit to 0 (sfr accessed with two wait states) before setting plc07 to 1 (pll operation). 7: pll operation mode can only be changed to high speed mode. if the pm20 bit is set to "0" (sfr accessed with two wait states ), set plc07 to 0 (pll turned off) before setting the pm20 bit to 1 (sfr accessed with one wait state). 8: set the cm06 bit to 1 (division by 8 mode) before changing back the operation mode from on-chip oscillator mode to high- or middle-speed mode. 9: when the cm21 bit is set to "0" (on-chip oscillator turned off) and the cm05 bit is set to "1" (main clock turned off), th e cm06 bit is fixed to 1 (divide-by-8 mode) and the cm15 bit is fixed to 1 (drive capability high).
7. clock generation circuit page 50 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m table 7.6.1. allowed transition and setting high-speed mode, middle-speed mode on-chip oscillator mode stop mode wait mode on-chip oscillator low power dissipation mode pll operation mode 2 low power dissipation mode low-speed mode 2 current state state after transition see table a 8 -- (8) (18) 5 (9) 7 -- (10) (11) 1, 6 (12) 3 (14) 4 -- -- -- -- -- (13) 3 (15) -- -- -- -- -- -- -- (10) -- -- -- -- -- -- -- -- (18) (18) -- -- (16) 1 (17) (16) 1 (17) (16) 1 (17) (16) 1 (17) (16) 1 (17) -- -- (18) 5 (18) 5 (18) (18) (18) (18) (18) (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) setting operation cm04 = 0 sub clock turned off cm04 = 1 sub clock oscillating cm06 = 0, cpu clock no division mode cm17 = 0 , cm16 = 0 cm06 = 0, cpu clock division by 2 mode cm17 = 0 , cm16 = 1 cm06 = 0, cpu clock division by 4 mode cm17 = 1 , cm16 = 0 cm06 = 1 cpu clock division by 8 mode cm06 = 0, cpu clock division by 16 mode cm17 = 1 , cm16 = 1 cm07 = 0 main clock, pll clock, or on-chip oscillator clock selected cm07 = 1 sub clock selected cm05 = 0 main clock oscillating cm05 = 1 main clock turned off plc07 = 0, cm11 = 0 main clock selected plc07 = 1, cm11 = 1 pll clock selected cm21 = 0 main clock or pll clock selected cm21 = 1 on-chip oscillator clock selected cm10 = 1 transition to stop mode wait instruction transition to wait mode hardware interrupt exit stop mode or wait mode notes: 1. avoid making a transition when the cm21 bit is set to 1 (oscillation stop, re-oscillation detection function enabled). set the cm21 bit to 0 (oscillation stop, re-oscillation detection function disabled) before transiting. 2. on-chip oscillator clock oscillates and stops in low-speed mode. in this mode, the on-chip oscillator can be used as periphe ral function clock. sub clock oscillates and stops in pll operation mode. in this mode, sub clock can be used as peripheral function clock. 3. pll operation mode can only be entered from and changed to high-speed mode. 4. set the cm06 bit to 1 (division by 8 mode) before transiting from on-chip oscillator mode to high- or middle-speed mode. 5. when exiting stop mode, the cm06 bit is set to 1 (division by 8 mode). 6. if the cm05 bit is set to 1 (main clock stop), then the cm06 bit is set to 1 (division by 8 mode). 7. a transition can be made only when sub clock is oscillating. 8. state transitions within the same mode (divide-by-n values changed or subclock oscillation turned on or off) are shown in th e table below. --: cannot transit (11) 1 high-speed mode, middle-speed mode on-chip oscillator mode stop mode wait mode on-chip oscillator low power dissipation mode pll operation mode 2 low power dissipation mode low-speed mode 2 see table a 8 see table a 8 (3) (3) (3) (3) (4) (4) (4) (4) (5) (7) (7) (5) (5) (5) (7) (7) (6) (6) (6) (6) no division divided by 2 (3) (3) (3) (3) (4) (4) (4) (4) (5) (5) (5) (5) (7) (7) (7) (7) (6) (6) (6) (6) (1) (1) (1) (1) (1) (2) (2) (2) (2) (2) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- sub clock oscillating sub clock turned off --: cannot transit divided by 4 divided by 8 divided by 16 no division divided by 2 divided by 4 divided by 8 divided by 16 no division divided by 4 sub clock oscillating sub clock turned off divided by 8 divided by 16 divided by 2 no division divided by 4 divided by 8 divided by 16 divided by 2 9. ( ) : setting method. refer to following table. cm04, cm05, cm06, cm07 : bits in the cm0 register cm10, cm11, cm16, cm17 : bits in the cm1 register cm20, cm21 : bits in the cm2 register plc07 : bit in the plc0 register
7. clock generation circuit page 51 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 7.7 system clock protective function when the main clock is selected for the cpu clock source, this function protects the clock from modifica- tions in order to prevent the cpu clock from becoming halted by run-away. if the pm21 bit in the pm2 register is set to 1 (clock modification disabled), the following bits are protected against writes: ? cm02, cm05, and cm07 bits in cm0 register ? cm10, cm11 bits in cm1 register ? cm20 bit in cm2 register ? all bits in plc0 register before the system clock protective function can be used, the following register settings must be made while the cm05 bit in the cm0 register is 0 (main clock oscillating) and cm07 bit is 0 (main clock selected for the cpu clock source): (1) set the prc1 bit in the prcr register to 1 (enable writes to pm2 register). (2) set the pm21 bit in the pm2 register to 1 (disable clock modification). (3) set the prc1 bit in the prcr register to 0 (disable writes to pm2 register). do not execute the wait instruction when the pm21 bit is set to 1 . 7.8 oscillation stop and re-oscillation detect function the oscillation stop and re-oscillation detect function allows the detection of main clock oscillation stop and reoscillation. at oscillation stop or re-oscillation detection, reset or oscillation stop, re-oscillation detection interrupt are generated. depending on the cm27 bit in the cm2 register. the oscillation stop detection function can be enabled and disabled by the cm20 bit in the cm2 register. table 7.8.1 lists a specification overview of the oscillation stop and re-oscillation detect function. table 7.8.1. specification overview of oscillation stop and re-oscillation detect function item specification oscillation stop detectable clock and f(x in ) 2 mhz frequency bandwidth enabling condition for oscillation stop, set the cm20 bit to 1 (enable) re-oscillation detection function operation at oscillation stop, ? reset occurs (when the cm27 bit is set to "0") re-oscillation detection ? oscillation stop, re-oscillation detection interrupt occurs(when the cm27 bit is set to "1")
7. clock generation circuit page 52 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 7.8.1 operation when the cm27 bit is set to "0" (oscillation stop detection reset) when main clock stop is detected when the cm20 bit is 1 (oscillation stop, re-oscillation detection function enabled), the microcomputer is initialized, coming to a halt (oscillation stop reset; refer to 4. sfr , 5. reset ). this status is reset with hardware reset 1 or hardware reset 2. also, even when re-oscillation is detected, the microcomputer can be initialized and stopped; it is, however, necessary to avoid such usage. (during main clock stop, do not set the cm20 bit to 1 and the cm27 bit to 0 .) 7.8.2 operation when the cm27 bit is set to "1" (oscillation stop and re-oscillation detect interrupt) when the main clock corresponds to the cpu clock source and the cm20 bit is 1 (oscillation stop and re-oscillation detect function enabled), the system is placed in the following state if the main clock comes to a halt: ? oscillation stop and re-oscillation detect interrupt request occurs. ? the on-chip oscillator starts oscillation, and the on-chip oscillator clock becomes the cpu clock and clock source for peripheral functions in place of the main clock. ? cm21 bit is set to "1" (on-chip oscillator clock for cpu clock source) ? cm22 bit is set to "1" (main clock stop detected) ? cm23 bit is set to "1" (main clock stopped) when the pll clock corresponds to the cpu clock source and the cm20 bit is 1 , the system is placed in the following state if the main clock comes to a halt: since the cm21 bit remains unchanged, set it to 1 (on-chip oscillator clock) inside the interrupt routine. ? oscillation stop and re-oscillation detect interrupt request occurs. ? cm22 bit is set to "1" (main clock stop detected) ? cm23 bit is set to "1" (main clock stopped) ? cm21 bit remains unchanged when the cm20 bit is 1 , the system is placed in the following state if the main clock re-oscillates from the stop condition: ? oscillation stop and re-oscillation detect interrupt request occurs. ? cm22 bit is set to "1" (main clock re-oscillation detected) ? cm23 bit is set to "0" (main clock oscillation) ? cm21 bit remains unchanged
7. clock generation circuit page 53 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 7.8.3 how to use oscillation stop and re-oscillation detect function ? the oscillation stop and re-oscillation detect interrupt shares the vector with the watchdog timer inter- rupt. if the oscillation stop, re-oscillation detection and watchdog timer interrupts both are used, read the cm22 bit in an interrupt routine to determine which interrupt source is requesting the interrupt. ? where the main clock re-oscillated after oscillation stop, return the main clock to the cpu clock and peripheral function clock source in the program. figure 7.8.3.1 shows the procedure for switching the clock source from the on-chip oscillator to the main clock. ? simultaneously with oscillation stop, re-oscillation detection interrupt occurrence, the cm22 bit be- comes 1 . when the cm22 bit is set at 1 , oscillation stop, re-oscillation detection interrupt are dis- abled. by setting the cm22 bit to 0 in the program, oscillation stop, re-oscillation detection interrupt are enabled. ? if the main clock stops during low speed mode where the cm20 bit is 1 , an oscillation stop, re-oscilla- tion detection interrupt request is generated. at the same time, the on-chip oscillator starts oscillating. in this case, although the cpu clock is derived from the sub clock as it was before the interrupt oc- curred, the peripheral function clocks now are derived from the on-chip oscillator clock. ? to enter wait mode while using the oscillation stop, re-oscillation detection function, set the cm02 bit to 0 (peripheral function clocks not turned off during wait mode). ? since the oscillation stop, re-oscillation detection function is provided in preparation for main clock stop due to external factors, set the cm20 bit to 0 (oscillation stop, re-oscillation detection function dis- abled) where the main clock is stopped or oscillated in the program, that is where the stop mode is selected or the cm05 bit is altered. ? this function cannot be used if the main clock frequency is 2 mhz or less. in that case, set the cm20 bit to 0 . figure 7.8.3.1. procedure to switch clock source from on-chip oscillator to main clock main clock switch inspect the cm23 bit do this check a number of times set the cm22 bit to 0 (main clock stop, re-oscillation not detected). set the cm21 bit to 0 (main clock for the cpu clock source)(note) 1(main clock stop) 0(main clock oscillation) the main clock is confirmed to be active a number of times. all of cm21-23 are the cm2 register bits end note: if the clock source for cpu clock is to be changed to pll clock, set to pll operation mode after set to high-speed mode.
8. protection page 54 ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r 8. protection note the m16c/26t do not use the prc3 bit in the prcr register. in the event that a program runs out of control, this function protects the important registers so that they will not be rewritten easily. figure 8.1 shows the prcr register. the following lists the registers protected by the prcr register. ? registers protected by prc0 bit: cm0, cm1, cm2, plc0, rocr and pclkr registers ? registers protected by prc1 bit: pm0, pm1, pm2, tb2sc, invc0 and invc1 registers ? registers protected by prc2 bit: pd9, pacr and nddr registers ? registers protected by prc3 bit: vcr2 and d4int registers set the prc2 bit to 1 (write enabled) and then write to any address, and the prc2 bit will be cleared to 0 (write protected). the registers protected by the prc2 bit should be changed in the next instruction after setting the prc2 bit to 1 . make sure no interrupts or dma transfers will occur between the instruction in which the prc2 bit is set to 1 and the next instruction. the prc0, prc1 and prc3 bits are not automati- cally cleared to 0 by writing to any address. they can only be cleared in a program. protect register symbol address after reset prcr 000a 16 xx000000 2 bit name bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 : write protected 1 : write enabled prc1 prc0 prc2 function rw note: the prc2 bit is set to "0" by writing to any address after setting it to "1". other bits are not set to "0" by writing to any address, and must therefore be set in a program. 0 rw rw rw nothing is assigned. when write, set to "0". when read, its content is indeterminate. reserved bit must set to "0" rw protect bit 0 protect bit 1 protect bit 2 enable write to cm0, cm1, cm2, rocr, plc0 and pclkr registers 0 : write protected 1 : write enabled enable write to pm0, pm1, pm2, tb2sc, invc0 and invc1 registers 0 : write protected 1 : write enabled enable write to pd9, pacr and nddr registers prc3 rw protect bit 3 0 : write protected 1 : write enabled enable write to vcr2 and d4int registers (b5-b4) (b7-b6) 0 figure 8.1. prcr register
9. interrupt page 55 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m ? maskable interrupt: an interrupt which can be enabled (disabled) by the interrupt enable flag (i flag) or whose interrupt priority can be changed by priority level. ? non-maskable interrupt: an interrupt which cannot be enabled (disabled) by the interrupt enable flag (i flag) or whose interrupt priority cannot be changed by priority level. figure 9.1.1. interrupts interrupt ? ? ? ? ? ? ? ? ? ? ? software (non-maskable interrupt) hardware ? ? ? ? ? ? ? ? special (non-maskable interrupt) peripheral function (note 1) (maskable interrupt) ? ? ? ? ? undefined instruction (und instruction) overflow (into instruction) brk instruction int instruction ? ? ? ? ? ? ? ? ? _______ nmi ________ dbc (note 2) watchdog timer oscillation stop and re-oscillation detection voltage down detection single step (note 2) address match note 1: peripheral function interrupts are generated by the microcomputer's internal functions. note 2: do not normally use this interrupt because it is provided exclusively for use by development support tools. 9. interrupt note m16c/26a(42-pin version) do not use uart0 transmission interrupt and uart0 reception interrupt of peripheral function. m16c/26t do not use voltage down detection interrupt. 9.1 type of interrupts figure 9.1.1 shows types of interrupts.
9. interrupt page 56 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 9.1.1 software interrupts a software interrupt occurs when executing certain instructions. software interrupts are non-maskable interrupts. 9.1.1.1 undefined instruction interrupt an undefined instruction interrupt occurs when executing the und instruction. 9.1.1.2 overflow interrupt an overflow interrupt occurs when executing the into instruction with the o flag set to 1 (the opera- tion resulted in an overflow). the following are instructions whose o flag changes by arithmetic: abs, adc, adcf, add, cmp, div, divu, divx, neg, rmpa, sbb, sha, sub 9.1.1.3 brk interrupt a brk interrupt occurs when executing the brk instruction. 9.1.1.4 int instruction interrupt an int instruction interrupt occurs when executing the int instruction. software interrupt nos. 0 to 63 can be specified for the int instruction. because software interrupt nos. 4, 8 to 31 are assigned to peripheral function interrupts, the same interrupt routine as for peripheral function interrupts can be executed by executing the int instruction. in software interrupt nos. 0 to 31, the u flag is saved to the stack during instruction execution and is cleared to 0 (isp selected) before executing an interrupt sequence. the u flag is restored from the stack when returning from the interrupt routine. in software interrupt nos. 32 to 63, the u flag does not change state during instruction execution, and the sp then selected is used.
9. interrupt page 57 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 9.1.2 hardware interrupts hardware interrupts are classified into two types special interrupts and peripheral function interrupts. 9.1.2.1 special interrupts special interrupts are non-maskable interrupts. _______ 9.1.2.1.1 nmi interrupt _______ _______ an nmi interrupt is generated when input on the nmi pin changes state from high to low. for details _______ _______ about the nmi interrupt, refer to the section 9.7 nmi interrupt . ________ 9.1.2.1.2 dbc interrupt this interrupt is exclusively for debugger, do not use in any other circumstances. 9.1.2.1.3 watchdog timer interrupt generated by the watchdog timer. once a watchdog timer interrupt is generated, be sure to initialize the watchdog timer. for details about the watchdog timer, refer to the section 10. watchdog timer . 9.1.2.1.4 oscillation stop and re-oscillation detection interrupt generated by the oscillation stop and re-oscillation detection function. for details about the oscilla- tion stop and re-oscillation detection function, refer to the section 7. clock generating circuit . 9.1.2.1.5 voltage down detection interrupt generated by the voltage detection circuit. for details about the voltage detection circuit, refer to the section 5.5 voltage detection circuit . 9.1.2.1.6 single-step interrupt do not normally use this interrupt because it is provided exclusively for use by development support tools. 9.1.2.1.7 address match interrupt an address match interrupt is generated immediately before executing the instruction at the address indicated by the rmad0 or rmad1 register, if the corresponding enable bit (the aier0 or aier1 bit in the aier register) is set to 1 . for details about the address match interrupt, refer to the section 9.9 address match interrupt . 9.1.2.2 peripheral function interrupts peripheral function interrupts are maskable interrupts and generated by the microcomputer's internal functions. the interrupt sources for peripheral function interrupts are listed in table 9.2.2.1 relocatable vector tables . for details about the peripheral functions, refer to the description of each peripheral function in this manual.
9. interrupt page 58 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m interrupt source vector table addresses remarks reference address (l) to address (h) undefined instruction fffdc 16 to fffdf 16 interrupt on und instruction m16c/60, m16c/20 overflow fffe0 16 to fffe3 16 interrupt on into instruction serise software brk instruction fffe4 16 to fffe7 16 maual address match fffe8 16 to fffeb 16 address match interrupt single step (note1) fffec 16 to fffef 16 watchdog timer ffff0 16 to ffff3 16 watchdog timer oscillation stop and re-oscillation detection clock generating circuit voltage down detection voltage detection circuit ________ dbc (note1) ffff4 16 to ffff7 16 _______ nmi ffff8 16 to ffffb 16 _______ nmi interrupt reset (note 2) ffffc 16 to fffff 16 reset note 1: do not normally use this interrupt because it is provided exclusively for use by development support tools. note 2: the b3 to b0 in address 0fffff 16 are reserve bits. set these bits to 1111 2 . figure 9.2.1. interrupt vector aaaaaaaaa aaaaaaaaa mid address aaaaaaaaa aaaaaaaaa low address aaaaaaaaa aaaaaaaaa 0 0 0 0 high address aaaaaaaaa aaaaaaaaa 0 0 0 0 0 0 0 0 vector address (l) lsb msb vector address (h) 9.2 interrupts and interrupt vector one interrupt vector consists of 4 bytes. set the start address of each interrupt routine in the respective interrupt vectors. when an interrupt request is accepted, the cpu branches to the address set in the corresponding interrupt vector. figure 9.2.1 shows the interrupt vector. table 9.2.1.1. fixed vector tables if the contents of address fffe7 16 is ff 16 , program ex- ecution starts from the address shown by the vector in the relocatable vector table. 9.2.1 fixed vector tables the fixed vector tables are allocated to the addresses from fffdc 16 to fffff 16 . table 9.2.1.1 lists the fixed vector tables. in the flash memory version of microcomputer, the vector addresses (h) of fixed vectors are used by the id code check function. for details, refer to the section 17.3 flash memory rewrite disabling function .
9. interrupt page 59 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m table 9.2.2.1. relocatable vector tables software interrupt number reference note 1: address relative to address in intb. note 2: set the ifsr6 and ifsr7 bits in the ifsr register. note 3: during i 2 c bus mode, nack and ack interrupts comprise the interrupt source. note 4: these interrupts cannot be disabled using the i flag. note 5: bus collision detection : during iebus mode, this bus collision detection constitutes the cause of an interrupt. during i 2 c bus mode, however, a start condition or a stop condition detection constitutes the cause of an interrupt. vector address (note 1) address (l) to address (h) 0 11 12 13 14 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 63 to 10 15 16 5 to 7 8 4 9 1 to 3 interrupt source brk instruction int3 int4 int5 (note 2) (note 2) dma0 dma1 key input interrupt a/d uart0 transmit uart0 receive uart1 transmit uart1 receive timer a0 timer a1 timer a2 timer a3 timer a4 timer b0 timer b1 timer b2 int0 int1 int2 software interrupt uart 2 bus collision detection uart2 transmit, nack2 (note 3) uart2 receive, ack2 (note 3) m16c/60, m16c/20 series software manual int interrupt int interrupt serial i/o dmac key input interrupt a/d convertor serial i/o timer int interrupt m16c/60, m16c/20 series software manual (note 4) (reserved) +0 to +3 (0000 16 to 0003 16 ) +44 to +47 (002c 16 to 002f 16 ) +48 to +51 (0030 16 to 0033 16 ) +52 to +55 (0034 16 to 0037 16 ) +56 to +59 (0038 16 to 003b 16 ) +68 to +71 (0044 16 to 0047 16 ) +72 to +75 (0048 16 to 004b 16 ) +76 to +79 (004c 16 to 004f 16 ) +80 to +83 (0050 16 to 0053 16 ) +84 to +87 (0054 16 to 0057 16 ) +88 to +91 (0058 16 to 005b 16 ) +92 to +95 (005c 16 to 005f 16 ) +96 to +99 (0060 16 to 0063 16 ) +100 to +103 (0064 16 to 0067 16 ) +104 to +107 (0068 16 to 006b 16 ) +108 to +111 (006c 16 to 006f 16 ) +112 to +115 (0070 16 to 0073 16 ) +116 to +119 (0074 16 to 0077 16 ) +120 to +123 (0078 16 to 007b 16 ) +124 to +127 (007c 16 to 007f 16 ) +128 to +131 (0080 16 to 0083 16 ) +252 to +255 (00fc 16 to 00ff 16 ) +40 to +43 (0028 16 to 002b 16 ) +60 to +63 (003c 16 to 003f 16 ) +64 to +67 (0040 16 to 0043 16 ) +32 to +35 (0020 16 to 0023 16 ) +16 to +19 (0010 16 to 0013 16 ) +36 to +39 (0024 16 to 0027 16 ) to (note 4) (note 5) (reserved) 9.2.2 relocatable vector tables the 256 bytes beginning with the start address set in the intb register comprise a reloacatable vector table area. table 9.2.2.1 lists the relocatable vector tables. setting an even address in the intb register results in the interrupt sequence being executed faster than in the case of odd addresses.
9. interrupt page 60 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 9.3 interrupt control the following describes how to enable/disable the maskable interrupts, and how to set the priority in which order they are accepted. what is explained here does not apply to nonmaskable interrupts. use the i flag in the flg register, ipl, and the ilvl2 to ilvl0 bits in the each interrupt control register to enable/disable the maskable interrupts. whether an interrupt is requested is indicated by the ir bit in each interrupt control register. figure 9.3.1 shows the interrupt control registers. figure 9.3.2 shows the ifsr, ifsr2a registers.
9. interrupt page 61 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 9.3.1. interrupt control registers symbol address after reset int3ic 0044 16 xx00x000 2 int5ic 0048 16 xx00x000 2 int4ic 0049 16 xx00x000 2 int0ic to int2ic 005d 16 to 005f 16 xx00x000 2 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a aa ilvl0 ir pol no functions are assigned. when writing to these bits, write 0 . the values in these bits when read are indeterminate. interrupt priority level select bit interrupt request bit polarity select bit reserved bit 0: interrupt not requested 1: interrupt requested 0 : selects falling edge (notes 3, 4) 1 : selects rising edge must always be set to 0 ilvl1 ilvl2 note 1: this bit can only be reset by writing 0 (do not write 1 ). note 2: to rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. for details, see the precautions for interrupts of the usage notes reference book. note 3: if the ifsri bit (i = 0 to 5) in the ifsr register is 1 (both edges), set the pol bit in the intiic register to 0 (falling edge). (note 1) interrupt control register (note 2) b7 b6 b5 b4 b3 b2 b1 b0 a a aa aa a a aa aa bit name function bit symbol rw symbol address after reset bcnic 004a 16 xxxxx000 2 dm0ic, dm1ic 004b 16 , 004c 16 xxxxx000 2 kupic 004d 16 xxxxx000 2 adic 004e 16 xxxxx000 2 s0tic to s2tic 0051 16 , 0053 16 , 004f 16 xxxxx000 2 s0ric to s2ric 0052 16 , 0054 16 , 0050 16 xxxxx000 2 ta0ic to ta4ic 0055 16 to 0059 16 xxxxx000 2 tb0ic to tb2ic 005a 16 to 005c 16 xxxxx000 2 ilvl0 ir interrupt priority level select bit interrupt request bit 0 : interrupt not requested 1 : interrupt requested ilvl1 ilvl2 no functions are assigned. when writing to these bits, write 0 . the values in these bits when read are indeterminate. (note 1) note 1: this bit can only be reset by writing 0 (do not write 1 ). note 2: to rewrite the interrupt control registers, do so at a point that does not generate the interrupt request for that register. for details, see the precautions for interrupts of the usage notes reference book. 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 0 rw rw rw rw (b7-b4) rw rw rw rw rw rw rw rw (b7-b6) (b5)
9. interrupt page 62 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 9.3.2. ifsr register and ifsr2a register interrupt request cause select register bit name function bit symbol rw symbol address after reset ifsr 035f 16 00 16 ifsr0 b7 b6 b5 b4 b3 b2 b1 b0 aa aa a a aa aa a a int0 interrupt polarity switching bit 0 : reserved 1 : int4 0 : reserved 1 : int5 0 : one edge 1 : both edges 0 : one edge 1 : both edges 0 : one edge 1 : both edges 0 : one edge 1 : both edges 0 : one edge 1 : both edges int1 interrupt polarity switching bit int2 interrupt polarity switching bit int3 interrupt polarity switching bit int4 interrupt polarity switching bit int5 interrupt polarity switching bit 0 : one edge 1 : both edges interrupt request cause select bit interrupt request cause select bit ifsr1 ifsr2 ifsr3 ifsr4 ifsr5 ifsr6 ifsr7 rw rw rw rw rw rw rw rw (note 1) (note 1) (note 1) (note 1) (note 1) (note 1) note 1: when setting this bit to 1 (= both edges), make sure the pol bit in the int0ic to int5ic register is set to 0 (= falling edge). interrupt request cause select register 2 bit name function bit symbol rw symbol address after reset ifsr2a 035e 16 xxxxxxx0 2 b7 b6 b5 b4 b3 b2 b1 b0 aa aa a a aa aa aa aa must be set to 1 . (b7-b1) nothing is assigned. when write, set to 0 . when read, their contents are indeterminate. ifsr20 1 reserved bit rw (note 1) note 1: set this bit to "1" before you enable interrupt after resetting.
9. interrupt page 63 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 9.3.1 i flag the i flag enables or disables the maskable interrupt. setting the i flag to 1 (= enabled) enables the maskable interrupt. setting the i flag to 0 (= disabled) disables all maskable interrupts. 9.3.2 ir bit the ir bit is set to 1 (= interrupt requested) when an interrupt request is generated. then, when the interrupt request is accepted and the cpu branches to the corresponding interrupt vector, the ir bit is cleared to 0 (= interrupt not requested). the ir bit can be cleared to 0 in a program. note that do not write 1 to this bit. 9.3.3 ilvl2 to ilvl0 bits and ipl interrupt priority levels can be set using the ilvl2 to ilvl0 bits. table 9.3.3.1 shows the settings of interrupt priority levels and table 9.3.3.2 shows the interrupt priority levels enabled by the ipl. the following are conditions under which an interrupt is accepted: i flag is set to 1 ir bit is set to 1 interrupt priority level > ipl the i flag, ir bit, ilvl2 to ilvl0 bits and ipl are independent of each other. in no case do they affect one another. table 9.3.3.2. interrupt priority levels enabled by ipl table 9.3.3.1. settings of interrupt priority levels ilvl2 to ilvl0 bits interrupt priority level priority order 000 2 001 2 010 2 011 2 100 2 101 2 110 2 111 2 level 0 (interrupt disabled) level 1 level 2 level 3 level 4 level 5 level 6 level 7 low high enabled interrupt priority levels interrupt levels 1 and above are enabled interrupt levels 2 and above are enabled interrupt levels 3 and above are enabled interrupt levels 4 and above are enabled interrupt levels 5 and above are enabled interrupt levels 6 and above are enabled interrupt levels 7 and above are enabled all maskable interrupts are disabled ipl 000 2 001 2 010 2 011 2 100 2 101 2 110 2 111 2
9. interrupt page 64 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 9.4 interrupt sequence an interrupt sequence (the devicebehavior from the instant an interrupt is accepted to the instant the inter- rupt routine is executed) is described here. if an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. if an interrupt occurs during execution of either the smovb, smovf, sstr or rmpa instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. the cpu behavior during the interrupt sequence is described below. figure 9.4.1 shows time required for executing the interrupt sequence. (1) the cpu gets interrupt information (interrupt number and interrupt request priority level) by reading the address 00000 16 . then it clears the ir bit for the corresponding interrupt to 0 (interrupt not requested). (2) the flg register immediately before entering the interrupt sequence is saved to the cpu s internal temporary register (note) . (3) the i, d and u flags in the flg register become as follows: the i flag is cleared to 0 (interrupts disabled). the d flag is cleared to 0 (single-step interrupt disabled). the u flag is cleared to 0 (isp selected). however, the u flag does not change state if an int instruction for software interrupt nos. 32 to 63 is executed. (4) the cpu s internal temporary register (note) is saved to the stack. (5) the pc is saved to the stack. (6) the interrupt priority level of the accepted interrupt is set in the ipl. (7) the start address of the relevant interrupt routine set in the interrupt vector is stored in the pc. after the interrupt sequence is completed, the processor resumes executing instructions from the start address of the interrupt routine. note: this register cannot be used by user. indeterminate (1) 123456789 1011 12 13 14 15 16 17 18 indeterminate (1) sp-2 contents sp-4 contents vec contents vec+2 contents interrupt information address 0000 16 indeterminate (1) sp-2 sp-4 vec vec+2 pc cpu clock address bus data bus wr (2) rd (2) notes: 1. the indeterminate state depends on the instruction queue buffer. a read cycle occurs when the instruction queue buffer is ready to accept instructions. 2. rd is the internal signal which is set to l when the internal memory is read out and wr is the internal signal which is set to l when the internal memory is written. figure 9.4.1. time required for executing interrupt sequence
9. interrupt page 65 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m interrupt sources 7 level that is set to ipl _______ watchdog timer, nmi, oscillation stop and re-oscillation detection, voltage down detection _________ software, address match, dbc, single-step not changed 9.4.2 variation of ipl when interrupt request is accepted when a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the ipl. when a software interrupt or special interrupt request is accepted, one of the interrupt priority levels listed in table 9.4.2.1 is set in the ipl. shown in table 9.4.2.1 are the ipl values of software and special interrupts when they are accepted. table 9.4.2.1. ipl level that is set to ipl when a software or special interrupt is accepted instruction interrupt sequence instruction in interrupt routine time interrupt response time (a) (b) interrupt request acknowledged interrupt request generated (a) the time from when an interrupt request is generated till when the instruction then executing is completed. the length of this time varies with the instruction being executed. the divx instruction requires the longest time, which is equal to 30 cycles (without wait state, the divisor being a register). (b) the time during which the interrupt sequence is executed. for details, see the table below. note, however, that the values in this table must be increased 2 cycles for the dbc interrupt and 1 cycle for the address match and single-step interrupts. interrupt vector address even even odd odd sp value even odd even odd without wait 18 cycles 19 cycles 19 cycles 20 cycles figure 9.4.1.1. interrupt response time 9.4.1 interrupt response time figure 9.4.1.1 shows the interrupt response time. the interrupt response or interrupt acknowledge time denotes the time from when an interrupt request is generated till when the first instruction in the interrupt routine is executed. specifically, it consists of the time from when an interrupt request is generated till when the instruction then executing is completed ((a) in figure 9.4.1.1) and the time during which the interrupt sequence is executed ((b) in figure 9.4.1.1).
9. interrupt page 66 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 9.4.3 saving registers in the interrupt sequence, the flg register and pc are saved to the stack. at this time, the 4 high-order bits of the pc and the 4 high-order (ipl) and 8 low-order bits in the flg register, 16 bits in total, are saved to the stack first. next, the 16 low-order bits of the pc are saved. figure 9.4.3.1 shows the stack status before and after an interrupt request is accepted. the other necessary registers must be saved in a program at the beginning of the interrupt routine. use the pushm instruction, and all registers except sp can be saved with a single instruction. address content of previous stack stack [sp] sp value before interrupt request is accepted. m m C 1 m C 2 m C 3 m C 4 stack status before interrupt request is acknowledged stack status after interrupt request is acknowledged content of previous stack m + 1 msb lsb m m C 1 m C 2 m C 3 m C 4 address flg l content of previous stack stack flg h pc h [sp] new sp value content of previous stack m + 1 msb lsb pc l pc m figure 9.4.3.1. stack status before and after acceptance of interrupt request
9. interrupt page 67 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 9.4.3.2. operation of saving register (2) sp contains odd number [sp] (odd) [sp] C 1 (even) [sp] C 2(odd) [sp] C 3 (even) [sp] C 4(odd) [sp] C 5 (even) address sequence in which order registers are saved (2) (1) finished saving registers in four operations. (3) (4) (1) sp contains even number [sp] (even) [sp] C 1(odd) [sp] C 2 (even) [sp] C 3(odd) [sp] C 4 (even) [sp] C 5 (odd) note: [sp] denotes the initial value of the sp when interrupt request is acknowledged. after registers are saved, the sp content is [sp] minus 4. address pc m stack flg l pc l sequence in which order registers are saved (2) saved simultaneously, all 16 bits (1) saved simultaneously, all 16 bits finished saving registers in two operations. pc m stack flg l pc l saved, 8 bits at a time flg h pc h flg h pc h the operation of saving registers carried out in the interrupt sequence is dependent on whether the sp (note) , at the time of acceptance of an interrupt request, is even or odd. if the stack pointer (note) is even, the flg register and the pc are saved, 16 bits at a time. if odd, they are saved in two steps, 8 bits at a time. figure 9.4.3.2 shows the operation of the saving registers. note: when any int instruction in software numbers 32 to 63 has been executed, this is the sp indicated by the u flag. otherwise, it is the isp.
9. interrupt page 68 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 9.5 interrupt priority if two or more interrupt requests are generated while executing one instruction, the interrupt request that has the highest priority is accepted. for maskable interrupts (peripheral functions), any desired priority level can be selected using the ilvl2 to ilvl0 bits. however, if two or more maskable interrupts have the same priority level, their interrupt priority is resolved by hardware, with the highest priority interrupt accepted. the watchdog timer and other special interrupts have their priority levels set in hardware. figure 9.5.1 shows the priorities of hardware interrupts. software interrupts are not affected by the interrupt priority. if an instruction is executed, control branches invariably to the interrupt routine. 9.4.4 returning from an interrupt routine the flg register and pc in the state in which they were immediately before entering the interrupt se- quence are restored from the stack by executing the reit instruction at the end of the interrupt routine. thereafter the cpu returns to the program which was being executed before accepting the interrupt request. return the other registers saved by a program within the interrupt routine using the popm or similar instruction before executing the reit instruction. 9.5.1 interrupt priority resolution circuit the interrupt priority resolution circuit is used to select the interrupt with the highest priority among those requested. figure 9.5.1.1 shows the circuit that judges the interrupt priority level. figure 9.5.1. hardware interrupt priority reset watchdog timer, oscillation stop and re-oscillation detection, voltage down detection peripheral function single step address match high low nmi dbc
9. interrupt page 69 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 9.5.1.1. interrupts priority select circuit timer b2 timer b0 timer a3 timer a1 timer b1 timer a4 timer a2 uart1 reception uart0 reception uart2 reception, ack2 a/d conversion dma1 uart 2 bus collision timer a0 uart1 transmission uart0 transmission uart2 transmission, nack2 key input interrupt dma0 ipl i flag int1 int2 int0 watchdog timer dbc nmi interrupt request accepted level 0 (initial value) priority level of each interrupt highest lowest priority of peripheral function interrupts (if priority levels are same) int3 int5 int4 address match interrupt request level resolution output to clock generating circuit (fig.7.1.) oscillation stop and re-oscillation detection voltage down detection
9. interrupt page 70 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m ______ 9.6 int interrupt _______ inti interrupt (i=0 to 5) is triggered by the edges of external inputs. the edge polarity is selected using the ifsri bit in the ifsr register. ________ ________ ________ to use the int4 interrupt, set the ifsr6 bit in the ifsr register to "1" (=int4). to use the int5 interrupt, set ________ the ifsr7 bit in the ifsr register to "1" (=int5). after modifiying the ifsr6 or ifsr7 bit, clear the corresponding ir bit to "0" (=interrupt not requested) before enabling the interrupt. ________ the int5 input has an effective digital debounce function for a noize rejection. refer to 16.6 digital debounce function for this detail. figure 9.6.1 shows the ifsr register. figure 9.6.1. ifsr register interrupt request cause select register bit name function bit symbol rw symbol address after reset ifsr 035f 16 00 16 ifsr0 b7 b6 b5 b4 b3 b2 b1 b0 aa aa a a aa aa a a int0 interrupt polarity switching bit 0 : reserved 1 : int4 0 : reserved 1 : int5 0 : one edge 1 : both edges 0 : one edge 1 : both edges 0 : one edge 1 : both edges 0 : one edge 1 : both edges 0 : one edge 1 : both edges int1 interrupt polarity switching bit int2 interrupt polarity switching bit int3 interrupt polarity switching bit int4 interrupt polarity switching bit int5 interrupt polarity switching bit 0 : one edge 1 : both edges interrupt request cause select bit interrupt request cause select bit ifsr1 ifsr2 ifsr3 ifsr4 ifsr5 ifsr6 ifsr7 rw rw rw rw rw rw rw rw (note 1) (note 1) (note 1) (note 1) (note 1) (note 1) note 1: when setting this bit to 1 (= both edges), make sure the pol bit in the int0ic to int5ic register is set to 0 (= falling edge).
9. interrupt page 71 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m interrupt control circuit kupic register key input interrupt request ki 3 ki 2 ki 1 ki 0 pu25 bit jouif pd10 register pd10_7 bit jouif pd10 register pull-up transistor pd10_7 bit jouif pd10 register pd10_6 bit jouif pd10 register pd10_5 bit jouif pd10 register pd10_4 bit jouif pd10 register pull-up transistor pull-up transistor pull-up transistor figure 9.8.1. key input interrupt ______ 9.7 nmi interrupt _______ _______ an nmi interrupt request is generated when input on the nmi pin changes state from high to low, after the _______ ______ nmi interrupt was enabled by writing a ??to pm24 bit in the pm2 register. the nmi interrupt is a non- maskable interrupt, once it is enabled. _______ the input level of this nmi interrupt input pin can be read by accessing the p8_5 bit in the p8 register. _______ nmi is disabled by default after reset (the pin is a gpio pin, p8 5 ) and can be enabled using pm24 bit in the pm2 register. once enabled, it can only be disabled by a reset signal. _______ the nmi input has an effective digital debounce function for a noise rejection. refer to 16.6 digital debounce function for this detail. 9.8 key input interrupt of p10 4 to p10 7 , a key input interrupt is generated when input on any of the p10 4 to p10 7 pins which has had the pd10_4 to pd10_7 bits in the pd10 register set to ??(= input) goes low. key input interrupts can be used as a key-on wakeup function, the function which gets the microcomputer out of wait or stop mode. however, if you intend to use the key input interrupt, do not use p10 4 to p10 7 as analog input ports. figure 9.8.1 shows the block diagram of the key input interrupt. note, however, that while input on any pin which has had the pd10_4 to pd10_7 bits set to ??(= input mode) is pulled low, inputs on all other pins of the port are not detected as interrupts.
9. interrupt page 72 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m table 9.9.2. relationship between address match interrupt sources and associated registers address match interrupt sources address match interrupt enable bit address match interrupt register address match interrupt 0 aier0 rmad0 address match interrupt 1 aier1 rmad1 9.9 address match interrupt an address match interrupt request is generated immediately before executing the instruction at the ad- dress indicated by the rmadi register (i=0 to 1). set the start address of any instruction in the rmadi register. use the aier register s aier0 and aier1 bits to enable or disable the interrupt. note that the address match interrupt is unaffected by the i flag and ipl. for address match interrupts, the value of the pc that is saved to the stack area varies depending on the instruction being executed (refer to saving registers ). (the value of the pc that is saved to the stack area is not the correct return address.) therefore, follow one of the methods described below to return from the address match interrupt. ? rewrite the content of the stack and then use the reit instruction to return. ? restore the stack to its previous state before the interrupt request was accepted by using the pop or similar other instruction and then use a jump instruction to return. table 9.9.1 shows the value of the pc that is saved to the stack area when an address match interrupt request is accepted. figure 9.9.1 shows the aier, rmad0 and rmad1 registers. ? 16-bit op-code instruction ? instruction shown below among 8-bit operation code instructions add.b:s #imm8,dest sub.b:s #imm8,dest and.b:s #imm8,dest or.b:s #imm8,dest mov.b:s #imm8,dest stz.b:s #imm8,dest stnz.b:s #imm8,dest stzx.b:s #imm81,#imm82,dest cmp.b:s #imm8,dest pushm src popm dest jmps #imm8 jsrs #imm8 mov.b:s #imm,dest (however, dest=a0 or a1) instructions other than the above instruction at the address indicated by the rmadi register value of the pc that is saved to the stack area the address indicated by the rmadi register +2 the address indicated by the rmadi register +1 value of the pc that is saved to the stack area : refer to saving registers . table 9.9.1. value of the pc that is saved to the stack area when an address match interrupt request is accepted.
9. interrupt page 73 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m bit name bit symbol symbol address after reset aier 0009 16 xxxxxx00 2 address match interrupt enable register function rw aaaaaaaaaaaaaa a aaaaaaaaaaaa a aaaaaaaaaaaaaa aaaaaaaaaaaaaa a aaaaaaaaaaaa a aaaaaaaaaaaaaa address match interrupt 0 enable bit 0 : interrupt disabled 1 : interrupt enabled aier0 address match interrupt 1 enable bit aier1 symbol address after reset rmad0 0012 16 to 0010 16 x00000 16 rmad1 0016 16 to 0014 16 x00000 16 b7 b6 b5 b4 b3 b2 b1 b0 address setting register for address match interrupt function setting range address match interrupt register i (i = 0 to 1) 00000 16 to fffff 16 0 : interrupt disabled 1 : interrupt enabled b0 b7 b0 b3 (b19) (b16) b7 b0 (b15) (b8) b7 (b23) rw rw (b7-b2) rw rw nothing is assigned. when write, set to 0 . when read, their contents are indeterminate. nothing is assigned. when write, set to 0 . when read, their contents are indeterminate. figure 9.9.1. aier register, rmad0 and rmad1 registers
10. watchdog timer page 74 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 10. watchdog timer the watchdog timer is the function of detecting when the program is out of control. therefore, we recom- mend using the watchdog timer to improve reliability of a system. the watchdog timer contains a 15-bit counter which counts down the clock derived by dividing the cpu clock using the prescaler. whether to generate a watchdog timer interrupt request or apply a watchdog timer reset as an operation to be per- formed when the watchdog timer underflows after reaching the terminal count can be selected using the pm12 bit in the pm1 register. the pm12 bit can only be set to 1 (reset). once this bit is set to 1 , it cannot be set to 0 (watchdog timer interrupt) in a program. refer to 5.3 watchdog timer reset for the details of watchdog timer reset. when the main clock source is selected for cpu clock, on-chip oscillator clock, pll clock, the wdc7 bit value in the wdc register for prescaler can be chosen to be 16 or 128. if a sub-clock is selected for cpu clock, the prescaler is always 2 no matter how the wdc7 bit is set. the period of watchdog timer can be calculated as given below. the period of watchdog timer is, however, subject to an error due to the prescaler. for example, when cpu clock = 16 mhz and the divide-by-n value for the prescaler= 16, the watchdog timer period is approx. 32.8 ms. the watchdog timer is initialized by writing to the wdts register. the prescaler is initialized after reset. note that the watchdog timer and the prescaler both are inactive after reset, so that the watchdog timer is activated to start counting by writing to the wdts register. in stop mode, wait mode and when erase/program opration is excuting in ew1 mode without erase sus- pend requeired, the watchdog timer and prescaler are stopped. counting is resumed from the held value when the modes or state are released. figure 10.1 shows the block diagram of the watchdog timer. figure 10.2 shows the watchdog timer-related registers. with main clock source chosen for cpu clock, on-chip oscillator clock, pll clock watchdog timer period = with sub-clock chosen for cpu clock watchdog timer period = prescaler dividing (16 or 128) x watchdog timer count (32768) cpu clock prescaler dividing (2) x watchdog timer count (32768) cpu clock figure 10.1. watchdog timer block diagram cpu clock write to wdts register reset pm12 = 0 watchdog timer set to 7fff 16 1/128 1/16 cm07 = 0 wdc7 = 1 cm07 = 0 wdc7 = 0 cm07 = 1 1/2 prescaler pm12 = 1 watchdog timer interrupt request reset pm22 = 0 pm22 = 1 on-chip oscillator clock
10. watchdog timer page 75 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 10.1 count source protective mode in this mode, a on-chip oscillator clock is used for the watchdog timer count source. the watchdog timer can be kept being clocked even when cpu clock stops as a result of run-away. before this mode can be used, the following register settings are required: (1) set the prc1 bit in the prcr register to ??(enable writes to pm1 and pm2 registers). (2) set the pm12 bit in the pm1 register to ??(reset when the watchdog timer underflows). (3) set the pm22 bit in the pm2 register to ??(on-chip oscillator clock used for the watchdog timer count source). (4) set the prc1 bit in the prcr register to ??(disable writes to pm1 and pm2 registers). (5) write to the wdts register (watchdog timer starts counting). setting the pm22 bit to ??results in the following conditions ?the on-chip oscillator starts oscillating, and the in-chip oscillator clock becomes the watchdog timer count source. ?the cm10 bit in the cm1 register is disabled against write. (writing a ??has no effect, nor is stop mode entered.) ?the watchdog timer does not stop when in wait mode. figure 10.2 wdc register and wdts register watchdog timer start register (note) symbol address after reset wdts 000e 16 indeterminate wo b7 b0 function the watchdog timer is initialized and starts counting after a write instruction to this register. the watchdog timer value is always initialized to 7fff 16 regardless of whatever value is written. rw note : write to the wdts register after the watchdog timer interrupt occurs. watchdog timer control register symbol address after reset wdc 000f 16 00xxxxxx 2 (note 2) function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 high-order bit of watchdog timer wdc7 bit name prescaler select bit 0 : divided by 16 1 : divided by 128 reserved bit must set to 0 0 ro rw rw rw cold start / warm start discrimination flag (note 1,2,3) 0 : cold start 1 : warm start wdc5 note 1: writing to the wdc register causes the wdc5 bit to be set to 1 (warm start). *guifwpmubhfbqqmjfeup7dd jtmfttuibo7 fjuifsxsjufupuijtsfhjtufsxifouif$16d mpdlgsfrvfodzjt.)[psxsjufuxjdf /puf5if8%$cjujttfuup dpmetubsu
xifoqpxfsjtu vsofepoboedbocftfuupczqsphsbnpomz note 3: do not use in m16c/26t. (b4-b0) (b6) watchdog timer period = watchdog timer count (32768) on-chip oscillator clock
10. watchdog timer page 76 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 10.3 typical operation of cold start / warm start 10.2 cold start / warm start the m16c/26t does not use this function. the wdc5 flag in the wdc register indicates the last reset by power on (cold start) or by reset signal (warm start). the wdc5 flag is set "0" at power on, and is set "1" at writing any data to the wdc register. the flag is not set to "0" by the software reset and the input of reset signal. figure 0.3 shows the operation of cold start/ warm start. 1 is held even if reset becomes 0 v. t2 program start t1 pch transistor on (about 4v) cpu reset exited set to 1 by program becomes 0 on the rising edge of vcc t > 100 sec. 5v 0v 5v 0v 1 0 vcc reset reset sequence wdc5 flag notes: 1. the timing of which wdc5 is set is affected by how the reset signal rises (time lag between t1 and t2). note
11. dmac page 77 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m a a a a a a aa aa aa aa a a aa aa aa aa aa aa aa aa aa data bus low-order bits (ec-01-um60) dma latch high-order bits dma latch low-order bits dma0 source pointer sar0(20) dma0 destination pointer dar0 (20) dma0 forward address pointer (20) (note) data bus high-order bits a a a a a a a aaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaa aaaaaaa aaaaaaa address bus a a a a a a a a dma1 destination pointer dar1 (20) dma1 source pointer sar1 (20) dma1 forward address pointer (20) (note) a a dma0 transfer counter reload register tcr0 (16) dma0 transfer counter tcr0 (16) dma1 transfer counter reload register tcr1 (16) dma1 transfer counter tcr1 (16) a a a a (addresses 0029 16 , 0028 16 ) (addresses 0039 16 , 0038 16 ) (addresses 0022 16 to 0020 16 ) (addresses 0026 16 to 0024 16 ) (addresses 0032 16 to 0030 16 ) (addresses 0036 16 to 0034 16 ) note: pointer is incremented by a dma request. a a a a a a a a a a a a a a a a a a a a aa aa aa a a a a 11. dmac note the m16c/26a(42-pin version) do not use uart0 transfer and uart0 reception interrupt request as a dma reqest. the dmac (direct memory access controller) allows data to be transferred without the cpu intervention. two dmac channels are included. each time a dma request occurs, the dmac transfers one (8 or 16-bit) data from the source address to the destination address. the dmac uses the same data bus as used by the cpu. because the dmac has higher priority of bus control than the cpu and because it makes use of a cycle steal method, it can transfer one word (16 bits) or one byte (8 bits) of data within a very short time after a dma request is generated. figure 11.1 shows the block diagram of the dmac. table 11.1 shows the dmac specifications. figures 11.2 to 11.4 show the dmac-related registers. a dma request is generated by a write to the dsr bit in the dmisl register (i = 0,1), as well as by an interrupt request which is generated by any function specified by the dms and dsel3 to dsel0 bits in the dmisl register. however, unlike in the case of interrupt requests, dma requests are not affected by the i flag and the interrupt control register, so that even when interrupt requests are disabled and no interrupt request can be accepted, dma requests are always accepted. furthermore, because the dmac does not affect interrupts, the ir bit in the interrupt control register does not change state due to a dma transfer. a data transfer is initiated each time a dma request is generated when the dmae bit in the dmicon register is set to 1 (dma enabled). however, if the cycle in which a dma request is generated is faster than the dma transfer cycle, the number of transfer requests generated and the number of times data is transferred may not match. for details, refer to 11.4 dma requests . figure 11.1 dmac block diagram
11. dmac page 78 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m table 11.1 dmac specifications item specification no. of channels 2 (cycle steal method) transfer memory space ? from any address in the 1m bytes space to a fixed address ? from a fixed address to any address in the 1m bytes space ? from a fixed address to a fixed address maximum no. of bytes transferred 128k bytes (with 16-bit transfers) or 64k bytes (with 8-bit transfers) dma request factors ________ ________ falling edge of int0 or int1 (note 1, note 2) ________ ________ both edge of int0 or int1 timer a0 to timer a4 interrupt requests timer b0 to timer b2 interrupt requests uart0 transfer, uart0 reception interrupt requests uart1 transfer, uart1 reception interrupt requests uart2 transfer, uart2 reception interrupt requests a/d conversion interrupt requests software triggers channel priority dma0 > dma1 (dma0 takes precedence) transfer unit 8 bits or 16 bits transfer address direction forward or fixed (the source and destination addresses cannot both be in the forward direction.) transfer mode single transfer transfer is completed when the dmai transfer counter (i = 0,1) underflows after reaching the terminal count. repeat transfer when the dmai transfer counter underflows, it is reloaded with the value of the dmai transfer counter reload register and a dma transfer is con tinued with it. dma interrupt request generation timing when the dmai transfer counter underflowed dma startup data transfer is initiated each time a dma request is generated when the dmae bit in the dmaicon register is set to 1 (enabled). dma shutdown single transfer ? when the dmae bit is set to 0 (disabled) ? after the dmai transfer counter underflows repeat transfer when the dmae bit is set to 0 (disabled) when a data transfer is started after setting the dmae bit to 1 (en abled), the forward address pointer is reloaded with the value of the sari or the dari pointer whichever is specified to be in the forward direction and the dmai transfer counter is reloaded with the value of the dmai transfer counter reload register. notes: 1. dma transfer is not effective to any interrupt. dma transfer is affected neither by the i flag nor by the interrupt control register. 2. the selectable causes of dma requests differ with each channel. 3. make sure that no dmac-related registers (addresses 0020 16 to 003f 16 ) are accessed by the dmac.
11. dmac page 79 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 11.2 dm0sl register dma0 request cause select register symbol address after reset dm0sl 03b8 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 dma request cause select bit dsel0 rw dsel1 dsel2 dsel3 nothing is assigned. when write, set to 0 . when read, its content is 0 . software dma request bit a dma request is generated by setting this bit to 1 when the dms bit is 0 (basic cause) and the dsel3 to dsel0 bits are 0001 2 (software trigger). the value of this bit when read is 0 . dsr dsel3 to dsel0 dms=0(basic cause of request) dms=1(extended cause of request) 0 0 0 0 2 falling edge of int0 pin C 0 0 0 1 2 software trigger C 0 0 1 0 2 timer a0 C 0 0 1 1 2 timer a1 C 0 1 0 0 2 timer a2 C 0 1 0 1 2 timer a3 C 0 1 1 0 2 timer a4 two edges of int0 pin 0 1 1 1 2 timer b0 C 1 0 0 0 2 timer b1 C 1 0 0 1 2 timer b2 C 1 0 1 0 2 uart0 transmit C 1 0 1 1 2 uart0 receive C 1 1 0 0 2 uart2 transmit C 1 1 0 1 2 uart2 receive C 1 1 1 0 2 a/d conversion C 1 1 1 1 2 uart1 transmit C bit name dma request cause expansion select bit dms 0: basic cause of request 1: extended cause of request rw rw rw rw rw rw (b5-b4) refer to note note: the causes of dma0 requests can be selected by a combination of dms bit and dsel3 to dsel0 bits in the manner described below.
11. dmac page 80 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 11.3 dm1sl register, dm0con register, and dm1con register dmai control register (i=0,1) symbol address after reset dm0con 002c 16 00000x00 2 dm1con 003c 16 00000x00 2 bit name function bit symbol transfer unit bit select bit b7 b6 b5 b4 b3 b2 b1 b0 0 : 16 bits 1 : 8 bits dmbit dmasl dmas dmae repeat transfer mode select bit 0 : single transfer 1 : repeat transfer dma request bit 0 : dma not requested 1 : dma requested 0 : disabled 1 : enabled 0 : fixed 1 : forward dma enable bit source address direction select bit (note 2) destination address direction select bit (note 2) 0 : fixed 1 : forward dsd dad nothing is assigned. when write, set to 0 . when read, its content is 0 . note 1: the dmas bit can be set to 0 by writing 0 in a program (this bit remains unchanged even if 1 is written). note 2: at least one of the dad and dsd bits must be 0 (address direction fixed). (note 1) dma1 request cause select register symbol address after reset dm1sl 03ba 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 dma request cause select bit dsel0 rw dsel1 dsel2 dsel3 software dma request bit dsr dsel3 to dsel0 dms=0(basic cause of request) dms=1(extended cause of request) 0 0 0 0 2 falling edge of int1 pin C 0 0 0 1 2 software trigger C 0 0 1 0 2 timer a0 C 0 0 1 1 2 timer a1 C 0 1 0 0 2 timer a2 C 0 1 0 1 2 timer a3 C 0 1 1 0 2 timer a4 C 0 1 1 1 2 timer b0 two edges of int1 1 0 0 0 2 timer b1 C 1 0 0 1 2 timer b2 C 1 0 1 0 2 uart0 transmit C 1 0 1 1 2 uart0 receive C 1 1 0 0 2 uart2 transmit C 1 1 0 1 2 uart2 receive/ack2 C 1 1 1 0 2 a/d conversion C 1 1 1 1 2 uart1 receive C bit name dma request cause expansion select bit dms rw rw rw rw rw rw (b5-b4) rw rw rw rw rw rw rw (b7-b6) note: the causes of dma1 requests can be selected by a combination of dms bit and dsel3 to dsel0 bits in the manner described below. nothing is assigned. when write, set to 0 . when read, its content is 0 . a dma request is generated by setting this bit to 1 when the dms bit is 0 (basic cause) and the dsel3 to dsel0 bits are 0001 2 (software trigger). the value of this bit when read is 0 . 0: basic cause of request 1: extended cause of request refer to note
11. dmac page 81 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 11.4 sar0 and sar1, dar0 and dar1, tcr0 and tcr1 registers (ec-03-um60) b7 b0 b7 b0 (b8) (b15) function set the transfer count minus 1. the written value is stored in the dmai transfer counter reload register, and when the dmae bit in the dmicon register is set to ?? (dma enabled) or the dmai transfer counter underflows when the dmasl bit in the dmicon register is ??(repeat transfer), the value of the dmai transfer counter reload register is transferred to the dmai transfer counter. when read, the dmai transfer counter is read. symbol address after reset tcr0 0029 16 , 0028 16 indeterminate tcr1 0039 16 , 0038 16 indeterminate dmai transfer counter (i = 0, 1) setting range 0000 16 to ffff 16 b7 (b23) b3 b0 b7 b0 b7 b0 (b8) (b16)(b15) (b19) function rw set the source address of transfer symbol address after reset sar0 0022 16 to 0020 16 indeterminate sar1 0032 16 to 0030 16 indeterminate dmai source pointer (i = 0, 1) (note) setting range 00000 16 to fffff 16 nothing is assigned. when write, set ?? when read, these contents are ?? symbol address after reset dar0 0026 16 to 0024 16 indeterminate dar1 0036 16 to 0034 16 indeterminate b3 b0 b7 b0 b7 b0 (b8) (b15) (b16) (b19) function set the destination address of transfer dmai destination pointer (i = 0, 1)(note) setting range 00000 16 to fffff 16 b7 (b23) rw rw rw rw rw note: if the dsd bit in the dmicon register is ??(fixed), this register can only be written to when the dmae bit in the dmicon register is 0 (dma disabled). if the dsd bit is set to 1 (forward direction), this register can be written to at any time. if the dsd bit is set to 1 and the dmae bit is 1 (dma enabled), the dmai forward address pointer can be read from this register. otherwise, the value written to it can be read. nothing is assigned. when write, set 0 . when read, these contents are 0 . note: if the dad bit in the dmicon register is 0 (fixed), this register can only be written to when the dmae bit in the dmicon register is 0 (dma disabled). if the dad bit is set to 1 (forward direction), this register can be written to at any time. if the dad bit is set to 1 and the dmae bit is 1 (dma enabled), the dmai forward address pointer can be read from this register. otherwise, the value written to it can be read.
11. dmac page 82 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 11.1 transfer cycles the transfer cycle consists of a memory or sfr read (source read) bus cycle and a write (destination write) bus cycle. the number of read and write bus cycles is affected by the source and destination addresses of transfer. furthermore, the bus cycle itself is extended by a software wait. 11.1.1 effect of source and destination addresses if the transfer unit is 16 bits and the source address of transfer begins with an odd address, the source read cycle consists of one more bus cycle than when the source address of transfer begins with an even address. similarly, if the transfer unit is 16 bits and the destination address of transfer begins with an odd address, the destination write cycle consists of one more bus cycle than when the destination address of transfer begins with an even address. 11.1.2 effect of software wait for memory or sfr accesses in which one or more software wait states are inserted, the number of bus cycles required for that access increases by an amount equal to software wait states. figure 11.1.1 shows the example of the cycles for a source read. for convenience, the destination write cycle is shown as one cycle and the source read cycles for the different conditions are shown. in reality, the destination write cycle is subject to the same conditions as the source read cycle, with the transfer cycle changing accordingly. when calculating transfer cycles, take into consideration each condition for the source read and the destination write cycle, respectively. for example, when data is transferred in 16 bit units and when both the source address and destination address are an odd address ((2) in figure 11.1.1), two source read bus cycles and two destination write bus cycles are required.
11. dmac page 83 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 11.1.1 transfer cycles for source read cpu clock address bus rd signal wr signal data bus cpu use cpu use cpu use cpu use source source destination destination dummy cycle dummy cycle (1) when the transfer unit is 8 or 16 bits and the source of transfer is an even address address bus rd signal wr signal data bus cpu use cpu use cpu use cpu use source source destination destination dummy cycle dummy cycle (3) when the source read cycle under condition (1) has one wait state inserted address bus rd signal wr signal data bus cpu use cpu use cpu use cpu use source source destination destination dummy cycle dummy cycle source + 1 source + 1 (2) when the transfer unit is 16 bits and the source address of transfer is an odd address address bus rd signal wr signal data bus cpu use cpu use cpu use cpu use source source destination destination dummy cycle dummy cycle source + 1 source + 1 (4) when the source read cycle under condition (2) has one wait state inserted note: the same timing changes occur with the respective conditions at the destination as at the source. cpu clock cpu clock cpu clock
11. dmac page 84 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 11.2. dma transfer cycles any combination of even or odd transfer read and write adresses is possible. table 11.2.1 shows the number of dma transfer cycles. table 11.2.2 shows the coefficient j, k. the number of dmac transfer cycles can be calculated as follows: no. of transfer cycles per transfer unit = no. of read cycles x j + no. of write cycles x k table 11.2.1 dma transfer cycles table 11.2.2 coefficient j, k transfer unit access address no. of read cycles no. of write cycles 8-bit transfers even 1 1 (dmbit= 1 ) odd 1 1 16-bit transfers even 1 1 (dmbit= 0 ) odd 2 2 internal area internal rom, ram sfr no wait with wait 1 1 2 2 2 2 j k 1 wait 2 wait 3 3 (note) (note) note: depends on the set value of pm20 bit in pm2 register.
11. dmac page 85 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 11.3 dma enable when a data transfer starts after setting the dmae bit in dmicon register (i = 0, 1) to 1 (enabled), the dmac operates as follows: (1) reload the forward address pointer with the sari register value when the dsd bit in the dmicon register is 1 (forward) or the dari register value when the dad bit in the dmicon register is 1 (forward). (2) reload the dmai transfer counter with the dmai transfer counter reload register value. if the dmae bit is set to 1 again while it remains set, the dmac performs the above operation. however, if a dma request may occur simultaneously when the dmae bit is being written, follow the steps below. step 1: write 1 to the dmae bit and dmas bit in dmicon register simultaneously. step 2: make sure that the dmai is in an initial state as described above (1) and (2) in a program. if the dmai is not in an initial state, the above steps should be repeated. 11.4 dma request the dmac can generate a dma request as triggered by the cause of request that is selected with the dms and dsel3 to dsel0 bits in the dmisl register (i = 0, 1) on either channel. table 11.4.1 shows the timing at which the dmas bit changes state. whenever a dma request is generated, the dmas bit is set to 1 (dma requested) regardless of whether or not the dmae bit is set. if the dmae bit was set to 1 (enabled) when this occurred, the dmas bit is set to 0 (dma not requested) immediately before a data transfer starts. this bit cannot be set to 1 in a program (it can only be set to 0 ). the dmas bit may be set to 1 when the dms or the dsel3 to dsel0 bits change state. therefore, always be sure to set the dmas bit to 0 after changing the dms or the dsel3 to dsel0 bits. because if the dmae bit is 1 , a data transfer starts immediately after a dma request is generated, the dmas bit in almost all cases is 0 when read in a program. read the dmae bit to determine whether the dmac is enabled. table 11.4.1 timing at which the dmas bit changes state dma factor software trigger peripheral function timing at which the bit is set to 1 timing at which the bit is set to 0 dmas bit in the dmicon register when the dsr bit in the dmisl register is set to 1 when the interrupt control register for the peripheral function that is selected by the dsel3 to dsel0 and dms bits in the dmisl register has its ir bit set to 1 ? immediately before a data transfer starts ? when set by writing 0 in a program
11. dmac page 86 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 11.5 channel priority and dma transfer timing if both dma0 and dma1 are enabled and dma transfer request signals from dma0 and dma1 are de- tected active in the same sampling period (one period from a falling edge to the next falling edge of cpu clock), the dmas bit on each channel is set to 1 (dma requested) at the same time. in this case, the dma requests are arbitrated according to the channel priority, dma0 > dma1. the following describes dmac operation when dma0 and dma1 requests are detected active in the same sampling period. figure 11.5.1 shows an example of dma transfer effected by external factors. dma0 request having priority is received first to start a transfer when a dma0 request and dma1 request are generated simultanelously. after one dma0 transfer is completed, a bus arbitration is returned to the cpu. when the cpu has completed one bus access, a dma1 transfer starts. after one dma1 transfer is completed, the bus arbitration is again returned to the cpu. in addition, dma requsts cannot be counted up since each channel has one dmas bit. therefore, when dma requests, as dma1 in figure 11.5.1, occurs more than one time, the dams bit is set to "0" as soon as getting the bus arbitration. the bus arbitration is returned to the cpu when one transfer is completed. figure 11.5.1 dma transfer by external factors aaaa aaaa dma0 aaaa aaaa dma1 dma0 request bit dma1 request bit aaa aaaaa aa aa aaaaa aa aa cpu int0 int1 obtainment of the bus right an example where dma requests for external causes are detected active at the same cpu clock
12. timer page 87 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m ? timer mode ? one-shot timer mode ? pulse width measuring (pwm) mode ? timer mode ? one-shot timer mode ? pwm mode ? timer mode ? one-shot timer mode ? pwm mode ? timer mode ? one-shot timer mode ? pwm mode ? timer mode ? one-shot timer mode ? pwm mode ? event counter mode ? event counter mode ? event counter mode ? event counter mode ? event counter mode ta0 in ta1 in ta2 in ta3 in ta4 in timer a0 timer a1 timer a2 timer a3 timer a4 f 8 f 32 f c32 timer a0 interrupt timer a1 interrupt timer a2 interrupt timer a3 interrupt timer a4 interrupt noise filter noise filter noise filter noise filter noise filter 1/32 f c32 1/8 1/4 f 1 or f 2 f 8 f 32 ? main clock ? pll clock ? on-chip oscillator clock x cin set the cpsr bit jouif cpsrf register to 1 (= prescaler reset) reset clock prescaler timer b2 overflow or underflow 1/2 f 1 f 2 pclk0 bit = 0 pclk0 bit = 1 f 1 or f 2 figure 12.1. timer a configuration 12. timer note the m16c/26a (42-pin version) do not include tb2in pin. do not use the function which needs this pin. eight 16-bit timers, each capable of operating independently of the others, can be classified by function as either timer a (five) and timer b (three). the count source for each timer acts as a clock, to control such timer operations as counting, reloading, etc. figures 12.1 and 12.2 show block diagrams of timer a and timer b configuration, respectively.
12. timer page 88 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 12.2. timer b configuration ? event counter mode ? event counter mode ? event counter mode ? timer mode ? pulse width measuring mode, pulse period measuring mode ? timer mode ? pulse width measuring mode, pulse period measuring mode ? timer mode ? pulse width measuring mode, pulse period measuring mode tb0 in tb1 in tb2 in timer b0 timer b1 timer b2 f 8 f 32 f c32 timer b0 interrupt noise filter noise filter noise filter 1/32 f c32 x cin reset clock prescaler timer b2 overflow or underflow ( to timer a count source) timer b1 interrupt timer b2 interrupt 1/8 1/4 f 8 f 32 1/2 f 1 or f 2 ? main clock ? pll clock ? on-chip oscillator clock set the cpsr bit jouif cpsrf register to 1 (= prescaler reset) f 1 f 2 pclk0 bit = 0 pclk0 bit = 1 f 1 or f 2
12. timer page 89 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 12.1 timer a figure 12.1.1 shows a block diagram of the timer a. figures 12.1.2 to 12.1.4 show registers related to the timer a. the timer a supports the following four modes. except in event counter mode, timers a0 to a4 all have the same function. use the tmod1 to tmod0 bits in the taimr register (i = 0 to 4) to select the desired mode. ? timer mode: the timer counts an internal count source. ? event counter mode: the timer counts pulses from an external device or overflows and underflows of other timers. ? one-shot timer mode: the timer outputs a pulse only once before it reaches the minimum count 0000 16 . ? pulse width modulation (pwm) mode: the timer outputs pulses in a given width successively. figure 12.1.2. ta0mr to ta4mr registers tabsr register up-count/down-count tai addresses taj tak timer a0 0387 16 - 0386 16 timer a4 timer a1 timer a1 0389 16 - 0388 16 timer a0 timer a2 timer a2 038b 16 - 038a 16 timer a1 timer a3 timer a3 038d 16 - 038c 16 timer a2 timer a4 timer a4 038f 16 - 038e 16 timer a3 timer a0 always counts down except in event counter mode reload register counter low-order 8 bits aaaa high-order 8 bits clock source selection ? timer (gate function) ? timer ? one shot ? pwm f 1 or f 2 f 8 f 32 tai in (i = 0 to 4) tb2 overflow ? event counter f c32 clock selection taj overflow (j = i C 1. note, however, that j = 4 when i = 0) pulse output toggle flip-flop tai out (i = 0 to 4) data bus low-order bits data bus high-order bits a a udf register down count tak overflow (k = i + 1. note, however, that k = 0 when i = 4) polarity selection to external trigger circuit (note) (note) note: overflow or underflow clock selection timer ai mode register (i=0 to 4) symbol address after reset ta0mr to ta4mr 0396 16 to 039a 16 00 16 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 0 0 : timer mode 0 1 : event counter mode 1 0 : one-shot timer mode 1 1 : pulse width modulation (pwm) mode b1 b0 tck1 mr3 mr2 mr1 tmod1 mr0 tmod0 tck0 function varies with each operation mode count source select bit operation mode select bit rw rw rw rw rw rw rw rw function varies with each operation mode figure 12.1.1. timer a block diagram
12. timer page 90 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 12.1.3. ta0 to ta4 registers, tabsr register, and udf register symbol address after reset ta0 0387 16 , 0386 16 indeterminate ta1 0389 16 , 0388 16 indeterminate ta2 038b 16 , 038a 16 indeterminate ta3 038d 16 , 038c 16 indeterminate ta4 038f 16 , 038e 16 indeterminate b7 b0 b7 b0 (b15) (b8) timer ai register (i= 0 to 4) (note 1) rw divide the count source by n + 1 where n = set value function setting range divide the count source by ffff 16 C n + 1 where n = set value when counting up or by n + 1 when counting down divide the count source by n where n = set value and cause the timer to stop modify the pulse width as follows: pwm period: (2 16 C 1) / fj high level pwm pulse width: n / fj where n = set value, fj = count source frequency 0000 16 to fffe 16 (note 3, 4) note 1: the register must be accessed in 16 bit units. note 2: if the tai register is set to 0000 16 , the counter does not work and timer ai interrupt requests are not generated either. furthermore, if pulse output is selected, no pulses are output from the taiout pin. note 3: if the tai register is set to 0000 16 , the pulse width modulator does not work, the output level on the taiout pin remains low, and timer ai interrupt requests are not generated either. the same applies when the 8 high-order bits of the timer tai register are set to 001 6 while operating as an 8-bit pulse width modulator. note 4: use the mov instruction to write to the tai register. note 5: the timer counts pulses from an external device or overflows or underflows in other timers. 00 16 to fe 16 (high-order address) 00 16 to ff 16 (low-order address) timer a4 up/down flag timer a3 up/down flag timer a2 up/down flag timer a1 up/down flag timer a0 up/down flag timer a2 two-phase pulse signal processing select bit timer a3 two-phase pulse signal processing select bit timer a4 two-phase pulse signal processing select bit symbol address after reset udf 0384 16 00 16 ta4p ta3p ta2p up/down flag (note 1) bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 ta4ud ta3ud ta2ud ta1ud ta0ud 0 : down count 1 : up count enabled by setting the taimr register s mr2 bit to 0 (= switching source in udf register) during event counter mode. 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing enabled symbol address after reset tabsr 0380 16 00 16 count start flag bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 aaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaaaaaaaaaaaa timer b2 count start flag timer b1 count start flag timer b0 count start flag timer a4 count start flag timer a3 count start flag timer a2 count start flag timer a1 count start flag timer a0 count start flag 0 : stops counting 1 : starts counting tb2s tb1s tb0s ta4s ta3s ta2s ta1s ta0s note 1: use mov instruction to write to this register. note 2: make sure the port direction bits for the ta2 in to ta4i n and ta2 out to ta4 out pins are set to 0 (input mode). note 3: when not using the two-phase pulse signal processing function, set the corresponding bit to 0 . rw rw wo wo wo rw rw rw rw rw rw rw rw rw rw rw rw rw rw wo wo wo timer mode event counter mode one-shot timer mode pulse width modulation mode (16-bit pwm) pulse width modulation mode (8-bit pwm) 0000 16 to ffff 16 0000 16 to ffff 16 0000 16 to ffff 16 (notes 2, 4) mode modify the pulse width as follows: pwm period: (2 8 C 1) x (m + 1)/ fj high level pwm pulse width: (m + 1)n / fj where n = high-order address set value, m = low-order address set value, fj = count source frequency (note 3, 4) (notes 2, 3) (note 5)
12. timer page 91 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m symbol address after reset cpsrf 0381 16 0xxxxxxx 2 clock prescaler reset flag bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 clock prescaler reset flag setting this bit to ??initializes the prescaler for the timekeeping clock. (when read, its content is ??) cpsr nothing is assigned. when write, set to ?? when read, their contents are indeterminate. ta1tgl symbol address after reset trgsr 0383 16 00 16 timer a1 event/trigger select bit 0 0 : input on ta1 in is selected (note 1) 0 1 : tb2 overflow is selected 1 0 : ta0 overflow is selected 1 1 : ta2 overflow is selected trigger select register bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 : input on ta2 in is selected (note 1) 0 1 : tb2 overflow is selected 1 0 : ta1 overflow is selected 1 1 : ta3 overflow is selected 0 0 : input on ta3 in is selected (note 1) 0 1 : tb2 overflow is selected 1 0 : ta2 overflow is selected 1 1 : ta4 overflow is selected 0 0 : input on ta4 in is selected (note 1) 0 1 : tb2 overflow is selected 1 0 : ta3 overflow is selected 1 1 : ta0 overflow is selected timer a2 event/trigger select bit timer a3 event/trigger select bit timer a4 event/trigger select bit ta1tgh ta2tgl ta2tgh ta3tgl ta3tgh ta4tgl ta4tgh b1 b0 b3 b2 b5 b4 b7 b6 note 1: make sure the port direction bits for the ta1 in to ta4 in pins are set to ??(= input mode). note 2: overflow or underflow ta1os ta2os ta0os one-shot start flag symbol address after reset onsf 0382 16 00 16 timer a0 one-shot start flag timer a1 one-shot start flag timer a2 one-shot start flag timer a3 one-shot start flag timer a4 one-shot start flag ta3os ta4os bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 ta0tgl ta0tgh 0 0 : input on ta0 in is selected 0 1 : tb2 overflow is selected 1 0 : ta4 overflow is selected 1 1 : ta1 overflow is selected timer a0 event/trigger select bit b7 b6 rw the timer starts counting by setting this bit to ??while the tmod1 to tmod0 bits jouif taimr register (i = 0 to 4) jttfuup 10 2 (= one- shot timer mode) and the mr2 bit jouif taimr register jttfuup 0 (=taios bit enabled). when read, its content is 0 . z-phase input enable bit tazie 0 : z-phase input disabled 1 : z-phase input enabled rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw (b6-b0) (note 2) (note 2) (note 2) note 1: make sure the pd7_1 bit in the pd7 register is set to 0 (= input mode). note 2: overflow or underflow (note 1) (note 2) (note 2) (note 2) (note 2) (note 2) (note 2) (note 2) (note 2) (note 2) (note 2) (note 2) (note 2) figure 12.1.4. onsf register, trgsr register, and cpsrf register
12. timer page 92 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m item specification count source f 1 , f 2 , f 8 , f 32 , f c32 count operation ? down-count ? when the timer underflows, it reloads the reload register contents and continues counting divide ratio 1/(n+1) n: set value of tai register (i= 0 to 4) 0000 16 to ffff 16 count start condition set tais bit in the tabsr register to 1 (= start counting) count stop condition set tais bit to 0 (= stop counting) interrupt request generation timing timer underflow tai in pin function i/o port or gate input tai out pin function i/o port or pulse output read from timer count value can be read by reading tai register write to timer ? when not counting and until the 1st count source is input after counting start value written to tai register is written to both reload register and counter ? when counting (after 1st count source input) value written to tai register is written to only reload register (transferred to counter when reloaded next) select function ? gate function counting can be started and stopped by an input signal to tai in pin ? pulse output function whenever the timer underflows, the output polarity of tai out pin is inverted. when not counting, the pin outputs a low. 12.1.1. timer mode in timer mode, the timer counts a count source generated internally (see table 12.1.1.1). figure 1.2.1.1.1 shows taimr register in timer mode. table 12.1.1.1. specifications in timer mode note 1: the port direction bit for the tai in pin must be set to 0 (= input mode). timer ai mode register (i=0 to 4) symbol address after reset ta0mr to ta4mr 0396 16 to 039a 16 00 16 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 0 : timer mode b1 b0 tmod1 tmod0 mr0 pulse output function select bit 0 : pulse is not output (ta iout pin is a normal port pin) 1 : pulse is output (ta iout pin is a pulse output pin) gate function select bit 0 0 : gate function not available 0 1 : (tai in pin functions as i/o port) 1 0 : counts while input on the tai in pin is low (note 1) 1 1 : counts while input on the tai in pin is high (note 1) b4 b3 mr2 mr1 mr3 must be set to 0 in timer mode 0 0 : f 1 or f 2 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 tck1 tck0 count source select bit 00 0 rw rw rw rw rw rw rw rw } figure 12.1.1.1. timer ai mode register in timer mode
12. timer page 93 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m item specification count source ? external signals input to tai in pin (i=0 to 4) (effective edge can be selected in program) ? timer b2 overflows or underflows, timer aj (j=i-1, except j=4 if i=0) overflows or underflows, timer ak (k=i+1, except k=0 if i=4) overflows or underflows count operation ? up-count or down-count can be selected by external signal or program ? when the timer overflows or underflows, it reloads the reload register con- tents and continues counting. when operating in free-running mode, the timer continues counting without reloading. divided ratio 1/ (ffff 16 - n + 1) for up-count 1/ (n + 1) for down-count n : set value of tai register 0000 16 to ffff 16 count start condition set tais bit in the tabsr register to 1 (= start counting) count stop condition set tais bit to 0 (= stop counting) interrupt request generation timing timer overflow or underflow tai in pin function i/o port or count source input tai out pin function i/o port, pulse output, or up/down-count select input read from timer count value can be read by reading tai register write to timer ? when not counting and until the 1st count source is input after counting start value written to tai register is written to both reload register and counter ? when counting (after 1st count source input) value written to tai register is written to only reload register (transferred to counter when reloaded next) select function ? free-run count function even when the timer overflows or underflows, the reload register content is not reloaded to it ? pulse output function whenever the timer underflows or underflows, the output polarity of tai out pin is inverted . when not counting, the pin outputs a low. 12.1.2. event counter mode in event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers. timers a2, a3 and a4 can count two-phase external signals. table 12.1.2.1 lists specifica- tions in event counter mode (when not processing two-phase pulse signal). table 12.1.2.2 lists specifica- tions in event counter mode (when processing two-phase pulse signal with the timers a2, a3 and a4). figure 12.1.2.1 shows taimr register in event counter mode (when not processing two-phase pulse signal). figure 12.1.2.2 shows ta2mr to ta4mr registers in event counter mode (when processing two- phase pulse signal with the timers a2, a3 and a4). table 12.1.2.1. specifications in event counter mode (when not processing two-phase pulse signal)
12. timer page 94 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m note 1: during event counter mode, the count source can be selected using the onsf and trgsr registers. note 2: effective when the taitgh and taitgl bits in the onsf or trgsr register are ?0 2 ?(tai in pin input). note 3: count down when input on tai out pin is low or count up when input on that pin is high. the port direction bit for tai out pin must be set to ??(= input mode). symbol address after reset ta0mr to ta4mr 0396 16 to 039a 16 00 16 w r b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 1 : event counter mode (note 1) b1 b0 tmod0 mr0 pulse output function select bit 0 : pulse is not output (ta iout pin functions as i/o port) 1 : pulse is output (tai out pin functions as pulse output pin) count polarity select bit (note 2) mr2 mr1 mr3 must be set to ??in event counter mode tck0 count operation type select bit 01 0 0 : counts external signal's falling edge 1 : counts external signal's rising edge up/down switching cause select bit 0 : udf register 1 : input signal to ta iout pin (note 3) 0 : reload type 1 : free-run type bit symbol bit name function rw tck1 can be ??or ??when not using two-phase pulse signal processing tmod1 timer ai mode register (i=0 to 4) (when not using two-phase pulse signal processing) rw rw rw rw rw rw rw rw figure 12.1.2.1. taimr register in event counter mode (when not using two-phase pulse signal processing)
12. timer page 95 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m item specification count source ? two-phase pulse signals input to tai in or tai out pins (i = 2 to 4) count operation ? up-count or down-count can be selected by two-phase pulse signal ? when the timer overflows or underflows, it reloads the reload register con- tents and continues counting. when operating in free-running mode, the timer continues counting without reloading. divide ratio 1/ (ffff 16 - n + 1) for up-count 1/ (n + 1) for down-count n : set value of tai register 0000 16 to ffff 16 count start condition set tais bit in the tabsr register to 1 (= start counting) count stop condition set tais bit to 0 (= stop counting) interrupt request generation timing timer overflow or underflow tai in pin function two-phase pulse input tai out pin function two-phase pulse input read from timer count value can be read by reading timer a2, a3 or a4 register write to timer ? when not counting and until the 1st count source is input after counting start value written to tai register is written to both reload register and counter ? when counting (after 1st count source input) value written to tai register is written to reload register (transferred to counter when reloaded next) select function (note) ? normal processing operation (timer a2 and timer a3) the timer counts up rising edges or counts down falling edges on taj in (j=2,3) pin when input signals on taj out pin is h . ? multiply-by-4 processing operation (timer a3 and timer a4) if the phase relationship is such that tak in (k=3, 4) pin goes h when the input signal on tak out pin is h , the timer counts up rising and falling edges on tak out and tak in pins. if the phase relationship is such that tak in pin goes l when the input signal on tak out pin is h , the timer counts down rising and falling edges on tak out and tak in pins. table 12.1.2.2. specifications in event counter mode (when processing two-phase pulse signal with timers a2, a3 and a4) taj out up- count up- count up- count down- count down- count down- count taj in (j=2,3) tak out tak in (k=3,4) count up all edges count up all edges count down all edges count down all edges ? counter initialization by z-phase input (timer a3) the timer count value is initialized to 0 by z-phase input. notes: 1. only timer a3 is selectable. timer a2 is fixed to normal processing operation, and timer a4 is fixed to multiply-by-4 processing operation.
12. timer page 96 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m note 1: tck1 bit is valid for timer a3 mode register. no matter how this bit is set, timers a2 and a4 always operate in normal processing mode and x4 processing mode, respectively. note 2: if two-phase pulse signal processing is desired, following register settings are required: ?set the taip bit in the udf register to ??(two-phase pulse signal processing function enabled). ?set the taitgh and taitgl bits in the trgsr register to ?0 2 ?(taiin pin input). ?set the p ort direction bits for tai in and tai out to ?? ( in p ut mode ) . timer ai mode register (i=2 to 4) (when using two-phase pulse signal processing) symbol address after reset ta2mr to ta4mr 0398 16 to 039a 16 00 16 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 1 : event counter mode b1 b0 tmod1 tmod0 mr0 to use two-phase pulse signal processing, set this bit to ?? mr2 mr1 mr3 tck1 tck0 01 0 bit name function rw count operation type select bit two-phase pulse signal processing operation select bit (note 1)(note 2) 0 : reload type 1 : free-run type 0 : normal processing operation 1 : multiply-by-4 processing operation 0 0 1 rw rw rw rw rw rw rw rw to use two-phase pulse signal processing, set this bit to ?? to use two-phase pulse signal processing, set this bit to ?? to use two-phase pulse signal processing, set this bit to ?? bit symbol figure 12.1.2.2. ta2mr to ta4mr registers in event counter mode (when using two-phase pulse signal processing with timer a2, a3 or a4)
12. timer page 97 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m mm+11 2 3 4 5 ta3 out (a phase) count source ta3 in (b phase) timer a3 int2 (z phase) (note) input equal to or greater than one clock cycle of count source note: this timing diagram is for the case where the pol bit in the int2ic register is set to 1 (= rising edge). 12.1.2.1 counter initialization by two-phase pulse signal processing this function initializes the timer count value to 0 by z-phase (counter initialization) input during two- phase pulse signal processing. this function can only be used in timer a3 event counter mode during two-phase pulse signal process- _______ ing, free-running type, x4 processing, with z-phase entered from the int2 pin. counter initialization by z-phase input is enabled by writing 0000 16 to the ta3 register and setting the tazie bit in onsf register to 1 (= z-phase input enabled). counter initialization is accomplished by detecting z-phase input edge. the active edge can be cho- sen to be the rising or falling edge by using the pol bit in the int2ic register. the z-phase pulse width _______ applied to the int2 pin must be equal to or greater than one clock cycle of the timer a3 count source. the counter is initialized at the next count timing after recognizing z-phase input. figure 12.1.2.1.1 shows the relationship between the two-phase pulse (a phase and b phase) and the z phase. if timer a3 overflow or underflow coincides with the counter initialization by z-phase input, a timer a3 interrupt request is generated twice in succession. do not use the timer a3 interrupt when using this function. figure 12.1.2.1.1. two-phase pulse (a phase and b phase) and the z phase
12. timer page 98 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m item specification count source f 1 , f 2 , f 8 , f 32 , f c32 count operation ? down-count ? when the counter reaches 0000 16 , it stops counting after reloading a new value ? if a trigger occurs when counting, the timer reloads a new count and restarts counting divide ratio 1/n n : set value of tai register 0000 16 to ffff 16 however, the counter does not work if the divide-by-n value is set to 0000 16 . count start condition tais bit in the tabsr register is set to 1 (start counting) and one of the following triggers occurs. ? external trigger input from the tai in pin ? timer b2 overflow or underflow, timer aj (j=i-1, except j=4 if i=0) overflow or underflow, timer ak (k=i+1, except k=0 if i=4) overflow or underflow ? the taios bit in the onsf register is set to 1 (= timer starts) count stop condition ? when the counter is reloaded after reaching 0000 16 ? tais bit is set to 0 (= stop counting) interrupt request generation timing when the counter reaches 0000 16 tai in pin function i/o port or trigger input tai out pin function i/o port or pulse output read from timer an indeterminate value is read by reading tai register write to timer ? when not counting and until the 1st count source is input after counting start value written to tai register is written to both reload register and counter ? when counting (after 1st count source input) value written to tai register is written to only reload register (transferred to counter when reloaded next) select function ? pulse output function the timer outputs a low when not counting and a high when counting. table 12.1.3.1. specifications in one-shot timer mode 12.1.3. one-shot timer mode in one-shot timer mode, the timer is activated only once by one trigger. (see table 12.1.3.1.) when the trigger occurs, the timer starts up and continues operating for a given period. figure 12.1.3.1 shows the taimr register in one-shot timer mode.
12. timer page 99 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 12.1.3.1. taimr register in one-shot timer mode bit name timer ai mode register (i=0 to 4) symbol address after reset ta0mr to ta4mr 396 16 to 039a 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 1 0 : one-shot timer mode b1 b0 tmod1 tmod0 mr0 pulse output function select bit 0 : pulse is not output (ta iout pin functions as i/o port) 1 : pulse is output (tai out pin functions as a pulse output pin) mr2 mr1 mr3 must be set to 0 in one-shot timer mode 0 0 : f 1 or f 2 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 tck1 tck0 count source select bit 10 0 0 : taios bit is enabled 1 : selected by taitgh to taitgl bits trigger select bit external trigger select bit (note 1) 0 : falling edge of input signal to tai in pin (note 2) 1 : rising edge of input signal to tai in pin (note 2) note 1: effective when the taitgh and taitgl bits in the onsf or trgsr register are 00 2 (tai in pin input). note 2: the port direction bit for the tai in pin must be set to 0 (= input mode). rw rw rw rw rw rw rw rw rw
12. timer page 100 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 12.1.4. pulse width modulation (pwm) mode in pwm mode, the timer outputs pulses of a given width in succession (see table 12.1.4.1). the counter functions as either 16-bit pulse width modulator or 8-bit pulse width modulator. figure 12.1.4.1 shows taimr register in pulse width modulation mode. figures 12.1.4.2 and 12.1.4.3 show examples of how a 16-bit pulse width modulator operates and how an 8-bit pulse width modulator operates. table 12.1.4.1. specifications in pulse width modulation mode item specification count source f 1 , f 2 , f 8 , f 32 , f c32 count operation ? d own-count (operating as an 8-bit or a 16-bit pulse width modulator) ? the timer reloads a new value at a rising edge of pwm pulse and continues counting ? the timer is not affected by a trigger that occurs during counting 16-bit pwm ? high level width n / fj n : set value of tai register (i=o to 4) ? cycle time (2 16 -1) / fj fixed fj: count source frequency (f 1 , f 2 , f 8 , f 32 , f c32 ) 8-bit pwm ? high level width n x (m+1) / fj n : set value of tai register high-order address ? cycle time (2 8 -1) x (m+1) / fj m : set value of tai register low-order address count start condition ? tais bit in thetabsr register is set to 1 (= start counting) ? the tais bit is set to "1" and external trigger input from the tai in pin ? the tais bit is set to "1" and one of the following external triggers occurs timer b2 overflow or underflow, timer aj (j=i-1, except j=4 if i=0) overflow or underflow, timer ak (k=i+1, except k=0 if i=4) overflow or underflow count stop condition tais bit is set to 0 (= stop counting) interrupt request generation timing pwm pulse goes l tai in pin function i/o port or trigger input tai out pin function pulse output read from timer an indeterminate value is read by reading tai register write to timer ? when not counting and until the 1st count source is input after counting start value written to tai register is written to both reload register and counter ? when counting (after 1st count source input) value written to tai register is written to only reload register (transferred to counter when reloaded next)
12. timer page 101 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 12.1.4.1. taimr register in pulse width modulation mode bit name (fb-10-um60) timer ai mode register (i= 0 to 4) symbol address after reset ta0mr to ta4mr 0396 16 to 039a 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 1 1 : pwm mode b1 b0 tmod1 tmod0 mr0 mr2 mr1 mr3 0 0 : f 1 or f 2 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 tck1 tck0 count source select bit rw 11 1 16/8-bit pwm mode select bit 0: functions as a 16-bit pulse width modulator 1: functions as an 8-bit pulse width modulator trigger select bit external trigger select bit (note 1) 0: falling edge of input signal to tai in pin(note 2) 1: rising edge of input signal to tai in pin(note 2) rw rw rw rw rw rw rw rw 0 : write ??to tais bit in the tasf register 1 : selected by taitgh to taitgl bits note 1: effective when the taitgh and taitgl bits in the onsf or trgsr register are ?0 2 ?(tai in pin input). note 2: the port direction bit for the tai in pin must be set to ??(= input mode). 0: pulse is not output(taiout pin functions as i/o port) 1: pulse is output(taiout pin functions as a pulse output pin) pulse output funcion select bit
12. timer page 102 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m count source (note1) input signal to ta iin pin underflow signal of 8-bit prescaler (note2) pwm pulse output from ta iout pin ? ? ? ? ? ? ? ? set to ??upon accepting an interrupt request or by writing in program note 1: the 8-bit prescaler counts the count source. note 2: the 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal. note 3: m = 00 16 to ff 16 ; n = 00 16 to fe 16 . note 4: this timing diagram is for the case where the tai register is set to "0202 16 ", the taitgh and taitgl bits in the onsf or trgsr register is set to "00 2 " (tai in pin input), the mr1 bit in the taimr register is set to "0"(falling edge), and the mr2 bit in the taimr register is set to "1" (trigger selected by taitgh and taitgl bits). aaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaa 1 / f j x (m + 1) x (2 e 1) 8 1 / f j x (m + 1) x n 1 / f j x (m + 1) ir bit in the taiic register f j : frequency of count source (f 1 , f 2 , f 8 , f 32 , f c32 ) i = 0 to 4 figure 12.1.4.2. example of 16-bit pulse width modulator operation figure 12.1.4.3. example of 8-bit pulse width modulator operation 1 / f i x (2 1) 16 count source input signal to ta iin pin pwm pulse output from ta iout pin trigger is not generated by this signal h h l l ir bit in the taiic register 1 0 f j : frequency of count source (f 1 , f 2 , f 8 , f 32 , f c32 ) i = 0 to 4 note 1: n = 0000 16 to fffe 16 . note 2: this timing diagram is for the case where the tai register is set to "0003 16 ", the taitgh and taitgl bits in the onsf or trgsr register is set to "00 2 " (tai in pin input), the mr1 bit in the taimr register is set to "1" (rising edge), and the mr2 bit in the taimr register is set to "1" (trigger selected by taitgh and taitgl bits). 1 / f j x n set to 0 upon accepting an interrupt request or by writing in program
12. timer page 103 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 12.2.1. timer b block diagram clock source selection ? event counter ? timer ? pulse period measuremnet, pulse width measurement reload register low-order 8 bits high-order 8 bits data bus low-order bits data bus high-order bits f 1 or f 2 f 8 f 32 tbj overflow (note) (j = i C 1, except j = 2 if i = 0) can be selected in only event counter mode tabsr register f c32 polarity switching, edge pulse tbi in (i = 0 to 2) counter reset circuit counter tbi address tbj timer b0 0391 16 - 0390 16 timer b2 timer b1 0393 16 - 0392 16 timer b0 timer b2 0395 16 - 0394 16 timer b1 clock selection note: overflow or underflow. 12.2 timer b note the m16c/26a(42-pin version) do not include tb2 in pin of timer b2. [precautions when using timer b2] ? event counter mode the external input signals cannot be counted. set the tck1 bit in the tb2mr register to 1 when using the event count mode. ? pulse period/pulse width measurement mode this mode connot be used. figure 12.2.1 shows a block diagram of the timer b. figures 12.2.2 and 12.2.3 show registers related to the timer b. timer b supports the following four modes. use the tmod1 and tmod0 bits in the tbimr register (i = 0 to 2) to select the desired mode. ? timer mode: the timer counts an internal count source. ? event counter mode: the timer counts pulses from an external device or overflows or underflows of other timers. ? pulse period/pulse width measuring mode: the timer measures an external signal's pulse period or pulse width. ? a/d trigger mode: the timer counts only once before it reaches the minimum count "0000 16 ". used in conjunction with the a/d converter.
12. timer page 104 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m timer bi mode register (i=0 to 2) symbol address after reset tb0mr to tb2mr 039b 16 to 039d 16 00xx0000 2 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 0 0 : timer mode or a/d trigger mode 0 1 : event counter mode 1 0 : pulse period measurement mode, pulse width measurement mode 1 1 : must not be set b1 b0 tck1 mr3 mr2 mr1 tmod1 mr0 tmod0 tck0 function varies with each operation mode count source select bit operation mode select bit (note 1) (note 2) note 1: timer b0. note 2: timer b1, timer b2. rw rw rw rw rw rw rw ro function varies with each operation mode figure 12.2.2. tb0mr to tb2mr registers
12. timer page 105 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m symbol address after reset tabsr 0380 16 00 16 count start flag bit name bit symbol b7 b6 b5 b4 b3 b2 b1 b0 aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa timer b2 count start flag timer b1 count start flag timer b0 count start flag timer a4 count start flag timer a3 count start flag timer a2 count start flag timer a1 count start flag timer a0 count start flag 0 : stops counting 1 : starts counting tb2s tb1s tb0s ta4s ta3s ta2s ta1s ta0s function symbol address after reset tb0 0391 16 , 0390 16 indeterminate tb1 0393 16 , 0392 16 indeterminate tb2 0395 16 , 0394 16 indeterminate b7 b0 b7 b0 (b15) (b8) timer bi register (i=0 to 2)(note 1) rw measures a pulse period or width function rw rw ro rw rw rw rw rw rw rw rw rw note 1: the register must be accessed in 16 bit units. note 2: the timer counts pulses from an external device or overflows or underflows of other timers. note 3: when this mode is used combining delayed trigger mode 0, set the larger value than the value of the timer b0 register to the timer b1 register. divide the count source by n + 1 where n = set value timer mode event counter mode 0000 16 to ffff 16 divide the count source by n + 1 where n = set value (note 2) 0000 16 to ffff 16 pulse period modulation mode, pulse width modulation mode symbol address after reset cpsrf 0381 16 0xxxxxxx 2 clock prescaler reset flag bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa clock prescaler reset flag cpsr nothing is assigned. when write, set to 0 . when read, their contents are indeterminate. rw rw (b6-b0) setting this bit to 1 initializes the prescaler for the timekeeping clock. (when read, the value of this bit is 0 .) mode setting range a/d trigger mode (note 3) divide the count source by n + 1 where n = set value and cause the timer stop rw 0000 16 to ffff 16 figure 12.2.3. tb0 to tb2 registers, tabsr register, cpsrf register
12. timer page 106 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m item specification count source f 1 , f 2 , f 8 , f 32 , f c32 count operation ? down-count ? when the timer underflows, it reloads the reload register contents and continues counting divide ratio 1/(n+1) n: set value of tbi register (i= 0 to 2) 0000 16 to ffff 16 count start condition set tbis bit (1) to 1 (= start counting) count stop condition set tbis bit to 0 (= stop counting) interrupt request generation timing timer underflow tbi in pin function i/o port read from timer count value can be read by reading tbi register write to timer ? when not counting and until the 1st count source is input after counting start value written to tbi register is written to both reload register and counter ? when counting (after 1st count source input) value written to tbi register is written to only reload register (transferred to counter when reloaded next) notes : 1. the tb0s to tb2s bits are assigned to the bit 5 to bit 7 in the tabsr register. 12.2.1 timer mode in timer mode, the timer counts a count source generated internally (see table 12.2.1.1). figure 12.2.1.1 shows tbimr register in timer mode. table 12.2.1.1 specifications in timer mode timer bi mode register (i= 0 to 2) symbol address after reset tb0mr to tb2mr 039b 16 to 039d 16 00xx0000 2 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 aa aa a a operation mode select bit 0 0 : timer mode or a/d trigger mode b1 b0 tmod1 tmod0 mr0 has no effect in timer mode can be set to 0 or 1 mr2 mr1 mr3 0 0 : f 1 or f 2 0 1 : f 8 1 0 : f 32 1 1 : f c32 tck1 tck0 count source select bit 0 0 tb0mr register must be set to 0 in timer mode b7 b6 rw rw rw rw rw rw rw ro tb1mr, tb2mr registers nothing is assigned. when write, set to 0 . when read, its content is indeterminate when write in timer mode, set to 0 . when read in timer mode, its content is indeterminate. figure 12.2.1.1 tbimr register in timer mode
12. timer page 107 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m item specification count source ? external signals input to tbi in pin (i=0 to 2) (effective edge can be selected in program) ? timer bj overflow or underflow (j=i-1, except j=2 if i=0) count operation ? down-count ? when the timer underflows, it reloads the reload register contents and continues counting divide ratio 1/(n+1) n: set value of tbi register 0000 16 to ffff 16 count start condition set tbis bit (1) to 1 (= start counting) count stop condition set tbis bit to 0 (= stop counting) interrupt request generation timing timer underflow tbi in pin function count source input read from timer count value can be read by reading tbi register write to timer ? when not counting and until the 1st count source is input after counting start value written to tbi register is written to both reload register and counter ? when counting (after 1st count source input) value written to tbi register is written to only reload register (transferred to counter when reloaded next) notes : 1. the tb0s to tb2s bits are assigned to the bit 5 to bit 7 in the tabsr register. 12.2.2 event counter mode in event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers (see table 12.2.2.1) . figure 12.2.2.1 shows tbimr register in event counter mode. table 12.2.2.1 specifications in event counter mode figure 12.2.2.1 tbimr register in event counter mode timer bi mode register (i=0 to 2) symbol address after reset tb0mr to tb2mr 039b 16 to 039d 16 00xx0000 2 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 aa operation mode select bit 0 1 : event counter mode b1 b0 tmod1 tmod0 mr0 count polarity select bit (note 1) mr2 mr1 mr3 tck1 tck0 01 0 0 : counts external signal's falling edges 0 1 : counts external signal's rising edges 1 0 : counts external signal's falling and rising edges 1 1 : must not be set b3 b2 note 1: effective when the tck1 bit is set to 0 (input from tbiin pin). if the tck1 bit is set to 1 (tbj overflow or underflow), these bits can be set to 0 or 1 . note 2: the port direction bit for the tbiin pin must be set to 0 (= input mode). has no effect in event counter mode. can be set to 0 or 1 . event clock select 0 : input from tbi in pin (note 2) 1 : tbj overflow or underflow (j = i C 1, except j = 2 if i = 0) rw rw rw rw rw rw rw ro tb0mr register must be set to 0 in timer mode tb1mr, tb2mr registers nothing is assigned. when write, set to 0 . when read, its content is indeterminate. when write in event counter mode, set to 0 . when read in event counter mode, its content is indeterminate.
12. timer page 108 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m item specification count source f 1 , f 2 , f 8 , f 32 , f c32 count operation up-count counter value is transferred to reload register at an effective edge of mea- surement pulse. the counter value is set to ?000 16 ? to continue counting. count start condition set tbis (i=0 to 2) bit (3) to ??(= start counting) count stop condition set tbis bit to ??(= stop counting) interrupt request generation timing ?when an effective edge of measurement pulse is input (1) ?timer overflow. when an overflow occurs, mr3 bit in the tbimr register is set to ??(overflowed) simultaneously. mr3 bit is cleared to ??(no over- flow) by writing to tbimr register at the next count timing or later after mr3 bit was set to ?? at this time, make sure tbis bit is set to ??(start count- ing). tbi in pin function measurement pulse input read from timer contents of the reload register (measurement result) can be read by reading tbi register (2) write to timer value written to tbi register is written to neither reload register nor counter notes: 1. interrupt request is not generated when the first effective edge is input after the timer started counting. 2. value read from tbi register is indeterminate until the second valid edge is input after the timer starts counting. 3. the tb0s to tb2s bits are assigned to the bit 5 to bit 7 in the tabsr register. 12.2.3 pulse period and pulse width measurement mode in pulse period and pulse width measurement mode, the timer measures pulse period or pulse width of an external signal (see table 12.2.3.1). figure 12.2.3.1 shows tbimr register in pulse period and pulse width measurement mode. figure 12.2.3.2 shows the operation timing when measuring a pulse period. figure 12.2.3.3 shows the operation timing when measuring a pulse width. table 12.2.3.1 specifications in pulse period and pulse width measurement mode figure 12.2.3.1 tbimr register in pulse period and pulse width measurement mode timer bi mode register (i=0 to 2) symbol address after reset tb0mr to tb2mr 039b 16 to 039d 16 00xx0000 2 bit name bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 1 0 : pulse period / pulse width measurement mode b1 b0 tmod1 tmod0 mr0 measurement mode select bit mr2 mr1 mr3 tck1 tck0 0 1 0 0 : pulse period measurement (measurement between a falling edge and the next falling edge of measured pulse) 0 1 : pulse period measurement (measurement between a rising edge and the next rising edge of measured pulse) 1 0 : pulse width measurement (measurement between a falling edge and the next rising edge of measured pulse and between a rising edge and the next falling edge) 1 1 : must not be set. function b3 b2 count source select bit timer bi overflow flag ( note) 0 : timer did not overflow 1 : timer has overflowed 0 0 : f 1 or f 2 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 note: this flag is indeterminate after reset. when the tbis bit is set to "1" (start counting), the mr3 bit is cleared to 0 (no overflow) by writing to the tbimr register at the next count timing or later after the mr3 bit was set to 1 (overflowed). the mr3 bit cannot be set to 1 in a program. the tb0s to tb2s bits are assigned to the bit 5 to bit 7 in the tabsr register. rw rw rw rw rw rw rw ro tb0mr register must be set to 0 in pulse period and pulse width measurement mode tb1mr, tb2mr registers nothing is assigned. when write, set to 0 . when read, its content turns out to be indeterminate.
12. timer page 109 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 12.2.3.3 operation timing when measuring a pulse width measurement pulse h count source timing at which counter reaches 0000 16 1 1 transfer (measured value) transfer (measured value) l 0 0 1 0 (note 1) (note 1) (note 1) transfer (measured value) (note 1) (note 2) transfer (indeterminate value) reload register counter transfer timing tbis bit ir bit in the tbiic register mr3 bit in the tbimr register note 1: counter is initialized at completion of measurement. note 2: timer has overflowed. note 3: this timing diagram is for the case where the mr1 to mr0 bits in the tbimr register are 10 2 (measure the interval from a falling edge to the next rising edge and the interval from a rising edge to the next falling edge of the measurement pulse). the tb0s to tb2s bits are assigned to the bit 5 to bit 7 in the tabsr register. set to 0 upon accepting an interrupt request or by writing in program i = 0 to 2 figure 12.2.3.2 operation timing when measuring a pulse period count source measurement pulse tbis bit ir bit in the tbiic register timing at which counter reaches 0000 16 h 1 transfer (indeterminate value) l 0 0 mr3 bit in thetbimr register 1 0 note 1: counter is initialized at completion of measurement. note 2: timer has overflowed. note 3: this timing diagram is for the case where the mr1 to mr0 bits in the tbimr register are 00 2 (measure the interval from falling edge to falling edge of the measurement pulse). (note 1) (note 1) (note 2) transfer (measured value) 1 reload register counter transfer timing the tb0s to tb2s bits are assigned to the bit 5 to bit 7 in the tabsr register. set to 0 upon accepting an interrupt request or by writing in program i = 0 to 2
12. timer page 110 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 12.2.4 a/d trigger mode a/d trigger mode is used as conversion start trigger for a/d converter in simultaneous sample sweep mode of a/d conversion or delayed trigger mode 0. this mode is used as conversion start trigger of a/d converter. a/d trigger mode is used in timer b0 and timer b1. in this mode, the timer is activated only by one trigger. a/d trigger mode is available only for tb0 and tb1. figure 12.2.4.1 shows the tbimr regis- ter in a/d trigger mode and figure 12.2.4.2 shows the tb2sc register. item specification count source f 1 , f 2 , f 8 , f 32 , and f c32 count operation ? down count ? when the timer underflows, reload register contents are reloaded before stopping counting ? when a trigger is generated during the count operation, the count is not affected divide ratio 1/(n+1) n: setting value of tbi register (i=0,1) 0000 16 -ffff 16 count start condition when the tbis (i=0,1) bit in the tabsr register is "1"(count started), tbien (i=0,1) bit in tb2sc register is "1", and the following trigger is generated. (selection based on tb2sel bit in the tb2sc register) ? timer b2 overflow or underflow ? underflow of timer b2 interrupt generation frequency counter setting count stop condition ? after the count value is 0000 16 and reload register contents are reloaded ? set the tbis bit to "0"(count stopped) i nterrupt request timer underflows (1) generation timing tbiin pin function i/o port read from timer count value can be read by reading tbi register write to timer (2) ? when writing in the tbi register during count stopped. value is written to both reload register and counter ? when writing in the tbi register during count. value is written to only reload register (transfered to counter when reloaded next) notes: 1. a/d conversion is started by the timer underflow. for details refer to section 14. a/d converter . 2. when using in delayed trigger mode 0, set the larger value than the value of the timer b0 register to the timer b1 register. table 12.2.4.1 a/d trigger mode specifications
12. timer page 111 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m timer bi mode register (i= 0 to 1) symbol address after reset tb0mr to tb1mr 039b 16 to 039c 16 00xx0000 2 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 aa a operation mode select bit 0 0 : timer mode or a/d trigger mode b1 b0 tmod1 tmod0 mr0 invalid in a/d trigger mode either "0" or "1" is enabled mr2 mr1 mr3 0 0 : f 1 or f 2 0 1 : f 8 1 0 : f 32 1 1 : f c32 tck1 tck0 count source select bit (note 1) 0 0 tb0mr register set to 0 in a/d trigger mode b7 b6 rw rw rw rw rw rw rw ro tb1mr register nothing is assigned. when write, set to 0 . when read, its content is indeterminate when write in a/d trigger mode, set to 0 . when read in a/d trigger mode, its content is indeterminate. note 1: when this bit is used in delayed trigger mode 0, set the same count source to the timer b0 and timer b1. figure 12.2.4.1 tbimr register in a/d trigger mode note 3. when setting the ivpcr1 bit to "1" (three-phase output forcible cutoff by sd pin input enabled), set the pd8_5 bit to "0" (= input mode). note 4. related pins are u(p8 0 ), u(p8 1 ), v(p7 2 ), v(p7 3 ), w(p7 4 ), w(p7 5 ). after forcible cutoff, input "h" to the p8 5 /nmi/sd pin. set the ivpcr1 bit to "0", and this forcible cutoff will be reset. if l is input to the p8 5 /nmi/sd pin, a three-phase motor control timer output will be disabled (inv03=0). at this time, when the ivpcr1 bit is "0", the target pins chang es to programmable i/o port. when the ivpcr1 bit is "1", the target pins changes to high-impedance state regardless of which functions of those pins are used. note 5. when this bit is used in delayed trigger mode 0, set the tb0en and tb1en bits to "1"(a/d trigger mode). note 6. when setting the tb2sel bit to "1" (underflow of tb2 interrupt generation frequency setting counter[ictb2]), set the inv02 bit to "1" (three-phase motor control timer function). note 7. refer to 16.6 digital debounce function for sd input. pwcom symbol address after reset tb2sc 039e 16 x0000000 2 timer b2 reload timing switch bit 0 : timer b2 underflow 1 : timer a output at odd-numbered timer b2 special mode register (note 1) bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 ivpcr1 three-phase output port sd control bit 1 0 : three-phase output forcible cutoff by sd pin input (high impedance) disabled 1 : three-phase output forcible cutoff by sd pin input (high impedance) enabled note 1. write to this register after setting the prc1 bit in the prcr register to "1" (write enabled). note 2. if the inv11 bit is "0" (three-phase mode 0) or the inv06 bit is "1" (triangular wave modulation mode), set this bit to "0" (timer b2 underflow). rw rw rw nothing is assigned. when write, set to 0 . when read, its content is 0 . (b7) tb2sel trigger select bit 0 : tb2 interrupt 1 : underflow of tb2 interrupt generation frequency setting counter [ictb2] rw rw tb0en timer b0 operation mode select bit 0 : other than a/d trigger mode 1 : a/d trigger mode (note 5) rw tb1en timer b1 operation mode select bit 0 : other than a/d trigger mode 1 : a/d trigger mode (note 5) rw (note 2) (note 3, 4, 7) (note 6) (b6-b5) reserved bits must set to "0" 0 0 figure 12.2.4.2 tb2sc register
12. timer page 112 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m item specification three-phase waveform output pin ___ ___ ___ six pins (u, u, v, v, w, w) forced cutoff input (note 1) _____ input l to sd pin used timers timer a4, a1, a2 (used in the one-shot timer mode) ___ timer a4: u- and u-phase waveform control ___ timer a1: v- and v-phase waveform control ___ timer a2: w- and w-phase waveform control timer b2 (used in the timer mode) carrier wave cycle control dead timer timer (3 eight-bit timer and shared reload register) dead time control output waveform triangular wave modulation, sawtooth wave modification enable to output h or l for one cycle enable to set positive-phase level and negative-phase level respectively carrier wave cycle triangular wave modulation: count source x (m+1) x 2 sawtooth wave modulation: count source x (m+1) m: setting value of tb2 register, 0 to 65535 count source: f 1 , f 2 , f 8 , f 32 , f c32 three-phase pwm output width triangular wave modulation: count source x n x 2 sawtooth wave modulation: count source x n n: setting value of ta4, ta1 and ta2 register (of ta4, ta41, ta1, ta11, ta2 and ta21 registers when setting the inv11 bit to 1 ), 1 to 65535 count source: f 1 , f 2 , f 8 , f 32 , f c32 dead time count source x p, or no dead time p: setting value of dtt register, 1 to 255 count source: f 1 , f 2 , f 1 divided by 2, f 2 divided by 2 active level eable to select h or l positive and negative-phase concurrent positive and negative-phases concurrent active disable function positive and negative-phases concurrent active detect function interrupt frequency for timer b2 interrupt, select a carrier wave cycle-to-cycle basis through 15 times carrier wave cycle-to-cycle basis 12.3 three-phase motor control timer function timers a1, a2, a4 and b2 can be used to output three-phase motor drive waveforms. table 12.3.1 lists the specifications of the three-phase motor control timer function. figure 12.3.1 shows the block diagram for three-phase motor control timer function. also, the related registers are shown on figure 12.3.2 to figure 12.3.8. table 12.3.1. three-phase motor control timer function specifications active disable function notes: _____ 1. when the inv02 bit in the invc0 register is set to 1 (three-phase motor control timer function), the sd _____ function of the p8 5 /sd pin is enabled. at this time, the p8 5 pin cannot be used as a programmable i/o _____ _____ port. when the sd function is not used, apply h to the p8 5 /sd pin. _____ 2. when the ivpcr1 bit in the tb2sc register is set to 1 (enable three-phase output forced cutoff by sd _____ pin input), and l is applied to the sd pin, the related pins enter high-impedance state regardless of the functions which are used. when the ivpcr1 bit is set to 0 (disabled three-phase output forced cutoff _____ _____ by sd pin input) and l is applied to the sd pin, the related pins can be selected as a programmable i/ o port and the setting of the port and port direction registers are enable. related pins p7 2 /clk 2 /ta1 out /v/rxd 1 _________ _________ ___ p7 3 /cts 2 /rts 2 /ta1 in /v/txd 1 p7 4 /ta2 out /w ____ p7 5 /ta2 in /w p8 0 /ta4 out /u ___ p8 1 /ta4 in /u
12. timer page 113 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m d r q 0 in v 12 1 trigger trigger ti mer b2 (ti mer mod e) signal t o be written to tim er b2 1 ti mer b2 int err upt re quest bit du1 bit d t q q q u three-phase o utpu t shift regi ster (u phase) de ad time timer n = 1 to 255 trigger trigger reload regi ster n = 1 to 255 tri gger trigger u phase o utpu t signal u v v v w w w pha se o utpu t cont rol circuit d q t d q t w d q t d q t v d q t d q t u w v u re loa d t imer a 1 count er (one-sh ot timer mod e) trigger t q reload t i mer a 2 counter (one - shot t imer mode) tri gger t q r elo ad timer a4 counter (one -s hot t imer mode ) trigger t q transf er trigger ( no t e 1 ) timer b2 un derfl o w du0 b it dub0 b it ta4 register ta41 register ta1 register ta11 register ta2 register ta21 register timer ai(i = 1, 2, 4) start trigger signal timer a4 reload control signal timer a4 one-shot pulse d ub1 bit dead t ime timer n = 1 t o 255 d ead time timer n = 1 to 255 interrupt occurrence set circuit ictb2 register n = 1 to 15 0 inv13 ictb2 counter n = 1 to 15 sd reset inv03 inv14 inv05 inv04 inv00 inv01 inv11 inv11 inv11 inv11 inv06 inv06 inv06 inv07 inv10 1/2 f1 or f2 pha se o utpu t cont rol circuit phase output control circu it p hase outpu t signal p hase outpu t signal phase outpu t signal p hase outpu t signal p hase outpu t signal rev erse cont rol reverse cont rol rever se control revers e cont rol rever se control d t d t q d t rever se co nt rol idw idv idu d q t d q t d q t b2 b0 b1 bits 2 through 0 of position-data - retain function control regi ster (address 034e 16 ) pd8_0 pd8_1 pd7_2 pd7_3 pd7_4 pd7_5 s q r reset sd ivprc1 data bus note : if the inv06 bit is set to "0" (triangular wave modulation mode), a transfer trigger is generated at only the first occu rrence of a timer b2 underflow after writing to the idb0 and idb1 registers. set to "0" when the ta2s bit is set to "0" set to "0" when ta1s bit = "0" set to "0" when ta4s bit = "0" diagram for switching to p8 0 , p81 and p7 2 - p7 5 is not shown. figure 12.3.1. three-phase motor control timer functions block diagram
12. timer page 114 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m three-phase pwm control register 0 (note 1) symbol address after reset invc0 0348 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 effective interrupt output polarity select bit inv00 bit symbol bit name description rw inv01 effective interrupt output specification bit inv02 mode select bit inv04 positive and negative phases concurrent output disable bit inv07 software trigger select bit inv06 modulation mode select bit inv05 positive and negative phases concurrent output detect flag inv03 output control bit 0: the ictb2 counter is incremented by one on the reising edge of the timer a1 reload control signal 1: the ictb2 counter is incremented by one on the falling edge of the timer a1 reload control signal 0: ictb2 counter incremented by 1 at a timer b2 underflow 1: selected by inv00 bit 0: three-phase motor control timer function unused 1: three-phase motor control timer function 0: three-phase motor control timer output disabled 1: three-phase motor control timer output enabled 0: simultaneous active output enabled 1: simultaneous active output disabled 0: not detected yet 1: already detected 0: triangular wave modulation mode 1: sawtooth wave modulation mode setting this bit to 1 generates a transfer trigger. if the inv06 bit is 1, a trigger for the dead time timer is also generated. the value of this bit when read is 0. (note 9) (note 3) (note 7) (note 2, note 3) note 1: write to this register after setting the prc1 bit in the prcr register to 1 (write enable). note also that inv00 to i nv02, inv04 and inv06 bits can only be rewritten when timers a1, a2, a4 and b2 are idle. note 2: if this bit needs to be set to 1, set any value in the ictb2 register before writing to it. note 3: effective when the inv11 bit is set to 1 (three-phase mode 1). if inv11 is set to 0 (three-phase mode 0), the ictb2 counter is incremented by 1 each time the timer b2 underflows, regardless of whether the inv00 and inv01 bits are set. when setting the inv01 bit to 1, set the timer a1 count start flag before the first timer b2 underflow. when the inv00 bit is set to 1, the first interrupt is generated when the timer b2 underflows n-1 times, if n is the value set in the ictb2 counter. subsequent interrupts are generated every n times the timer b2 underflow. note 4: setting the inv02 bit to 1 activates the dead time timer, u/v/w-phase output control circuits and ictb2 counter. note 5: when the inv02 bit is set to 1 (theee-phase control timer functions) and the inv03 is set to "0"(three-phase motor control timer output disabled), u, u, v, v, w and w pins, including pins shared with other output functions, enter a high- impedance state. note 6: the inv03 bit is set to 0 in the following cases: when reset when positive and negative go active (inv05="1") simultaneously while inv04 bit is set to 1 when set to 0 in a program when input on the sd pin changes state from h to l (the inv03 bit cannot be set to 1 when sd input is l .) when both the inv04 and the inv05 bits are set to 1 , the inv03 bit is set to 0 . note 7: can only be set by writing 0 in a program, and cannot be set to 1 . note 8: the effects of the inv06 bit are described in the table below. (note 4) rw rw rw rw rw rw rw rw (note 5) (note 8) item mode timing at which transferred from idb0 to idb1 registers to three-phase output shift register timing at which dead time timer trigger is generated when inv16 bit is 0 inv13 bit inv06=0 triangular wave modulation mode transferred only once synchronously with the transfer trigger after writing to the idb0 to idb1 registers synchronous with the falling edge of timer a1, a2, or a4 one-shot pulse effective when inv11 is 1 and inv06 is 0 inv06=1 sawtooth wave modulation mode transferred every transfer trigger synchronous with the transfer trigger and the falling edge of timer a1, a2, or a4 one-shot pulse transfer trigger: timer b2 underflow, write to the inv07 bit or write to the tb2 register when inv10 is 1 note 9: if the inv06 bit is 1 , set the inv11 bit to 0 (three-phase mode 0) and set the pwcon bit to 0 (timer b2 reloaded by a timer b2 underflow). note10: individual pins can be disabled using pfcr register. (note 6) has no effect (note 10) (note 5) figure 12.3.2. invc0 register
12. timer page 115 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 12.3.3. invc1 register three-phase pwm control register 1 (note 1) symbol address after reset invc1 0349 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 timer a1, a2, a4 start trigger signal select bit inv10 bit symbol bit name description rw inv11 timer a1-1, a2-1, a4-1 control bit inv12 dead time timer count source select bit inv14 output polarity control bit (b7) reserved bit inv16 dead time timer trigger select bit inv15 dead time invalid bit inv13 carrier wave detect flag 0: timer b2 underflow 1: timer b2 underflow and write to the tb2 register 0: three-phase mode 0 1: three-phase mode 1 0 : f 1 or f 2 1 : f 1 divided by 2 or f 2 divided by 2 0: timer a1 reload control signal is ? 1: timer a1 reload control signal is ? 0 : output waveform ??active 1 : output waveform ??active 0: dead time timer enabled 1: dead time timer disabled 0: falling edge of timer a4, a1 or a2 one-shot pulse 1: rising edge of three-phase output shift register (u, v or w phase) output this bit should be set to ? note 1: write to this register after setting the prc1 bit in the prcr register to ??(write enable). note also that this register can only be rewritten when timers a1, a2, a4 and b2 are idle. note 2: a start trigger is generated by writing to the tb2 register only while timer b2 stops. note 3: the effects of the inv11 bit are described in the table below. (note 6) (note 5) rw rw rw rw rw rw rw ro (note 3) item mode ta11, ta21, ta41 registers inv00 bit, inv01 bit inv13 bit inv11=0 three-phase mode 1 three-phase mode 0 not used has no effect. ictb2 counted every time timer b2 underflows regardless of whether the inv00 to inv01 bits are set. has no effect inv11=1 used effect effective when inv11 bit is set to ?? and inv06 bit is set to ? note 4: if the inv06 bit is set to ??(sawtooth wave modulation mode), set this bit to ??(three-phase mode 0). also, if the inv11 bit is ?? set the pwcon bit to ??(timer b2 reloaded by a timer b2 underflow). note 5: the inv13 bit is effective only when the inv06 bit is set to ??(triangular wave modulation mode) and the inv1 1 bit is set to ??(three-phase mode 1). note 6: if all of the following conditions hold true, set the inv16 bit to ??(dead time timer triggered by the rising edge of three-phase output shift register output) ?the inv15 bit is set to ??(dead time timer enabled) ?when the inv03 bit is set to ??(three-phase motor control timer output enabled), the dij bit and dibj bit (i:u, v, or w, j: 0 to 1) have always different values (the positive-phase and negative-phase always output different levels during the period other than dead time). conversely, if either one of the above conditions holds false, set the inv16 bit to ??(dead time timer triggered by the falling edge of one-shot pulse). (note 4) 0 (note 2)
12. timer page 116 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m timer b2 interrupt occurrences frequency set counter symbol address after reset ictb2 034d 16 x? 16 function setting range b7 b0 if the inv01 bit is 0 (ictb2 counter counted every time timer b2 underflows), assuming the set value = n, a timer b2 interrupt is generated at every n th occurrence of a timer b2 underflow. if the inv01 bit is 1 (ictb2 counter count timing selected by the inv00 bit), assuming the set value = n, a timer b2 interrupt is generated at every n'th occurrence of a timer b2 underflow that meets the condition selected by the inv00 bit. 1 to 15 note : use mov instruction to write to this register. if the inv01 bit is set to 1 , make sure the tb2s bit also is set to 0 (timer b2 count stopped) when writing to this register. if the inv01 bit is set to 0 , although this register can be written even when the tb2s bit is set to 1 (timer b2 count start), do not write synchronously with a timer b2 underflow. rw wo (note) nothing is assigned. when write, set to 0 . when read, its content is indeterminate. b3 three-phase output bu ff er re g ister(i=0,1) (note) symbol address when reset idb0 034a 16 3f 16 idb1 034b 16 3f 16 rw rw rw rw bit name function bit dui dubi dvi u phase output buffer i note: the idb0 and idb1 register values are transferred to the three-phase shift register by a transfer trigger. the value written to the idb0 register aftera transfer trigger represents the output signal of each phase, and the next value written to the idb1 register at the falling edge of the timer a1, a2 or a4 one-shot pulse represents the output signal of each phase. (b7-b6) rw dvbi nothing is assigned. when write, set to "0". when read, these contents are "0". write the output level 0: active level 1: inactive level when read, these bits show the three-phase output shift register value. dwi dwbi rw rw u phase output buffer i v phase output buffer i v phase output buffer i w phase output buffer i w phase output buffer i b 7 b5 b 4 b3 b 2b1b0 dead time timer (note 1, note 2) symbol address when reset dtt 034c 16 ?? 16 wo rw function setting range note 1: use mov instruction to write to this register. note 2: effective when the inv15 bit is set to 0 (dead time timer enable). if the onv15 bit is set to 1 , the dead time timer is disabled and has no effect. 1 to 255 b7 b6 b5 b4 b3 b2 b1 b0 assuming the set value = n, upon a start trigger the timer starts counting the count souce selected by the inv12 bit and stops after counting it n times. the positive or negative phase whichever is going from an inactive to an active level changes at the same time the dead time timer stops. figure 12.3.4. idb0 register, idb1register, dtt register, and icctb2 register
12. timer page 117 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 12.3.5. ta1, ta2, ta4, ta11, ta21 and ta41 registers symbol address after reset ta1 0389 16 -0388 16 ta2 038b 16 -038a 16 indeterminate ta4 038f 16 -038e 16 indeterminate ta11 (note6,7) 0343 16 -0342 16 indeterminate ta21 (note6,7) 0345 16 -0344 16 indeterminate ta41 (note6,7) 0347 16 -0346 16 indeterminate b7 b0 b7 b0 (b15) ( b8) rw assuming the set value = n, upon a start trigger the timer starts counting the count source and stops after counting it n times. the positive and negative phases change at the same time timer a, a2 or a4 stops. function setting range timer ai, ai-1 register (i=1, 2, 4) (note 1, note 2, note 3, note 4, note 5) note 1: the register must be accessed in 16 bit units. note 2: when the timer ai register is set to "0000 16 ", the counter does not operate and a timer ai interrupt does not occur. note 3: use mov instruction to write to these registers. note 4: if the inv15 bit is "0" (dead time timer enable), the positive or negative phase whichever is going from an inactive to an active level changes at the same time the dead time timer stops. note 5: if the inv11 bit is "0" (three-phase mode 0), the tai register value is transferred to the reload register by a timer ai (i = 1, 2 or 4) start trigger. if the inv11 bit is "1" (three-phase mode 1), the tai1 register value is transferred to the reload register by a timer ai start trigger first and then the tai register value is transferred to the reload register by the next timer ai start trigger. thereafter, the tai1 register and tai register values are transferred to the reload register alternately. note 6: do not write to tai1 registers synchronously with a timer b2 underflow in three-phase mode 1. . . note 7: write to the tai1 register as follows: (1) write a value to the tai1 register (2) wait for one cycle of timer ai count source. (3) write the same value to the tai1 register again. wo 0000 16 to ffff 16 indeterminate
12. timer page 118 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m note 3. when setting the ivpcr1 bit to "1" (three-phase output forcible cutoff by sd pin input enabled), set the pd8_5 bit to "0" (= input mode). note 4. related pins are u(p8 0 ), u(p8 1 ), v(p7 2 ), v(p7 3 ), w(p7 4 ), w(p7 5 ). after forcible cutoff, input "h" to the p8 5 /nmi/sd pin. set the ivpcr1 bit to "0", and this forcible cutoff will be reset. if l is input to the p8 5 /nmi/sd pin, a three-phase motor control timer output will be disabled (inv03=0). at this time, when the ivpcr1 bit is "0", the target pins chang es to programmable i/o port. when the ivpcr1 bit is "1", the target pins changes to high-impedance state regardless of which functions of those pins are used. note 5. when this bit is used in delayed trigger mode 0, set the tb0en and tb1en bits to "1"(a/d trigger mode). note 6. when setting the tb2sel bit to "1" (underflow of tb2 interrupt generation frequency setting counter[ictb2]), set the inv02 bit to "1" (three-phase motor control timer function). note 7. refer to 16.6 digital debounce function for sd input. ivpcr1 bit status of u/v/w pins remarks p8 5 /nmt/sd pin inputs "1" (three-phase output forcrible cutoff enable) "0" (three-phase output forcrible cutoff disable) h l h l high impedance peripheral input/output or input/output port peripheral input/output or input/output port peripheral input/output or input/output port three-phase output forcrible cutoff(note 1) note 1: the three-phase output forcrible cutoff function becomes effective if the inpcr1 bit is set to "1" (three-phase output forcrible cutoff function enable) even when inv03 bit is "0"(three-phase motor control timer output disalbe) ivpcr1 bit status of u/v/w pins remarks p8 5 /nmt/sd pin inputs (note 3) "1" (three-phase output forcrible cutoff enable) "0" (three-phase output forcrible cutoff disable) h l(note 1) h l(note 1) high impedance three-phase output forcrible cutoff note 1: when "l" is input to the p8 5 /nmi/sd pin, inv03 bit changes in "0" at the same time. note 2: the value of the port register and the port direction register becomes effective. note 3: when sd function isn't used, set to "0"(input) in pd8 5 and pullup to "h" in p8 5 /nmi/sd pin from outside. input/output port(note 2) three-phase pwm output three-phase pwm output the effect of p8 5 /nmi/sd pin input is below. 1.case of inv03 = "1"(three-phase motor control timer output enabled) 2.case of inv03 = "0"(three-phase motor control timer output disabled) pwcom symbol address after reset tb2sc 039e 16 x0000000 2 timer b2 reload timing switch bit 0 : timer b2 underflow 1 : timer a output at odd-numbered timer b2 special mode register (note 1) bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 ivpcr1 three-phase output port sd control bit 1 0 : three-phase output forcible cutoff by sd pin input (high impedance) disabled 1 : three-phase output forcible cutoff by sd pin input (high impedance) enabled note 1. write to this register after setting the prc1 bit in the prcr register to "1" (write enabled). note 2. if the inv11 bit is "0" (three-phase mode 0) or the inv06 bit is "1" (triangular wave modulation mode), set this bit to "0" (timer b2 underflow). rw rw rw nothing is assigned. when write, set to 0 . when read, its content is 0 . (b7) tb2sel trigger select bit 0 : tb2 interrupt 1 : underflow of tb2 interrupt generation frequency setting counter [ictb2] rw rw tb0en timer b0 operation mode select bit 0 : other than a/d trigger mode 1 : a/d trigger mode (note 5) rw tb1en timer b1 operation mode select bit 0 : other than a/d trigger mode 1 : a/d trigger mode (note 5) rw (note 2) (note 3, 4, 7) (note 6) (b6-b5) reserved bits must set to "0" 0 0 figure 12.3.6. tb2sc registers
12. timer page 119 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 12.3.7. tb2 register, trgsr register, and tabsr register ta1tgl symbol address after reset trgsr 0383 16 00 16 timer a1 event/trigger select bit to use the v-phase output control circuit, set these bits to 01 2 (tb2 underflow). trigger select register bit name function bit symbol b0 to use the w-phase output control circuit, set these bits to 01 2 (tb2 underflow). 0 0 : input on ta3 in is selected (note 1) 0 1 : tb2 overflow is selected (note 2) 1 0 : ta2 overflow is selected (note 2) 1 1 : ta4 overflow is selected (note 2) to use the u-phase output control circuit, set these bits to 01 2 (tb2 underflow). timer a2 event/trigger select bit timer a3 event/trigger select bit timer a4 event/trigger select bit rw ta1tgh ta2tgl ta2tgh ta3tgl ta3tgh ta4tgl ta4tgh b5 b4 note 1: set the corresponding port direction bit to 0 (input mode). note 2: overflow or underflow. b7 b6 b5 b4 b3 b2 b1 symbol address after reset tabsr 0380 16 00 16 count start flag bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa timer b2 count start flag timer b1 count start flag timer b0 count start flag timer a4 count start flag timer a3 count start flag timer a2 count start flag timer a1 count start flag timer a0 count start flag 0 : stops counting 1 : starts counting tb2s tb1s tb0s ta4s ta3s ta2s ta1s ta0s rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw symbol address after reset tb2 0395 16 -0394 16 indeterminate b7 b0 b7 b0 (b15) ( b8) rw 0000 16 to ffff 16 function setting rang e timer b2 register (note ) note : the register must be accessed in 16 bit units. rw divide the count source by n + 1 where n = set value. timer a1, a2 and a4 are started at every occurrence of underflow.
12. timer page 120 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m bit name timer ai mode register symbol address after reset ta1mr 0397 16 00 16 ta2mr 0398 16 00 16 ta4mr 039a 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit must set to 10 2 (one-shot timer mode) for the three-phase motor control timer function tmod1 tmod0 mr0 pulse output function select bit must set to 0 for the three-phase motor control timer function mr2 mr1 mr3 must set to 0 for the three-phase motor control timer function 0 0 : f 1 or f 2 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 tck1 tck0 count source select bit 1 0 0 must set to 1 (selected by event/trigger select register) for the three-phase motor control timer function trigger select bit external trigger select bit rw timer b2 mode register symbol address after reset tb2mr 039d 16 00xx0000 2 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 aa aa aa aa operation mode select bit set to 00 2 (timer mode) for the three- phase motor control timer function tmod1 tmod0 mr0 mr2 mr1 mr3 0 0 : f 1 or f 2 0 1 : f 8 1 0 : f 32 1 1 : f c32 tck1 tck0 count source select bit 0 when write in three-phase motor control timer function, write 0 . when read, its content is indeterminate. 0 b7 b6 1 0 has no effect for the three-phase motor control timer function rw rw rw rw rw rw rw rw rw rw rw rw rw rw ro has no effect for the three-phase motor control timer function. when write, set to 0 . when read, its content is indeterminate. must set to 0 for the three-phase motor control timer function 0 figure 12.3.8. ta1mr, ta2mr, ta4mr, and tb2mr registers
12. timer page 121 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m start trigger signal for timer a4* timer b2 u phase c arr i er wave signal wave u phase output signal * m nn p p m u phase u phase u phase inv14 = 0 timer a4 one-shot pulse* inv14 = 1 dead time dead time transfer to three-phase output shift register rewriting idb0, idb1 registers * internal signals. see the block diagram of the three-phase motor control timer function. an example for changing pwm outputs is shown below. (1)when inv11=1(three-phase mode 1) inv01=0, ictb2=2 16 (timer b2 interrupt is generated at every 2 th occurrence of a timer b2 underflow), or inv01=1, inv00=1, ictb2=1 16 (the timer b2 interrupt is generated on the falling edge of the timer a1 reload control signal) initial timer value: ta41=m, ta4=m. the ta4 and ta41 registers are modified every time a timer b2 interrupt occurs. first time, ta41= n, ta4 = n. second time, ta41 = p, ta4 = p. initial values of idb0 and idb1 registers: du0 = 1, dub0 = 0, du1 = 0, dub1 = 1.the register values are changed to du0 = 1, dub0 = 0, du1= 1 and dub1 = 0 the third time a timer b2 interrupt occurs. (2)when inv11=0(three-phase mode 0) inv01=0, ictb2=1 16 (timer b2 interrupt is generated at every occurrence of a timer b2 underflow) initial timer value: ta4 = m. the ta4 register is modified each time a timer b2 interrupt occurs. first time, ta4 = m. second time, ta4 = n. third time, ta4 = n. fourth time, ta4 = p. fifth time, ta4 = p. initial values of idb0 and idb1 registers: du0=1, dub0=0, du1=0, dub1=1.the register values are changed to du0 = 1, dub0 = 0, du1= 1 and dub1 = 0 the sixth time a timer b2 interrupt occurs. tb2s bit in the tabsr register inv13 (inv11=1(three-phase mode 1)) shown here is a typical waveform for the case where invc0 = 00xx11xx 2 (x = set as suitable for the system) and invc1 = 010xxxx0 2 . u phase output signal * ( l active) ( h active) the value written to the ta4 register and ta41 register are transferred on the rising edge of the timer a1 reload signal. figure 12.3.9. triangular wave modulation operation the three-phase motor control timer function is enabled by setting the inv02 bit in the vc0 register to 1 . when this function is on, timer b2 is used to control the carrier wave, and timers a4, a1 and a2 are used to __ ___ ___ control three-phase pwm outputs (u, u, v, v, w and w). the dead time is controlled by a dedicated dead- time timer. figure 12.3.9 shows the example of triangular modulation waveform, and figure 12.3.10 shows the example of sawtooth modulation waveform.
12. timer page 122 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m timer b2 u phase carrier wave signal wave u phase output signal * u phase u phase output signal * u phase u phase inv14 = 0 carrier wave: sawtooth waveform inv14 = 1 transfer to three-phase output shift register rewriting idb0, idb1 registers * internal signals. see the block diagram of the three-phase motor control timer function. shown here is a typical waveform for the case where invc0= 01xx110x 2 (x = set as suitable for the system) and invc1 = 010xxx00 2 . an example for changing pwm outputs is shown below. ? initial values of idb0 and idb1 registers: du0=0, dub0=1, du1=1, dub1=1. the register values are changed to du0=1, dub0=0, du1=1, dub1=1 a timer b2 interrupt occurs. start trigger signal for timer a4* timer a4 one-shot pulse* dead time dead time ( h active) ( l active) figure 12.3.10. sawtooth wave modulation operation
12. timer page 123 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 12.3.1 position-data-retain function this function is used to retain the position data synchronously with the three-phase waveform output.there are three position-data input pins for u, v, and w phases. a trigger to retain the position data (hereafter, this trigger is referred to as "retain trigger") can be selected by the retain-trigger polarity select bit(bit 3 of the position-data-retain function control register, at address 034e 16 ). this bit selects the retain trigger to be the falling edge of each positive phase, or the rising edge of each positive phase. 12.3.1.1 operation of the position-data-retain function figure 12.3.1.1.1 shows a usage example of the position-data-retain function (u phase) when the retain trigger is selected as the falling edge of the positive signal. (1) at the falling edge of the u-phase waveform ouput, the state at pin idu is transferred to the u- phase position data retain bit ( bit2 at address 034e 16 ). (2) until the next falling edge of the uphase waveform output,the above value is retained. transferred carrier wave u-phase waveform output u-phase waveform output 1 2 transferred transferred transferred pin idu u-phase position data retain bit (bit 2 at address 034e 16 ) note: n o t e : the retain trigger is the falling edge of the positive signal. figure 12.3.1.1.1 usage example of position-data-retain function ( u phase )
12. timer page 124 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 12.3.1.2 position-data-retain function control register figure 12.3.1.2.1 shows the structure of the position-data-retain function contol register. p osition-data-retain f unction control re g ister (note) symbol address when reset pdrf 034e 16 xxxx 0000 2 ro ro ro rw bit name function bit symbol pdrw pdrv pdru w-phase position data retain bit input level at pin idu is read out. 0: "l" level 1: "h" level note: this register is valid only in the three-phase mode. retain-trigger polarity select bit (b7-b4) rw pdrt v-phase position data retain bit nothing is assigned. when write, set to "0". when read, contents are indeterminate. u-phase position data retain bit input level at pin idv is read out. 0: "l" level 1: "h" level input level at pin idw is read out. 0: "l" level 1: "h" level 0: rising edge of positive phase 1: falling edge of positive phase b 7 b3 b 2b1b0 figure 12.3.1.2.1. pdrf register 12.3.1.2.1 w-phase position data retain bit (pdrw) this bit is used to retain the input level at pin idw. 12.3.1.2.2 v-phase position data retain bit (pdrv) this bit is used to retain the input level at pin idv. 12.3.1.2.3 u-phase position data retain bit (pdru) t his bit is used to retain the input level at pin idu. 12.3.1.2.4 retain-trigger polarity select bit (pdrt) this bit is used to select the trigger polarity to retain the position data. when this bit is set to "0", the rising edge of each positive phase selected. when this bit is set to "1", the falling edge of each pocitive phase selected.
12. timer page 125 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 12.3.2.1. usage example of three-phse/port output switch function 12.3.2 three-phase/port output switch function when the invc03 bit in the invc0 register set to 1 (timer output enabled for three-phase motor control) and setting the pfci (i=0 to 5) in the pfcr register to 0 (i/o port), the three-phase pwm output pin (u, __ __ ___ u, v, v, w and w) functions as i/o port. each bit in the pfci bits (i=0 to 5) is applicable for each one of three-phase pwm output pins. figure 12.3.2.1 shows the example of three-phase/port output switch function. figure 12.3.2.2 shows the pfcr register and the three-phase protect control register. timer b2 u phase v phase w phase writing pfcr register (note) pfc0 bit : "1" pfc2 bit : "1" pfc4 bit : "0" functions as port p7 4 functions as port p7 2 writing pfcr register (note) pfc0 bit : "1" pfc2 bit : "0" pfc4 bit : "1" note : a hazard may be generated at the output signal, depending on the output switch timing. also, do not generate (short) be switching to port output during the dead time of three-phase output.
12. timer page 126 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 12.3.2.2. pfcr register, and tprc register p ort f unction control re g ister (note) symbol address when reset pfcr 0358 16 0011 1111 2 rw rw rw rw bit name function bit symbol pfc0 pfc1 pfc2 port p8 0 output function select bit note: this register is valid only when the invc03 bit in the invc0 register is set to "1"(three-phase motor control timer output enabled). write to this register after setting the tprc0 bit in the tprc register to "1" (write enable). (b7-b6) rw pfc3 nothing is assigned. when write, set to "0". when read, these contents are "0". 0: input/output port p8 0 1: three-phase pwm output (u phase output) pfc4 pfc5 rw rw port p8 1 output function select bit port p7 2 output function select bit port p7 3 output function select bit port p7 4 output function select bit port p7 5 output function select bit 0: input/output port p8 1 1: three-phase pwm output (u phase output) 0: input/output port p7 2 1: three-phase pwm output (v phase output) 0: input/output port p7 3 1: three-phase pwm output (v phase output) 0: input/output port p7 4 1: three-phase pwm output (w phase output) 0: input/output port p7 5 1: three-phase pwm output (w phase output) b 7 b5 b 4 b3 b 2b1b0 th ree-p h ase protect contro l re gi ster symbol address when reset tprc 025a 16 00 16 rw rw bit name function bit symbol tprc0 three-phase protect control bit (b7-b1) nothing is assigned. when write, set to "0". when read, these contents are "0". enable write to pfcr register 0: write protected 1: write enabled b 7 b5 b 4 b3 b 2b1b0
13. serial i/o page 127 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 13. serial i/o note the m16c/26a (42-pin version) do not use uart0. serial i/o is configured with three channels: uart0 to uart2. 13.1. uarti (i=0 to 2) uarti each have an exclusive timer to generate a transfer clock, so they operate independently of each other. figure 13.1.1 shows the block diagram of uarti. figures 13.1.2 and 13.1.3 shows the block diagram of the uarti transmit/receive. uarti has the following modes: ? clock synchronous serial i/o mode ? clock asynchronous serial i/o mode (uart mode). ? special mode 1 (i 2 c bus mode) : uart2 ? special mode 2 : uart2 ? special mode 3 (bus collision detection function, iebus mode) : uart2 ? special mode 4 (sim mode) : uart2 figures 13.1.4 to 13.1.9 show the uarti-related registers. refer to tables listing each mode for register setting.
13. serial i/o page 128 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m clock synchronous type (when internal clock is selected) clock synchronous type (when external clock is selected) clock source selection internal external cts/rts disabled cts/rts selected rxd 0 1 / (n 0 +1) 1/16 1/16 1/2 u0brg registe r clk 0 cts 0 / rts 0 f 1sio or f 2sio f 8sio f 32sio v cc rts 0 cts 0 txd 0 (uart0) clk1 to clk0 00 2 01 2 10 2 ckdir=0 ckdir=1 ckpol ckdir=0 ckdir= 1 crs=1 crs=0 crd=0 crd=1 rcsp=0 rcsp=1 v cc crd=0 crd=1 uart reception clock synchronous type uart transmission clock synchronous type clock synchronous type (when internal clock is selected) receive clock transmit clock reception control circuit transmission control circuit transmit/ receive unit clk polarity reversing circuit cts/rts disabled cts 0 from uart 1 uart reception clock synchronous type rxd 1 txd 1 (uart1) 1 / (n 1 +1) 1/16 1/16 1/2 u1brg register clk 1 f 1sio or f 2sio f 8sio f 32sio clk1 to clk0 00 2 01 2 10 2 ckdir=0 ckdir=1 ckpol ckdir=0 ckdir= 1 v cc crd=0 crd=1 clkmd0=0 clkmd1=0 crs=1 crs=0 rcsp=0 rcsp=1 clkmd0=1 clkmd1=1 clock source selection internal external uart transmission clock synchronous type clock synchronous type (when internal clock is selected) receive clock transmit clock reception control circuit transmission control circuit transmit/ receive unit clock synchronous type (when external clock is selected) clock synchronous type (when internal clock is selected) clk polarity reversing circuit rts1 cts1 clock output pin select cts/rts disable d cts/rts disable d cts/rts selecte d cts 0 from uart 0 cts 1 / rts 1 / cts 0 / clks 1 i = 0 to 2 n i : values set to the uibrg register smd2 to smd0, ckdir: bits in the uimr clk1 to clk0, ckpol, crd, crs: bits in the uic0 register s clkmd0, clkmd1, rcsp: bits in the ucon register rxd 2 clk 2 cts 2 / rts 2 rts 2 cts 2 txd 2 (uart2) 1 / (n 2 +1) 1/16 1/16 1/2 u2brg registe r f 1sio or f 2sio f 8sio f 32sio clk1 to clk0 00 2 01 2 10 2 ckdir=0 ckdir=1 ckpol ckdir=0 ckdir= 1 crs=1 crs=0 v cc crd=0 crd=1 reception control circuit transmission control circuit uart reception clock synchronous type uart transmission clock synchronous type clock synchronous type (when internal clock is selected) receive clock transmit clock rxd polarity reversing circuit internal external clock source selection txd polarity reversing circuit transmit/ receive unit clock synchronous type (when internal clock is selected) clock synchronous type (when external clock is selected) clk polarity reversing circuit cts/rts disabled cts/rts disabled cts/rts selecte d main clock or on-chip oscillator clock 1/2 1/8 1/4 f 1sio f 2sio f 8sio f 32sio f 1sio or f 2sio pclk1=1 pclk1=0 smd2 to smd0 smd2 to smd0 smd2 to smd0 figure 13.1.1. block diagram of uarti (i = 0 to 2)
13. serial i/o page 129 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m sp sp pa r 2sp 1sp uart uart (7 bits) uart (8 bits) uart (7 bits) uart (9 bits) clock synchronous type clock synchronous type txdi uarti transmit register par enabled par disabled d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 sp: stop bit par: parity bit uarti ? transmit buffer register msb/lsb conversion circuit uart (8 bits) uart (9 bits) clock synchronous type uarti receive buffer register uarti receive registe r 2sp 1sp stps=0 pa r enabled par disabled uart uart (7 bits) uart (9 bits) clock synchronous type clock synchronous type uart (7 bits) uart (8 bits ) rxdi clock synchronous type uart (8 bits) uart (9 bits) address 03a6 16 address 03a7 16 address 03ae 16 address 03af 16 address 03a2 16 address 03a3 16 address 03aa 16 address 03ab 16 data bus low-order bit s msb/lsb conversion circuit d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 8 0000000 sp sp par 0 data bus high-order bits stps=1 prye=0 prye=1 stps=0 stps=1 prye=0 prye=1 smd2 to smd0, stps, prye, iopol, ckdir : bit in the uimr register 0 00 1 11 smd2 to smd0 0 1 smd2 to smd0 1 1 0 0 figure 13.1.2. block diagram of uarti (i = 0, 1) transmit/receive unit
13. serial i/o page 130 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m sp sp pa r 2sp 1sp uart uart (7 bits) uart (8 bits) uart(7 bits) uart (9 bits) clock synchronous type clock synchronous type data bus low-order bits txd2 uarti transmit registe r par disabled par enabled d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 uart2 transmit buffer register uart (8 bits) uart (9 bits) clock synchronous type uart2 receive buffer registe r uarti receive registe r 2sp 1sp uart (7 bits) uart (8 bits) uart(7 bits) uart (9 bits) clock synchronous type clock synchronous type rxd2 uart (8 bits) uart (9 bits) address 037e 16 address 037f 16 address 037a 16 address 037b 16 data bus high-order bit s d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 8 0000000 sp sp par 0 reverse no revers e error signal output circui t rxd data reverse circuit error signal output enable error signal output disable reverse no reverse logic reverse circuit + msb/lsb conversion circuit logic reverse circuit + msb/lsb conversion circuit par enabled par disabled uart clock synchronous type txd data reverse circuit sp: stop bit par: parity bit stps=0 stps=1 prye=0 prye=1 stps=0 stps=1 prye=0 prye=1 iopol=0 iopol=1 iopol =0 iopol =1 u2ere =0 u2ere =1 smd2 to smd0, stps, prye, iopol, ckdir : bit in the u2mr register u2ere : bit in the u2c1 register 0 1 smd2 to smd0 11 0 0 0 1 smd2 to smd0 1 1 0 0 figure 13.1.3. block diagram of uart2 transmit/receive unit
13. serial i/o page 131 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m (b15) b7 b0 (b8) b7 b0 uarti transmit buffer register (i=0 to 2)(note) function transmit data nothing is assigned. in an attempt to write to these bits, write 0 . the value, if read, turns out to be indeterminate. symbol address after reset u0tb 03a3 16 -03a2 16 indeterminate u1tb 03ab 16 -03aa 16 indeterminate u2tb 037b 16 -037a 16 indeterminate r w note: use mov instruction to write to this register. wo b7 uarti baud rate generation register (i=0 to 2)(note 1) b0 symbol address after reset u0brg 03a1 16 indeterminate u1brg 03a9 16 indeterminate u2brg 0379 16 indeterminate function assuming that set value = n, uibrg divides the count source by n + 1 00 16 to ff 1 6 setting range note 1: write to this register while serial i/o is neither transmitting nor receiving. use mov instruction to write to this register. the transfer clock is shown below when the setting value in the uibrg register is set as n. (1) when the ckdir bit in the uimr register to 0 (internal clock) ? clock synchronous serial i/o mode : fj/(2(n+1)) ? clock asynchronous serial i/o (uart) mode : fj/(16(n+1)) (2) when the ckdir bit in the uimr register to 1 (external clock) ? clock synchronous serial i/o mode : f ext ? clock asynchronous serial i/o (uart) mode : f ext /(16(n+1)) r w w o note 1: when the smd2 to smd0 bits in the uimr register is set to 0002 (serial i/o disabled) or the re bit in the uic1 register is set to 0 (reception disabled), all of the sum, per, fer and oer bits are set to 0 (no error). the sum bit is set to 0 (no error) when all of the per, fer and oer bits is set to 0 (no error). also, the per and fer bits are set to 0 by reading the lower byte of the uirb register. note 2: the abt bit is set to 0 by writing 0 in a program. (writing 1 has no effect.) nothing assignd at the bit 11 in the u0rb and u1rb registers. when write, set to 0 . when read, its contents is 0 . (b15) symbol address after reset u0rb 03a7 16 -03a6 16 indeterminate u1rb 03af 16 -03ae 16 indeterminate u2rb 037f 16 -037e 16 indeterminate b7 b0 (b8) b7 b0 uarti receive buffer register (i=0 to 2) function bit name bit symbol 0 : no framing error 1 : framing error found 0 : no parity error 1 : parity error found 0 : no error 1 : error found oer fer per sum overrun error flag (note 1) framing error flag (note 1) parity error flag (note 1) error sum flag (note 1) 0 : no overrun error 1 : overrun error found receive data (d 7 to d 0 ) abt arbitration lost detecting flag (note 2) 0 : not detected 1 : detected r w r w r o r o r o r o r o (b7-b0) (b10-b9) receive data (d 8 ) r o (b8) nothing is assigned. in an attempt to write to these bits, write 0 . the value, if read, turns out to be 0 . figure 13.1.4. u0tb to u2tb registers, u0rb to u2rb registers, u0brg to u2brg registers
13. serial i/o page 132 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m uarti transmit/receive mode register (i=0, 1) symbol address after reset u0mr, u1mr 03a0 16 , 03a8 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol rw ckdir smd1 smd0 serial i/o mode select bit (note 2) smd2 internal/external clock select bit stps pry prye (b7) parity enable bit 0 : internal clock 1 : external clock (note 1) stop bit length select bit odd/even parity select bit reserve bit 0 : one stop bit 1 : two stop bits 0 : parity disabled 1 : parity enabled 0 0 0 : serial i/o disabled 0 0 1 : clock synchronous serial i/o mode 1 0 0 : uart mode transfer data 7 bits long 1 0 1 : uart mode transfer data 8 bits long 1 1 0 : uart mode transfer data 9 bits long do not set value other than the above b2 b1 b0 effective when prye = 1 0 : odd parity 1 : even parity write to "0" function note 1: set the corresponding port direction bit for each clki pin to 0 (input mode). note 2: to receive data, set the corresponding port direction bit for each rxdi pin to 0 (input mode). rw rw rw rw rw rw rw rw uart2 transmit/receive mode register symbol address after reset u2mr 0378 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol rw ckdir smd1 smd0 serial i/o mode select bit (note 2) smd2 internal/external clock select bit stps pry prye iopol parity enable bit 0 : internal clock 1 : external clock (note 1) stop bit length select bit odd/even parity select bit txd, rxd i/o polarity reverse bit 0 : one stop bit 1 : two stop bits 0 : parity disabled 1 : parity enabled 0 0 0 : serial i/o disabled 0 0 1 : clock synchronous serial i/o mode 0 1 0 : i 2 c bus mode 1 0 0 : uart mode transfer data 7 bits long 1 0 1 : uart mode transfer data 8 bits long 1 1 0 : uart mode transfer data 9 bits long must not be set except above b2 b1 b0 effective when prye = 1 0 : odd parity 1 : even parity 0 : no reverse 1 : reverse function note 1: set the corresponding port direction bit for each clk2 pin to 0 (input mode). note 2: to receive data, set the corresponding port direction bit for each rxd2 pin to 0 (input mode). note 3: set the corresponding port direction bit for scl2 and sda2 pins to 0 (input mode). rw rw rw rw rw rw rw rw (note 3) figure 13.1.5. u0mr to u2mr registers
13. serial i/o page 133 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 13.1.6. u0c0 to u2c0 registers and ucon register uarti transmit/receive control register 0 (i=0 to 2) symbol address after reset u0c0 to u2c0 03a4 16 , 03ac 16 , 037c 16 00001000 2 b7 b6 b5 b4 b3 b2 b1 b0 function txept clk1 clk0 crs crd nch ckpol brg count source select bit transmit register empty flag 0 : transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : transmit data is output at rising edge of transfer clock and receive data is input at falling edge clk polarity select bit cts/rts function select bit cts/rts disable bit data output select bit 0 0 : f 1sio or f 2sio is selected 0 1 : f 8sio is selected 1 0 : f 32sio is selected 1 1 : %poputfuupuijtwbmvf b1 b0 0 : lsb first 1 : msb first 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) 0 : cts/rts function enabled 1 : cts/rts function disabled (p6 0 , p6 4 and p7 3 can be used as i/o ports) 0 : txdi/sda2 and scl2 pins are cmos output 1 : txdi/sda2 and scl2 pins are n-channel open-drain output uform transfer format select bit (note 2) effective when crd = 0 0 : cts function is selected (note 1) 1 : rts function is selected bit name bit symbol note 1: set the corresponding port direction bit for each ctsi pin to 0 (input mode). note 2: effective for clock synchronous serial i/o mode, uart mode transfer data 8 bits long and special mode 2. note 3: cts 1 /rts 1 can be used when the clkmd1 bit in the ucon register is set to 0 (only clk 1 output) and the rcsp bit in the ucon register is set to 0 (cts 0 /rts 0 not separated). note 4: sda2 and scl2 are effective when i = 2. note 5: when the smd2 to smd0 bits in uimr regiser are set to 000 2 (serial i/o disable), do not set nch bit to 1 (txdi/sda2 and scl2 pins are n-channel open-drain output). note 6: when the u1map bit in pacr register is 1 (p7 3 to p7 0 ), cts/rts pin in uart1 is assigned to p7 0 . rw rw rw rw rw rw rw rw ro (note 3) (note 4) (note 5) (note 6) note 1: when using multiple transfer clock output pins, make sure the following conditions are met: set the ckdir bit in the u1mr register to 0 (internal clock) note 2: when the u1map bit in pacr register is set to 1 (p7 3 to p7 0 ), cts 0 is supplied from the p7 0 pin. uart transmit/receive control register 2 symbol address after reset ucon 03b0 16 x0000000 2 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol r w function clkmd0 clkmd1 uart0 transmit interrupt cause select bit uart0 continuous receive mode enable bit 0 : continuous receive mode disabled 1 : continuous receive mode enable uart1 continuous receive mode enable bit uart1 clk/clks select bit 0 uart1 transmit interrupt cause select bit 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) 0 : output from clk1 only 1 : transfer clock output from multiple pins function selected 0 : continuous receive mode disabled 1 : continuous receive mode enabled nothing is assigned. when write, set to 0 . when read, its content is indeterminate. u0irs u1irs u0rrm u1rrm uart1 clk/clks select bit 1 (note 1) effective when the clkmd1 bit is set to 1 0 : clock output from clk1 1 : clock output from clks1 rcsp separate uart0 cts/rts bit 0 : cts/rts shared pin 1 : cts/rts separated (cts 0 supplied from the p6 4 pin) r w r w r w r w r w r w r w (b7) (note 2)
13. serial i/o page 134 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m uarti transmit/receive control register 1 (i=0, 1) symbol address after reset u0c1, u1c1 03a5 16 ,03ad 16 00000010 2 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol rw function te ti re ri transmit enable bit receive enable bit receive complete flag transmit buffer empty flag 0 : transmission disabled 1 : transmission enabled 0 : data present in uitb register 1 : no data present in uitb register 0 : reception disabled 1 : reception enabled 0 : no data present in uirb register 1 : data present in uirb register nothing is assigned. when write, set 0 . when read, these contents are 0 . uart2 transmit/receive control register 1 symbol address after reset u2c1 037d 16 00000010 2 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol function te ti re ri transmit enable bit receive enable bit receive complete flag transmit buffer empty flag 0 : transmission disabled 1 : transmission enabled 0 : reception disabled 1 : reception enabled u2irs uart2 transmit interrupt cause select bit 0 : transmit buffer empty (ti = 1) 1 : transmit is completed (txept = 1) u2rrm uart2 continuous receive mode enable bit 0 : continuous receive mode disabled 1 : continuous receive mode enabled data logic select bit 0 : no reverse 1 : reverse u2lch u2ere error signal output enable bit 0 : output disabled 1 : output enabled rw rw ro ro rw rw rw rw rw rw rw ro ro (b7-b4) 0 : data present in u2tb register 1 : no data present in u2tb register 0 : no data present in u2rb register 1 : data present in u2rb register figure 13.1.7. u0c1 to u2c1 registers, pacr register pin assignment control register (note) symbpl address after reset pacr 025d 16 00000000 2 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 pin enabling bit nothing is assigned. in an attempt to write to these bits, write 0 . the value, if read, turns out to be 0 . rw (b6-b3) 001 : 42 pin 100 : 48 pin all other values are reserved. do not use. pacr0 pacr1 pacr2 rw rw reserved bits u1map uart1 pin remapping bit uart1 pins assigned to 0 : p6 7 to p6 4 1 : p7 3 to p7 0 rw note : make sure the pacr register is written to by the next instruction after setting the prc2 bit in the prcr register to 1 (write enable).
13. serial i/o page 135 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m uart2 special mode register symbol address after reset u2smr 0377 16 x0000000 2 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol function abscs acse sss i 2 c bus mode select bit bus busy flag 0 : stop condition detected 1 : start condition detected (busy) bus collision detect sampling clock select bit arbitration lost detecting flag control bit 0 : other than i 2 c bus mode 1 : i 2 c bus mode 0 : update per bit 1 : update per byte iicm abc bbs 0 : not synchronized to r x di 1 : synchronized to r x di (note 2) set to 0 transmit start condition select bit 0 : rising edge of transfer clock 1 : underflow signal of timer a0 auto clear function select bit of transmit enable bit 0 : no auto clear function 1 : auto clear at occurrence of bus collision note 1: the bbs bit is set to 0 by writing 0 in a program. (writing 1 has no effect.). note 2: when a transfer begins, the sss bit is set to 0 (not synchronized to r x di). (note1) nothing is assigned. when write, set to 0 . when read, its content is indeterminate. r w r w r w r w r w r w r w r w (b7) 0 (b3) reserved bit figure 13.1.8. u2smr register and u2smr2 register uart2 special mode register 2 symbol address after reset u2smr2 0376 16 x0000000 2 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol rw function stac swc2 sdhi i c bus mode select bit 2 scl wait output bit 0 : disabled 1 : enabled sda output stop bit uart initialization bit clock-synchronous bit refer to table 13.3.4. i 2 c bus mode functions 0 : disabled 1 : enabled iicm2 csc swc als 0 : disabled 1 : enabled sda output disable bit scl wait output bit 2 0: enabled 1: disabled (high impedance) 0 : disabled 1 : enabled 0: transfer clock 1: l output 2 nothing is assigned. when write, set 0 . when read, its content is indeterminate. rw rw rw rw rw rw rw (b7)
13. serial i/o page 136 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m uart2 special mode register 3 symbol address after reset u2smr3 0375 16 000x0x0x 2 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol function dl2 sda digital delay setup bit (note 1, note 2) dl0 dl1 0 0 0 : without delay 0 0 1 : 1 to 2 cycle(s) of uibrg count source 0 1 0 : 2 to 3 cycles of uibrg count source 0 1 1 : 3 to 4 cycles of uibrg count source 1 0 0 : 4 to 5 cycles of uibrg count source 1 0 1 : 5 to 6 cycles of uibrg count source 1 1 0 : 6 to 7 cycles of uibrg count source 1 1 1 : 7 to 8 cycles of uibrg count source nothing is assigned. when write, set 0 . when read, its content is indeterminate. b7 b6 b5 0 : without clock delay 1 : with clock delay clock phase set bit 0 : clki is cmos output 1 : clki is n-channel open drain output clock output select bit ckph nodc note 1 : the dl2 to dl0 bits are used to generate a delay in sda2 output by digital means during i 2 c bus mode. in other than i 2 c bus mode, set these bits to 000 2 (no delay). note 2 : the amount of delay varies with the load on scl2 and sda2 pins. also, when using an external clock, the amount of delay increases by about 100 ns. rw rw rw rw rw rw (b0) nothing is assigned. when write, set 0 . when read, its content is indeterminate. nothing is assigned. when write, set 0 . when read, its content is indeterminate. (b2) (b4) figure 13.1.9. u2smr3 register and u2smr4 register uart2 special mode register 4 symbol address after reset u2smr4 0374 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol rw function ackc sclhi swc9 start condition generate bit (note) stop condition generate bit (note) 0 : clear 1 : start scl,sda output select bit ack data bit restart condition generate bit (note) 0 : clear 1 : start 0 : clear 1 : start stareq rstareq stpreq ackd 0 : start and stop conditions not output 1 : start and stop conditions output scl output stop enable bit ack data output enable bit 0 : disabled 1 : enabled 0 : ack 1 : nack 0 : serial i/o data output 1 : ack data output note: set to 0 when each condition is generated. stspsel 0 : scl l hold disabled 1 : scl l hold enabled scl wait bit 3 rw rw rw rw rw rw rw rw
13. serial i/o page 137 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 13.1.1. clock synchronous serial i/o mode the clock synchronous serial i/o mode uses a transfer clock to transmit and receive data. table 13.1.1.1 lists the specifications of the clock synchronous serial i/o mode. table 13.1.1.2 lists the registers used in clock synchronous serial i/o mode and the register values set. table 13.1.1.1. clock synchronous serial i/o mode specifications item specification transfer data format ? transfer data length: 8 bits transfer clock ? the ckdir bit in the uimr(i=0 to 2) register is set to 0 (internal clock) : fj/ (2(n+1)) fj = f 1sio , f 2sio , f 8sio , f 32sio . n: setting value of uibrg register 00 16 to ff 16 ? the ckdir bit is set to 1 (external clock ) : input from clki pin transmission, reception control _______ _______ _______ _______ ? selectable from cts function, rts function or cts/rts function disable transmission start condition ? before transmission can start, the following requirements must be met (note 1) _ the te bit in the uic1 register is set to "1" (transmission enabled) _ the ti bit in the uic1 register is set to "0" (data present in uitb register) _______ _______ _ if cts function is selected, input on the ctsi pin is l reception start condition ? before reception can start, the following requirements must be met (note 1) _ the re bit in the uic1 register is set to "1" (reception enabled) _ the te bit in the uic1 register is set to "1" (transmission enabled) _ the ti bit in the uic1 register is set to "0" (data present in the uitb register) ? for transmission, one of the following conditions can be selected _ the uiirs bit (note 3) is set to "0" (transmit buffer empty): when transferring data from the uitb register to the uarti transmit register (at start of transmission) _ the uiirs bit is set to "1" (transfer completed): when the serial i/o finished sending data from the uarti transmit register ? for reception when transferring data from the uarti receive register to the uirb register (at completion of reception) error detection ? overrun error (note 2) this error occurs if the serial i/o started receiving the next data before reading the uirb register and received the 7th bit of the next data select function ? clk polarity selection transfer data input/output can be chosen to occur synchronously with the rising or the falling edge of the transfer clock ? lsb first, msb first selection whether to start sending/receiving data beginning with bit 0 or beginning with bit 7 can be selected ? continuous receive mode selection reception is enabled immediately by reading the uirb register ? switching serial data logic (uart2) this function reverses the logic value of the transmit/receive data ? transfer clock output from multiple pins selection (uart1) the output pin can be selected in a program from two uart1 transfer clock pins that have been set _______ _______ ? separate cts/rts pins (uart0) _________ _________ cts 0 and rts 0 are input/output from separate pins ? uart1 pin remapping selection the uart1 pin can be selected from the p6 7 to p6 4 or p7 3 to p7 0 . note 1: when an external clock is selected, the conditions must be met while if the ckpol bit in the uic0 register 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the external clock is in th e high state; if the ckpol bit in the uic0 register 1 (transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state. note 2: if an overrun error occurs, the value of uirb register will be indeterminate. the ir bit in the siric register does not change. note 3: the u0irs and u1irs bits respectively are the ucon register bits 0 and 1; the u2irs bit is the u2c1 register bit 4.
13. serial i/o page 138 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m table 13.1.1. 2. registers to be used and settings in clock synchronous serial i/o mode register bit function uitb (note3) 0 to 7 set transmission data uirb (note3) 0 to 7 reception data can be read oer overrun error flag uibrg 0 to 7 set a transfer rate uimr (note3) smd2 to smd0 set to 001 2 ckdir select the internal clock or external clock iopol(i=2)(note 4) set to 0 uic0 clk1 to clk0 select the count source for the uibrg register crs _______ _______ select cts or rts to use txept transmit register empty flag crd _______ _______ enable or disable the cts or rts function nch select txdi pin output mode ckpol select the transfer clock polarity uform select the lsb first or msb first uic1 te set this bit to 1 to enable transmission/reception ti transmit buffer empty flag re set this bit to 1 to enable reception ri reception complete flag u2irs (note 1) select the source of uart2 transmit interrupt u2rrm (note 1) set this bit to 1 to use uart2 continuous receive mode u2lch(note 3) set this bit to 1 to use uart2 inverted data logic u2ere(note 3) set to 0 u2smr 0 to 7 set to 0 u2smr2 0 to 7 set to 0 u2smr3 0 to 2 set to 0 nodc select clock output mode 4 to 7 set to 0 u2smr4 0 to 7 set to 0 ucon u0irs, u1irs select the source of uart0/uart1 transmit interrupt u0rrm, u1rrm set this bit to 1 to use continuous receive mode clkmd0 select the transfer clock output pin when clkmd1 = 1 clkmd1 set this bit to 1 to output uart1 transfer clock from two pins rcsp _________ set this bit to 1 to accept as input the uart0 cts 0 signal from the p6 4 pin or p7 0 pin 7 set to 0 note 1: set bit 4 and bit 5 in the u0c1 and u1c1 register are set to 0 . the u0irs, u1irs, u0rrm and u1rrm bits are in the ucon register. note 2: not all register bits are described above. set those bits to 0 when writing to the registers in clock synchronous serial i/o mode. note 3: set the bit 6 and bit 7 in the u0c1 and u1c1 register to "0". note 4: set the bit 7 in the u0mr and u1mr register to "0". i=0 to 2
13. serial i/o page 139 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m table 13.1.1.3 lists the functions of the input/output pins during clock synchronous serial i/o mode. table 13.3 shows pin functions for the case where the multiple transfer clock output pin select function is dese- lected. table 13.1.1.4 lists the p6 4 pin functions during clock synchronous serial i/o mode. note that for a period from when the uarti operation mode is selected to when transfer starts, the txdi pin outputs an h . (if the n-channel open-drain output is selected, this pin is in a high-impedance state.) table 13.1.1.3. pin functions(note 1) ( when not select multiple transfer clock output pin function ) pin name function method of selection txdi (i = 0 to 2) (p6 3 , p6 7 , p7 0 ) serial data output serial data input transfer clock output transfer clock input i/o port (outputs dummy data when performing reception only) rxdi (p6 2 , p6 6 , p7 1 ) clki (p6 1 , p6 5 , p7 2 ) set the ckdir bit in the uimr register to "0" set the ckdir bit in the uimr register to "1" set the pd6_1 bit and pd6_5 bit in the pd6 register, and the pd7_2 bit in the pd7 register to "0" set the pd6_2 bit and pd6_6 bit in the pd6 register, and pd7_1 bit in the pd7 register to "0"(can be used as an input port when performing transmission only) set the crd bit in the uic0 register to "0" set the crs bit in the uic0 register to "0" set the pd6_0 bit and pd6_4 bit in the pd6 register is set to "0", the pd7_3 bit in the pd7 register to "0" set the crd bit in the uic0 register to "0" set the crs bit in the uic0 register to "1" set the crd bit in the uic0 register to "1" cts input rts output ctsi/rtsi (p6 0 , p6 4 , p7 3 ) note 1: when the u1map bit in pacr register is 1 (p7 3 to p7 0 ), uart1 pin is assgined to p7 3 to p7 0 . pin function bit set value u1c0 register ucon register pd6 register crd crs rcsp clkmd1 clkmd0 pd6_4 p6 4 1 0 0 input: 0, output: 1 cts 1 0 00 0 rts 1 1 00 cts 0 (note2) 0 clks 1 0 0 00 1 0 1(note 3) 1 note 1: when the u1map bit in pacr register is 1 (p7 3 to p7 0 ), this table lists the p7 0 functions. note 2: in addition to this, set the crd bit in the u0c0 register to 0 (ct0 0 /rt0 0 enabled) and the crs bit in the u0c0 register to 1 (rts 0 selected). note 3: when the clkmd1 bit is set to "1" and the clkmd0 bit is set to "0", the following logiclevels are output: ? high if the clkpol bit in the u1c0 register is set to "0" ? low if the clkpol bit in the u1c0 register is set to "1" table 13.1.1.4. p6 4 pin functions(note 1)
13. serial i/o page 140 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 tc t clk stopped pulsing because the te bit = 0 write data to the uitb register tc = t clk = 2(n + 1) / fj fj: frequency of uibrg count source (f 1sio , f 2sio , f 8sio , f 32sio ) n: value set to uibrg register i: 0 to 2 transfer clock uic1 register te bit uic1 register ti bit clki txdi h l 0 1 0 1 0 1 ctsi 0 1 stopped pulsing because ctsi = h 1 / f ext write dummy data to uitb register uic1 register te bit uic1 register ti bit clki rxdi uic1 register ri bit rtsi h l 0 1 0 1 0 1 uic1 register re bit 0 1 receive data is taken in transferred from uitb register to uarti transmit register read out from uirb register transferred from uarti receive register to uirb register siric register ir bit 0 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 transferred from uitb register to uarti transmit register make sure the following conditions are met when input to the clki pin before receiving data is high: ? te bit in the uic0 register is set to "1" (transmit enabled) ? re bit in the uic0 register is set to "1" (receive enabled) ? write dummy data to the uitb register the above timing diagram applies to the case where the register bits are set as follows: ? ckdir bit in the uimr register is set to "0"(internal clock) ? crd bit in the uic0 register is set to "0" (cts/rts enabled), crs bit to "0" (cts selected) ? ckpol bit in the uic0 register is set to "0" (transmit data output at the falling edge and receive data taken in at the rising edge of the transfer clock) ? uiirs bit is set to "0" (an interrupt request occurs when the transmit buffer becomes empty): u0irs bit is the ucon register b it 0, u1irs bit is the ucon register bit 1, and u2irs bit is the u2c1 register bit 4 cleared to 0 when interrupt request is accepted, or cleared to 0 in a program cleared to 0 when interrupt request is accepted, or cleared to 0 in a program the above timing diagram applies to the case where the register bits are set as follows: ? ckdir bit in the uimr register is set to "1" (external clock) ? crd bit in the uic0 register is set to "0" (cts/rts enabled), crs bit to "1" (rts selected) ? ckpol bit in the uic0 register is set to "0" (transmit data output at the falling edge and receive data taken in at the rising edge o f the trans f er clock) uic0 register txept bit sitic register ir bit even if the reception is completed, the rts does not change. the rts becomes l when the ri bit changes to 0 from 1 . (1) example of transmit timing (2) example of receive timing figure 13.1.1.1. typical transmit/receive timings in clock synchronous serial i/o mode
13. serial i/o page 141 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 13.1.1.1 counter measure for communication error occurs if a communication error occurs while transmitting or receiving in clock synchronous serial i/o mode, follow the procedures below. ? resetting the uirb register (i=0 to 2) (1) set the re bit in the uic1 register to 0 (reception disabled) (2) set the smd2 to smd0 bits in the uimr register to 000b (serial i/o disabled) (3) set the smd2 to smd0 bits in the uimr register to 001b (clock synchronous serial i/o mode) (4) set the re bit in the uic1 register to 1 (reception enabled) ? resetting the uitb register (i=0 to 2) (1) set the smd2 to smd0 bits in the uimr register to 000b (serial i/o disabled) (2) set the smd2 to smd0 bits in the uimr register to 001b (clock synchronous serial i/o mode) (3) 1 is written to re bit in the uic1 register (reception enabled), regardless to the te bit in the uic1 register. 13.1.1.2 clk polarity select function use the ckpol bit in the uic0 register (i = 0 to 2) to select the transfer clock polarity. figure 13.1.1.2.1 shows the polarity of the transfer clock. figure 13.1.1.2.1. polarity of transfer clock (2) when the ckpol bit in the uic0 register is set to "1" (transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock) d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 0 t x d i r x d i clk i (1) when the ckpol bit in the uic0 register is set to "0" (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock) d 1 d 2 d 3 d 4 d 5 d 6 d 7 d0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 t x d i r x d i clk i note 1: this applies to the case where the uform bit in the uic0 register is set to "0" ( lsb first) and the uilch bit in the uic1 register is set to "0" (no reverse). note 2: when not transferring, the clki pin outputs a high signal. note 3: when not transferring, the clki pin outputs a low signal. i = 0 to 2 (note 2) (note 3)
13. serial i/o page 142 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 13.1.1.3 lsb first/msb first select function use the uform bit in the uic0 register (i = 0 to 2) to select the transfer format. figure 13.1.1.3.1 shows the transfer format. figure 13.1.1.3.1 transfer format 13.1.1.4 continuous receive mode when the uirrm bit (i = 0 to 2) is set to "1" (continuous receive mode), the ti bit in the uic1 register is set to 0 (data present in the uitb register) by reading the uirb register. in this case, i.e., uirrm bit is set to "1", do not write dummy data to the uitb register in a program. the u0rrm and u1rrm bits are the bit 2 and bit 3 in the ucon register, respectively, and the u2rrm bit is the bit 5 in the u2c1 register. (1) when the uform bit in the uic0 register "0" (lsb first) d0 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 1 d 2 d 3 d 4 d 5 d 6 d 7 t x d i r x d i clk i (2) when the uform bit in the uic0 register is set to "1" (msb first) d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 t x d i r x d i clk i note: this applies to the case where the ckpol bit in the uic0 register is set to "0" (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock) and the uilch bit in the uic1 register "0" (no reverse). i = 0 to 2
13. serial i/o page 143 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 13.1.1.4.1. serial data logic switch timing d0 d1 d2 d3 d4 d5 d6 d7 transfer clock txd 2 (no reverse) h l h l txd 2 (reverse) d0 d1 d2 d3 d4 d5 d6 d7 h l (1) when the u2lch bit in the u2c1 register is set to "0" (no reverse) transfer clock h l (2) when the u2lch bit in the u2c1 register is set to "1" (reverse) note: this applies to the case where the ckpol bit in the u2c0 register is set to "0" (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock) and the uform bit is set to "0" (lsb first). 13.1.1.6 transfer clock output from multiple pins function (uart1) the clkmd1 to clkmd0 bits in the ucon register can choose one from two transfer clock output pins. (see figure 13.1.1.6.1) this function is valid when the internal clock is selected for uart1. figure 13.1.1.6.1 transfer clock output from multiple pins 13.1.1.5 serial data logic switch function (uart2) when the u2lch bit in the u2c1 register is set to "1" (reverse), the data written to the u2tb register has its logic reversed before being transmitted. similarly, the received data has its logic reversed when read from the u2rb register. figure 13.1.1.4.1 shows serial data logic. microcomputer t x d 1 (p6 7 ) clks 1 (p6 4 ) clk 1 (p6 5 ) in clk in clk note 1: this applies to the case where the ckdir bit in the u1mrregister is set to "0" (internal clock) and the clkmd1 bit in the ucon register is set to "1" (transfer clock output from multiple pins). note 2: this applies to the case where u1map bit in pacr register is set to 0 (p6 7 to p6 4 ). transfer enabled when the clkmd0 bit in the ucon register is set to "0" transfer enabled when the clkmd0 bit in the ucon register is set to "1"
13. serial i/o page 144 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m _______ _______ 13.1.1.7 cts/rts separate function (uart0) _______ _______ _______ _______ this function separates cts 0 /rts 0 , outputs rts 0 from the p6 0 pin, and accepts as input the cts 0 from the p6 4 pin. to use this function, set the register bits as shown below. _______ _______ ? the crd bit in the u0c0 register is set to "0" (enables uart0 cts/rts) _______ ? the crs bit in the u0c0 register is set to "1" (outputs uart0 rts) _______ _______ ? the crd bit in the u1c0 register is set to "0" (enables uart1 cts/rts) _______ ? the crs bit in the u1c0 register is set to "0" (inputs uart1 cts) _______ ? the rcsp bit in the ucon register is set to "1" (inputs cts 0 from the p6 4 pin) ? the clkmd1 bit in the ucon register is set to "0" (clks 1 not used) _______ _______ _______ _______ note that when using the cts/rts separate function, uart1 cts/rts separate function cannot be used. figure 13.1.1.7.1. cts/rts separate function usage microcomputer t x d 0 (p6 3 ) r x d 0 (p6 2 ) in out cts rts cts 0 (p6 4 ) rts 0 (p6 0 ) ic clk 0 (p6 1 ) clk note 1: this applies to the case where u1map bit in pacr register is set to 0 (p6 7 to p6 4 ).
13. serial i/o page 145 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m item specification transfer data format ? character bit (transfer data): selectable from 7, 8 or 9 bits ? start bit: 1 bit ? parity bit: selectable from odd, even, or none ? stop bit: selectable from 1 or 2 bits transfer clock ? the ckdir bit in the uimr(i=0 to 2) register is set to "0" (internal clock) : fj/(16(n+1)) fj = f 1sio , f 2sio , f 8sio , f 32sio . n: setting value of uibrg register 00 16 to ff 16 ? ckdir bit is set to 1 (external clock ) : f ext /(16(n+1)) f ext : input from clki pin. n :setting value of uibrg register 00 16 to ff 16 transmission, reception control _______ _______ _______ _______ ? selectable from cts function, rts function or cts/rts function disable transmission start condition ? before transmission can start, the following requirements must be met _ the te bit in the uic1 register is set to "1" (transmission enabled) _ the ti bit in the uic1 register "0" (data present in uitb register) _______ _______ _ if cts function is selected, input l to the ctsi pin reception start condition ? before reception can start, the following requirements must be met _ the re bit in the uic1 register is set to "1" (reception enabled) _ start bit detection ? for transmission, one of the following conditions can be selected _ the uiirs bit (note 2) is set to "0" (transmit buffer empty): when transferring data from the uitb register to the uarti transmit register (at start of transmission) _ the uiirs bit is set to "1" (transfer completed): when the serial i/o finished sending data from the uarti transmit register ? for reception when transferring data from the uarti receive register to the uirb register (at completion of reception) error detection ? overrun error (note 1) this error occurs if the serial i/o started receiving the next data before reading the uirb register and received the bit one before the last stop bit of the next data ? framing error this error occurs when the number of stop bits set is not detected ? parity error this error occurs when if parity is enabled, the number of 1 s in parity and character bits does not match the number of 1 s set ? error sum flag this flag is set (= 1) when any of the overrun, framing, and parity errors is encountered select function ? lsb first, msb first selection whether to start sending/receiving data beginning with bit 0 or beginning with bit 7 can be selected ? serial data logic switch (uart2) this function reverses the logic of the transmit/receive data. the start and stop bits are not reversed. ? t x d, r x d i/o polarity switch (uart2) this function reverses the polarities of hte t x d pin output and r x d pin input. the logic levels of all i/o data is reversed. _______ _______ ? separate cts/rts pins (uart0) _________ _________ cts 0 and rts 0 are input/output from separate pins ? uart1 pin remapping selection the uart1 pin can be selected from the p6 7 to p6 4 or p7 3 to p7 0 . note 1: if an overrun error occurs, the value of uirb register will be indeterminate. the ir bit in the siric register does not change . note 2: the u0irs and u1irs bits respectively are the bits "0" and "1" in the ucon register; the u2irs bit is the bit 4 in the u2c1 reg ister. 13.1.2. clock asynchronous serial i/o (uart) mode the uart mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. tables 13.1.2.1 lists the specifications of the uart mode. interrupt request generation timing table 13.1.2.1. uart mode specifications
13. serial i/o page 146 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m table 13.1.2.2. registers to be used and settings in uart mode register bit function uitb 0 to 8 set transmission data (note 1) uirb 0 to 8 reception data can be read (note 1) oer,fer,per,sum error flag uibrg 0 to 7 set a transfer rate uimr smd2 to smd0 set these bits to 100 2 when transfer data is 7 bits long set these bits to 101 2 when transfer data is 8 bits long set these bits to 110 2 when transfer data is 9 bits long ckdir select the internal clock or external clock stps select the stop bit pry, prye select whether parity is included and whether odd or even iopol(i=2)(note 4) select the txd/rxd input/output polarity uic0 clk0, clk1 select the count source for the uibrg register crs _______ _______ select cts or rts to use txept transmit register empty flag crd _______ _______ enable or disable the cts or rts function nch select txdi pin output mode ckpol set to 0 uform lsb first or msb first can be selected when transfer data is 8 bits long. set this bit to 0 when transfer data is 7 or 9 bits long. uic1 te set this bit to 1 to enable transmission ti transmit buffer empty flag re set this bit to 1 to enable reception ri reception complete flag u2irs (note 2) select the source of uart2 transmit interrupt u2rrm (note 2) set to 0 u2lch (note 3) set this bit to 1 to use uart2 inverted data logic u2ere (note 3) set to 0 u2smr 0 to 7 set to 0 u2smr2 0 to 7 set to 0 u2smr3 0 to 7 set to 0 u2smr4 0 to 7 set to 0 ucon u0irs, u1irs select the source of uart0/uart1 transmit interrupt u0rrm, u1rrm set to 0 clkmd0 invalid because clkmd1 = 0 clkmd1 set to 0 rcsp _________ set this bit to 1 to accept as input the uart0 cts 0 signal from the p6 4 pin or p7 0 pin 7 set to 0 note 1: the bits used for transmit/receive data are as follows: bit 0 to bit 6 when transfer data is 7 bits long; bit 0 to bit 7 when transfer data is 8 bits long; bit 0 to bit 8 when transfer data is 9 bits long. note 2: set the bit 4 to bit 5 in the u0c1 and u1c1 registers to 0 . the u0irs, u1irs, u0rrm and u1rrm bits are included in the ucon register. note 3: set the bit 6 to bit 7 in the u0c1 and u1c1 registers to 0 . note 4: set the bit 7 the u0mr and u1mr registers to 0 . i=0 to 2
13. serial i/o page 147 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m table 13.1.2.3 lists the functions of the input/output pins during uart mode. table 13.1.2.4 lists the p6 4 pin functions during uart mode. note that for a period from when the uarti operation mode is selected to when transfer starts, the txdi pin outputs an h . (if the n-channel open-drain output is selected, this pin is in a high-impedance state.) table 13.1.2.3. i/o pin functions in uart mode(note 1) pin name function method of selection txdi (i = 0 to 2) (p6 3 , p6 7 , p7 0 ) serial data output serial data input input/output port transfer clock input input/output port (outputs "h" when performing reception only) rxdi (p6 2 , p6 6 , p7 1 ) clki (p6 1 , p6 5 , p7 2 ) set the ckdir bit in the uimr register to "0" set the ckdir bit in the uimr register to "1" set the pd6_1 bit and pd6_5 bit in the pd6 register to "0", pd7_2 bit in the pd7 register to "0" pd6_2 bit, pd6_6 bit in the pd6 register and the pd7_1 bit in the pd7 register (can be used as an input port when performing transmission only) set the crd bit in the uic0 register to "0" set the crs bit in the uic0 register to "0" set the pd6_0 bit and pd6_4 bit in the pd6 register to "0", the pd7_3 bit in the pd7 register "0" set the crd bit in the uic0 register to "0" set the crs bit in the uic0 register to "1" set the crd bit in the uic0 register "1" cts input rts output ctsi/rtsi (p6 0 , p6 4 , p7 3 ) note 1: when the u1map bit in pacr register is set to 1 (p7 3 to p7 0 ), uart1 pin is assgined to p7 3 to p7 0 . table 13.1.2.4. p6 4 pin functions in uart mode(note 1) pin function bit set value u1c0 register ucon register pd6 register crd crs rcsp clkmd1 pd6_4 p6 4 1 0 0 input: 0, output: 1 cts 1 0000 rts 1 10 0 cts 0 (note 2) 0 0 0 00 1 0 note 1: when the u1map bit in pacr register is 1 (p7 3 to p7 0 ), this table lists the p7 0 functions. note 2: in addition to this, set the crd bit in the u0c0 register to 0 (cts 0 /rts 0 enabled) and the crs bit in the u0c0 register to 1 (rts 0 selected).
13. serial i/o page 148 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 13.1.2.1. typical transmit timing in uart mode (uart0, uart1) start bit parity bit txdi ctsi 1 0 1 l h 0 1 tc = 16 (n + 1) / fj or 16 (n + 1) / f ext fj : frequency of uibrg count source (f 1sio , f 2sio , f 8sio , f 32sio ) f ext : frequency of uibrg count source (external clock) n : value set to uibrg i: 0 to 2 0 1 txdi 0 1 0 1 0 1 transfer clock tc 0 1 tc transfer clock d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 sp st p sp d 0 d 1 st stop bit start bit the transfer clock stops momentarily as ctsi is h when the stop bit is checked. the transfer clock starts as the transfer starts immediately ctsi changes to l . d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st sp d 8 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st d 8 d 0 d 1 st sp sp stop bit stop bit 0 sp stopped pulsing because the te bit = 0 write data to the uitb register uic1 register te bit uic1 register ti bit uic0 register txept bit sitic register ir bit transferred from uitb register to uarti transmit register the above timing diagram applies to the case where the register bits are set as follows: ? set the prye bit in the uimr register to "1" (parity enabled) ? set the stps bit in the uimr register to "0" (1 stop bit) ? set the crd bit in the uic0 register to "0" (cts/rts enabled), the crs bit to "0" (cts selected) ? set the uiirs bit to "1" (an interrupt request occurs when transmit completed): u0irs bit is the ucon register bit 0, u1irs bit is the ucon register bit 1, and u2irs bit is the u2c1 register bit 4 cleared to 0 when interrupt request is accepted, or cleared to 0 in a program uic1 register te bit uic1 register ti bit uic0 register txept bit sitic register ir bit cleared to 0 when interrupt request is accepted, or cleared to 0 in a program write data to the uitb register transferred from uitb register to uarti transmit register tc = 16 (n + 1) / fj or 16 (n + 1) / f ext fj : frequency of uibrg count source (f 1sio , f 2sio , f 8sio , f 32sio ) f ext : frequency of uibrg count source (external clock) n : value set to uibrg i: 0 to 2 the above timing diagram applies to the case where the register bits are set as follows: ? set the prye bit in the uimr register to "0" (parity disabled) ? set the stps bit in the uimr register to "1" (2 stop bits) ? set the crd bit in the uic0 register to "1"(cts/rts disabled) ? set the uiirs bit to "0" (an interrupt request occurs when transmit buffer becomes empty): u0irs bit is the ucon register bit 0, u1irs bit is the ucon register bit 1, and u2irs bit is the u2c1 register bit 4 ? example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) ? example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)
13. serial i/o page 149 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m ? example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) figure 13.1.2.2. receive operation d 0 start bit sampled l uibrg count source rxdi transfer clock rtsi stop bit 1 0 0 1 h l 0 1 reception triggered when transfer clock is generated by falling edge of start bit uic1 register re bit uic1 register ri bit siric register ir bit cleared to 0 when interrupt request is accepted, or cleared to 0 in a program receive data taken in d 7 d 1 transferred from uarti receive register to uirb register the above timing diagram applies to the case where the register bits are set as follows: ? set the prye bit in the uimr register to "0"(parity disabled) ? set the stps bit in the uimr register to "0" (1 stop bit) ? set the crd bit in the uic0 register to "0" (ctsi/rtsi enabled), the crs bit to "1" (rtsi selected) i = 0 to 2 13.1.2.1. bit rates in uart mode, the frequency set by the uibrg register (i=0 to 2) divided by 16 become the bit rates. table 13.1.2.1.1 lists example of bit rate and settings. table 13.1.2.1.1 example of bit rates and settings bit rate count source peripheral function clock : 16mhz peripheral function clock : 20mhz (bps) of brg set value of brg : n actual time (bps) set value of brg : n actual time (bps) 1200 f8 103(67h) 1202 129(81h) 1202 2400 f8 51(33h) 2404 64(40h) 2404 4800 f8 25(19h) 4808 32(20h) 4735 9600 f1 103(67h) 9615 129(81h) 9615 14400 f1 68(44h) 14493 86(56h) 14368 19200 f1 51(33h) 19231 64(40h) 19231 28800 f1 34(22h) 28571 42(2ah) 29070 31250 f1 31(1fh) 31250 39(27h) 31250 38400 f1 25(19h) 38462 32(20h) 37879 51200 f1 19(13h) 50000 24(18h) 50000
13. serial i/o page 150 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 13.1.2.3.1. transfer format (1) when the uform bit in the uic0 register is set to "0" (lsb first) (2) when the uform bit in the uic0 register "1" (msb first) note: this applies to the case where the ckpol bit in the uic0 register is set to "0" (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the uilch bit in the uic1 register is set to "0" (no reverse), the stps bit in the uimr register is set to "0" (1 stop bit) and the prye bit in the uimr register is set to "1" (parity enabled). d 1 d 2 d 3 d 4 d 5 d 6 sp d0 d 1 d 2 d 3 d 4 d 5 d 6 sp d 0 t x d i r x d i clk i d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 t x d i r x d i clk i st st d 7 p d 7 p sp sp st st p p d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 st : start bit p : parity bit sp : stop bit i = 0 to 2 13.1.2.2. counter measure for communication error if a communication error occurs while transmitting or receiving in uart mode, follow the procedure below. ? resetting the uirb register (i=0 to 2) (1) set the re bit in the uic1 register to 0 (reception disabled) (2) set the re bit in the uic1 register to 1 (reception enabled) ? resetting the uitb register (i=0 to 2) (1) set the smd2 to smd0 bits in uimr register 000b (serial i/o disabled) (2) set the smd2 to smd0 bits in uimr register 001b , 101b , 110b (3) 1 is written to re bit in the uic1 register (reception enabled), regardless of the te bit in the uic1 register 13.1.2.3. lsb first/msb first select function as shown in figure 14.1.2.3.1, use the uform bit in the uic0 register to select the transfer format. this function is valid when transfer data is 8 bits long.
13. serial i/o page 151 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 13.1.2.5. txd and rxd i/o polarity inverse function (uart2) this function inverses the polarities of the t x d2 pin output and r x d2 pin input. the logic levels of all input/output data (including the start, stop and parity bits) are inversed. figure 13.1.2.5.1 shows the t x d pin output and r x d pin input polarity inverse. figure 13.1.2.5.1. t x d and r x d i/o polarity inverse 13.1.2.4. serial data logic switching function (uart2) the data written to the u2tb register has its logic reversed before being transmitted. similarly, the received data has its logic reversed when read from the u2rb register. figure 13.1.2.4.1 shows serial data logic. figure 13.1.2.4.1. serial data logic switching transfer clock h l d0 d1 d2 d3 d4 d5 d6 d7 p sp st txd 2 (no reverse) h l txd 2 (reverse) sp st d3 d4 d5 d6 d7 p d0 d1 d2 h l (1) when the u2lch bit in the u2c1 register is set to "0" (no reverse) (2) when the u2lch bit in the u2c1 register is set "1" (reverse) transfer clock h l note: this applies to the case where the ckpol bit in the u2c0 register is set to "0" (transmit data output at the falling edge of the transfer clock), the uform bit in the u2c0 register is set to "0" (lsb first), the stps bit in the u2mr register is set to "0" (1 stop bit) and the prye bit in the u2mr register is set to "1" (parity enabled). st : start bit p : parity bit sp : stop bit (1) when the iopol bit in the u2mr register is set to "0" (no reverse) (2) when the iopol bit in the u2mr register is set to "1" (reverse) note: this applies to the case where the uform bit in the u2c0 register is set to "0"(lsb first), the stps bit in the u2mr register is set to "0 " (1 stop bit) and the prye bit in the u2mr register is set to "1"( parity enabled). st : start bit p : parity bit sp : stop bit d0 d1 d2 d3 d4 d5 d6 d7 p sp st sp st d3 d4 d5 d6 d7 p d0 d1 d2 d0 d1 d2 d3 d4 d5 d6 d7 p sp st h sp st d3 d4 d5 d6 d7 p d0 d1 d2 transfer clock txd 2 (no reverse) rxd 2 (no reverse) transfer clock txd 2 (reverse) rxd 2 (reverse) l h l h l h l h l h l
13. serial i/o page 152 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m _______ _______ 13.1.2.6. cts/rts separate function (uart0) _______ _______ _______ _______ this function separates cts 0 /rts 0 , outputs rts 0 from the p6 0 pin, and accepts as input the cts 0 from the p6 4 pin. to use this function, set the register bits as shown below. _______ _______ ? set the crd bit in the u0c0 register to "0" (enables uart0 cts/rts) _______ ? set the crs bit in the u0c0 register to "1"(outputs uart0 rts) _______ _______ ? set the crd bit in the u1c0 register to "0" (enables uart1 cts/rts) _______ ? set the crs bit in the u1c0 register to "0" (inputs uart1 cts) _______ ? set the rcsp bit in the ucon register to "1" (inputs cts 0 from the p6 4 pin) ? set the clkmd1 bit in the ucon register to "0" (clks 1 not used) _______ _______ _______ _______ note that when using the cts/rts separate function, uart1 cts/rts separate function cannot be used. _______ _______ figure 13.1.2.6.1. cts/rts separate function microcomputer t x d 0 (p6 3 ) r x d 0 (p6 2 ) in out cts rts cts 0 (p6 4 ) rts 0 (p6 0 ) ic note 1: this applies to the case where u1map bit in pacr register is set to 0 (p6 7 to p6 4 ).
13. serial i/o page 153 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 13.1.3 special mode 1 (i 2 c bus mode)(uart2) i 2 c bus mode is provided for use as a simplified i 2 c bus interface compatible mode. table 13.1.3.1 lists the specifications of the i 2 c bus mode. table 13.1.3.2 and 13.1.3.3 list the registers used in the i 2 c bus mode and the register values set. table 13.1.3.4 lists the i 2 c bus mode fuctions. figure 13.1.3.1 shows the block diagram for i 2 c bus mode. figure 13.1.3.2 shows scl 2 timing. as shown in table 13.1.3.2, the microcomputer is placed in i 2 c bus mode by setting the smd2 to smd0 bits to 010 2 and the iicm bit to 1 . because sda 2 transmit output has a delay circuit attached, sda output does not change state until scl 2 goes low and remains stably low. table 13.1.3.1. i 2 c bus mode specifications item specification transfer data format ? transfer data length: 8 bits transfer clock ? during master the ckdir bit in the u2mr register is set to 0 (internal clock) : fj/ (2(n+1)) fj = f 1sio , f 2sio , f 8sio , f 32sio . n: setting value in the u2brg register 00 16 to ff 16 ? during slave the ckdir bit is set to 1 (external clock ) : input from scl pin transmission start condition ? before transmission can start, the following requirements must be met (note 1) _ the te bit in the u2c1 register is set to "1" (transmission enabled) _ the ti bit in the u2c1 register is set to "0" (data present in u2tb register) reception start condition ? before reception can start, the following requirements must be met (note 1) _ the re bit in the u2c1 register is set to "1" (reception enabled) _ the te bit in the u2c1 register is set to "1" (transmission enabled) _ the ti bit in the u2c1 register is set to "0" (data present in the uitb register) when start or stop condition is detected, acknowledge undetected, and acknowledge detected error detection ? overrun error (note 2) this error occurs if the serial i/o started receiving the next data before reading the u2rb register and received the 8th bit of the next data select function ? arbitration lost timing at which the abt bit in the u2rb register is updated can be selected ? sda2 digital delay no digital delay or a delay of 2 to 8 u2brg count source clock cycles selectable ? clock phase setting with or without clock delay selectable note 1: when an external clock is selected, the conditions must be met while the external clock is in the high state. note 2: if an overrun error occurs, the value in the u2rb register will be indeterminate. the ir bit in the s2ric register does not change . interrupt request generation timing
13. serial i/o page 154 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m clk control falling edge detection external clock internal clock start/stop condition detection interrupt request start condition detection stop condition detection reception register bus busy transmission register arbitration noise filter sda2 scl2 uart2 d t q d t q d t q nack ack uart2 uart2 uart2 r uart2 transmit, nack interrupt request uart2 receive, ack interrupt request, dma1 request iicm=1 and iicm2=0 s r q als r s swc iicm=1 and iicm2=0 iicm2=1 iicm2=1 swc2 sdhi dma0, dma1 request noise filter iicm : bit in the u2smr iicm2, swc, als, swc2, sdhi : bits in the u2smr2 stspsel, ackd, ackc : bits in the u2smr4 iicm=0 iicm=1 dma0 stspsel=0 stspsel=1 stspsel=1 stspsel=0 sda stsp scl stsp ackc=1 ackc=0 q port register (note) i/o port 9th bit falling edge 9th bit ackd bit delay circuit this diagram applies to the case where the smd2 to smd0 bits in the the u2mr register is set to "010 2 " and the iicm bit in the u2smr register is set to "1". note: if the iicm bit is set to "1", the pin can be read even when the pd7_1 bit is set to "1" (output mode). start and stop condition generation block figure 13.1.3.1. i 2 c bus mode block diagram
13. serial i/o page 155 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m table 13.1.3.2. registers to be used and settings in i 2 c bus mode (1) (continued) register bit function master slave u2tb 0 to 7 set transmission data set transmission data (note 1) u2rb 0 to 7 reception data can be read reception data can be read (note 1) 8 ack or nack is set in this bit ack or nack is set in this bit abt arbitration lost detection flag invalid oer overrun error flag overrun error flag u2brg 0 to 7 set a transfer rate invalid u2mr smd2 to smd0 set to 010 2 set to 010 2 (note 1) ckdir set to 0 set to 1 iopol set to 0 set to 0 u2c0 clk1, clk0 select the count source for the u2brg invalid register crs invalid because crd = 1 invalid because crd = 1 txept transmit buffer empty flag transmit buffer empty flag crd set to 1 set to 1 nch set to 1 set to 1 ckpol set to 0 set to 0 uform set to 1 set to 1 u2c1 te set this bit to 1 to enable transmission set this bit to 1 to enable transmission ti transmit buffer empty flag transmit buffer empty flag re set this bit to 1 to enable reception set this bit to 1 to enable reception ri reception complete flag reception complete flag u2irs invalid invalid u2rrm, set to 0 set to 0 u2lch, u2ere u2smr iicm set to 1 set to 1 abc select the timing at which arbitration-lost invalid is detected bbs bus busy flag bus busy flag 3 to 7 set to 0 set to 0 u2smr2 iicm2 refer to table 13.1.3.4 i 2 c bus mode functions refer to table 13.1.3.4 i 2 c bus mode functions csc set this bit to 1 to enable clock set to 0 synchronization swc set this bit to 1 to have scl 2 output set this bit to 1 to have scl 2 output fixed to l at the falling edge of the 9th fixed to l at the falling edge of the 9 th bit of clock bit of clock als set this bit to 1 to have sda 2 output set to 0 stopped when arbitration-lost is detected stac set to 0 set this bit to 1 to initialize uart2 at start condition detection swc2 set this bit to 1 to have scl 2 output set this bit to 1 to have scl 2 output forcibly pulled low forcibly pulled low sdhi set this bit to 1 to disable sda 2 output set this bit to 1 to disable sda 2 output 7 set to 0 set to 0 u2smr3 0, 2, 4 and nodc set to 0 set to 0 ckph refer to table 13.1.3.4 i 2 c bus mode functions refer to table 13.1.3.4 i 2 c bus mode functions dl2 to dl0 set the amount of sda 2 digital delay set the amount of sda 2 digital delay note 1: not all register bits are described above. set those bits to 0 when writing to the registers in i 2 c bus mode.
13. serial i/o page 156 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m u2smr4 stareq set this bit to 1 to generate start set to 0 condition rstareq set this bit to 1 to generate restart set to 0 condition stpreq set this bit to 1 to generate stop set to 0 condition stspsel set this bit to 1 to output each condition set to 0 ackd select ack or nack select ack or nack ackc set this bit to 1 to output ack data set this bit to 1 to output ack data sclhi set this bit to 1 to have scl2 output set to 0 stopped when stop condition is detected swc9 set to 0 set this bit to 1 to set the scl 2 to l hold at the falling edge of the 9th bit of clock register bit function master slave table 13.1.3.3. registers to be used and settings in i 2 c bus mode (2) (continued) note 1: not all bits in the register are described above. set those bits to 0 when writing to the registers in i 2 c bus mode.
13. serial i/o page 157 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m function i 2 c bus mode (smd2 to smd0 = 010 2 , iicm = 1) clock synchronous serial i/o mode (smd2 to smd0 = 001 2 , iicm = 0) factor of interrupt number 15 (note 1) (refer to fig. 13.1.3.2.) no acknowledgment detection (nack) rising edge of scl 2 9th bit factor of interrupt number 16 (note 1) (refer to fig. 13.1.3.2.) start condition detection or stop condition detection (refer to figure 13.1.3.2.1. stspsel bit function ) uart2 transmission output delay functions of p7 0 pin noise filter width read rxd2 and scl 2 pin levels factor of interrupt number 10 (note 1) (refer to fig. 13.1.3.2.) acknowledgment detection (ack) rising edge of scl 2 9th bit initial value of txd2 and sda 2 outputs uart2 transmission transmission started or completed (selected by u2irs) uart2 reception when 8th bit received ckpol = 0 (rising edge) ckpol = 1 (falling edge) not delayed txd2 output rxd2 input clk2 input or output selected 15ns possible when the corresponding port direction bit = 0 ckpol = 0 (h) ckpol = 1 (l) delayed sda 2 input/output scl 2 input/output (cannot be used in i 2 c mode) initial and end values of scl 2 h 200ns always possible no matter how the corresponding port direction bit is set the value set in the port register before setting i 2 c bus mode (note 2) timing for transferring data from the uart reception shift register to the u2rb registe r iicm2 = 0 (nack/ack interrupt) iicm2 = 1 (uart transmit/ receive interrupt) ckph = 1 (clock delay) ckph = 1 (clock delay) uart2 transmission rising edge of scl 2 9th bit uart2 transmission falling edge of scl 2 next to the 9th bit uart2 transmission falling edge of scl 2 9th bit ckpol = 0 (rising edge) ckpol = 1 (falling edge) rising edge of scl 2 9th bit falling edge of scl 2 9th bit falling and rising edges of scl 2 9th bit . . dma1 factor (refer to fig. 14.1.3.2.) uart2 reception acknowledgment detection (ack) uart2 reception falling edge of scl 2 9th bi t store received data 1st to 8th bits are stored in u2rb register bit 0 to bit 7 1st to 8th bits are stored in u2rb register bit 7 to bit 0 1st to 7th bits are stored in u2rb register bit 6 to bit 0, with 8th bit stored in u2rb register bit 8 l read u2rb register bit 6 to bit 0 as bit 7 to bit 1, and bit 8 as bit 0 (note 4) read received data u2rb register status is read directly as is ckph = 0 (no clock delay) ckph = 0 (no clock delay) h l 1st to 8th bits are stored in u2rb register bit 7 to bit 0 (note 3) functions of p7 1 pin functions of p7 2 pin note 1: if the source or cause of any interrupt is changed, the ir bit in the interrupt control register for the changed interrupt may inadvertently be set to 1 (interrupt requested). (refer to notes on interrupts in precautions.) if one of the bits shown below is changed, the interrupt source, the interrupt timing, etc. change. therefore, always be sure to clear the ir bit to 0 (interrupt not requested) after changing those bits. smd2 to smd0 bits in the u2mr register, iicm bit in the u2smr register, iicm2 bit in the u2smr2 register, ckph bit in the u2smr3 register note 2: set the initial value of sda 2 output while the smd2 to smd0 bits in the u2mr register is set to 000 2 (serial i/o disabled). note 3: second data transfer to u2rb register (rising edge of scl 2 9th bit) note 4. first data transfer to u2rb register (falling edge of scl 2 9th bit) table 13.1.3.4. i 2 c bus mode functions
13. serial i/o page 158 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 13.1.3.2. transfer to u2rb register and interrupt timing (4) when the iicm2 bit is set to "1" and the ckph bit is set to "1" (3) when the iicm2 bit is set to "1" (uart transmit or receive interrupt) and the ckph bit is set to "0" sda2 scl2 receive interrupt (dma request) transmit interrupt sda2 scl2 the above timing applies to the following setting : ? the ckdir bit in the u2mr register is set to "1" (slave) (1) when the iicm2 bit is set to "0" (ack or nack interrupt) and the ckph bit is set to "0" (no clock delay) d 6 d 5 d 4 d 3 d 2 d 1 d 8 (ack or nack) d 7 sda2 scl2 d 0 ack interrupt (dma request) or nack interrupt (2) when the iicm2 bit is set to "0" and the ckph bit is set to "1" (clock delay) sda2 scl2 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit b15 ??? b9 b8 b7 b0 d 8 contents of the u2rb register b15 ??? b9 b8 b7 b0 b15 ??? b9 b8 b7 b0 b15 ??? b9 b8 b7 b0 b15 ??? b9 b8 b7 b0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 6 d 5 d 4 d 3 d 2 d 1 d 7 d 0 ack interrupt (dma request) or nack interrupt d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 6 d 5 d 4 d 3 d 2 d 1 d 7 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 6 d 5 d 4 d 3 d 2 d 1 d 7 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 8 (ack or nack) 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit d 8 (ack or nack) 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit d 8 (ack or nack) 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit data is transferred to the u2rb register data is transferred to the u2rb register data is transferred to the u2rb register receive interrupt (dma request) transmit interrupt data is transferred to the u2rb register data is transferred to the u2rb register contents of the u2rb register contents of the u2rb register contents of the u2rb register contents of the u2rb register
13. serial i/o page 159 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 13.1.3.1 detection of start and stop condition whether a start or a stop condition has been detected is determined. a start condition-detected interrupt request is generated when the sda 2 pin changes state from high to low while the scl 2 pin is in the high state. a stop condition-detected interrupt request is generated when the sda 2 pin changes state from low to high while the scl 2 pin is in the high state. because the start and stop condition-detected interrupts share the interrupt control register and vec- tor, check the bbs bit in the u2smr register to determine which interrupt source is requesting the interrupt. setup time hold time scl2 sda2 (start condition) sda2 (stop condition) note: when the pclk1 bit in the pclkr register is set to "1", the cycles indicates the f1sio's generation frequency cycles; when pclk1 bit is set to "0", the cycles indicated the f2sio's generation frequency cycles. 3 to 6 cycles < setup time (note) 3 to 6 cycles < hold time (note) figure 13.1.3.1.1. detection of start and stop condition 13.1.3.2 output of start and stop condition a start condition is generated by setting the stareq bit in the u2smr4 register to 1 (start). a restart condition is generated by setting the rstareq bit in the u2smr4 register to 1 (start). a stop condition is generated by setting the stpreq bit in the u2smr4 register to 1 (start). the output procedure is described below. (1) set the stareq bit, rstareq bit or stpreq bit to 1 (start). (2) set the stspsel bit in the u2smr4 register to 1 (output). make sure that no interrupts or dma transfers will occur between (1) and (2). the function of the stspsel bit is shown in table 13.1.3.2.1 and figure 13.1.3.2.1.
13. serial i/o page 160 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m table 13.1.3.2.1. stspsel bit functions figure 13.1.3.2.1. stspsel bit functions function output of scl2 and sda2 pins start/stop condition interrupt request generation timing stspsel = 0 output transfer clock and data/ program with a port determines how the start condition or stop condition is output start/stop condition are de- tected stspsel = 1 the stareq, rstareq and stpreq bit determine how the start condition or stop condition is output start/stop condition generation are completed 4%" 4ubsudpoejujpoefufdujpo joufssvqu 4upqdpoejujpoefufdujpo joufssvqu
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4514&-cju 4514&-cju 4fuupcz bqsphsbn 4fuupcz bqsphsbn 4fuupcz bqsphsbn 4fuupcz bqsphsbn tu oe se ui ui ui ui uicju tu oe se ui ui ui ui uicju ui ui 13.1.3.3 arbitration unmatching of the transmit data and sda 2 pin input data is checked synchronously with the rising edge of scl 2 . use the abc bit in the u2smr register to select the timing at which the abt bit in the u2rb register is updated. if the abc bit is set to "0" (updated bitwise), the abt bit is set to 1 at the same time unmatching is detected during check, and is cleared to 0 when not detected. in cases when the abc bit is set to 1 , if unmatching is detected even once during check, the abt bit is set to 1 (unmatching detected) at the falling edge of the clock pulse of 9th bit. if the abt bit needs to be updated bytewise, clear the abt bit to 0 (undetected) after detecting acknowledge in the first byte, before transferring the next byte. setting the als bit in the u2smr2 register to 1 (sda output stop enabled) causes arbitration-lost to occur, in which case the sda 2 pin is placed in the high-impedance state at the same time the abt bit is set to 1 (unmatching detected).
13. serial i/o page 161 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 13.1.3.4 transfer clock data is transmitted/received using a transfer clock like the one shown in figure 13.1.3.2.1. the csc bit in the u2smr2 register is used to synchronize the internally generated clock (internal scl2) and an external clock supplied to the scl 2 pin. in cases when the csc bit is set to 1 (clock synchronization enabled), if a falling edge on the scl 2 pin is detected while the internal scl 2 is high, the internal scl 2 goes low, at which time the u2brg register value is reloaded with and starts count- ing in the low-level interval. if the internal scl 2 changes state from low to high while the scl 2 pin is low, counting stops, and when the scl 2 pin goes high, counting restarts. in this way, the uart2 transfer clock is comprised of the logical product of the internal scl 2 and scl 2 pin signal. the transfer clock works from a half period before the falling edge of the internal scl 2 1st bit to the rising edge of the 9 th bit. to use this function, select an internal clock for the transfer clock. the swc bit in the u2smr2 register allows to select whether the scl 2 pin should be fixed to or freed from low-level output at the falling edge of the 9th clock pulse. if the sclhi bit in the u2smr4 register is set to 1 (enabled), scl 2 output is turned off (placed in the high-impedance state) when a stop condition is detected. setting the swc2 bit in the u2smr2 register is set to "1" (0 output) makes it possible to forcibly output a low-level signal from the scl 2 pin even while sending or receiving data. clearing the swc2 bit to 0 (transfer clock) allows the transfer clock to be output from or supplied to the scl 2 pin, instead of outputting a low-level signal. if the swc9 bit in the u2smr4 register is set to 1 (scl hold low enabled) when the ckph bit in the u2smr3 register is set to "1", the scl 2 pin is fixed to low-level output at the falling edge of the clock pulse next to the ninth. setting the swc9 bit is set to "0" (scl hold low disabled) frees the scl 2 pin from low-level output. 13.1.3.5 sda output the data written to the bit 7 to bit 0 (d 7 to d 0 ) in the u2tb register is sequentially output beginning with d 7 . the ninth bit (d 8 ) is ack or nack. the initial value of sda 2 transmit output can only be set when iicm is set to "1" (i 2 c bus mode) and the smd2 to smd0 bits in the the u2mr register are set to 000 2 (serial i/o disabled). the dl2 to dl0 bits in the u2smr3 register allow to add no delays or a delay of 2 to 8 u2brg count source clock cycles to sda 2 output. setting the sdhi bit in the u2smr2 register is set to "1" (sda output disabled) forcibly places the sda 2 pin in the high-impedance state. do not write to the sdhi bit synchronously with the rising edge of the uart2 transfer clock. this is because the abt bit may inadvertently be set to 1 (detected). 13.1.3.6 sda input when the iicm2 bit is set to "0", the 1st to 8th bits (d 7 to d 0 ) of received data are stored in the bit 7 to bit 0 in the u2rb register. the 9th bit (d 8 ) is ack or nack. when the iicm2 bit is set to "1", the 1st to 7th bits (d 7 to d 1 ) of received data are stored in the bit 6 to bit 0 in the u2rb register and the 8th bit (d 0 ) is stored in the bit 8 in the u2rb register. even when the iicm2 bit is set to "1", providing the ckph bit to "1", the same data as when the iicm2 bit is set to "0" can be read out by reading the u2rb register after the rising edge of the corresponding clock pulse of 9th bit.
13. serial i/o page 162 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 13.1.3.7 ack and nack if the stspsel bit in the u2smr4 register is set to 0 (start and stop conditions not generated) and the ackc bit in the u2smr4 register is set to 1 (ack data output), the value of the ackd bit in the u2smr4 register is output from the sda 2 pin. if the iicm2 bit is set to "0", a nack interrupt request is generated if the sda 2 pin remains high at the rising edge of the 9th bit of transmit clock pulse. an ack interrupt request is generated if the sda 2 pin is low at the rising edge of the 9th bit of transmit clock pulse. if ack2 is selected for the cause of dma1 request, a dma transfer can be activated by detection of an acknowledge. 13.1.3.8 initialization of transmission/reception if a start condition is detected while the stac bit is set to "1" (uart2 initialization enabled), the serial i/o operates as described below. - the transmit shift register is initialized, and the content of the u2tb register is transferred to the transmit shift register. in this way, the serial i/o starts sending data synchronously with the next clock pulse applied. however, the uart2 output value does not change state and remains the same as when a start condition was detected until the first bit of data is output synchronously with the input clock. - the receive shift register is initialized, and the serial i/o starts receiving data synchronously with the next clock pulse applied. - the swc bit is set to 1 (scl wait output enabled). consequently, the scl 2 pin is pulled low at the falling edge of the ninth clock pulse. note that when uart2 transmission/reception is started using this function, the ti does not change state. note also that when using this function, the selected transfer clock should be an external clock.
13. serial i/o page 163 ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r 13.1.4 special mode 2 (uart2) multiple slaves can be serially communicated from one master. transfer clock polarity and phase are selectable. table 13.1.4.1 lists the specifications of special mode 2. table 13.1.4.2 lists the registers used in special mode 2 and the register values set. figure 13.1.4.1 shows communication control ex- ample for special mode 2. table 13.1.4.1. special mode 2 specifications item specification transfer data format ? transfer data length: 8 bits transfer clock ? master mode the ckdir bit in the u2mr register is set to 0 (internal clock) : fj/ (2(n+1)) fj = f 1sio , f 2sio , f 8sio , f 32sio . n: setting value of u2brg register 00 16 to ff 16 ? slave mode the ckdir bit is set to 1 (external clock selected) : input from clk2 pin transmit/receive control controlled by input/output ports transmission start condition ? before transmission can start, the following requirements must be met (note 1) _ the te bit in the u2c1 register is set to "1" (transmission enabled) _ the ti bit in the u2c1 register is set to "0" (data present in u2tb register) reception start condition ? before reception can start, the following requirements must be met (note 1) _ the re bit in the u2c1 register is set to "1" (reception enabled) _ the te bit in the u2c1 register is set to "1" (transmission enabled) _ the ti bit in the u2c1 register is set to "0" (data present in the u2tb register) ? while transmitting, one of the following conditions can be selected _ the u2irs bit in the u2c1 register is set to "0" (transmit buffer empty): when trans ferring data from the u2tb register to the uart2 transmit register (at start of transmission) _ the u2irs bit is set to "1" (transfer completed): when the serial i/o finished sending data from the uart2 transmit register ? while receiving when transferring data from the uart2 receive register to the u2rb register (at completion of reception) error detection ? overrun error (note 2) this error occurs if the serial i/o started receiving the next data before reading the u2rb register and received the 7th bit of the next data select function ? clock phase setting selectable from four combinations of transfer clock polarities and phases note 1: when an external clock is selected, the conditions must be met while if the ckpol bit in the u2c0 register 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the external clock is in the high state; if the ckpol bit in the u2c0 register 1 (transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state. note 2: if an overrun error occurs, the value of u2rb register will be indeterminate. the ir bit in the s2ric register does not change. interrupt request generation timing
13. serial i/o page 164 ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r p1 3 p1 2 p7 0( txd 2 ) p7 2( clk 2 ) p7 1( rxd 2 ) p9 3 p7 0( txd 2 ) p7 2( clk 2 ) p7 1( rxd 2 ) p9 3 p7 0( txd 2 ) p7 2( clk 2 ) p7 1( rxd 2 ) microcomputer (master) microcomputer (slave) microcomputer (slave) figure 13.1.4.1. serial bus communication control example (uart2)
13. serial i/o page 165 ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r table 13.1.4.2. registers to be used and settings in special mode 2 register bit function u2tb (note) 0 to 7 set transmission data u2rb (note) 0 to 7 reception data can be read oer overrun error flag u2brg 0 to 7 set a transfer rate u2mr (note) smd2 to smd0 set to 001 2 ckdir set this bit to 0 for master mode or 1 for slave mode iopol set to 0 u2c0 clk1, clk0 select the count source for the u2brg register crs invalid because crd = 1 txept transmit register empty flag crd set to 1 nch select txd2 pin output format ckpol clock phases can be set in combination with the ckph bit in the u2smr3 register uform set to 0 u2c1 te set this bit to 1 to enable transmission ti transmit buffer empty flag re set this bit to 1 to enable reception ri reception complete flag u2irs select uart2 transmit interrupt cause u2rrm, set to 0 u2lch, u2ere u2smr 0 to 7 set to 0 u2smr2 0 to 7 set to 0 u2smr3 ckph clock phases can be set in combination with the ckpol bit in the u2c0 register nodc set to 0 0, 2, 4 to 7 set to 0 u2smr4 0 to 7 set to 0 note : not all bits in the register are described above. set those bits to 0 when writing to the registers in special mode 2.
13. serial i/o page 166 ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r 13.1.4.1 clock phase setting function one of four combinations of transfer clock phases and polarities can be selected using the ckph bit in the u2smr3 register and the ckpol bit in the u2c0 register. make sure the transfer clock polarity and phase are the same for the master and slave to communi- cate. 13.1.4.1.1 master (internal clock) figure 13.1.4.1.1.1 shows the transmission and reception timing in master (internal clock). 13.1.4.1.2 slave (external clock) figure 13.1.4.1.2.1 shows the transmission and reception timing (ckph=0) in slave (external clock) while figure 13.1.4.1.2.2 shows the transmission and reception timing (ckph=1) in slave (external clock). data output timing data input timing d 0 d 1 d 2 d 3 d 4 d 6 d 7 d 5 clock output (ckpol=0, ckph=0) "h" "l" clock output (ckpol=1, ckph=0) "h" "l" clock output (ckpol=0, ckph=1) "h" "l" clock output (ckpol=1, ckph=1) "h" "l" "h" "l" figure 13.1.4.1.1.1. transmission and reception timing in master mode (internal clock)
13. serial i/o page 167 ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r figure 13.1.4.1.2.1. transmission and reception timing (ckph=0) in slave mode (external clock) figure 13.1.4.1.2.2. transmission and reception timing (ckph=1) in slave mode (external clock) slave control input clock input (ckpol=0, ckph=0) clock input (ckpol=1, ckph=0) data output timing data input timing "h" "l" "h" "l" "h" "l" "h" "l" d 0 d 1 d 2 d 3 d 4 d 6 d 7 d 5 indeterminate clock input (ckpol=0, ckph=1) clock input (ckpol=1, ckph=1) data output timing data input timing "h" "l" "h " "l" "h " "l " "h " "l" d 0 d 1 d 2 d 3 d 6 d 7 d 4 d 5 . slave control input
13. serial i/o page 168 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 13.1.5 special mode 3 (ie bus mode )(uart2) in this mode, one bit of ie bus is approximated with one byte of uart mode waveform. table 13.1.5.1 lists the registers used in ie bus mode and the register values set. figure 13.1.5.1 shows the functions of bus collision detect function related bits. if the txd2 pin output level and rxd2 pin input level do not match, a uart2 bus collision detect interrupt request is generated. table 13.1.5.1. registers to be used and settings in ie bus mode register bit function u2tb 0 to 8 set transmission data u2rb (note) 0 to 8 reception data can be read oer,fer,per,sum error flag u2brg 0 to 7 set a transfer rate u2mr smd2 to smd0 set to 110 2 ckdir select the internal clock or external clock stps set to 0 pry invalid because prye=0 prye set to 0 iopol select the txd/rxd input/output polarity u2c0 clk1, clk0 select the count source for the u2brg register crs invalid because crd=1 txept transmit register empty flag crd set to 1 nch select txd2 pin output mode ckpol set to 0 uform set to 0 u2c1 te set this bit to 1 to enable transmission ti transmit buffer empty flag re set this bit to 1 to enable reception ri reception complete flag u2irs select the source of uart2 transmit interrupt u2rrm, set to 0 u2lch, u2ere u2smr 0 to 3, 7 set to 0 abscs select the sampling timing at which to detect a bus collision acse set this bit to 1 to use the auto clear function of transmit enable bit sss select the transmit start condition u2smr2 0 to 7 set to 0 u2smr3 0 to 7 set to 0 u2smr4 0 to 7 set to 0 note : not all bits in the registers are described above. set those bits to 0 when writing to the registers in ie bus mode.
13. serial i/o page 169 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m (2) the acse bit in the u2smr register (auto clear of transmit enable bit) (1) the abscs bit in the u2smr register (bus collision detect sampling clock select) if abscs=0, bus collision is determined at the rising edge of the transfer clock transfer clock timer a0 (3) the sss bit in the u2smr register (transmit start condition select) transmission enable condition is met if sss bit = 1, the serial i/o starts sending data at the rising edge (note 1) of rxd2 txd2 clk2 txd2 rxd2 txd2 rxd2 st d0 d1 d2 d3 d4 d5 d6 d7 d8 sp input to ta0 in if abscs is set to "1", bus collision is determined when timer a0 (one-shot timer mode) underflows . txd2 rxd2 st d0 d1 d2 d3 d4 d5 d6 d7 d8 sp st d0 d1 d2 d3 d4 d5 d6 d7 d8 sp st d0 d1 d2 d3 d4 d5 d6 d7 d8 sp transfer clock bcnic register ir bit (note) u2c1 register te bit if acse bit is set to "1" automatically clear when bus collision occurs), the te bit is cleared to "0" (transmission disabled) when the ir bit in the bcnic register is set to "1" (unmatching detected). if sss bit is set to "0", the serial i/o starts sending data one transfer clock cycle after the transmission enable condition i s met. transfer clock (note 2) note 1: the falling edge of rxd2 when the iopol is set to "0"; the rising edge of rxd2 when the iopol is set to "1". note 2: the transmit condition must be met before the falling edge (note 1) of rxd. this diagram applies to the case where the iopol is set to "1" (reversed) . figure 13.1.5.1. bus collision detect function-related bits
13. serial i/o page 170 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m item specification transfer data format ?direct format ?inverse format transfer clock ?the ckdir bit in the u2mr register is set to ??(internal clock) : fi/(16(n+1)) fi = f 1sio , f 2sio , f 8sio , f 32sio . n: setting value in u2brg register 00 16 to ff 16 ?the ckdir bit is set to ??(external clock ) : f ext /(16(n+1)) f ext : input from clk 2 pin. n: setting value in u2brg register 00 16 to ff 16 transmission start condition ?before transmission can start, the following requirements must be met _ the te bit in the u2c1 register is set to "1" (transmission enabled) _ the ti bit in the u2c1 register is set to "0" (data present in u2tb register) reception start condition ?before reception can start, the following requirements must be met _ the re bit in the u2c1 register is set to "1" (reception enabled) _ start bit detection for transmission when the serial i/o finished sending data from the u2tb transfer register (the u2irs bit is set to "1") (note 2) ? for reception when transferring data from the uart2 receive register to the u2rb register (at completion of reception) error detection ?overrun error (note 1) this error occurs if the serial i/o started receiving the next data before reading the u2rb register and received the bit one before the last stop bit of the next data ?framing error this error occurs when the number of stop bits set is not detected ?parity error during reception, if a parity error is detected, parity error signal is output from the txd 2 pin. during transmission, a parity error is detected by the level of input to the r x d 2 pin when a transmission interrupt occurs ?error sum flag this flag is set to "1" when any of the overrun, framing, and parity errors is encountered note 1: if an overrun error occurs, the value of u2rb register will be indeterminate. the ir bit in the s2ric register does not change. note 2: a transmit interrupt request is generated by setting the u2irs bit in the u2c1 register to ? (transmission complete) and the u2ere bit to ??(error signal output) after reset. therefore, when using sim mode, be sure to clear the ir bit to ??(no interrupt request) after setting these bits. 13.1.6 special mode 4 (sim mode) (uart2) based on uart mode, this is an sim interface compatible mode. direct and inverse formats can be implemented, and this mode allows output of a low from the txd2 pin when a parity error is detected. tables 13.1.6.1 lists the specifications of sim mode. table 13.1.6.2 lists the registers used in the sim mode and the register values set. table 13.1.6.1. sim mode specifications interrupt request generation timing
13. serial i/o page 171 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m table 13.1.6.2. registers to be used and settings in sim mode register bit function u2tb (note) 0 to 7 set transmission data u2rb (note) 0 to 7 reception data can be read oer,fer,per,sum error flag u2brg 0 to 7 set a transfer rate u2mr smd2 to smd0 set to 101 2 ckdir select the internal clock or external clock stps set to 0 pry set this bit to 1 for direct format or 0 for inverse format prye set to 1 iopol set to 0 u2c0 clk1, clk0 select the count source for the u2brg register crs invalid because crd=1 txept transmit register empty flag crd set to 1 nch set to 0 ckpol set to 0 uform set this bit to 0 for direct format or 1 for inverse format u2c1 te set this bit to 1 to enable transmission ti transmit buffer empty flag re set this bit to 1 to enable reception ri reception complete flag u2irs set to 1 u2rrm set to 0 u2lch set this bit to 0 for direct format or 1 for inverse format u2ere set to 1 u2smr (note) 0 to 3 set to 0 u2smr2 0 to 7 set to 0 u2smr3 0 to 7 set to 0 u2smr4 0 to 7 set to 0 note: not all bits in registers are described above. set those bits to 0 when writing to the registers in sim mode.
13. serial i/o page 172 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 13.1.6.1. transmit and receive timing in sim mode transfer clock an l level is output from txd 2 due to the occurrence of a parity error read the u2rb register cleared to 0 when interrupt request is accepted, or cleared to 0 in a program u2c1 register te bit d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p 0 1 0 1 0 1 0 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp tc sp d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p txd 2 0 1 0 1 0 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp tc sp d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp sp d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp sp txd 2 rxd 2 pin level u2c1 register ti bit parity error signal sent back from receiver (note) u2c0 register txept bit s2tic register ir bit start bit parity bit stop bit write data to u2tb register transferred from u2tb register to uart2 transmit register an l level returns due to the occurrence of a parity error. the level is detected by the interrupt routine. the level is detected by the interrupt routine. the ir bit is set to 1 at the falling edge of transfer clock note : because txd 2 and rxd 2 are connected, this is composite waveform consisting of the transmitter's transmit waveform and the parity error signal received. note : because txd 2 and rxd 2 are connected, this is composite waveform consisting of the txd 2 output and the parity error signal sent back from receiver. tc = 16 (n + 1) / fi or 16 (n + 1) / f ext fi : frequency of u2brg count source (f 1sio , f 2sio , f 8sio , f 32sio ) f ext : frequency of u2brg count source (external clock) n : value set to u2brg tc = 16 (n + 1) / fi or 16 (n + 1) / f ext fi : frequency of u2brg count source (f 1sio , f 2sio , f 8sio , f 32sio ) f ext : frequency of u2brg count source (external clock) n : value set to u2brg the above timing diagram applies to the case where data is transferred in the direct format. ? stps bit jou if u2mr register jttfu u p 0 (1 stop bit) ? pry bit jou if u2mr register jttfu u p 1 (even) ? uform bit jou if u2c0 register jttfu u p (lsb first) ? u2lch bit jou if u2c1 register jttfu u p (no reverse) ? u2irsch bit jou if u2c1 register jttfu u p (transmit is completed) start bit parity bit stop bit cleared to 0 when interrupt request is accepted, or cleared to 0 in a program read the u2rb register (1) transmission transfer clock u2c1 register re bit rxd 2 pin level transmitter's transmit waveform (note) u2c0 register ri bit s2ric register ir bit (1) reception the above timing diagram applies to the case where data is transferred in the direct format. ? stps bit jou if u2mr register jttfu u p (1 stop bit) ? pry bit jou if u2mr register jttfu u p (even) ? uform bit jou if u2c0 register jttfu u p (lsb first) ? u2lch bit jou if u2c1 register jttfu u p (no reverse) ? u2irsch bit jou if u2c1 register jttfu u p (transmit is completed)
13. serial i/o page 173 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 13.1.6.2 shows the example of connecting the sim interface. connect t x d 2 and r x d 2 and apply pull-up. figure 13.1.6.2. sim interface connection microcomputer sim card txd 2 rxd 2 13.1.6.1 parity error signal output the parity error signal is enabled by setting the u2ere bit in the u2c1 register to 1 . ? when receiving the parity error signal is output when a parity error is detected while receiving data. this is achieved by pulling the txd2 output low with the timing shown in figure 13.1.6.1.1. if the r2rb register is read while outputting a parity error signal, the per bit is cleared to 0 and at the same time the txd2 output is returned high. ? when transmitting a transmission-finished interrupt request is generated at the falling edge of the transfer clock pulse that immediately follows the stop bit. therefore, whether a parity signal has been returned can be determined by reading the port that shares the rxd2 pin in a transmission-finished interrupt service routine. figure 13.1.6.1.1. parity error signal output timing st : start bit p : even parity sp : stop bit d0 d1 d2 d3 d4 d5 d6 d7 p sp st (note) transfer clock rxd 2 txd 2 u2c1 register ri bit h l h l h l 1 0 this timing diagram applies to the case where the direct format is implemented. note: the output of microcomputer is in the high-impedance state (pulled up externally).
13. serial i/o page 174 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 13.1.6.2 format ? direct format set the pry bit in the u2mr register to 1 , the uform bit in the u2c0 register to 0 and the u2lch bit in the u2c1 register to 0 . ? inverse format set the pry bit to 0 , uform bit to 1 and u2lch bit to 1 . figure 13.1.6.2.1 shows the sim interface format. figure 13.1.6.2.1. sim interface format p : even parity d0 d1 d2 d3 d4 d5 d6 d7 p transfer clcck txd 2 txd 2 d7 d6 d5 d4 d3 d2 d1 d0 p transfer clcck (1) direct format h l h l (2) inverse format p : odd parity h l h l
14. a/d converter page 175 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m item performance a/d conversion method successive approximation (capacitive coupling amplifier) analog input voltage (note 1) 0v to av cc (v cc ) operating clock fad (note 2) f ad /divided-by-2 or f ad /divided-by-3 or f ad /divided-by-4 or f ad /divided-by-6 or f ad /divided-by-12 or f ad resolution 8-bit or 10-bit (selectable) integral nonlinearity error when av cc = v ref = 5v ? with 8-bit resolution: 2lsb ? with 10-bit resolution: 3lsb when av cc = v ref = 3.3v ? with 8-bit resolution: 2lsb ? with 10-bit resolution: 5lsb operating modes one-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, repeat sweep mode 1, simultaneous sample sweep mode and delayed trigger mode 0,1 analog input pins (note 3) 8 pins (an 0 to an 7 ) + 3 pins (an 30 to an 32 ) + 1 pins (an 24 ) (48pin-ver.) 8 pins (an 0 to an 7 ) + 2 pins (an 30 , an 31 ) (42pin-ver.) conversion speed per pin ? without sample and hold function 8-bit resolution: 49 f ad cycles , 10-bit resolution: 59 f ad cycles ? with sample and hold function 8-bit resolution: 28 f ad cycles , 10-bit resolution: 33 f ad cycles table 14.1 a/d converter performance note 1: not dependent on use of sample and hold function. note 2: set the fad frequency to 10 mhz or less. without sample-and-hold function, set the fad frequency to 250kh z or more. with the sample and hold function, set the fad frequency to 1mh z or more. 14. a/d converter note thers is no external connections for port p9 2 to p9 3 (an 32 , an 24 ) in the m16c/26a (42-pin version). do not use port p9 2 to p9 3 (an 32 , an 24 ) for analog input pin in the m16c/26a (42-pin version). the microcomputer contains one a/d converter circuit based on 10-bit successive approximation method configured with a capacitive-coupling amplifier. the analog inputs share the pins with p10 0 to p10 7 (an 0 to ___________ an 7 ), p9 0 to p9 3 (an3 0 to an3 2 , an2 4 ). similarly, ad trg input shares the pin with p1 5 . therefore, when using these inputs, make sure the corresponding port direction bits are set to 0 (input mode). when not using the a/d converter, set the vcut bit to 0 (v ref unconnected), so that no current will flow from the v ref pin into the resistor ladder, helping to reduce the power consumption of the chip. the a/d conversion result is stored in the i bits in the a/d register for an i , an 3i , and an 2i pins (i = 0 to 7). table 14.1 shows the a/d converter performance. figure 14.1 shows the a/d converter block diagram and figures 14.2 to 14.4 show the a/d converter associated with registers.
14. a/d converter page 176 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 14.1 a/d converter block diagram =000 2 =001 2 =010 2 =011 2 =100 2 =101 2 =110 2 =111 2 an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 an 30 an 31 an 32 v ref v in ch2 to ch0 decoder for channel selection a/d register 0(16) data bus low-order v ref av ss vcut=0 vcut=1 data bus high-order port p10 group port p9 group adgsel1 to adgsel0=01 2 adgsel1 to adgsel0=00 2 an 24 adgsel1 to adgsel0=11 2 f ad cks0=1 cks0=0 cks1=1 cks1=0 1/3 cks2=0 cks2=1 1/2 1/2 ? ad a/d conversion rate selection (03c1 16 to 03c0 16 ) (03c3 16 to 03c2 16 ) (03c5 16 to 03c4 16 ) (03c7 16 to 03c6 16 ) (03c9 16 to 03c8 16 ) (03cb 16 to 03ca 16 ) (03cd 16 to 03cc 16 ) (03cf 16 to 03ce 16 ) resistor ladder successive conversion register adcon0 register (address 03d6 16 ) adcon1 register (address 03d7 16 ) comparator 0 addresses decoder for a/d register a/d register 1(16) a/d register 2(16) a/d register 3(16) a/d register 4(16) a/d register 5(16) a/d register 6(16) a/d register 7(16) adcon2 register (address 03d4 16 ) port p9 group =000 2 =001 2 =010 2 =100 2 ch2 to ch0 ch2 to ch0 sse = 1 ch2 to ch0=001 2 comparator 1 adgsel1 to adgsel0=00 2 adgsel1 to adgsel0=01 2 v in1 note 1: an 32 and an 24 are available for only 48-pin package. (note 1) (note 1)
14. a/d converter page 177 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 14.2 adcon0 to adcon2 registers a/d control register 0 (note 1) symbol address after reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a/d operation mode select bit 0 0 0 : one-shot mode or delayed trigger mode 0,1 0 1 : repeat mode 1 0 : single sweep mode or simultaneous sample sweep mode 1 1 : repeat sweep mode 0 or repeat sweep mode 1 md0 md1 trigger select bit 0 : software trigger 1 : hardware trigger trg adst a/d conversion start flag 0 : a/d conversion disabled 1 : a/d conversion started frequency select bit 0 see table 14.2 a/d conversion frequency select cks0 rw a/d control register 1 (note 1) symbol address after reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a/d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut v ref connect bit (note2) a/d operation mode select bit 1 0 : other than repeat sweep mode 1 1 : repeat sweep mode 1 0 : v ref not connected 1 : v ref connected b4 b3 note 1: if the adcon0 register is rewritten during a/d conversion, the conversion result will be indeterminate. frequency select bit 1 cks1 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw function varies with each operation mode function varies with each operation mode see table 14.2 a/d conversion frequency select note 1: if the adcon1 register is rewritten during a/d conversion, the conversion result will be indeterminate. note 2: if the vcut bit is reset from 0 (v ref unconnected) to 1 (v ref connected), wait for 1 s or more before starting a/d conversion. nothing is assigned. when write, set to 0 . when read, its content is 0 . (b7-b6) note 1: if the adcon2 register is rewritten during a/d conversion, the conversion result will be indeterminate. a/d control register 2 (note 1) symbol address after reset adcon2 03d4 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 a/d conversion method select bit 0 : without sample and hold 1 : with sample and hold bit symbol bit name function rw smp reserved bit set to 0 0 a/d input group select bit 0 0 : select port p10 group 0 1 : select port p9 group (an 3i ) 1 0 : do not set 1 1 : select port p9 group (an 24 ) b2 b1 frequency select bit 2 cks2 adgsel0 adgsel1 rw rw rw rw rw (b3) nothing is assigned. when write, set to 0 . when read, its content is 0 . (b7-b6) rw trg1 trigger select bit see table 14.2 a/d conversion frequency select function varies with each operation mode
14. a/d converter page 178 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m a/d trigger control register (note 1)(note 2) symbol address after reset adtrgcon 03d2 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 a/d operation mode select bit 2 0 : other than simultaneous sample sweep mode or delayed trigger mode 0,1 1 : simultaneous sample sweep mode or delayed trigger mode 0,1 bit symbol bit name function rw sse a/d operation mode select bit 3 hptrg1 dte hptrg0 rw rw rw rw nothing is assigned. when write, set to 0 . when read, its content is 0 . (b7-b4) 0 : other than delayed trigger mode 0,1 1 : delayed trigger mode 0,1 note 1: if the adtrgcon register is rewritten during a/d conversion, the conversion result will be indeterminate. note 2: set 00 16 in this register in one-shot mode, repeat mode, single sweep mode, repeat sweep mode 0 and repeat sweep mode 1. an1 trigger select bit an0 trigger select bit function varies with each operation mode function varies with each operation mode figure 14.3 adtrgcon register note : set the ? ad frequency to 10 mhz or less. the selected ? ad frequency is determined by a combination of the cks0 bit in the adcon0 register, cks1 bit in the adcon1 register and the cks2 bit in the adcon2 register. cks2 cks1 cks0 ? ad 000 001 010 100 101 110 111 divided-by-4 of f ad divided-by-2 of f ad f ad divided-by-12 of f ad 011 divided-by-6 of f ad divided-by-3 of f ad table 14.2 a/d conversion frequency select
14. a/d converter page 179 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 14.4 adstat0 register and ad0 to ad7 registers a/d register i (i=0 to 7) symbol address after reset ad0 03c1 16 to 03c0 16 indeterminate ad1 03c3 16 to 03c2 16 indeterminate ad2 03c5 16 to 03c4 16 indeterminate ad3 03c7 16 to 03c6 16 indeterminate ad4 03c9 16 to 03c8 16 indeterminate ad5 03cb 16 to 03ca 16 indeterminate ad6 03cd 16 to 03cc 16 indeterminate ad7 03cf 16 to 03ce 16 indeterminate eight low-order bits of a/d conversion result function (b15) b7 b7 b0 b0 (b8) when the bits bit in the adcon1 register is 1 (10-bit mode) nothing is assigned. when write, set to 0 . when read, its content is 0 . when read, its content is indeterminate rw ro ro two high-order bits of a/d conversion result when the bits bit in the adcon1 register is 0 (8-bit mode) a/d conversion result a/d conversion status register 0 (note 1) symbol address after reset adstat0 03d3 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 an1 trigger status flag 0 : an1 trigger did not occur during an0 conversion 1 : an1 trigger occured during an0 conversion bit symbol bit name function rw aderr0 conversion termination flag an0 conversion status flag adstt0 aderr1 adtcsf rw ro rw ro ro nothing is assigned. when write, set to 0 . when read, its content is 0 . (b2) adstrt0 an0 conversion completion status flag 0 : conversion not terminated 1 : conversion terminated by timer b0 underflow delayed trigger sweep status flag 0 : sweep not in progress 1 : sweep in progress 0 : an0 conversion not in progress 1 : an0 conversion in progress adstt1 rw 0 : an0 conversion not completed 1 : an0 conversion completed adstrt1 rw an1 conversion status flag 0 : an1 conversion not in progress 1 : an1 conversion in progress an1 conversion completion status flag 0 : an1 conversion not completed 1 : an1 conversion completed note 1: adstat0 register is valid only when the dte bit in the adtrgcon register is set to 1 .
14. a/d converter page 180 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 14.5 tb2sc register note 3. when setting the ivpcr1 bit to "1" (three-phase output forcible cutoff by sd pin input enabled), set the pd8_5 bit to "0" (= input mode). note 4. related pins are u(p8 0 ), u(p8 1 ), v(p7 2 ), v(p7 3 ), w(p7 4 ), w(p7 5 ). after forcible cutoff, input "h" to the p8 5 /nmi/sd pin. set the ivpcr1 bit to "0", and this forcible cutoff will be reset. if l is input to the p8 5 /nmi/sd pin, a three-phase motor control timer output will be disabled (inv03=0). at this time, when the ivpcr1 bit is "0", the target pins chang es to programmable i/o port. when the ivpcr1 bit is "1", the target pins changes to high-impedance state regardless of which functions of those pins are used. note 5. when this bit is used in delayed trigger mode 0, set the tb0en and tb1en bits to "1"(a/d trigger mode). note 6. when setting the tb2sel bit to "1" (underflow of tb2 interrupt generation frequency setting counter[ictb2]), set the inv02 bit to "1" (three-phase motor control timer function). note 7. refer to 16.6 digital debounce function for sd input. pwcom symbol address after reset tb2sc 039e 16 x0000000 2 timer b2 reload timing switch bit 0 : timer b2 underflow 1 : timer a output at odd-numbered timer b2 special mode register (note 1) bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 ivpcr1 three-phase output port sd control bit 1 0 : three-phase output forcible cutoff by sd pin input (high impedance) disabled 1 : three-phase output forcible cutoff by sd pin input (high impedance) enabled note 1. write to this register after setting the prc1 bit in the prcr register to "1" (write enabled). note 2. if the inv11 bit is "0" (three-phase mode 0) or the inv06 bit is "1" (triangular wave modulation mode), set this bit to "0" (timer b2 underflow). rw rw rw nothing is assigned. when write, set to 0 . when read, its content is 0 . (b7) tb2sel trigger select bit 0 : tb2 interrupt 1 : underflow of tb2 interrupt generation frequency setting counter [ictb2] rw rw tb0en timer b0 operation mode select bit 0 : other than a/d trigger mode 1 : a/d trigger mode (note 5) rw tb1en timer b1 operation mode select bit 0 : other than a/d trigger mode 1 : a/d trigger mode (note 5) rw (note 2) (note 3, 4, 7) (note 6) (b6-b5) reserved bits must set to "0" 0 0
14. a/d converter page 181 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 14.1 operation modes 14.1.1 one-shot mode in one-shot mode, analog voltage applied to a selected pin is once converted to a digital code. table 14.1.1.1 shows the one-shot mode specifications. figure 14.1.1.1 shows the operation example in one- shot mode. figure 14.1.1.2 shows the adcon0 to adcon2 registers in one-shot mode. table 14.1.1.1 one-shot mode specifications item specification function the ch2 to ch0 bits in the adcon0 register and the adgsel1 to adgsel0 bits in the adcon2 register select pins. analog voltage applied to a selected pin is once converted to a digital code a/d conversion start ? when the trg bit in the adcon0 register is 0 (software trigger) condition set the adst bit in the adcon0 register to 1 (a/d conversion started) ? when the trg bit in the adcon0 register is 1 (hardware trigger) ___________ the ad trg pin input changes state from h to l after setting the adst bit to 1 (a/d conversion started) a/d conversion stop ? a/d conversion completed (if a software trigger is selected, the adst bit is condition set to 0 (a/d conversion halted)). ? set the adst bit to 0 interrupt request generation timing a/d conversion completed analog input pin select one pin from an 0 to an 7 , an 30 to an 32 , an 24 readout of a/d conversion result readout one of the ad0 to ad7 registers that corresponds to the selected pin figure 14.1.1.1 operation example in one-shot mode ? example when selecting an 2 to an analog input pin (ch2 to ch0=010 2 ) an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 a/d conversion started a/d interrupt request generated a/d pin input voltage sampling a/d pin conversion
14. a/d converter page 182 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m a/d control register 0 (note 1) symbol address after reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit (note 2, 3) ch0 bit symbol bit name function ch1 ch2 a/d operation mode select bit 0 (note 3) md0 md1 trigger select bit trg adst a/d conversion start flag 0 : a/d conversion disabled 1 : a/d conversion started frequency select bit 0 cks0 rw a/d control register 1 (note 1) symbol address after reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a/d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut v ref connect bit (note 2) a/d operation mode select bit 1 1 : v ref connected 0 0 0 0 : one-shot mode or delayed trigger mode 0,1 b4 b3 1 frequency select bit 1 cks1 0 : any mode other than repeat sweep mode 1 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw see table 14.2 a/d conversion frequency select refer to table 14.2 a/d conversion frequency select (b7-b6) 0 note 1: if the adcon2 register is rewritten during a/d conversion, the conversion result will be indeterminate. a/d control register 2 (note 1) symbol address after reset adcon2 03d4 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 a/d conversion method select bit bit symbol bit name function rw smp reserved bit set to 0 0 a/d input group select bit 0 0 : select port p10 group (an i ) 0 1 : select port p9 group (an 3i ) 1 0 : do not set 1 1 : select port p9 group (an 24 ) b2 b1 frequency select bit 2 cks2 adgsel0 adgsel1 rw rw rw rw rw (b3) nothing is assigned. when write, set to 0 . when read, its content is 0 . (b7-b6) rw trg1 trigger select bit 1 b2 b1 b0 0 0 0 : select an 0 0 0 1 : select an 1 0 1 0 : select an 2 0 1 1 : select an 3 1 0 0 : select an 4 1 0 1 : select an 5 1 1 0 : select an 6 1 1 1 : select an 7 note 1: if the adcon0 register is rewritten during a/d conversion, the conversion result will be indeterminate. note 2: an 30 to an 32 and an 24 can be used in the same way as an 0 to an 7 . use the adgsel1 to adgsel0 bits in the adcon2 register to select the desired pin. note 3: after rewriting the md1 to md0 bits, set the ch2 to ch0 bits over again using an another instruction. 0 : software trigger 1 : hardware trigger (ad trg trigger) invalid in one-shot mode nothing is assigned. when write, set to 0 . when read, its content is 0 . note 1: if the adcon1 register is rewritten during a/d conversion, the conversion result will be indeterminate. note 2: if the vcut bit is reset from 0 (v ref unconnected) to 1 (v ref connected), wait for 1 s or more before starting a/d conversion. 0 : without sample and hold 1 : with sample and hold set to "0" in one-shot mode see table 14.2 a/d conversion frequency select 0 figure 14.1.1.2 adcon0 to adcon2 registers in one-shot mode
14. a/d converter page 183 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 14.1.2 repeat mode in repeat mode, analog voltage applied to a selected pin is repeatedly converted to a digital code. table 14.1.2.1 shows the repeat mode specifications. figure 14.1.2.1 shows the operation example in repeat mode. figure 14.1.2.2 shows the adcon0 to adcon2 registers in repeat mode. item specification function the ch2 to ch0 bits in the adcon0 register and the adgsel1 to adgsel0 bits in the adcon2 register select pins. analog voltage applied to a selected pin is repeatedly converted to a digital code a/d conversion start ? when the trg bit in the adcon0 register is 0 (software trigger) condition set the adst bit in the adcon0 register to 1 (a/d conversion started) ? when the trg bit in the adcon0 register is 1 (hardware trigger) the ad trg pin input changes state from h to l after setting the adst bit to 1 (a/d conversion started) a/d conversion stop condition set the adst bit to 0 (a/d conversion halted) interrupt request generation timing none generated analog input pin select one pin from an 0 to an 7 , an 30 to an 32 and an 24 readout of a/d conversion result readout one of the ad0 to ad7 registers that corresponds to the selected pin table 14.1.2.1 repeat mode specifications figure 14.1.2.1 operation example in repeat mode ? example when selecting an 2 to an analog input pin (ch2 toch0=010 2 ) a/d conversion started an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 a/d pin input voltage sampling a/d pin conversion
14. a/d converter page 184 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m a/d control register 0 (note 1) symbol address after reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit (note 2, 3) ch0 bit symbol bit name function ch1 ch2 a/d operation mode select bit 0 (note 3) md0 md1 trigger select bit trg adst a/d conversion start flag 0 : a/d conversion disabled 1 : a/d conversion started frequency select bit 0 cks0 rw a/d control register 1 (note 1) symbol address after reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a/d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut v ref connect bit (note 2) a/d operation mode select bit 1 1 : v ref connected 0 0 0 1 : repeat mode b4 b3 1 frequency select bit 1 cks1 0 : any mode other than repeat sweep mode 1 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw refer to table 14.2 a/d conversion frequency select refer to table 14.2 a/d conversion frequency select (b7-b6) 1 note 1: if the adcon2 register is rewritten during a/d conversion, the conversion result will be indeterminate. a/d control register 2 (note 1) symbol address after reset adcon2 03d4 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 a/d conversion method select bit bit symbol bit name function rw smp reserved bit set to 0 0 a/d input group select bit 0 0 : select port p10 group (an i ) 0 1 : select port p9 group (an 3i ) 1 0 : do not set 1 1 : select port p9 group (an 24 ) b2 b1 frequency select bit 2 cks2 adgsel0 adgsel1 rw rw rw rw rw (b3) nothing is assigned. when write, set to 0 . when read, its content is 0 . (b7-b6) see table 14.2 a/d conversion frequency select rw trg1 trigger select bit 1 b2 b1 b0 0 0 0 : select an 0 0 0 1 : select an 1 0 1 0 : select an 2 0 1 1 : select an 3 1 0 0 : select an 4 1 0 1 : select an 5 1 1 0 : select an 6 1 1 1 : select an 7 note 1: if the adcon0 register is rewritten during a/d conversion, the conversion result will be indeterminate. note 2: an 30 to an 32 and an 24 can be used in the same way as an 0 to an 7 . use the adgsel1 to adgsel0 bits in the adcon2 register to select the desired pin. note 3: after rewriting the md1 to md0 bits, set the ch2 to ch0 bits over again using an another instruction. 0 : software trigger 1 : hardware trigger (ad trg trigger) invalid in repeat mode nothing is assigned. when write, set to 0 . when read, its content is 0 . note 1: if the adcon1 register is rewritten during a/d conversion, the conversion result will be indeterminate. note 2: if the vcut bit is reset from 0 (v ref unconnected) to 1 (v ref connected), wait for 1 s or more before starting a/d conversion. 0 : without sample and hold 1 : with sample and hold set to "0" in repeat mode 0 figure 14.1.2.2 adcon0 to adcon2 registers in repeat mode
14. a/d converter page 185 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 14.1.3 single sweep mode in single sweep mode, analog voltages applied to the selected pins are converted one-by-one to a digital code. table 14.1.3.1 shows the single sweep mode specifications. figure 14.1.3.1 shows the operation example in single sweep mode. figure 14.1.3.2 shows the adcon0 to adcon2 registers in single sweep mode. item specification function the scan1 to scan0 bits in the adcon1 register and the adgsel1 to adgsel0 bits in the adcon2 register select pins. analog voltage applied to the selected pins is converted one-by-one to a digital code a/d conversion start condition ? when the trg bit in the adcon0 register is 0 (software trigger) set the adst bit in the adcon0 register to 1 (a/d conversion started) ? when the trg bit in the adcon0 register is 1 (hardware trigger) the ad trg pin input changes state from h to l after setting the adst bit to 1 (a/d conversion started) a/d conversion stop condition ? a/d conversion completed(when selecting a software trigger, the adst bit is set to 0 (a/d conversion halted)). ? set the adst bit to 0 interrupt request generation timing a/d conversion completed analog input pin select from an 0 to an 1 (2 pins), an 0 to an 3 (4 pins), an 0 to an 5 (6 pins), an 0 to an 7 (8 pins) (note 1) readout of a/d conversion result readout one of the ad0 to ad7 registers that corresponds to the selected pin table 14.1.3.1 single sweep mode specifications note 1: an 30 to an 32 can be used in the same way as an 0 to an 7 . however, all input pins need to belong to the same group. figure 14.1.3.1 operation example in single sweep mode ? example when selecting an 0 to an 3 to analog input pins (scan1 to scan0=01 2 ) a/d conversion started a/d interrupt request generated an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 a/d pin input voltage sampling a/d pin conversion
14. a/d converter page 186 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m a/d control register 0 (note 1) symbol address after reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a/d operation mode select bit 0 md0 md1 trigger select bit trg adst a/d conversion start flag 0 : a/d conversion disabled 1 : a/d conversion started frequency select bit 0 cks0 rw a/d control register 1 (note 1) symbol address after reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a/d sweep pin select bit (note 2) scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut v ref connect bit (note 3) a/d operation mode select bit 1 1 : v ref connected 1 0 1 frequency select bit 1 cks1 0 : any mode other than repeat sweep mode 1 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw refer to table 14.2 a/d conversion frequency select refer to table 14.2 a/d conversion frequency select (b7-b6) 0 note 1: if the adcon2 register is rewritten during a/d conversion, the conversion result will be indeterminate. a/d control register 2 (note 1) symbol address after reset adcon2 03d4 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 a/d conversion method select bit bit symbol bit name function rw smp reserved bit set to 0 0 a/d input group select bit 0 0 : select port p10 group (an i ) 0 1 : select port p9 group (an 3i ) 1 0 : do not set 1 1 : do not set b2 b1 frequency select bit 2 cks2 adgsel0 adgsel1 rw rw rw rw rw (b3) nothing is assigned. when write, set to 0 . when read, its content is 0 . (b7-b6) refer to table 14.2 a/d conversion frequency select rw trg1 trigger select bit 1 note 1: if the adcon0 register is rewritten during a/d conversion, the conversion result will be indeterminate. 0 : software trigger 1 : hardware trigger (ad trg trigger) nothing is assigned. when write, set to 0 . when read, its content is 0 . 0 : without sample and hold 1 : with sample and hold set to "0" in single sweep mode invalid in single sweep mode 1 0 : single sweep mode or simultaneous sample sweep mode b4 b3 when selecting single sweep mode 0 0 : an 0 to an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 5 (6 pins) 1 1 : an 0 to an 7 (8 pins) b1 b0 note 1: if the adcon1 register is rewritten during a/d conversion, the conversion result will be indeterminate. note 2: an 30 to an 32 can be used in the same way as an 0 to an 7 . use the adgsel1 to adgsel0 bits in the adcon2 register to select the desired pin. note 3: if the vcut bit is reset from 0 (v ref unconnected) to 1 (v ref connected), wait for 1 s or more before starting a/d conversion. 0 figure 14.1.3.2 adcon0 to adcon2 registers in single sweep mode
14. a/d converter page 187 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m item specification function the scan1 to scan0 bits in the adcon1 register and the adgsel1 to adgsel0 bits in the adcon2 register select pins. analog voltage applied to the selected pins is repeatedly converted to a digital code a/d conversion start condition ? when the trg bit in the adcon0 register is 0 (software trigger) set the adst bit in the adcon0 register to 1 (a/d conversion started) ? when the trg bit in the adcon0 register is 1 (hardware trigger) the ad trg pin input changes state from h to l after setting the adst bit to 1 (a/d conversion started) a/d conversion stop condition set the adst bit to 0 (a/d conversion halted) interrupt request generation timing none generated analog input pin select from an 0 to an 1 (2 pins), an 0 to an 3 (4 pins), an 0 to an 5 (6 pins), an 0 to an 7 (8 pins) (note 1) readout of a/d conversion result readout one of the ad0 to ad7 registers that corresponds to the selected pin 14.1.4 repeat sweep mode 0 in repeat sweep mode 0, analog voltages applied to the selected pins are repeatedly converted to a digital code. table 14.1.4.1 shows the repeat sweep mode 0 specifications. figure 14.1.4.1 shows the operation example in repeat sweep mode 0. figure 14.1.4.2 shows the adcon0 to adcon2 registers in repeat sweep mode 0. table 14.1.4.1 repeat sweep mode 0 specifications note 1: an 30 to an 32 can be used in the same way as an 0 to an 7 . however, all input pins need to belong to the same group. figure 14.1.4.1 operation example in repeat sweep mode 0 ? example when selecting an 0 to an 3 to analog input pins (scan1 to scan0=01 2 ) a/d conversion started an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 a/d pin input voltage sampling a/d pin conversion
14. a/d converter page 188 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m a/d control register 1 (note 1) symbol address after reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a/d sweep pin select bit (note 2) scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut v ref connect bit (note 3) a/d operation mode select bit 1 1 : v ref connected 0 1 frequency select bit 1 cks1 0 : any mode other than repeat sweep mode 1 rw rw rw rw rw rw rw refer to table 14.2 a/d conversion frequency select (b7-b6) nothing is assigned. when write, set to 0 . when read, its content is 0 . note 1: if the adcon1 register is rewritten during a/d conversion, the conversion result will be indeterminate. note 2: an 30 to an 32 can be used in the same way as an 0 to an 7 . use the adgsel1 to adgset0 bits in the adcon2 register to select the desired pin. noe 3: if the vcut bit is reset from 0 (v ref unconnected) to 1 (v ref connected), wait for 1 s or more before starting a/d conversion. when selecting repeat sweep mode 0 0 0 : an 0 to an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 5 (6 pins) 1 1 : an 0 to an 7 (8 pins) b1 b0 note 1: if the adcon2 register is rewritten during a/d conversion, the conversion result will be indeterminate. a/d control register 2 (note 1) symbol address after reset adcon2 03d4 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 a/d conversion method select bit bit symbol bit name function rw smp reserved bit set to 0 0 a/d input group select bit 0 0 : select port p10 group (an i ) 0 1 : select port p9 group (an 3i ) 1 0 : do not set 1 1 : do not set b2 b1 frequency select bit 2 cks2 adgsel0 adgsel1 rw rw rw rw rw (b3) nothing is assigned. when write, set to 0 . when read, its content is 0 . (b7-b6) refer to table 14.2 a/d conversion frequency select rw trg1 trigger select bit 1 0 : without sample and hold 1 : with sample and hold set to "0" in repeat sweep mode 0 0 a/d control register 0 (note 1) symbol address after reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a/d operation mode select bit 0 md0 md1 trigger select bit tr g adst a/d conversion start flag 0 : a/d conversion disabled 1 : a/d conversion started frequency select bit 0 cks0 rw 1 rw rw rw rw rw rw rw rw refer to table 14.2 a/d conversion frequency select 1 note 1: if the adcon0 register is rewritten during a/d conversion, the conversion result will be indeterminate. 0 : software trigger 1 : hardware trigger (ad trg trigger) invalid in repeat sweep mode 0 1 1 : repeat sweep mode 0 or repeat sweep mode 1 b4 b3 figure 14.1.4.2 adcon0 to adcon2 registers in repeat sweep mode 0
14. a/d converter page 189 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 14.1.5 repeat sweep mode 1 in repeat sweep mode 1, analog voltages applied to the all selected pins are converted to a digital code, with mainly used in the selected pins. table 14.1.5.1 shows the repeat sweep mode 1 specifications. figure 14.1.5.1 shows the operation example in repeat sweep mode 1. figure 14.1.5.2 shows the adcon0 to adcon2 registers in repeat sweep mode 1. table 14.1.5.1 repeat sweep mode 1 specifications item specification function the scan1 to scan0 bits in the adcon1 register and the adgsel1 to adgsel0 bits in the adcon2 register mainly select pins. analog voltage applied to the all selected pins is repeatedly converted to a digital code example : when selecting an 0 analog voltage is converted to a digital code in the following order an 0 an 1 an 0 an 2 an 0 an 3 , and so on. a/d conversion start condition ? when the trg bit in the adcon0 register is 0 (software trigger) set the adst bit in the adcon0 register to 1 (a/d conversion started) ? when the trg bit in the adcon0 register is 1 (hardware trigger) the ad trg pin input changes state from h to l after setting the adst bit to 1 (a/d conversion started) a/d conversion stop condition set the adst bit to 0 (a/d conversion halted) interrupt request generation timing none generated analog input pins mainly select from an 0 (1 pins), an 0 to an 1 (2 pins), an 0 to an 2 (3 pins), used in a/d conversions an 0 to an 3 (4 pins) (note 1) readout of a/d conversion result readout one of the ad0 to ad7 registers that corresponds to the selected pin note 1: an 30 to an 32 can be used in the same way as an 0 to an 7 . however, all input pins need to belong to the same group. figure 14.1.5.1 operation example in repeat sweep mode 1 ? example when selecting an 0 to analog input pins (scan1 to scan0=00 2 ) an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 a/d conversion started a/d pin input voltage sampling a/d pin conversion
14. a/d converter page 190 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m a/d control register 0 (note 1) symbol address after reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a/d operation mode select bit 0 md0 md1 trigger select bit trg adst a/d conversion start flag 0 : a/d conversion disabled 1 : a/d conversion started frequency select bit 0 cks0 rw a/d control register 1 (note 1) symbol address after reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a/d sweep pin select bit (note 2) scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut v ref connect bit (note 3) a/d operation mode select bit 1 1 : v ref connected 1 1 1 frequency select bit 1 cks1 1 : repeat sweep mode 1 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw refer to table 14.2 a/d conversion frequency select refer to table 14.2 a/d conversion frequency select (b7-b6) 1 note 1: if the adcon2 register is rewritten during a/d conversion, the conversion result will be indeterminate. a/d control register 2 (note 1) symbol address after reset adcon2 03d4h 00h b7 b6 b5 b4 b3 b2 b1 b0 a/d conversion method select bit bit symbol bit name function rw smp reserved bit set to 0 0 a/d input group select bit 0 0 : select port p10 group (an i ) 0 1 : select port p9 group (an 3i ) 1 0 : do not set 1 1 : do not set b2 b1 frequency select bit 2 cks2 adgsel0 adgsel1 rw rw rw rw rw (b3) nothing is assigned. when write, set to 0 . when read, its content is 0 . (b7-b6) refer to table 14.2 a/d conversion frequency select rw trg1 trigger select bit 1 note 1: if the adcon0 register is rewritten during a/d conversion, the conversion result will be indeterminate. 0 : software trigger 1 : hardware trigger (ad trg trigger) nothing is assigned. when write, set to 0 . when read, its content is 0 . note 1: if the adcon1 register is rewritten during a/d conversion, the conversion result will be indeterminate. note 2: an 30 to an 32 can be used in the same way as an 0 to an 7 . use the adgsel1 to adgsel0 bits in the adcon2 register to select the desired pin. note 3: if the vcut bit is reset from 0 (v ref unconnected) to 1 (v ref connected), wait for 1 s or more before starting a/d conversion. 0 : without sample and hold 1 : with sample and hold set to "0" in repeat sweep mode 1 invalid in repeat sweep mode 1 1 1 : repeat sweep mode 0 or repeat sweep mode 1 b4 b3 when selecting repeat sweep mode 1 0 0 : an 0 (1 pin) 0 1 : an 0 to an 1 (2 pins) 1 0 : an 0 to an 2 (3 pins) 1 1 : an 0 to an 3 (4 pins) b1 b0 0 figure 14.1.5.2 adcon0 to adcon2 registers in repeat sweep mode 1
14. a/d converter page 191 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m item specification function the scan1 to scan0 bits in the adcon1 register and adgsel1 to adgsel0 bits in the adcon2 register select pins. analog voltage applied to the selected pins is converted one-by-one to a digital code. at this time, the input voltage of an 0 and an 1 are sampled simultaneously. a/d conversion start condition when the trg bit in the adcon0 register is "0" (software trigger) set the adst bit in the adcon0 register to 1 (a/d conversion started) when the trg bit in the adcon0 register is "1" (hardware trigger) the trigger is selected by trg1 and hptrg0 bits (see table 14.1.6.2 ) the ad trg pin input changes state from h to l after setting the adst bit to 1 (a/d conversion started) timer b0, b2 or timer b2 interrupt generation frequency setting counter underflow after setting the adst bit to 1 (a/d conversion started) a/d conversion stop condition a/d conversion completed (if selecting software trigger, the adst bit is automatically set to "0". set the adst bit to "0" (a/d conversion halted) interrupt generation timing a/d conversion completed analog input pin select from an 0 to an 1 (2 pins), an 0 to an 3 (4 pins), an 0 to an 5 (6 pins), or an 0 to an 7 (8 pins) (note 1) readout of a/d conversion result readout one of the an0 to an7 registers that corresponds to the selected pin note 1: an 30 to an 32 can be used in the same way as an 0 to an 7 . however, all input pins need to belong to the same group. 14.1.6 simultaneous sample sweep mode in simultaneous sample sweep mode, analog voltages applied to the selected pins are converted one-by- one to a digital code. at this time, the input voltage of an 0 and an 1 are sampled simultaneously using two circuits of sample and hold circuit. table 14.1.6.1 shows the simultaneous sample sweep mode specifica- tions. figure 14.1.6.1 shows the operation example in simultaneous sample sweep mode. figure 14.1.6.2 shows adcon0 to adcon2 registers and figure 14.1.6.3 shows adtrgcon registers in simultaneous sample sweep mode. table 14.1.6.2 shows the trigger select bit setting in simultaneous sample sweep mode. in simultaneous sample sweep mode, timer b0 underflow can be selected as a trigger by combining software trigger, ad trg trigger, timer b2 underflow, timer b2 interrupt generation frequency setting counter underflow or a/d trigger mode of timer b. ? example when selecting an 0 to an 3 to analog input pins (scan1 to scan0=01 2 ) a/d conversion started a/d interrupt request generated an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 a/d pin input voltage sampling a/d pin conversion figure 14.1.6.1 operation example in simultaneous sample sweep mode table 14.1.6.1 simultaneous sample sweep mode specifications
14. a/d converter page 192 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 14.1.6.2 adcon0 to adcon2 registers for simultaneous sample sweep mode a/d control register 0 (note 1) symbol address after reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a/d operation mode select bit 0 md0 md1 trigger select bit trg adst a/d conversion start fag 0 : a/d conversion disabled 1 : a/d conversion started frequency select bit 0 cks0 rw a/d control register 1 (note 1) symbol address after reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a/d sweep pin select bit (note 2) scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut v ref connect bit (note 3) a/d operation mode select bit 1 1 : v ref connected 1 0 1 frequency select bit 1 cks1 0 : any mode other than repeat sweep mode 1 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw refer to table 14.2 a/d conversion frequency select refer to table 14.2 a/d conversion frequency select (b7-b6) 0 note 1: if the adcon2 register is rewritten during a/d conversion, the conversion result will be indeterminate. a/d control register 2 (note 1) symbol address after reset adcon2 03d4 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 a/d conversion method select bit bit symbol bit name function rw smp reserved bit set to 0 0 a/d input group select bit 0 0 : select port p10 group (an i ) 0 1 : select port p9 group (an 3i ) 1 0 : do not set 1 1 : do not set b2 b1 frequency select bit 2 cks2 adgsel0 adgsel1 rw rw rw rw rw (b3) nothing is assigned. when write, set to 0 . when read, its content is 0 . (b7-b6) refer to table 14.2 a/d conversion frequency select rw trg1 trigger select bit 1 note 1: if the adcon0 register is rewritten during a/d conversion, the conversion result will be indeterminate. refer to table 14.1.6.2 trigger select bit setting in simultaneous sample sweep mode note 1: if the adcon1 register is rewritten during a/d conversion, the conversion result will be indeterminate. note 2: an 30 to an 32 can be used in the same way as an 0 to an 7 . use the adgsel1 to adgset0 bits in the adcon2 register to select the desired pin. note 3: if the vcut bit is reset from 0 (v ref unconnected) to 1 (v ref connected), wait for 1 s or more before starting a/d conversion. invalid in simultaneous sample sweep mode 1 0 : single sweep mode or simultaneous sample sweep mode b4 b3 when selecting simultaneous sample sweep mode 0 0 : an 0 to an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 5 (6 pins) 1 1 : an 0 to an 7 (8 pins) b1 b0 1 refer to table 14.1.6.2 trigger select bit setting in simultaneous sample sweep mode set to 1 in simultaneous sample sweep mode nothing is assigned. when write, set to 0 . when read, its content is 0 .
14. a/d converter page 193 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 14.1.6.3 adtrgcon register in simultaneous sample sweep mode a/d trigger control register (note 1) symbol address after reset adtrgcon 03d2 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 a/d operation mode select bit 2 bit symbol bit name function rw sse a/d operation mode select bit 3 an1 trigger select bit hptrg1 dte hptrg0 rw rw rw rw nothing is assigned. when write, set to ?? when read, its content is ?? (b7-b4) an0 trigger select bit note 1: if adtrgcon register is rewritten during a/d conversion, the conversion result will be indeterminate. 0 0 : any mode other than delayed trigger mode 0,1 1 : simultaneous sample sweep mode or delayed trigger mode 0, 1 1 0 refer to table 14.1.6.2 trigger select bit setting in simultaneous sample sweep mode set to "0" in simultaneous sample sweep mode table 14.1.6.2 trigger select bit setting in simultaneous sample sweep mode trg hptrg0 trg1 trigger 0 1 1 1 - 1 0 0 software trigger timer b0 underflow (note 1) timer b2 or timer b2 interrupt generation frequency setting counter underflow (note 2) ad trg - - 1 0 note 1: a count can be started for timer b2, timer b2 interrupt generation frequency setting counter underflow or the int5 pin falling edge as count start conditions of timer b0. note 2: select timer b2 or timer b2 interrupt generation frequency setting counter using the tb2sel bit in the tb2sc register.
14. a/d converter page 194 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m item specification function the scan1 to scan0 bits in the adcon1 register and adgsel1 to adgsel0 bits in the adcon2 register select pins. analog voltage applied to the input voltage of the selected pins are converted one-by-one to the digital code. at this time, timer b0 under flow generation starts an 0 pin conversion. timer b1 underflow generation starts con version after the an 1 pin. (note 1) a/d conversion start an 0 pin conversion start condition ? when timer b0 underflow is generated if timer b0 underflow is generated again before timer b1 underflow is generated , the conversion is not affected ? when timer b0 underflow is generated during a/d conversion of pins after the an 1 pin, conversion is halted and the sweep is restarted from an 0 pin an 1 pin conversion start condition ? when timer b1 underflow is generated during a/d conversion of the an 0 pin, the input voltage of the an 1 pin is sampled. the an 1 conversion and the rest of the sweep start when an 0 conversion is completed. a/d conversion stop ? when single sweep conversion from the an 0 pin is completed condition ? set the adst bit to "0" (a/d conversion halted)(note 2) interrupt request a/d conversion completed generation timing analog input pin select from an 0 to an 1 (2 pins), an 0 to an 3 (4 pins), an 0 to an 5 (6 pins) and an 0 to an 7 (8 pins)(note 3) readout of a/d conversion result readout one of the an0 to an7 registers that corresponds to the selected pins note 1: set the larger value than the value of the timer b0 register to the timer b1 register. note 2: do not write 1 (a/d conversion started) to the adst bit in delayed trigger mode 0. when write 1 , unexpected interrupts may be generated. note 3: an 30 to an 32 can be used in the same way as an 0 to an 7 . however, all input pins need to belong to the same group. 14.1.7 delayed trigger mode 0 in delayed trigger mode 0, analog voltages applied to the selected pins are converted one-by-one to a digital code. the delayed trigger mode 0 used in combination with a/d trigger mode of timer b. the timer b0 underflow starts a single sweep conversion. after completing the an 0 pin conversion, the an 1 pin is not sampled and converted until the timer b1 underflow is generated. when the timer b1 under- flow is generated, the single sweep conversion is restarted with the an 1 pin. table 14.1.7.1 shows the delayed trigger mode 0 specifications. figure 14.1.7.1 shows the operation example in delayed trigger mode 0. figure 14.1.7.2 and figure 14.1.7.3 show each flag operation in the adstat0 register that corresponds to the operation example. figure 14.1.7.4 shows the adcon0 to adcon2 registers in delayed trigger mode 0. figure 14.1.7.5 shows the adtrgcon register in delayed trigger mode 0 and table 14.1.7.2 shows the trigger select bit setting in delayed trigger mode 0. table 14.1.7.1 delayed trigger mode 0 specifications
14. a/d converter page 195 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m an 0 an 1 an 2 an 3 timer b0 underflow a/d pin input voltage sampling a/d pin conversion an 0 an 1 an 2 an 3 timrt b0 underflow (an interrupt does not affect a/d conversion) timer b0 underflow timer b1 underflow timer b1 underflow ? example when selecting an 0 to an 3 to analog input pins (scan1 to scan0=01 2 ) example 1: when timer b1 underflow is generated during an 0 pin conversion an 0 an 1 an 2 an 3 timer b0 underflow timer b1 underflow example 2: when timer b1 underflow is generated after an 0 pin conversion an 0 an 1 an 2 an 3 timer b0 underflow (abort othrt pins conversion) timer b0 underflow timer b1 under flow timer b1 underflow example 3: when timer b0 underflow is generated during a/d conversion of any pins except an 0 pin example 4: when timer b0 underflow is generated again before timer b1 underflow is generated after timer b0 underflow generation figure 14.1.7.1 operation example in delayed trigger mode 0
14. a/d converter page 196 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 14.1.7.2 each flag operation in adstat0 register associated with the operation example in delayed trigger mode 0 (1) an 0 an 1 an 2 an 3 timer b0 underflow "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" an 0 an 1 an 2 an 3 "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" a/d pin input voltage sampling a/d pin conversion do not set to "1" by program do not set to "1" by program set to "0" by an interrupt request acknowledgement or a program set to "0" by an interrupt request acknowledgement or a program set to 0" by program set to "0" by program adst flag: bit 6 in the adcon0 register aderr0, aderr1, adtcsf, adstt0, adstt1, adstrt0 and adstrt1 flag: bits 0, 1, 3, 4, 5, 6 and 7 in the adstat0 register adst flag aderr0 flag aderr1 flag adtcsf flag adstt0 flag adstt1 flag adstrt0 flag adstrt1 flag ir bit in the adic register adst flag aderr0 flag aderr1 flag adtcsf flag adstt0 flag adstt1 flag adstrt0 flag adstrt1 flag ir bit in the adic register timer b0 underflow timer b1 underflow timer b1 underflow ? example when selecting an 0 to an 3 to analog input pins (scan1 to scan0=01 2 ) example 1: when timer b1 underflow is generated during an 0 pin conversion example 2: when timer b1 underflow is generated after an 0 pin conversion
14. a/d converter page 197 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m an 0 an 1 an 2 an 3 timer b0 underflow (abort othrt pins conversion ) "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" a/d pin input voltage sampling a/d pin conversion do not set to "1" by program set to "0" by interrupt request acknowledgement or a program set to "0" by program adst flag: bit 6 in the adcon0 register aderr0, aderr1, adtcsf, adstt0, adstt1, adstrt0 and adstrt1 flag: bits 0, 1, 3, 4, 5, 6 and 7 in the adstat0 register adst flag aderr0 flag aderr1 flag adtcsf flag adstt0 flag adstt1 flag adstrt0 flag adstrt1 flag ir bit in the adic register timer b0 underflow timer b1 underflow timer b1 underflow example 3: when timer b0 underflow is generated during a/d pin conversion of any pins except an 0 pin an 0 an 1 an 2 an 3 timrt b0 underflow (an interrupt does not affect a/d conversion) "1" "0" "1" "0" "1" "0" - "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" do not set to "1" by program set to "0" by interrupt request acknowledgement or a program set to "0" by program adst flag aderr0 flag aderr1 flag adtcsf flag adstt0 flag adstt1 flag adstrt0 flag adstrt1 flag ir bit in the adic register timer b0 underflow timer b1 underflow example 4: after timer b0 underflow is generated and when timer b0 underflow is generated again before timer b1 underflow is genetaed figure 14.1.7.3 each flag operation in adstat0 register associated with the operation example in delayed trigger mode 0 (2)
14. a/d converter page 198 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 14.1.7.4 adcon0 to adcon2 registers in delayed trigger mode 0 a/d control register 0 (note 1) symbol address after reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a/d operation mode select bit 0 md0 md1 trigger select bit refer to table 14.1.7.2 trigger select bit setting in delayed trigger mode 0 trg adst a/d conversion start flag (note 2) 0 : a/d conversion disabled 1 : a/d conversion started frequency select bit 0 cks0 rw a/d control register 1 (note 1) symbol address after reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a/d sweep pin select bit (note 2) scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut v ref connect bit (note 3) a/d operation mode select bit 1 1 : v ref connected 01 when selecting delayed trigger sweep mode 0 0 1 1 1 : set to "111b" in delayed trigger mode 0 b2 b1 b0 0 0 : one-shot mode or delayed trigger mode 0,1 b4 b3 1 frequency select bit 1 cks1 0 : any mode other than repeat sweep mode 1 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw refer to table 14.2 a/d conversion frequency select note 1: if the adcon0 register is rewritten during a/d conversion, the conversion result will be indeterminate. note 2: do not write 1 in delayed trigger mode 0. when write, set to "0". note 1: if the adcon1 register is rewritten during a/d conversion, the conversion result will be indeterminate. note 2: an 30 to an 32 can be used in the same way as an 0 to an 7 . use the adgsel1 to adgsel0 bits in the adcon2 register to select the desired pin. note 3: if the vcut bit is reset from 0 (v ref unconnected) to 1 (v ref connected), wait for 1 s or more before starting a/d conversion. refer to table 14.2 a/d conversion frequency select (b7-b6) 1 1 0 b1 b0 0 0: an 0 to an 1 (2 pins) 0 1: an 0 to an 3 (4 pins) 1 0: an 0 to an 5 (6 pins) 1 1: an 0 to an 7 (8 pins) note 1: if the adcon2 register is rewritten during a/d conversion, the conversion result will be indeterminate. note 2: set to 1 in delayed trigger mode 0. a/d control register 2 (note 1) symbol address after reset adcon2 03d4 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 a/d conversion method select bit (note 2) 1 : with sample and hold bit symbol bit name function rw smp reserved bit set to 0 0 a/d input group select bit 0 0 : select port p10 group (an i ) 0 1 : select port p9 group (an 3i ) 1 0 : do not set 1 1 : do not set b2 b1 frequency select bit 2 cks2 adgsel0 adgsel1 rw rw rw rw rw (b3) nothing is assigned. when write, set to 0 . when read, its content is 0 . (b7-b6) refer to table 14.2 a/d conversion frequency select rw trg1 trigger select bit 1 1 refer to table 14.1.7.2 trigger select bit setting in delayed trigger mode 0 nothing is assigned. when write, set to 0 . when read, its content is 0 . 0 0
14. a/d converter page 199 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 14.1.7.5 adtrgcon register in delayed trigger mode 0 a/d trigger control register (note 1) symbol address after reset adtrgcon 03d2 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 a/d operation mode select bit 2 bit symbol bit name function rw sse a/d operation mode select bit 3 an1 trigger select bit hptrg1 dte hptrg0 rw rw rw rw nothing is assigned. when write, set to 0 . when read, its content is 0 . (b7-b4) an0 trigger select bit note 1: if adtrgcon reigster is rewritten during a/d conversion, the conversion result will be indeterminate. 1 delayed trigger mode 0, 1 simultaneous sample sweep mode or delayed trigger mode 0,1 1 refer to table 14.1.7.2 trigger select bit setting in delayed trigger mode 0 refer to table 14.1.7.2 trigger select bit setting in delayed trigger mode 0 1 1 trigger timer b0, b1 underflow trg 0 hptrg0 1 trg1 0 hptrg1 1 table 14.1.7.2 trigger select bit setting in delayed trigger mode 0
14. a/d converter page 200 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 14.1.8 delayed trigger mode 1 in delayed trigger mode 1, analog voltages applied to the selected pins are converted one-by-one to a digital code. when the input of the ad trg pin (falling edge) changes state from h to l , a single sweep conversion is started. after completing the an 0 pin conversion, the an 1 pin is not sampled and converted until the second ad trg pin falling edge is generated. when the second ad trg falling edge is generated, the single sweep conversion of the pins after the an 1 pin is restarted. table 14.1.8.1 shows the delayed trigger mode 1 specifications. figure 14.1.8.1 shows the operation example of delayed trigger mode 1. figure 14.1.8.2 to figure 14.1.8.3 show each flag operation in the adstat0 register that corresponds to the operation example. figure 14.1.8.4 shows the adcon0 to adcon2 registers in delayed trigger mode 1. figure 14.1.8.5 shows the adtrgcon register in delayed trigger mode 1 and table 15.1.8.2 shows the trigger select bit setting in delayed trigger mode 1. table 14.1.8.1 delayed trigger mode 1 specifications item specification function the scan1 to scan0 bits in the adcon1 register and adgsel1 to adgsel0 bits in the adcon2 register select pins. analog voltages applied to the selected pins are converted one-by-one to a digital code. at this time, the ad trg pin falling edge starts an 0 pin conversion and the second ad trg pin falling edge starts conversion of the pins after an 1 pin a/d conversion start an 0 pin conversion start condition condition the ad trg pin input changes state from h to l (falling edge)(note 1) an 1 pin conversion start condition (note 2) the ad trg pin input changes state from h to l (falling edge) ? when the second ad trg pin falling edge is generated during or after a/d conversion of the an 0 pin, input voltage of an 1 pin is sampled at the time of ad trg falling edge. the conversion of an 1 and the rest of the sweep starts when an 0 conversion is completed. ? when the ad trg pin falling edge is generated again during single sweep conver sion of pins after the an 1 pin, the conversion is not affected a/d conversion stop ? a/d conversion completed condition ? set the adst bit to "0" (a/d conversion halted)(note 3) interrupt request single sweep conversion completed generation timing analog input pin select from an 0 to an 1 (2 pins), an 0 to an 3 (4 pins), an 0 to an 5 (6 pins) and an 0 to an 7 (8 pins)(note 4) readout of a/d conversion result readout one of the an0 to an7 registers that corresponds to the selected pins ___________ note 1: when a thrid ad trg pin falling edge is generated again during a/d conversion, its trigger is ignored. ___________ ___________ note 2: the ad trg pin falling edge is detected synchronized with the operation clock ad . therefore, when the ad trg ___________ pin falling edge is generated in shorter periods than ad , the second ad trg pin falling edge may not be ___________ detected. do not generate the ad trg pin falling edge in shorter periods than ad . note 3: do not write 1 (a/d conversion started) to the adst bit in delayed trigger mode 1. when write 1 , unexpected interrupts may be generated. note 4: an 30 to an 32 can be used in the same way as an 0 to an 7 . however, all input pins need to belong to the same group.
14. a/d converter page 201 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m ? example when selecting an 0 to an 3 to analog input pins (scan1 to scan0=01 2 ) a/d pin input voltage sampling a/d pin conversion an 0 an 1 an 2 an 3 ad trg pin input example 1: when ad trg pin falling edge is generated during an 0 pin conversion an 0 an 1 an 2 an 3 example 2: when ad trg pin falling edge is generated again after an 0 pin conversion ad trg pin input example 3: when ad trg pin falling edge is generated more than two times after an 0 pin conversion an 0 an 1 an 2 an 3 (invalid) (valid after single sweep conversion) ad trg pin input figure 14.1.8.1 operation example in delayed trigger mode1
14. a/d converter page 202 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m ? example when selecting an 0 to an 3 to analog input pins (scan1 to scan0=01 2 ) a/d pin input voltage sampling a/d pin conversion an 0 an 1 an 2 an 3 an 0 an 1 an 2 an 3 example 2: when ad trg pin falling edge is generated again after an 0 pin conversion ad trg pin input example 1: when ad trg pin falling edge is generated during an 0 pin conversion adst flag aderr0 flag aderr1 flag adtcsf flag adstt0 flag adstt1 flag adstrt0 flag adstrt1 flag ir bit in the adic register "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" set to "0" by interrupt request acknowledgement or a program adst flag aderr0 flag aderr1 flag adtcsf flag adstt0 flag adstt1 flag adstrt0 flag adstrt1 flag ir bit in the adic register "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" adst flag: bit 6 in the adcon0 register aderr0, aderr1, adtcsf, adstt0, adstt1, adstrt0 and adstrt1 flag: bits 0, 1, 3, 4, 5, 6 and 7 in the adstat0 register set to "0" by program set to "0" by interrupt request acknowledgment or a program set to "0" by program do not set to "1" by program do not set to "1" by program ad trg pin input figure 14.1.8.2 each flag operation in adstat0 register associated with the operation example in delayed trigger mode 1 (1)
14. a/d converter page 203 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m example 3: when ad trg input falling edge is generated more than two times after an 0 pin conversion an 0 an 1 an 2 an 3 (invalid) (valid after single sweep conversion) adst flag aderr0 flag aderr1 flag adtcsf flag adstt0 flag adstt1 flag adstrt0 flag adstrt1 flag ir bit in the adic register "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" "0" set to "0" when interrupt request acknowledgement or a program set to "0" by program do not set to "1" by program a/d pin input voltage sampling a/d pin conversion adst flag: bit 6 in the adcon0 register aderr0, aderr1, adtcsf, adstt0, adstt1, adstrt0 and adstrt1 flag: bits 0, 1, 3, 4, 5, 6 and 7 in the adstat0 register ad trg pin input figure 14.1.8.2 each flag operation in adstat0 register associated with the operation example in delayed trigger mode 1 (2)
14. a/d converter page 204 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m a/d control register 0 (note 1) symbol address after reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a/d operation mode select bit 0 md0 md1 trigger select bit refer to table 14.1.8.2 trigger select bit setting in delayed trigger mode 1 trg adst a/d conversion start flag (note 2) 0 : a/d conversion disabled 1 : a/d conversion started frequency select bit 0 cks0 rw a/d control register 1 (note 1) symbol address after reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a/d sweep pin select bit (note 2) scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut v ref connect bit (note 3) a/d operation mode select bit 1 1 : v ref connected 01 when selecting delayed trigger mode 1 0 1 1 1 : set to "111b" in delayed trigger mode 1 b2 b1 b0 0 0 : one-shot mode or delayed trigger mode 0,1 b4 b3 1 frequency select bit 1 cks1 0 : any mode other than repeat sweep mode 1 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw refer to table 14.2 a/d conversion frequency select note 1: if the adcon0 register is rewritten during a/d conversion, the conversion result will be indeterminate. note 2: do not write 1 in delayed trigger mode 1. when write, set to "0". note 1: if the adcon1 register is rewritten during a/d conversion, the conversion result will be indeterminate. note 2: an 30 to an 32 can be used in the same way as an 0 to an 7 . use the adgsel1 to adgset0 bits in the adcon2 register to select the desired pin. note 3: if the vcut bit is reset from 0 (v ref unconnected) to 1 (v ref connected), wait for 1 s or more before starting a/d conversion. refer to table 14.2 a/d conversion frequency select (b7-b6) 1 1 0 b1 b0 0 0: an 0 to an 1 (2 pins) 0 1: an 0 to an 3 (4 pins) 1 0: an 0 to an 5 (6 pins) 1 1: an 0 to an 7 (8 pins) note 1: if the adcon2 register is rewritten during a/d conversion, the conversion result will be indeterminate. note 2: set to 1 in delayed trigger mode 1. a/d control register 2 (note 1) symbol address after reset adcon2 03d4 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 a/d conversion method select bit (note 2) 1 : with sample and hold bit symbol bit name function rw smp reserved bit set to 0 0 a/d input group select bit 0 0 : select port p10 group (an i ) 0 1 : select port p9 group (an 3i ) 1 0 : do not set 1 1 : do not set b2 b1 frequency select bit 2 cks2 adgsel0 adgsel1 rw rw rw rw rw (b3) nothing is assigned. when write, set to 0 . when read, its content is 0 . (b7-b6) refer to table 14.2 a/d conversion frequency select rw trg1 trigger select bit 1 1 refer to table 14.1.8.2 trigger select bit setting in delayed trigger mode 1 nothing is assigned. when write, set to 0 . when read, its content is 0 . 1 0 figure 14.1.8.4 adcon0 to adcon2 registers in delayed trigger mode 1
14. a/d converter page 205 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m a/d trigger control register (note 1) symbol address after reset adtrgcon 03d2 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 a/d operation mode select bit 2 bit symbol bit name function rw sse a/d operation mode select bit 3 an1 trigger select bit hptrg1 dte hptrg0 rw rw rw rw nothing is assigned. when write, set to 0 . when read, its content is 0 . (b7-b4) an0 trigger select bit note 1: if adtrgcon is rewritten during a/d conversion, the conversion result will be indeterminate. 1 delayed trigger mode 0, 1 simultaneous sample sweep mode or delayed trigger mode 0,1 1 0 refer to table 14.1.8.2 trigger select bit setting in delayed trigger mode 1 refer to table 14.1.8.2 trigger select bit setting in delayed trigger mode 1 0 figure 14.1.8.5 adtrgcon register in delayed trigger mode 1 trigger trg 0 hptrg0 0 trg1 1 ad trg hptrg1 0 table 14.1.8.2 trigger select bit setting in delayed trigger mode 1
14. a/d converter page 206 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 14.2 resolution select function the bits bit in the adcon1 register determines the resolution. when the bits bit is set to 1 (10-bit precision), the a/d conversion result is stored into bits 0 to 9 in the a/d register i (i=0 to 7). when the bits bit is set to 0 (8-bit precision), the a/d conversion result is stored into bits 0 to 7 in the adi register. 14.3 sample and hold when the smp bit in the adcon 2 register is set to 1 (with the sample and hold function), a/d conver- sion rate per pin increases to 28 ad cycles for 8-bit resolution or 33 ad cycles for 10-bit resolution. the sample and hold function is available in one-shot mode, repeat mode, single sweep mode, repeat sweep mode 0 and repeat sweep mode 1. in these modes, start a/d conversion after selecting whether the sample and hold circuit is to be used or not. in simultaneous sample sweep mode, delayed trigger mode 0 or delayed trigger mode 1, set to use the sample and hold function before starting a/d conversion. 14.4 power consumption reducing function when the a/d converter is not used, the vcut bit in the adcon1 register isolates the resistor ladder of the a/d converter from the reference voltage input pin (v ref ). power consumption is reduced by shutting off any current flow into the resistor ladder from the v ref pin. when using the a/d converter, set the vcut bit to 1 (v ref connected) before setting the adst bit in the adcon0 register to 1 (a/d conversion started). do not set the adst bit and vcut bit to 1 simulta- neously, nor set the vcut bit to 0 (v ref unconnected) during a/d conversion.
14. a/d converter page 207 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 14.5 output impedance of sensor under a/d conversion to carry out a/d conversion properly, charging the internal capacitor c shown in figure 14.5.1 has to be completed within a specified period of time. t (sampling time) as the specified time. let output imped- ance of sensor equivalent circuit be r0, microcomputer s internal resistance be r, precision (error) of the a/d converter be x, and the a/d converter s resolution be y (y is 1024 in the 10-bit mode, and 256 in the 8-bit mode). vc is generally vc = vin{1-e c(r0+r) } and when t = t, vc=vin- vin=vin(1- ) e c(r0+r) = - t = ln hence, r0 = - - r figure 14.5.1 shows analog input pin and externalsensor equivalent circuit. when the difference be- tween vin and vc becomes 0.1lsb, we find impedance r0 when voltage between pins. vc changes from 0 to vin-(0.1/1024) vin in timer t. (0.1/1024) means that a/d precision drop due to insufficient capacitor chage is held to 0.1lsb at time of a/d conversion in the 10-bit mode. actual error however is the value of absolute precision added to 0.1lsb. when f(xin) = 10mhz, t=0.3 s in the a/d conversion mode with sample & hold. output inpedance r0 for sufficiently charging capacitor c within time t is determined as follows. t = 0.3 s, r = 7.8k ? , c = 1.5pf, x = 0.1, and y = 1024. hence, r0 = - - 7.8 x 10 3 ? 13.9 x 10 3 thus, the allowable output impedance of the sensor circuit capable of thoroughly driving the a/d con- verter turns out of be approximately 13.9k ? . figure 14.5.1 analog input pin and external sensor equivalent circuit r 0 r (7.8k ? ) c (1.5pf) v in v c sampling time sample-and-hold function enabled: sample-and-hold function disabled: 3 f ad microcomputer sensor equivalent circuit 2 f ad 1 1 t t c(r0+r) 1 x y x y x y x y t c ? ln x y 1.5x10 -12 ? ln 0.1 1024 0.3x10 -6
15. crc calculation circuit page 208 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 15. crc calculation circuit the cyclic redundancy check (crc) operation detects an error in data blocks. the microcomputer uses a generator polynomial of crc_ccitt (x 16 + x 12 + x 5 + 1) or crc-16 (x 16 + x 15 + x 2 + 1) to generate crc code. the crc code is a 16-bit code generated for a block of a given data length in multiples of bytes. the code is updated in the crc data register everytime one byte of data is transferred to a crc input register. the data register needs to be initialized before use. generation of crc code for one byte of data is completed in two machine cycles. figure 15.1 shows the block diagram of the crc circuit. figure 15.2 shows the crc-related registers. figure 15.3 shows the calculation example using the crc_ccitt operation. 15.1. crc snoop the crc circuit includes the ability to snoop reads and writes to certain sfr addresses. this can be used to accumulate the crc value on a stream of data without using extra bandwidth to explicitly write data into the crcin register. for example, it may be useful to snoop the writes to a uart tx buffer , or the reads from a uart rx buffer. this can only be used on usb, uart, and ssi registers. to snoop an sfr address, the target address is written to the crc snoop address register (crcsar). the two most significant bits in this register enable snooping on reads or writes to the target address. if the target sfr is written to by the cpu or dma, and the crc snoop write bit is set (the crcsw bit is set to "1"), the crc will latch the data into the crcin register. the new crc code will be set in the crcd register. similarly, if the target sfr is read by the crc or dma, and the crc snoop read bit is set (the crcsr bit is set to "1"), the crc will latch the data from the target into the crcin register and calculate the crc. the crc circuit can only calculate crc codes on data byte at a time. therefore, if a target sfr is accessed in a word (16 bit) bus cycle, only the byte of data going to or from the target snooped into crcin, the other byte of the word access is ignored. figure 15.1 crc circuit block diagram aaaaa eight low-order bits aaaaa eight high-order bits data bus high-order data bus low-order aaaaaaaaaa aaaaaaaaaa aaaaa aaaaa crcd register (16) crc input register (8) aaaaaaaaaa a aaaaaaaa a aaaaaaaaaa crc code generating circuit x 16 + x 12 + x 5 + 1 or x 16 + x 15 + x 2 + 1 address bus snoopb lock snoop enable snoop address aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa equal? (address 03bd 16 , 03bc 16 ) (address 03be 16 )
15. crc calculation circuit page 209 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m symbol address after reset crcd 03bd 16 to 03bc 16 indeterminate b7 b0 b7 b0 (b15) (b8) crc data register function setting range 0000 16 to ffff 16 rw rw symbol address after reset crcin 03be 16 indeterminate b7 b0 crc input register data input function 00 16 to ff 16 rw rw setting range crc calculation result output symbol address after reset crcsar 03b5 16 to 03b4 16 00xxxxxx xxxxxxxx 16 b7 b0 b7 b0 (b15) (b8) crc snoop address register symbol address after reset crcmr 03b6 16 0xxxxxx0 2 b7 b0 crc mode register crc mode polynomial selection bit function 0: lsb first 1: msb first rw rw bit name bit symbol crc mode selection bit crcps crcms rw nothing is assigned. write "0" when writing to this bit. the value is indeterminate if read. 0: x 16 +x 12 +x 5 +1 (crc-ccitt) 1: x 16 +x 15 +x 2 +1 (crc-16) crc mode polynomial selection bit function 0: lsb first 1: msb first rw rw bit name bit symbol crc mode selection bit crcps crcms rw nothing is assigned. write "0" when writing to this bit. the value is indeterminate if read. 0: x 16 +x 12 +x 5 +1 (crc-ccitt) 1: x 16 +x 15 +x 2 +1 (crc-16) crc mode polynomial selection bit function rw rw bit name bit symbol crcsr rw nothing is assigned. write "0" when writing to this bit. the value is indeterminate if read. sfr address to snoop function 0: disabled 1: enabled rw crcsw crcsar9-0 crc snoop on read enable bit crc snoop on write enable bit 0: disabled 1: enabled rw (b6-b1) (b13-b10) figure 15.2. crcd, crcin, crcmr, crcsar register
15. crc calculation circuit page 210 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 15.3. crc calculation (1) setting 0000 16 (initial value) b15 b0 1 0001 0000 0010 0001 1000 0000 0000 0000 0000 0000 1000 1000 0001 0000 1 1000 0001 0000 1000 0 1000 1000 0001 0000 1 1001 0001 1000 1000 1000 1000 msb modulo-2 operation is operation that complies with the law given below. 0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 0 -1 = 1 the code resulting from sending 01 16 in lsb first mode is (10000 0000).this the crc code in the generating polynomial, (x 16 + x 12 + x 5 + 1), becomes the remainder resulting from dividing(1000 0000)x 16 by ( 1 0001 0000 0010 0001) in conformity with the modulo-2 operation. (2) setting 01 16 b0 b7 b15 b0 1189 16 2 cycles after crc calculation is complete thus the crc code becomes ( 1001 0001 1000 1000). since the operation is in lsb first mode, the (1001 0001 1000 1000) corresponds to 1189 16 in hexadecimal notation. if the crc operation in msb first mode is necessary, set the crc mode selection bit to "1". crc data register stores crc code for msb first mode. crd data register crcd [03bd 16 , 03bc 16 ] crc input register crcin [03be 16 ] crd data register crcd [03bd 16 , 03bc 16 ] crc input register crcin [03be 16 ] (3) setting 23 16 b0 b7 b15 b0 0a41 16 after crc calculation is complete crd data register crcd [03bd 16 , 03bc 16 ] 98 11 msb lsb lsb stores crc code stores crc code
16. programmable i/o ports page 211 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 16. programmable i/o ports note there is no external connections for port p6 0 to p6 3 , p9 2 and p9 3 in the m16c/26a (42-pin version) the programmable input/output ports (hereafter referred to simply as i/o ports ) consist of 39 lines p1 5 to p1 7 , p6, p7, p8, p9 0 to p9 3 , p10 for the 48-pin version, or 33 lines p1 5 to p1 7 , p6 4 to p6 7 , p7, p8, p9 0 to p9 1 , p10 for the 42-pin version. each port can be set for input or output every line by using a direction register, and can also be chosen to be or not be pulled high in sets of 4 lines. figures 16.1 to 16.4 show the i/o ports. figure 16.5 shows the i/o pins. each pin functions as an i/o port, a peripheral function input/output. for details on how to set peripheral functions, refer to each functional description in this manual. if any pin is used as a peripheral function input, set the direction bit for that pin to 0 (input mode). any pin used as an output pin for peripheral functions is directed for output no matter how the corresponding direction bit is set. 16.1 port pi direction register (pdi register, i = 1, 6 to 10) figure 16.1.1 shows the direction registers. this register selects whether the i/o port is to be used for input or output. the bits in this register corre- spond one for one to each port. 16.2 port pi register (pi register, i = 1, 6 to 10) figure 16.2.1 shows the pi registers. data input/output to and from external devices are accomplished by reading and writing to the pi register. the pi register consists of a port latch to hold the output data and a circuit to read the pin status. for ports set for input mode, the input level of the pin can be read by reading the corresponding pi register, and data can be written to the port latch by writing to the pi register. for ports set for output mode, the port latch can be read by reading the corresponding pi register, and data can be written to the port latch by writing to the pi register. the data written to the port latch is output from the pin. the bits in the pi register correspond one for one to each port. 16.3 pull-up control register 0 to pull-up control register 2 (pur0 to pur2 registers) figure 16.3.1 shows the pur0 to pur2 registers. the bits in the pur0 to pur2 registers can be used to select whether or not to pull the corresponding port high in 4 bit units. the port chosen to be pulled high has a pull-up resistor connected to it when the direction bit is set for input mode. ____________ also, p6 7 is connected to a pull-up resistor when the cnv ss pin is h , and the reset pin is l .
16. programmable i/o ports page 212 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 16.4 port control register figure 16.4.1 shows the port control register. when the p1 register is read after setting the pcr0 bit in the pcr register to 1 , the corresponding port latch can be read no matter how the pd1 register is set. 16.5 pin assignment control register (pacr) figure 16.5.1 shows the pacr. after reset set the pacr2 to pacr0 bit before you input and output it to each pin. when the pacr register isn t set up, the input and output function of some of the pins doesn t work. pacr2 to pacr0 bits: control the pins enabled for use. at reset these bits equal 000 . when using the 48 pin version of the m16c/26a and the 48 pin version of the m16c/26t set these bits to 100 2 . when using the 42 pin version of the m16c/26a set these bits to 001 2 . u1map: controls the assignment of uart1 pins. if the u1map bit is set to 0 (p6 7 to p6 4 ) the uart1 functions are mapped to p6 4 /cts 1 /rts 1 , p6 5 /clk 1 , p6 6 /rxd 1 , and p6 7 /txd 1 . if the u1map bit is set to 1 (p7 3 to p7 0 ) the uart1 functions are mapped to p7 0 /cts 1 /rts 1 , p7 1 /clk 1 , p7 2 /rxd 1 , and p7 3 /txd 1 . pacr is write protected by prc2 bit in the prcr register. prc2 bit must be set immediately before the write to pacr. 16.6 digital debounce function two digital debounce function circuits are provided. level is determined when level is held, after applying either a falling edge or rising edge to the pin, longer than the programmed filter width time. this enables noise reduction. ________ _______ _____ this function is assigned to int5/inpc17 and nmi/sd. digital filter width is set in the nddr register and the p17ddr register respectively. additionally, a digital debounce function is disabled to the port p1 7 input and port p8 5 input. figure 16.6.1 shows the nddr register and the p17ddr register. filter width : f8 1 / (n+1) n: count value set in the nddr register and p17ddr register the nddr register and the p17ddr register decrement count value with f8 as the count source. the nddr register and the p17ddr register indicate count time. count value is reloaded if a falling edge or a rising edge is applied to the pin. the nddr register and the p17ddr register can be set 00 16 to ff 16 when using the digital debounce function. setting to ff 16 disables the digital filter. see figure 16.6.2 for details.
16. programmable i/o ports page 213 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 16.1. i/o ports (1) p9 3 (inside dotted-line included) data bus (note 1) analog input pull-up selection direction register port latch p6 0 , p6 1 , p6 4 , p6 5 , p7 3 , p7 5 , p8 1 note 1: symbolizes a parasitic diode. make sure the input voltage on each port will not exceed vcc. p7 4 , p7 6 , p8 0 (inside dotted-line not included) (inside dotted-line included) "1" output data bus direction register port latch pull-up selection (note 1) input to respective peripheral functions p1 5 to p1 6 data bus p1 7 (inside dotted-line not included) (inside dotted-line included) direction register port latch pull-up selection (note 1) port p1 control register input to respective peripheral functions int5 digital debounce
16. programmable i/o ports page 214 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 16.2. i/o ports (2) p8 2 to p8 4 (note 1) p7 7 (inside dotted-line not included) p9 0 to p9 2 (inside dotted-line included) data bus pull-up selection direction register port latch data bus pull-up selection direction register port latch input to respective peripheral functions input to respective peripheral functions (note 1) p7 0 , p7 1 , p7 2 "1" output data bus direction register port latch pull-up selection (note 1) input to respective peripheral functions note 1: symbolizes a parasitic diode. make sure the input voltage on each port will not exceed vcc. switching between cmos and nch analog input
16. programmable i/o ports page 215 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 16.3. i/o ports (3) p6 2 , p6 6 data bus pull-up selection direction register port latch input to respective peripheral functions (note 1) p8 5 p6 3 , p6 7 output 1 data bus pull-up selection direction register port latch (note 1) switching between cmos and nch note 1: symbolizes a parasitic diode. make sure the input voltage on each port will not exceed vcc. switching between cmos and nch data bus pull-up selection direction register port latch nmi interrupt input nmi enable digital debounce nmi enable sd (note 1)
16. programmable i/o ports page 216 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 16.4. i/o ports (4) data bus direction register pull-up selection port latch analog input input to respective peripheral functions p10 0 to p10 3 (inside dotted-line not included) p10 4 to p10 7 (inside dotted-line included) (note 1) p8 7 p8 6 fc rf rd data bus direction register pull-up selection port latch direction register pull-up selection port latch data bus (note) (note) note: symbolizes a parasitic diode. make sure the input voltage on each port will not exceed vcc.
16. programmable i/o ports page 217 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 16.5. i/o pins cnv ss cnv ss signal input reset reset signal input (note 1) (note 1) note 1: symbolizes a parasitic diode. make sure the input voltage on each port will not exceed vcc.
16. programmable i/o ports page 218 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 16.1.1. pd1, pd6, pd7, pd8, pd9, and pd10 registers port pi direction register (i=6 to 8, and 10) (note) symbol address after reset pd6 to pd8 03ee 16 , 03ef 16 , 03f2 16 00 16 pd10 03f6 16 00 16 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 pdi_0 port pi 0 direction bit pdi_1 port pi 1 direction bit pdi_2 port pi 2 direction bit pdi_3 port pi 3 direction bit pdi_4 port pi 4 direction bit pdi_5 port pi 5 direction bit pdi_6 port pi 6 direction bit pdi_7 port pi 7 direction bit 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) (i = 6 to 8, and 10) note: ports must be enabled using the pacr in 48 pin version set pacr2, pacr1, pacr0 to "100 2 " in 42 pin version set pacr2, pacr1, pacr0 to "001 2 " rw rw rw rw rw rw rw rw port p1 direction register (note 1) symbol address after reset pd1 03e3 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) rw pd1_5 port p1 5 direction bit rw pd1_6 port p1 6 direction bit rw pd1_7 port p1 7 direction bit rw nothing is assigned. in an attempt to write to this bit, write 0 . the value, if read, turns out to be indeterminate. (b4-b0) note 1: ports must be enabled using the pacr in 48 pin version set pacr2, pacr1, pacr0 to "100 2 " in 42 pin version set pacr2, pacr1, pacr0 to "001 2 " port p9 direction register (note 1,2) symbol address after reset pd9 03f3 16 xxxx0000 2 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 pd9_0 port p9 0 direction bit pd9_1 port p9 1 direction bit pd9_2 port p9 2 direction bit pd9_3 port p9 3 direction bit 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) rw rw rw rw rw nothing is assigned. in an attempt to write to this bit, write 0 . the value, if read, turns out to be indeterminate. (b7-b4) note 1: make sure the pd9 register is written to by the next instruction after setting the prcr register's prc2 bit to "1"(write enabled). note 2: ports must be enabled using the pacr in 48 pin version set pacr2, pacr1, pacr0 to "100 2 " in 42 pin version set pacr2, pacr1, pacr0 to "001 2 "
16. programmable i/o ports page 219 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m symbol address after reset p6 to p8 03ec 16 , 03ed 16 , 03f0 16 indeterminate p10 03f4 16 indeterminate port pi register (i=6 to 8 and 10) (note1) bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 pi_0 port pi 0 bit pi_1 port pi 1 bit pi_2 port pi 2 bit pi_3 port pi 3 bit pi_4 port pi 4 bit pi_5 port pi 5 bit pi_6 port pi 6 bit pi_7 port pi 7 bit the pin level on any i/o port which is set for input mode can be read by reading the corresponding bit in this register. the pin level on any i/o port which is set for output mode can be controlled by writing to the corresponding bit in this register 0 : l level 1 : h level (note 1) (i = 6 to 8 and 10) rw rw rw rw rw rw rw rw note1: ports must be enabled using the pacr in 48 pin version set pacr2, pacr1, pacr0 to "100 2 " in 42 pin version set pacr2, pacr1, pacr0 to "001 2 " port p1 register (note1) symbol address after reset p1 03e1 16 indeterminate bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 p1_5 port p1 5 bit p1_6 port p1 6 bit p1_7 port p1 7 bit the pin level on any i/o port which is set for input mode can be read by reading the corresponding bit in this register. the pin level on any i/o port which is set for output mode can be controlled by writing to the corresponding bit in this register 0 : l level 1 : h level rw rw rw rw note1: ports must be enabled using the pacr in 48 pin version set pacr2, pacr1, pacr0 to "100 2 " in 42 pin version set pacr2, pacr1, pacr0 to "001 2 " nothing is assigned. in an attempt to write to this bit, write 0 . the value, if read, turns out to be indeterminate. (b4-b0) port p9 register (note1) symbol address after reset p9 03f1 16 indeterminate bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 p9_0 port p9 0 bit p9_1 port p9 1 bit p9_2 port p9 2 bit p9_3 port p9 3 bit the pin level on any i/o port which is set for input mode can be read by reading the corresponding bit in this register. the pin level on any i/o port which is set for output mode can be controlled by writing to the corresponding bit in this register 0 : l level 1 : h level rw rw rw rw rw note1: ports must be enabled using the pacr in 48 pin version set pacr2, pacr1, pacr0 to "100 2 " in 42 pin version set pacr2, pacr1, pacr0 to "001 2 " nothing is assigned. in an attempt to write to this bit, write 0 . the value, if read, turns out to be indeterminate. (b7-b4) figure 16.2.1. p1, p6, p7, p8, p9, and p10 registers
16. programmable i/o ports page 220 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m pull-up control register 0 symbol address after reset pur0 03fc 16 00 16 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 pu03 p1 5 to p1 7 pull-up 0 : not pulled high 1 : pulled high (note) rw note : the pin for which this bit is 1 (pulled high) and the direction bit is 0 (input mode) is pulled high. pull-up control register 2 symbol address after reset pur2 03fe 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 pu20 p8 0 to p8 3 pull-up pu21 p8 4 to p8 7 pull-up pu22 p9 0 to p9 3 pull-up pu24 p10 0 to p10 3 pull-up pu25 p10 4 to p10 7 pull-up nothing is assigned. in an attempt to write to these bits, write 0 . the value, if read, turns out to be 0 . 0 : not pulled high 1 : pulled high (note) rw rw rw rw rw rw (b7-b6) note : the pin for which this bit is 1 (pulled high) and the direction bit is 0 (input mode) is pulled high. nothing is assigned. in an attempt to write to these bits, write 0 . the value, if read, turns out to be 0 . (b2-b0) nothing is assigned. in an attempt to write to these bits, write 0 . the value, if read, turns out to be 0 . (b7-b4) pull-up control register 1 symbol address after reset(note 5) pur1 03fd 16 00000000 2 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 pu14 p6 0 to p6 3 pull-up pu15 p6 4 to p6 7 pull-up pu16 p7 0 to p7 3 pull-up pu17 p7 4 to p7 7 pull-up 0 : not pulled high 1 : pulled high (note) note : the pin for which this bit is 1 (pulled high) and the direction bit is 0 (input mode) is pulled high. rw rw rw rw rw nothing is assigned. in an attempt to write to these bits, write 0 . the value, if read, turns out to be 0 . (b3-b0) 0 : not pulled high 1 : pulled high (note) nothing is assigned. in an attempt to write to these bits, write 0 . the value, if read, turns out to be 0 . (b3) figure 16.3.1. pur0 to pur2 registers
16. programmable i/o ports page 221 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 16.4.1. pcr register port control register symbpl address after reset pcr 03ff 16 00 16 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 pcr0 port p1 control bit nothing is assigned. in an attempt to write to these bits, write 0 . the value, if read, turns out to be 0 . rw (b7-b1) operation performed when the p1 register is read 0: when the port is set for input, the input levels of p10 to p17 pins are read. when set for output, the port latch is read. 1: the port latch is read regardless of whether the port is set for input or output. figure 16.5.1. pacr register pin assignment control register (note) symbpl address after reset pacr 025d 16 00000000 2 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 pin enabling bit nothing is assigned. in an attempt to write to these bits, write 0 . the value, if read, turns out to be 0 . rw (b6-b3) 001 : 42 pin 100 : 48 pin all other values are reserved. do not use. pacr0 pacr1 pacr2 rw rw reserved bits u1map uart1 pin remapping bit uart1 pins assigned to 0 : p6 7 to p6 4 1 : p7 3 to p7 0 rw note : make sure the pacr register is written to by the next instruction after setting the prc2 bit in the prcr re g ister to 1 (write enable).
16. programmable i/o ports page 222 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 16.6.1. nddr and p17ddr registers nmi digital debounce register (note) symbol address after reset nddr 033e 16 ff 16 rw b7 b0 function rw note 1 : if the microcomputer is to be moved out of stop mode by nmi interrupt, make sure nddr register is set to ff 16 (the digital debounce filter is disabled) before entering stop mode. note 2 : make sure the pacr register is written to by the next instruction after setting the prc2 bit in the prcr register to "1" (write enable). setting range 00 16 ~ff 16 assuming that set value =n, for n = 0 to feh, nmi / sd pulse whose width is greater than (v1/8) / ( n + 1) will be input. for n = ffh, the digital debounce filter is disabled. all signals are input. p1 7 digital debounce register symbol address after reset p17ddr 033f 16 ff 16 rw b7 b0 function rw setting range 00 16 ~ff 16 assuming that set value =n, for n = 0 to feh, inpc1 7 /int5 pulse whose width is greater than (v1/8) / ( n + 1) will be input. for n = ffh, the digital debounce filter is disabled. all signals are input. note : if the microcomputer is to be moved out of stop mode by int5 interrupt, make sure p17ddr register is set to ff 16 (the digital debounce filter is disabled) before entering stop mode.
16. programmable i/o ports page 223 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 16.6.2. functioning of digital debounce filter f 8 p8 5 / p1 7 data bus 1. (condition after reset). reload = ff, port in = signal out continuosly. 2. reload = 03. at edge of port in != signal out, counter gets reload value and stats counting down. 3. port in = signal out, counting stops. 4. at edge of port in != signal out, counter gets reload value and starts counting. 5. counter underflows, stops, and port in is driven to signal out. 6. at edge of port in != signal out, counter gets reload value and starts counting. 7. counter underflows, stops, and port in is driven to signal out. 8. at edge of port in != signal out, counter gets reload value and starts counting. 9. ff is written to reload value. counter is stopped and loaded with ff. port in = signal out continuously. clock port in reload value (write) digital debounce filter signal out count value (read) to nmi and sd / int5 and inpc17 data bus f 8 reload value port in signal out count value reload value (continued) port in (continued) signal out (continued) count value (continued) ff 03 ff 03 02 01 03 02 01 00 ff 03 ff 03 02 01 00 ff ff 03 02 ff 1 2 3 4 5 6 7 8 9
16. programmable i/o ports page 224 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m pin name connection ports p1, p6 to p10 x out (note 3) av ss , v ref av cc after setting for input mode, connect every pin to v ss via a resistor(pull-down); or after setting for output mode, leave these pins open. (note 1, note 2, note 4) open connect to v cc connect to v ss note 1: when setting the port for output mode and leave it open, be aware that the port remains in input mode until it is switched to output mode in a program after reset. for this reason, the voltage level on the pin becomes indeterminate, causing the power supply current to increase while the port remains in input mode. futhermore, by considering a possibility that the contents of the direction registers could be changed by noise or noise-induced runaway, it is recommended that the contents of the directionregisters be periodically reset in software, for the increased reliability of the program. note 2: make sure the unused pins are processed with the shortest possible wiring from the microcomputer pins (within 2 cm). note 3: with external clock or v cc input to x in pin. note 4: when using the 48pin version, set pacr2, pacr1, pacr0 to "100 2 ". when using the 42pin version, set pacr2, pacr1, pacr0 to "001 2 ". note 5: when the main clock oscillation circuit is not used, set the cm05 bit in the cm0 register to 0 (main clock stops) to reduce power consumption. connect via resistor to v cc (pull-up) (note 5) xin table 16.1. unassigned pin handling in single-chip mode figure 16.7. unassigned pins handling (input mode) (input mode) (output mode) x out av cc av ss v ref microcomputer v cc v ss in single-chip mode open open note : when using the 48pin version, set pacr2, pacr1, pacr0 to "100 2 ". when using the 42pin version, set pacr2, pacr1, pacr0 to "001 2 ". (note) port p1, p6 to p10 x in
17. flash memory version page 225 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m table 17.1. flash memory version specifications item flash memory operating mode erase block program method erase method program, erase control method protect method number of commands program/erase endurance(note1) rom code protection specification 3 modes (cpu rewrite, standard serial i/o, parallel i/o) see figure 17.2.1 to17.2.3 flash memory block diagram in units of word block erase program and erase controlled by software command all user blocks are write protected by bit fmr16. in addition, the block 0 and block 1 are write protected by bit fmr02. 5 commands 100 times (u3, u5) 1,000 times (u7, u9) 100 times (u3, u5) 10,000 times (u7, u9) parallel i/o and standard serial i/o modes are supported. data retention 20 years (topr=55 c) block 0 to 3 (program area) block a and b (data are) (note2) note 1: program and erase endurance definition program and erase endurance are the erase endurance of each block. if the program and erase endurance are n times (n=100,1,000,10,000), each block can be erased n times. for example, if a 2-kbyte block a is erased after writing 1 word data 1024 times, each to different addresses, this is counted as one program and erasure. however, data cannot be written to the same address more than once without erasing the block. (rewrite disabled) note 2: to use the limited number of erasure efficiently, write to unused address within the block instead of rewrite. erase block only after all possible address are used. for example, an 8-word program can be written 128 times before erase is necessary. maintaining an equal number of erasure between block a and b will also improve efficiency. we recommend keeping track of the number of times erasure is used. 17. flash memory version 17.1 flash memory performance the flash memory version is functionally the same as the mask rom version except that it internally con- tains flash memory. in the flash memory version, the flash memory can perform in three rewrite mode : cpu rewrite mode, standard serial i/o mode and parallel i/o mode. table 17.1 shows the flash memory version specifications. (refer to table 1.1 performance outline of m16c/26a group (48-pin device)" for the items not listed in table 17.1. or table 1.2 performance outline of m16c/26a group (42-pin device) ).
17. flash memory version page 226 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m table 17.2. flash memory rewrite modes overview flash memory cpu rewrite mode standard serial i/o mode parallel i/o mode rewrite mode function area which user rom area user rom area user rom area can be rewritten operation single chip mode boot mode parallel i/o mode mode rom none serial programmer parallel programmer programmer the user rom area is rewrit- ten when the cpu executes software command ew0 mode: rewrite in area other than flash memory ew1 mode: rewrite in flash memory the user rom area is rewrit- ten using a dedicated serial programmer. standard serial i/o mode 1: clock synchronous serial i/o standard serial i/o mode 2: uart the user rom area is rewrit- ten using a dedicated paral- lel programmer
17. flash memory version page 227 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 17.2 memory map the flash memory contains the user rom area and the boot rom area (reserved area). figures 17.2.1 to 17.2.3 show the flash memory block diagram. the user rom area has space to store the microcomputer operation program in single-chip mode and a separate 2-kbyte space as the block a and b. the user rom area is divided into several blocks. the user rom area can be rewritten in cpu rewrite, standard serial input/output, and parallel input/output modes. however, if block 0 and 1 are rewritten in cpu rewrite mode, setting the fmr02 bit in the fmr0 register to 1 (block 0, 1 rewrite enabled) and the fmr16 bit in the fmr1 register to 1 (blocks 0 to 3 rewrite enabled) enable rewriting. also, if blocks 2 to 3 are rewritten in cpu rewrite mode, setting the fmr16 bit in the fmr1 register to 1 (blocks 0 to 3 rewrite enabled) enables writing. setting the pm10 bit in the pm1 register to 1 (data area access enabled) for block a and b enables to use. the boot rom area is reserved area. this boot rom area has a standard serial i/o mode control program stored in it when shipped from the factory. do not rewrite the boot rom area. 00ffff 16 block b :2k bytes (note 2) 00f000 16 4k bytes (note 4) 0ff000 16 0fffff 16 boot rom area 0fe000 16 0fc000 16 0fdfff 16 0f8000 16 block 2 : 16k bytes 0fbfff 16 0f7fff 16 0f0000 16 0fffff 16 user rom area block a :2k bytes (note 2) block 2 : 16k bytes (note 5) block 3 : 32k bytes (note 5) block 1 : 8k bytes (note 3) block 0 : 8k bytes (note 3) 00f7ff 16 00f800 16 note 1: to specify a block, use the maximum even address in the block. note 2: blocks a and b are enabled to use when the pm10 bit in the pm1 register is set to "1". note 3: blocks 0 and 1 are enabled for programs and erases when the fmr02 bit in the fmr0 register is set to "1" and the fmr16 bit in the fmr1 register is set to "1". (cpu rewrite mode only) note 4: the boot rom area is reserved. do not access. note 5: blocks 2 and 3 are enabled for programs and erases when the fmr16 bit in the fmr1 register is set to "1". (cpu rewrite mode only) figure 17.2.1. flash memory block diagram (rom capacity 64k byte)
17. flash memory version page 228 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 00ffff 16 block b :2k bytes (note 2) 00f000 16 4k bytes (note 4) 0ff000 16 0fffff 16 boot rom area 0fe000 16 0fc000 16 0fdfff 16 0f8000 16 0fbfff 16 0f7fff 16 0f4000 16 0fffff 16 user rom area block 2 : 16k bytes (note 5) block a :2k bytes (note 2) block 1 : 8k bytes (note 3) block 0 : 8k bytes (note 3) block 3 : 16k bytes (note 5) 00f7ff 16 00f800 16 note 1: to specify a block, use the maximum even address in the block. note 2: blocks a and b are enabled to use when the pm10 bit in the pm1 register is set to "1". note 3: blocks 0 and 1 are enabled for programs and erases when the fmr02 bit in the fmr0 register is set to "1" and the fmr16 bit in the fmr1 register is set to "1". (cpu rewrite mode only) note 4: the boot rom area is reserved. do not access. note 5: blocks 2 and 3 are enabled for programs and erases when the fmr16 bit in the fmr1 register is set to "1". (cpu rewrite mode only) figure 17.2.2. flash memory block diagram (rom capacity 48k byte)
17. flash memory version page 229 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 00ffff 16 block b :2k bytes (note 2) 00f000 16 4k bytes (note 4) 0ff000 16 0fffff 16 boot rom area 0fe000 16 0fc000 16 0fdfff 16 0fa000 16 0fbfff 16 0fffff 16 user rom area block a :2k bytes (note 2) block 2 : 8k bytes (note 5) block 1 : 8k bytes (note 3) block 0 : 8k bytes (note 3) 00f7ff 16 00f800 16 note 1: to specify a block, use the maximum even address in the block. note 2: blocks a and b are enabled to use when the pm10 bit in the pm1 register is set to "1". note 3: blocks 0 and 1 are enabled for programs and erases when the fmr02 bit in the fmr0 register is set to "1" and the fmr16 bit in the fmr1 register is set to "1". (cpu rewrite mode only) note 4: the boot rom area is reserved. do not access. note 5: blocks 2 is enabled for programs and erases when the fmr16 bit in the fmr1 register is set to "1". (cpu rewrite mode only) figure 17.2.3. flash memory block diagram (rom capacity 24k byte)
17. flash memory version page 230 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 17.3 functions to prevent flash memory from rewriting the flash memory has a built-in rom code protect function for parallel i/o mode and a built-in id code check function for standard input/output mode to prevent the flash memory from reading or rewriting. 17.3.1 rom code protect function the rom code protect function prevents the flash memory from reading and rewriting in parallel input/ output mode. figure 17.3.1.1 shows the romcp register. the romcp register is located in the user rom area. the romcp1 bit consists of two bits. the rom code protect function is enabled and reading and rewriting flash memory is disabled when setting either or both of two romcp1 bits to 0 other than the romcr bit is 00 2 . however, when setting the romcr bit to 00 2 , the flash memory can be read or rewritten. once the rom code protect function is enabled, the romcr bits can not be changed in paral- lel input/output mode. therefore, use the standard serial input/output or other modes to rewrite the flash memory. 17.3.2 id code check function use the id code check function in standard serial input/output mode. unless the flash memory is blank, the id codes sent from the programmer and the seven bytes id codes written in the flash memory are compared to see if they match. if the id codes do not match, the commands sent from the programmer are not acknowledged. the id code consists of 8-bit data, starting with the first byte, into addresses, 0fffdf 16 , 0fffe3 16 , 0fffeb 16 , 0fffef 16 , 0ffff3 16 , 0ffff7 16 , and 0ffffb 16 . the flash memory has a program with the id code set in these addresses.
17. flash memory version page 231 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 17.3.1.1. romcp address figure 17.3.2.1. address for id code stored symbol address factory setting romcp 0fffff 16 ff 16 (note 4) rom code protect control address bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 00: disables protect 01: 10: 11: 00: 01: 10: 11: disables protect rom code protect reset bit (note 2, note 4) rom code protect level 1 set bit (note 1, note 3, note 4) romcr romcp1 b5 b4 b7 b6 1 1 reserved bit set this bit to 1 reserved bit set this bit to 1 reserved bit set this bit to 1 reserved bit set this bit to 1 enables romcp1 bit } enables protect } note 1: when the romcr bits are set to other than 00 2 and the romcp1 bits are set to other than 11 2 (rom code protect enabled), the flash memory is disabled against reading and rewriting in parallel input/output mode. note 2: when the romcr bits are set to 00 2 , the rom code protect level 1 is reset. because the romcr bits can not be modified in parallel input/output mode, modify in standard serial input/ output mode. note 3: the romcp1 bits are valid when the romcr bits are 01 2 , 10 2 or 11 2 . note 4: this bit can not be set to 1 once it is set to 0 . the romcp address is set to ff 16 when a block, including the romcp address, is erased. 1 1 rw rw rw rw rw rw rw rw rw reset vector watchdog timer vector single step vector address match vector brk instruction vector overflow vector undefined instruction vector id7 id6 id5 id4 id3 id2 id1 dbc vector nmi vector 0fffff 16 to 0ffffc 16 0ffffb 16 to 0ffff8 16 0ffff7 16 to 0ffff4 16 0ffff3 16 to 0ffff0 16 0fffef 16 to 0fffec 16 0fffeb 16 to 0fffe8 16 0fffe7 16 to 0fffe4 16 0fffe3 16 to 0fffe0 16 0fffdf 16 to 0fffdc 16 4 bytes address romcp
17. flash memory version page 232 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m item ew0 mode ew1 mode (note 2) operation mode single chip mode single chip mode area where user rom area user rom area rewrite control program can be placed area where the rewrite control program must be the rewrite control program can be rewrite control transferred to any area other than executed in the user rom area program can be the flash memory (e.g., ram) before executed being executed area which can be user rom area user rom area rewritten however, this excludes blocks with the rewrite control program software command none ? program, block erase command restrictions cannot be executed in a block having the rewrite control program ? read status register command can not be used mode after programming read status register mode read array mode or erasing cpu state during auto- operation hold state (i/o ports retain the state write and auto-erase before the command is executed (note 1) flash memory status ? read the fmr00, fmr06 and read the fmr0 register's fmr00, detection(note 2) fmr07 bits in the fmr0 register by fmr06, and fmr07 bits in a program a program ? execute the read status register command and read the sr7, sr5 and sr4 bits condition for transferring set the fmr40 and fmr41 bits in the fmr40 bit in the fmr4 register to erase-suspend (note 3) the fmr4 register to "1" by program. is set to "1" and the interrupt request of 17.4 cpu rewrite mode in cpu rewrite mode, the user rom area can be rewritten when the cpu executes software commands. therefore, the user rom area can be rewritten directly while the microcomputer is mounted on-board without using a rom programmer, etc. verify the program and the block erase commands are executed only on blocks in the user rom area. for interrupts requested during an erasing operation in cpu rewrite mode, the m16c/26a flash module offers an erase-suspend function which the erasing operation to be suspended, and access made available to the flash. erase-write 0 (ew0) mode and erase-write 1 (ew1) mode are provided as cpu rewrite mode. table 17.4.1 shows the differences between erase-write 0 (ew0) and erase-write 1 (ew1) modes. 1 wait is required for the cpu erase-write control. table 17.4.1. ew0 mode and ew1 mode note 1: do not generate a dma transfer. note 2: block 1 and 0 are enabled to rewrite by setting the fmr02 bit in the fmr0 register to "1" and setting the fmr16 bit in the fmr1 register to "1". block 2 to 3 are enabled to rewrite by setting the fmr16 bit in the fmr1 register to "1". note 3: the time, until entering erase suspend and reading flash is enabled, is maximum td (sr-es) after satisfying the conditions.
17. flash memory version page 233 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 17.4.1 ew0 mode the microcomputer enters cpu rewrite mode by setting the fmr01 bit in the fmr0 register to 1 (cpu rewrite mode enabled) and is ready to acknowledge the software commands. ew0 mode is selected by setting the fmr11 bit in the fmr1 register to 0 . when setting the fmr01 bit to 1 , set to 1 after first writing 0 . the software commands control pro- gramming and erasing. the fmr0 register or the status register indicates whether a programming or erasing operations is completed. when entering the erase-suspend during the auto-erasing, set the fmr40 bit to 1 (erase-suspend enabled) and the fmr41 bit to 1 (suspend request). and wait for td(sr-es). after verifying the fmr46 bit is set to 1 (auto-erase stop), access to the user rom area. when setting the fmr41 bit to 0 (erase restart), auto-erasing is restarted. 17.4.2 ew1 mode ew1 mode is selected by setting the fmr11 bit to 1 after the fmr01 bit is set to 1 . (set to 1 after first writing 0 ). the fmr0 register indicates whether or not a programming or an erasing operation is com- pleted. do not execute the software commands of read status register in ew1 mode. when an erase/program operation is initiated the cpu halts all program execution until the operation is completed or erase-suspend is requested. when enabling an erase suspend function, set the fmr40 bit to 1 (erase suspend enabled) and ex- ecute block erase commands. also, preliminarily set an interrupt to enter the erase-suspend to an inter- rupt enabled status. after td(sr-es) from an interrupt request and entering erase suspend, an interrupt can be acknowledged. when an interrupt request is generated, the fmr41 bit is automatically set to 1 (suspend request) and an auto-erasing is halted. if an auto-erasing is not completed (the fmr00 bit is 0 ) after an interrupt process completed, set the fmr41 bit to 0 (erase restart) and execute block erase commands again.
17. flash memory version page 234 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 17.5 register description figure 17.5.1 shows the flash memory control register 0 and flash memory control register 1. figure 17.5.2 shows the flash memory control register 4. 17.5.1 flash memory control register 0 (fmr0) ? fmr 00 bit this bit indicates the operation status of the flash memory. the bit is 0 during programming, erasing, or erase-suspend mode; otherwise, the bit is 1 . ? fmr01 bit the microcomputer enables to acknowledge commands by setting the fmr01 bit to 1 (cpu rewrite mode). to set this bit to 1 , it is necessary to set to 1 after first setting to 0 . set this bit to 0 by only writing 0 . ? fmr02 bit the combined setting of the fmr02 bit and the fmr16 bit enable to program and erase in the user rom area. see table 17.5.2.1 for setting details. to set this bit to 1 , it is necessary to set to 1 after first setting to 0 . set this bit to 0 by only writing 0 . this bit is enabled only when the fmr01 bit is 1 (cpu rewrite mode enable). ? fmstp bit this bit resets the flash memory control circuits and minimizes power consumption in the flash memory. access to the flash memory is disabled when the fmstp bit is set to 1 . set the fmstp bit by a program in a space other than the flash memory. set the fmstp bit to 1 if one of the following occurs: ? a flash memory access error occurs during erasing or programming in ew0 mode (fmr00 bit does not switch back to 1 (ready)). ? low-power consumption mode or on-chip oscillator low-power consumption mode is entered. figure 17.5.1.3 shows a flow chart illustrating how to start and stop the flash memory before and after entering low power mode. follow the procedure on this flow chart. when entering stop or wait mode, the flash memory is automatically turned off. when exiting stop or wait mode, the flash memory is turned back on. the fmr0 register does not need to be set. ? fmr06 bit this is a read-only bit indicating an auto-program operation status. this bit is set to 1 when a pro- gram error occurs; otherwise, it is set to 0 . for details, refer to 17.8.4 full status check . ? fmr07 bit this is a read-only bit indicating an auto-erase operation status. the bit is set to 1 when an erase error occurs; otherwise, it is set to 0 . for details, refer to 17.8.4 full status check . figure 17.5.1.1 shows a ew0 mode set/reset flowchart, figure 17.5.1.2 shows a ew1 mode set/reset flowchart.
17. flash memory version page 235 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 17.5.2 flash memory control register 1 (fmr1) ? fmr11 bit ew1 mode is entered by setting the fmr11 bit to 1 (ew1 mode). this bit is enabled only when the fmr01 bit is 1 . ? fmr16 bit the combined setting of the fmr02 bit and the fmr16 bit enables to program and erase in the user rom area. to set this bit to 1 , it is necessary to set to 1 after first setting to 0 . set this bit to 0 by only writing 0 . this bit is enabled only when the fmr01 bit is 1 . ? fmr17 bit if fmr17 bit is 1 (with wait state), regardless of the content of the pm17 bit, 1 wait is inserted at the access to block a and block b. regardless of the content of the fmr17 bit, access to other block and the internal ram is determined by pm17 bit setting. set this bit to 1 (with wait state) when rewriting more than 100 times (option). table 17.5.2.1. protection using fmr16 and fmr02 fmr16 fmr02 block a, block b block 0, block 1 other user block 0 0 write enabled write disabled write disabled 0 1 write enabled write disabled write disabled 1 0 write enabled write disabled write enabled 1 1 write enabled write enabled write enabled 17.5.3 flash memory control register 4 (fmr4) ? fmr40 bit the erase-suspend function is enabled by setting the fmr40 bit is set to 1 (enabled). ? fmr41 bit when setting the fmr41 bit to 1 in a program during auto-erasing in ew0 mode the flash module enters erase suspend mode. in ew1 mode, the fmr41 bit is automatically set to 1 (suspend re- quest) when an interrupt request of an enabled interrupt is generated, the fmr41 bit is automatically set to 1 (suspend request) and when an auto-erasing operation is restarted, set the fmr41 bit to 0 (erase restart). ? fmr46 bit the fmr46 bit is set to 0 during auto-erasing execution and set to 1 during erase-suspend mode. do not access to flash memory while this bit is 0 .
17. flash memory version page 236 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m note 1: when setting this bit to 1 , set to 1 immdediately after setting it first to 0 . do not generate an interrupt or a dma transfer between setting the bit to 0 and setting it to 1 . set this bit while the p8 5 /nmi/sd pin is h when selecting the nmi function. set by program in a space other than the flash memory in ew0 mode. set this bit to read alley mode and 0 note 2: set this bit to 1 immediately after setting it first to 0 while the fmr01 bit is set to 1 . do not generate an interrupt or a dma transfer between setting this bit to 0 and setting it to 1 . note 3: set this bit by a program in a space other than the flash memory. note 4: this bit is set to 0 by executing the clear status command. note 5: this bit is enabled when the fmr01 bit is set to 1 (cpu rewrite mode). this bit can be set to 1 when the fmr01 bit is set to 0 . however, the flash memory does not enter low-power consumption status and it is not initialized. flash memory control register 0 symbol address after reset fmr0 01b7 16 00000001 2 b7 b6 b5 b4 b3 b2 b1 b0 fmr00 bit symbol bit name function rw 0: busy (during writing or erasing) 1: ready cpu rewrite mode select bit (note1) 0: disables cpu rewrite mode (disables software command) 1: enables cpu rewrite mode (enables software commands) fmr01 block 0, 1 rewrite enable bit (note 2) set write protection for user rom area (see table 17.5.2.1) flash memory stop bit (note 3, 5) fmr02 fmstp 0 ry/by status flag reserved bit set to 0 0: terminated normally 1: terminated in error program status flag fmr06 0: terminated normally 1: terminated in error erase status flag fmr07 rw rw rw rw ro ro ro (b5-b4) 0: starts flash memory operation 1: stops flash memory operation (enters low-power consumption state and flash memory reset) 0 (note 4) (note 4) flash memory control register 1 symbol address after reset fmr1 01b5 16 000xxx0x 2 b7 b6 b5 b4 b3 b2 b1 b0 bit symbol bit name function ew1 mode select bit (note1) 0: ew0 mode 1: ew1 mode fmr11 block a, b access wait bit ( note 3) reserved bit when read, its content is indeterminate reserved bit set to 0 nothing is assigned. when write, set to 0 . when read, its contect is indeterminate. rw ro rw rw rw (b0) (b4) reserved bit (b3-b2) ro note 1: set this bit to 1 immediately after setting it first to 0 . do not generate an interrupt or a dma transfer between setting the bit to 0 and setting it to 1 . set this bit while the p8 5 /nmi/sd pin is h when the nmi function is selected. if the fmr01 bit is set to 0 , the fmr01 bit and fmr11 bit are both set to 0 note 2: set this bit to 1 immediately after setting it first to 0 . do not generate an interrupt or a dma transfer after setting to 0 . note 3: when rewriting more than 100 times, set this bit to 1 (with wait state). when the fmr17 bit is 1 (with wait state), regardless of the content of the pm17 bit, 1 wait is inserted at the access to the block a and b. regardless of the content of the fmr17 bit, access to other block and the internal ram is determined be pm17 bit setting. (b5) fmr16 rw block 0 to 3 rewrite enable bit (note2) fmr17 set write protection for user rom area (see table 17.5.2.1) 0: disable 1: enable 0: pm17 enabled 1: with wait state (1 wait) when read, its content is indeterminate figure 17.5.1. fmr0 and fmr1 register
17. flash memory version page 237 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m flash memory control register 4 symbol address after reset fmr4 01b3 16 01000000 2 b7 b6 b5 b4 b3 b2 b1 b0 bit symbol bit name function erase suspend request bit (note 2) 0: erase restart 1: suspend request fmr41 0 reserved bit set to 0 erase suspend function enable bit (note 1) 0: disabled 1: enabled reserved bit set to 0 0 0 rw rw rw ro rw fmr40 (b5-b2) (b7) ro note 1: when setting this bit to 1 , set to 1 immediately after setting it first to 0 . do not generate an interrupt or a dma transfer between setting the bit to 0 and setting it to 1 . set by a program in a space other than the flash memory in ew0 mode. note 2: this bit is valid only when the erase-suspend enable bit (fmr40) is 1 . writing is enabled only between executing an erase command and completing erase (this bit is set to 1 other than the above duration). this bit can be set to 0 or 1 by a program in ew0 mode. in ew1 mode, this bit is automatically set to 1 when the fmr40 bit is 1 and a maskable interrupt is generated during erasing. do not write to 1 by a program (writing 0 is enabled). fmr46 00 erase status 0: during auto-erase operation 1: auto-erase stop (erase suspend mode) figure 17.5.2. fmr4 register
17. flash memory version page 238 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m execute the read array command (note 3) single-chip mode set cm0, cm1, and pm1 registers (note 1) execute software commands jump to the rewrite control program transfered to an internal ram area (in the following steps, use the rewrite control program internal ram area) transfer a rewrite control program to internal ram area write 0 to the fmr01 bit (cpu rewrite mode disabled) set the fmr01 bit to 1 after writing 0 ( cpu rewrite mode enabled) (note 2) ew0 mode operation procedure rewrite control program jump to a specified address in the flash memory note 1: select 10 mhz or below for cpu clock using the cm06 bit in the cm0 register and cm17 to 16 bits in the cm1 register. also, set the pm17 bit in the pm1 register to 1 (with wait state). note 2: set the fmr01 bit to 1 immediately after setting it to 0 . do not generate an interrupt or a dma transfer between setting the bit to 0 and setting it to 1 . set the fmr01 bit in a space other than the internal flash memory. also, set only when the p8 5 /nmi/sd pin is h at the time of the nmi function selected. note 3: disables the cpu rewrite mode after executing the read array command. figure 17.5.1.1. setting and resetting of ew0 mode single-chip mode (note 1) set cm0, cm1, and pm1 registers (note 2) set the fmr01 bit to 1 (cpu rewrite mode enabled) after writing 0 set the fmr11 bit to 1 (ew1 mode) after writing 0 (note 3) program in rom ew1 mode operation procedure execute software commands set the fmr01 bit to 0 (cpu rewrite mode disabled) note 1: in ew1 mode, do not set boot mode. note 2: select 10 mhz or below for cpu clock using the cm06 bit in the cm0 register and cm17 to 16 bits. in the cm1 register. also, set the pm17 bit in the pm1 register to 1 (with wait state). note 3: set the fmr01 bits to 1 immediately after setting it to 0 . do not generate an interrupt or a dma transfer between setting the bit to 0 and setting the bit to 1 . set the fmr01 bit in a space other than the internal flash memory. set only when the p8 5 /nmi/sd pin is h at the time of the nmi function selected. figure 17.5.1.2. setting and resetting of ew1 mode
17. flash memory version page 239 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 17.5.1.3. processing before and after low power dissipation mode start main clock oscillation transfer a low power internal consumption mode program to ram area switch the clock source of cpu clock. turn main clock off. (note 2) jump to the low power consumption mode program transferred to internal ram area. (in the following steps, use the low-power consumption mode program or internal ram area) wait until the flash memory circuit stabilizes (t ps ) (note 3) set the fmstp bit to 0 (flash memory operation) set the fmstp bit to 1 (flash memory stopped. low power consumption state)(note 1) process of low power consumption mode or on-chip oscillator low power consumption mode switch the clock source of the cpu clock (note 2) low power consumption mode program set the fmr01 bit to 0 (cpu rewrite mode disabled) set the fmr01 bit to 1 after setting 0 ( cpu rewrite mode enabled) jump to a desired address in the flash memory wait until oscillation stabilizes note 1: set the fmrstp bit to 1 after setting the fmr01 bit to 1 (cpu rewrite mode). note 2: wait until the clock stabilizes to switch the clock source of the cpu clock to the main clock or the sub clock. note 3: add a t ps wait time by a program. do not access the flash memory during this wait time.
17. flash memory version page 240 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 17.6 precautions in cpu rewrite mode described below are the precautions to be observed when rewriting the flash memory in cpu rewrite mode. 17.6.1 operation speed when cpu clock source is the main clock, before entering cpu rewrite mode (ew0 or ew1 mode), select 10 mhz or below for cpu clock using the cm06 bit in the cm0 register and the cm17 to cm16 bits in the cm1 register. also, when selecting f 3 (roc) of a on-chip oscillator as a cpu clock source, before entering cpu rewrite mode (ew0 or ew1 mode), the rocr3 to rocr2 bits in the rocr register set the cpu clock division rate to divide-by-4 or divide-by-8 . on both cases, set the pm17 bit in the pm1 register to 1 (with wait state). 17.6.2 prohibited instructions the following instructions cannot be used in ew0 mode because the cpu tries to read data in the flash memory: und instruction, into instruction, jmps instruction, jsrs instruction, and brk in- struction 17.6.3 interrupts ew0 mode ? to use interrupts having vectors in a relocatable vector table, the vectors must be relocated to the ram area. _______ ? the nmi and watchdog timer interrupts can be used since the fmr0 and fmr1 registers are forcibly reset when either interrupt is generated. however, the jump addresses for each interrupt service routines to the fixed vector table are set and interrupt programs are required. flash memory rewrite operation is halted when the nmi or watchdog timer interrupt is generated. set the fmr01 bit to 1 and execute the rewrite and erase program again after exiting the interrupt rou- tine. ? the address match interrupt can not be used since the cpu tries to read data in the flash memory. ew1 mode ? do not acknowledge any interrupts with vectors in the relocatable vector table or the address match interrupt during the auto-program or erase-suspend function. 17.6.4 how to access to set the fmr01, fmr02, fmr11 or fmr16 bit to 1 , write 1 after first setting the bit to 0 . do not generate an interrupt or a dma transfer between the instruction to set the bit to 0 and the instruction _______ to set it to 1 . when the nmi function is selected, set the bit while an h signal is applied to the p8 5 / _______ _____ nmi/sd pin. 17.6.5 writing in the user rom space 17.6.5.1 ew0 mode ? if the supply voltage drops while rewriting the block where the rewrite control program is stored, the flash memory can not be rewritten, because the rewrite control program is not correctly rewrit- ten. if this error occurs, rewrite the user rom area in standard serial i/o mode or parallel i/o mode. 17.6.5.2 ew1 mode ? do not rewrite the block where the rewrite control program is stored.
17. flash memory version page 241 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 17.6.6 dma transfer in ew1 mode, do not perform a dma transfer while the fmr00 bit in the fmr0 register is set to 0 . (the auto-programming or auto-erasing duration ). 17.6.7 writing command and data write the command code and data to even addresses in the user rom area. 17.6.8 wait mode when entering wait mode, set the fmr01 bit to 0 (cpu rewrite mode disabled) before executing the wait instruction. 17.6.9 stop mode when entering stop mode, set the fmr01 bit to 0 (cpu rewrite mode disabled) and disable the dma transfer before setting the cm10 bit to 1 (stop mode). 17.6.10 low power consumption mode and on-chip oscillator-low power consump- tion mode if the cm05 bit is set to 1 (main clock stopped), do not execute the following commands. ? program ? block erase
17. flash memory version page 242 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 17.7 software commands read or write 16-bit commands and data from or to even addresses in the user rom area. when writing a command code, 8 high-order bits (d 15 C d 8 ) are ignored. table 17.7.1. software commands 17.7.1 read array command (ff 16 ) this command reads the flash memory. by writing command code xxff 16 in the first bus cycle, read array mode is entered. content of a specified address can be read in 16-bit unit after the next bus cycle. the microcomputer remains in read array mode until an another command is written. therefore, contents of multiple addresses can be read consecutively. 17.7.2 read status register command (70 16 ) this command reads the status register. by writing command code xx70 16 in the first bus cycle, the status register can be read in the second bus cycle (refer to 17.8 status register ). read an even address in the user rom area. do not execute this command in ew1 mode. command program clear status register read array read status register first bus cycle second bus cycle block erase write write write write write mode read write write mode x wa ba address srd wd xxd0 16 data (d 15 to d 0 ) xxff 16 xx70 16 xx50 16 xx40 16 xx20 16 data (d 15 to d 0 ) x x x wa x address srd: status register data (d 7 to d 0 ) wa : write address (however,even address) wd : write data (16 bits) ba : highest-order block address (however,even address) x : any even address in the user rom area xx : 8 high-order bits of command code (ignored)
17. flash memory version page 243 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m start program completed yes no note 1: write the command code and data at even address. note 2: refer to "figure 17.8.4.1. full status check and handling procedure for each error" write command code xx40 16 to the write address (note 1) write data to the write address (note 1) fmr00=1? full status check (note 2) figure 17.7.4.1. flow chart of program command 17.7.3 clear status register command (50 16 ) this command clears the status register to 0 . by writing xx50 16 in the first bus cycle, and the fmr06 to fmr07 bits in the fmr0 register and sr4 to sr5 bits in the status register are set to 0 . 17.7.4 program command (40 16 ) the program command writes 2-byte data to the flash memory. by writing xx40 16 in the first bus cycle and data to the write address specified in the second bus cycle, the auto-programming/erasing (data prorgramming and verify) start. set the address value specified in the first bus cycle to same and even address as the write address specified in the second bus cycle. the fmr00 bit in the fmr0 register indicates whether an auto-programming operation has been completed. the fmr00 bit is set to 0 during the auto-programming and 1 when the auto-programming operation is completed. after the auto-programming operation is completed, the fmr06 bit in the fmr0 register indicates whether or not the auto-programming operation has been completed as expected. (refer to 17.8.4 full status check ). also, each block disables writing (refer to table 17.5.2.1 ). do not write additions to the address which is already programmed. when commands other than a program command are ex- ecuted immediately after a program command, set the same address as the write address specified in the second bus cycle of the program command, to the specified address value in the first bus cycle of the following command. in ew1 mode, do not execute this command on the blocks where the rewrite control program is allocated. in ew0 mode, the microcomputer enters read status register mode as soon as the auto-programming operation starts and the status register can be read. the sr7 bit in the status register is set to 0 as soon as the auto-programming operation starts. this bit is set to 1 when the auto-programming operation is completed. the microcomputer remains in read status regis- ter mode until the read array command is written. after completion of the auto-programming operation, the status register indicates whether or not the auto-programming operation has been completed as expected.
17. flash memory version page 244 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m note 1: write the command code and data at even address. note 2: refer to "figure 17.8.4.1. full status check and handling porcedure for each error". note 3: execute the clear status register command and block erase command at least 3 times until an erase error is not generated when an erase error is generated. write ?xd0 16 ?to the highest-order block address (note 1) start block erase completed yes no write command code ?x20 16 (note 1) fmr00=1? full status check (note 2,3) figure 17.7.5.1. flow chart of block erase command (when not using erase suspend function) 17.7.5 block erase by writing ?x20 16 ?in the first bus cycle and ?xd0 16 ?in the second bus cycle to the highest-order (even addresse of a block) and the auto-programming/erasing (erase and erase verify) start. the fmr00 bit in the fmr0 register indicates whether the auto-programming operation has been completed. the fmr00 bit is set to ??during the auto-erasing operation and ??when the auto-erasing operation is completed. when using the erase-suspend function in ew0 mode, the fmr46 bit in the fmr4 register indicates whether a flash memory has entered erase-suspend mode. the fmr46 bit is set to ? during auto-erasing operation and ??when the auto-erasing operation is completed (entering erase- suspend). after the completion of an auto-erasing operation, the fmr07 bit in the fmr0 register indicates whether or not the auto erasing-operation has been completed as expected. (refer to 17.8.4 full status check ). also, each block disables erasing. (refer to ?able 17.5.2.1?. figure 17.7.5.1 shows a flow chart of the block erase command programming when not using the erase-suspend function. figure 17.7.5.2 shows a flow chart of the block erase command programming when using an erase-suspend function. in ew1 mode, do not execute this command on the block where the rewrite control program is allocated. in ew0 mode, the microcomputer enters read status register mode as soon as the auto-erasing operation starts and the status register can be read. the sr7 bit in the status register is set to ??as soon as the auto-erasing operation starts. this bit is set to ??when the auto- erasing operation is completed. the microcomputer remains in read status register mode until the read array command is written. also excute the clear status register command and block erase com- mand at least 3 times until an erase error is not generated when an erase error is generated.
17. flash memory version page 245 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m note 1: write the command code and data to even address. note 2: execute the clear status register command and block erase command at least 3 times until an erase error is not generated when an erase error is generated. note 3: in ew0 mode, allocate an interrupt vector table of an interrupt, to be used, to a ram area note 4: refer to "figure 17.8.4.1. full status check and handling porcedure for each error". start block erase completed write the command code xx20 16 (note 1) write xxd0 16 to the highest-order block address (note 1) yes no fmr00=1? full status check (note 2,4) fmr40=1 interrupt service routine (note 3) fmr41=1 yes no fmr46=1? access flash memory return (interrupt service routine end) fmr41=0 (ew0 mode) (ew1 mode) start block erase completed write the command code xx20 16 (note 1) write xxd0 16 to the highest-order block address (note 1) yes no fmr00=1? full status check (note 2,4) fmr40=1 fmr41=0 interrupt service routine (note 3) access flash memory return (interrupt service routine end) figure 17.7.5.2. block erase command (at use erase suspend)
17. flash memory version page 246 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m bits in the srd register sr4 (d 4 ) sr5 (d 5 ) sr7 (d 7 ) sr6 (d 6 ) status name contents sr1 (d 1 ) sr2 (d 2 ) sr3 (d 3 ) sr0 (d 0 ) program status erase status sequence status reserved reserved reserved reserved "1" ready terminated by error terminated by error - - - - - "0" busy completed normally completed normally - - - - - reserved bits in the fmr0 register fmr00 fmr07 fmr06 value after reset 1 0 0 table 17.8.1. status register 17.8 status register the status register indicates the operating status of the flash memory and whether an erasing or a pro- gramming operates normally and an error ends. the fmr00, fmr06, and fmr07 bits in the fmr0 register indicate the status of the status register. table 17.8.1 shows the status register. in ew0 mode, the status register can be read in the following cases: (1) when a given even address in the user rom area is read after writing the read status register command (2) when a given even address in the user rom area is read after executing the program or block erase command but before executing the read a rray command. 17.8.1 sequence status (sr7 and fmr00 bits ) the sequence status indicates the operating status of the flash memory. this bit is set to 0 (busy) during an auto-programming and auto-erasing and 1 (ready) as soon as these operations are com- pleted. this bit indicates 0 (busy) in erase-suspend mode. 17.8.2 erase status (sr5 and fmr07 bits) refer to 17.8.4 full status check . 17.8.3 program status (sr4 and fmr06 bits) refer to 17.8.4 full status check . ? d 7 to d 0 : indicates the data bus which is read out when executing the read status register command. ? the fmr07 bit (sr5) and fmr06 bit (sr4) are set to 0 by executing the clear status register command. ? when the fmr07 bit (sr5) or fmr06 bit (sr4) is 1, the program, and block erase command are not acknowledged.
17. flash memory version page 247 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 17.8.4 full status check when an error occurs, the fmr06 to fmr07 bits in the fmr0 register are set to 1 , indicating occur- rence of each specific error. therefore, execution results can be verified by checking these status bits (full status check). table 17.8.4.1 shows errors and the status of fmr0 register. figure 17.8.4.1 shows a flow chart of the full status check and handling procedure for each error. table 17.8.4.1. errors and fmr0 register status fmr00 register (srd register) status error error occurrence condition fmr07 fmr06 (sr5) (sr4) 1 1 command ? when any commands are not written correctly sequence error ? a value other than xxd0 16 or xxff 16 is written in the second bus cycle of the block erase command (note 1) ? when the block erase command is executed on protected blocks ? when the program command is executed on protected blocks 1 0 erase error ? when the block erase command is executed on unprotected blocks but the blocks are not automatically erased correctly 0 1 program error ? when the program command is executed on unprotected blocks but the blocks are not automatically programmed correctly. note 1: the flash memory enters read array mode by writing command code xxff 16 in the second bus cycle of these commands. the command code written in the first bus cycle becomes invalid.
17. flash memory version page 248 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m full status check fmr06 =1 and fmr07=1? no command sequence error yes fmr07= 0? yes erase error no (1) execute the clear status register command and set the status flag to 0 whether the command is entered. (2) reexecute the command after checking that it is entered correctly or the program command or the block erase command is not executed for the blocks which are protected. (1) execute the clear status register command and set the erase status flag to 0 . (2) reexecute the block erase command. (3) execute (1) and (2) at least 3 times until an erase error is not generated. note 4: if the fmr06 or fmr07 bits is 1 , any of the program or block erase command can not be aknowledged. execute the clear status register command before executing those commands. fmr06= 0? yes program error no full status check completed note 1: if the error still occurs, the block can not be used. (1) execute the clear status register command and set the program status flag to 0 . (2) reexecute the program command. note 2: if the error still occurs, the block can not be used. [during programming] figure 17.8.4.1. full status check and handling procedure for each error
17. flash memory version page 249 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 17.9 standard serial i/o mode in standard serial input/output mode, the user rom area can be rewritten while the microcomputer is mounted on-board by using a serial programmer which is applicable for the m16c/26a group. for more information about serial programmers, contact the manufacturer of your serial programmer. for details on how to use the serial programmer, refer to the user s manual included with your serial programmer. table 17.9.1 shows pin functions (flash memory standard serial input/output mode). figures 17.9.1 and 17.9.2 show pin connections for standard serial input/output mode. 17.9.1 id code check function this function determines whether the id codes sent from the serial programmer and those written in the flash memory match. (refer to 17.3 functions to prevent flash memory from rewriting. )
17. flash memory version page 250 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m pin description v cc ,v ss apply the voltage guaranteed for program and erase to vcc pin and 0 v to vss pin. cnv ss connect to vcc pin. reset x in connect a ceramic resonator or crystal oscillator between x in and x out pins. to input an externally generated clock, input it to x in pin and open x out pin. x out av cc , av ss v ref connect avss to vss and avcc to vcc, respectively. enter the reference voltage for ad from this pin. p1 5 , p1 7 input "h" or "l" level signal or open. p6 0 to p6 3 input "h" or "l" level signal or open. p6 4 standard serial i/o mode 1: busy signal output pin standard serial i/o mode 2: monitor signal output pin for boot program operation check p6 5 p6 6 serial data input pin p6 7 serial data output pin p7 0 to p7 7 input "h" or "l" level signal or open. p8 0 to p8 4 , p8 7 input "h" or "l" level signal or open. p9 0 to p9 3 , input "h" or "l" level signal or open. p10 0 to p10 7 input "h" or "l" level signal or open. name power input cnv ss reset input clock input clock output analog power supply input reference voltage input input port p1 input port p6 busy output sclk input rxd input txd output input port p7 input port p8 input port p9 input port p10 i/o i i i o i i i o i i o i i i i p8 5 rp input i connect this pin to vss while reset is low. (note 2) standard serial i/o mode 1: serial clock input pin standard serial i/o mode 2: input "l". reset input pin. while reset pin is "l" level, wait for td(roc). (note 1) p8 6 ce input i connect this pin to vcc while reset is low. (note 2) p1 6 p1 6 input connect this pin to vcc while reset is low. (note 2) i table 17.9.1. pin functions (flash memory standard serial i/o mode) note 1: when using standard serial input/output mode 1, to input h to the txd pin is necessary while the ___________ reset pin is l . therefore, connect this pin to v cc via a resistor. adjust the pull-up resistor value on a system not to affect a data transfer after reset, because this pin changes to a data-output pin note 2: set following either or both _____ ? connect the ce pin to v cc . _____ ? connect the rp pin to v ss and the p1 6 pin to v cc .
17. flash memory version page 251 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 17.9.1. pin connections for serial i/o mode (1) m16c/26a group (flash memory version) 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 1 6 1 5 1 4 1 3 2 7 2 8 2 9 3 0 busy sclk rxd txd vcc vss reset connect oscillator circuit mode setup method signal cnvss reset value vcc vss to vcc package: 42p2r ce note rp note 1 7 2 1 2 0 1 9 1 8 2 6 2 2 2 3 2 4 2 5 note: set following either or both in serial i/o mode while the reset pin is held l . ? connect the ce pin to v cc . ? connect the rp pin to v ss and the p1 6 pin to v cc . p1 6 note
17. flash memory version page 252 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m figure 17.9.2. pin connections for serial i/o mode (2) m16c/26a group (flash memory version) 1 2 3 4 5 6 7 8 9 10 11 12 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 36 35 34 33 32 31 30 29 28 27 26 25 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 mode setup method signal cnvss reset value vcc vss to vcc package: 48p6q-a busy sclk rxd txd connect oscillator circuit vcc vss reset ce note rp note p1 6 note note: set following either or both in serial i/o mode while the reset pin is held l . ? connect the ce pin to v cc . ? connect the rp pin to v ss and the p1 6 pin to v cc .
17. flash memory version page 253 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 17.9.2 example of circuit application in standard serial i/o mode figure 17.9.2.1 shows an example of a circuit application in standard serial i/o mode 1 and figure 17.9.2.2 shows an example of a circuit application in standard serial i/o mode 2. refer to the user's manual for a serial writer to handle pins controlled by the serial writer. figure 17.9.2.1. circuit application in standard serial i/o mode 1 sclk input busy output txd output rxd input busy sclk t x d cnvss p8 6 (ce) reset rxd reset input user reset singnal microcomputer (1) controlling pins and external circuits vary with the serial programmer. for more information, refer to the user's manual included with the serial programmer. (2) in this example, a selector controls the input voltage applied to cnvss to switch between single-chip mode and standard serial i/o mode. (3) in standard serial input/output mode 1, if the user reset signal becomes l while the microcomputer is communicating with the serial programmer, break the connection between the user reset signal and the reset pin using a jumper switch. p8 5 (rp) (note 1) (note 1) note 1. set following either or both ? connect the ce pin to v cc ? connect the rp pin to v ss and the p1 6 pin to v cc p1 6 (note 1)
17. flash memory version page 254 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m monitor output rxd input txd output busy sclk txd cnvss p8 6 (ce) rxd microcomputer (1) in this example, a selector controls the input voltage applied to cnvss to switch between single-chip mode and standard serial i/o mode. p8 5 (rp) (note 1) (note 1) note 1. set following either or both ? connect the ce pin to v cc ? connect the rp pin to v ss and the p1 6 pin to v cc p1 6 (note 1) figure 17.9.2.2. circuit application in standard serial i/o mode 2
17. flash memory version page 255 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 17.10 parallel i/o mode in parallel input/output mode, the user rom can be rewritten using a parallel programmer which is appli- cable for the m16c/26a group. for more information about the parallel programmer, contact your parallel programmer manufacturer. for details on how to use the parallel programmer, refer to the user s manual of the parallel programmer. 17.10.1 rom code protect function the rom code protect function prevents the flash memory from being read or rewritten. (refer to 17.3 function to prevent flash memory from rewriting .)
18. electrical characteristics (m16c/26a) page 256 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 18. electrical characteristics please contact renesas technology corp. or an authorized renesas technology corp. product distributor for electrical characteristics of v-ver. 18.1. normal version table 18.1. absolute maximum ratings o p e r a t i n g a m b i e n t t e m p e r a t u r e p a r a m e t e ru n i t i n p u t v o l t a g e analog supply voltage s u p p l y v o l t a g e o u t p u t v o l t a g e v o - 0 . 3 t o v c c + 0 . 3 - 0 . 3 t o v c c + 0 . 3 p d p o w e r d i s s i p a t i o n storage temperature r a t e d v a l u e v v v c o n d i t i o n v i av cc v c c t stg t o p r s y m b o l m w v p 1 5 t o p 1 7 , p 6 0 t o p 6 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p 9 0 t o p 9 3 , p 1 0 0 t o p 1 0 7 , x i n , v r e f , r e s e t , c n v s s v c c = a v c c v cc =av cc -0.3 to 6.5 -0.3 to 6.5 -65 to 150 3 0 0 - 2 0 t o 8 5 / - 4 0 t o 8 5 -40 c topr 85 c c p1 5 to p1 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p10 0 to p10 7 , x out when the microcomputer is operating f l a s h p r o g r a m e r a s e 0 t o 6 0 < = < = program area (block 0 to block 3) p r o g r a m a r e a ( b l o c k a , b l o c k b ) c c c -20 to 85 / -40 to 85
18. electrical characteristics (m16c/26a) page 257 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m table 18.2. recommended operating conditions (note 1) 2.7 5.5 typ. max. unit parameter v cc supply voltage symbol min. standard analog supply voltage v cc avcc v v 0 0 analog supply voltage supply voltage v ih i oh (avg) high average output current ma ma vss avss 0.7v cc v v v v cc 0.3v cc 0 low input voltage i oh (peak) high peak output current high input voltage -5.0 -10.0 low peak output current 10.0 5.0 ma f (x in ) main clock input oscillation frequency (note 3) low average output current i ol (peak) ma i ol (avg) v v il 33 x v cc -80 v cc =3.0 to 5.5v v cc =2.7 to 3.0v 0 0 mhz mhz 20 f (x cin ) sub-clock oscillation frequency khz 50 32.768 note 1: referenced to v cc = 2.7 to 5.5v at topr = -20 to 85 c / -40 to 85 c unless otherwise specified. note 2: the mean output current is the mean value within 100ms. note 3: relationship between main clock oscillation frequency, pll clock oscillation frequency and supply voltage are followed. note 4: the total i ol(peak) for all ports must be 80ma max. the total i oh(peak) for all ports must be -80ma max. f 1 (roc) on-chip oscillation frequency 1 mhz 1 f (pll) pll clock oscillation frequency (note 3) v cc =3.0 to 5.5v v cc =2.7 to 3.0v 10 10 mhz mhz f (bclk) cpu operation clock 0 mhz 20 t su (pll) pll frequency synthesizer stabilization wait time v cc =5.0v v cc =3.0v 50 20 ms ms p1 5 to p1 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p10 0 to p10 7 f 2 (roc) on-chip oscillation frequency 2 f 3 (roc) on-chip oscillation frequency 3 mhz 2 mhz 16 p1 5 to p1 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p10 0 to p10 7 , p1 5 to p1 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p10 0 to p10 7 , p1 5 to p1 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p10 0 to p10 7 p1 5 to p1 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p10 0 to p10 7 p1 5 to p1 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p10 0 to p10 7 33 x v cc -80 20 0.5 1 8 2 4 26 x in , reset, cnv ss v ih high input voltage low input voltage v il x in , reset, cnv ss 0.8v cc v v cc v 0.2v cc 0 main clock input oscillation frequency 20.0 0.0 f(x in ) operating maximum frequency [mh z ] v cc [v] (main clock: no division) 5.5 3.0 10.0 2.7 aaaaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaaa 33.3 x v cc -80mh z pll clock oscillation frequency 0.0 f(pll) operating maximum frequency [mh z ] v cc [v] (pll clock oscillation) 5.5 10.0 2.7 aaaaaaa aaaaaaa aaaaaaa 3.0 33.3 x v cc -80mh z 20.0
18. electrical characteristics (m16c/26a) page 258 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m table 18.3. a /d conversion characteristics (note 1) standard min. typ. max. C inl resolution integral non- linearity error bits v ref =v cc 10 symbol parameter measuring condition unit lsb 3 lsb v ref =v cc =3.3v, 5v 8 bit 2 r ladder t conv ladder resistance conversion time(10bit), sample & hold function available reference voltage analog input voltage k ? s v v ia v ref v 0 2.0 10 v cc v ref 40 3.3 conversion time(8bit), sample & hold function available s 2.8 t conv v ref =v cc v ref =v cc =5v, ? ad =10mhz v ref =v cc =5v, ? ad =10mhz dnl differential non-linearity error offset error gain error C C lsb lsb lsb 1 3 3 10 bit lsb 5 lsb 3 lsb v ref =v cc =3.3v, 5v 8 bit 2 lsb 5 C absolute accuracy v ref =v cc =3.3v v ref =v cc =5v 10 bit v ref =v cc =3.3v v ref =v cc =5v note 1: referenced to vcc=avcc=vref=3.3 to 5.5v, vss=avss=0v at topr = -20 to 85 c / -40 to 85 c unless otherwise specified. note 2: ad operation clock frequency ( ? ad frequency) must be 10 mhz or less. and divide the fad if vcc is less than 4.2v, and make ? ad frequency equal to or lower than fad/2. note 3: a case without sample & hold function turn ? ad frequency into 250 khz or more in addition to a limit of note 2. a case with sample & hold function turn ? ad frequency into 1mhz or more in addition to a limit of note 2. note 4: in a case with sample & hold function, the sampling time is 3 ? ad. in a case without sample & hold function, the sampling time is 2 ? ad.
18. electrical characteristics (m16c/26a) page 259 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m table 18.4. flash memory version electrical characteristic (note 1): program area for u3 and u5, data area for u7 and u9 word program time (vcc=5.0v, topr=25 c) block erase time 75 0.2 600 9 s s parameter standard min. typ. (note 2) max unit symbol C C 0.4 9 s 0.7 9s 1.2 9s 2kbyte block 8kbyte block 16kbyte block 32kbyte block C erase/write cycle (note 3) cycle td(sr-es) C time delay from suspend request until erase suspend data retention time (note 5) ms year 8 20 word program time (vcc=5.0v, topr=25 c) block erase time(vcc=5.0v, topr=25 c) 100 s parameter standard min. typ. (note 2) max unit symbol C C 0.3 s (2kbyte block) C erase/write cycle (note 3, 8, 9) 10000 (note 4, 10) cycle td(sr-es) time delay from suspend request until erase suspend ms 8 t ps flash memory circuit stabilization wait time s 15 C data retention time (note 5) year 20 t ps flash memory circuit stabilization wait time s 15 100/1000 (note 4, 11) table 18.5. flash memory version electrical characteristics (note 6): data area for u7 and u9 (note 7) erase suspend request (interrupt request) fmr46 td(sr-es) note 1: when not otherwise specified, vcc = 2.7 to5.5v; topr = 0 to 60 c. note 2: vcc = 5v; topr = 25 c. note 3: program and erase endurance refers to the number of times a block erase can be performed. if the program and erase end urance is n (n=100, 1,000, 10,000), each block can be erased n times. for example, if a 2kbytes block a is erased after writing 1 word data 1,024 time s, each to a different address, this counts as one program and erase endurance. data cannot be written to the same address more than once without erasing the bloc k. (rewrite prohibited) note 4: maximum number of e/w cycles for which opration is guaranteed. note 5: topr = 55 c. note 6: when not otherwise specified, vcc = 2.7 to 5.5v; topr = -20 to 85 c / -40 to 85 c (option). note 7: table18.5 applies for block a or b e/w cycles > 1000. otherwise, use table 18.4. note 8: to reduce the number of program and erase endurance when working with systems requiring numerous rewrites, write to unu sed word addresses within the block instead of rewrite. erase block only after all possible addresses are used. for example, an 8-word program can be w ritten 256 times maximum before erase becomes necessary. maintaining an equal number of erasure between block a and block b will also improve efficiency . it is important to track the total number of times erasure is used. note 9: should erase error occur during block erase, attempt to execute clear status register command, then clock erase command at least three times until erase error disappears. note 10: when block a or b e/w cycles exceed 100, select one wait state per block access. when fmr17 is set to "1", one wait st ate is inserted per access to block a or b - regardless of the value of pm17. wait state insertion during access to all other blocks, as well as to int ernal ram, is controlled by pm17 - regardless of the setting of fmr17. note 11: the program area and the data area for u3 and u5 are 100 e/w cycles; the program area for u7 and u9 is 1,000 e/w cy cles. note 12: customers desiring e/w failure rate information should contact their renesas technical support representative.
18. electrical characteristics (m16c/26a) page 260 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m table 18.6. voltage detection circuit electrical characteristics (note 1, note 3 ) table 18.7. power supply circuit timing characteristics symbol standard typ. unit measuring condition min. max. parameter vdet4 voltage down detection voltage (note 1) v v cc =1.7 to 5.5v note 1: vdet4 > vdet3 note 2: vdet3s is the min voltage at which "hardware reset 2" is maintained. note 3: the voltage detection circuit is designed to use when v cc is set to 5v. note 4: when reset level detection voltage is 2.7v or below, operating with f(bclk) y 10mhz is guaranteed if the supply voltage is over the reset level detection voltage excluding a/d conversion accuracy, serial i/o and flash memory program and erase. 3.2 vdet3 reset level detection voltage (notes 1, note 3) v v symbol standard typ. unit measuring condition min. max. parameter 2 v cc =2.7 to 5.5v note 1: when v cc = 5v 150 6 (note 1) td(r-s) stop release time 20 20 td(s-r) hardware reset 2 release wait time s ms vdet3s low voltage reset retention voltage (note 2) vdet3r low voltage reset release voltage v td(p-r) time for internal power supply stabilization during powering-on td(e-a) + oltage detection circuit operation start time ms v cc =2.7 to 5.5v v cc =vdet3r to 5.5v td(w-s) low power dissipation mode wait mode release time 150 s 3.8 4.45 td(roc) time for internal on-chip oscillator stabilization during powering-on 40 2.3 2.8 3.4 1.7 2.35 2.9 3.5 s s < = t d(p-r) time for internal power supply stabilization during powering-on cpu clock t d(r-s) (a) (b) t d(w-s) t d(r-s) stop release time t d(w-s) low power dissipation mode wait mode release time t d(s-r) vdet3r v cc cpu clock vc26, vc27 t d(e-a) stop operate interrupt for (a) stop mode release or (b) wait mode release t d(s-r) voltage down detection reset (hardware reset 2) release wait time t d(e-a) voltage detection circuit operation start time voltage detection circuit roc reset vcc td(roc) td(p-r) t d(r 0$ ) time for internal on-chip oscillator stabilization during powering-on
18. electrical characteristics (m16c/26a) page 261 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m table 18.8. electrical characteristics (note 1 ) symbol v oh v oh high output voltage v oh v ol low output voltage low output voltage v ol v ol high output voltage high output voltage standard typ. unit measuring condition v v v x out v 2.0 0.45 v v x out 2.0 2.0 min. max. parameter i oh =-1ma i oh =-0.5ma i ol =1ma i ol =0.5ma highpower lowpower highpower lowpower highpower lowpower high output voltage x cout with no load applied with no load applied 2.5 1.6 v hysteresis hysteresis high input current i ih low input current i il v ram ram retention voltage v t+- v t- v t+- v t- clk 0 to clk 2 ,ta2 out to ta4 out , 0.2 1.0 v 0.2 2.5 v 5.0 a a at stop mode 2.0 v reset ta0 in to ta4 in , tb0 in to tb2 in , ad trg , cts 0 to cts 2 , v i =5v v i =0v -5.0 r fxin r fxcin feedback resistance x in feedback resistance x cin 15 1.5 m ? m ? p1 5 to p1 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p10 0 to p10 7, x in , reset, cnvss r pullup pull-up resistance 50 k ? int 0 to int 5 , nmi, v x cout 0 0 with no load applied with no load applied highpower lowpower v i =0v 30 170 ki 0 to ki 3 , rxd 0 to rxd 2 , v cc -2.0 v cc -2.0 note 1: re f erenced to vcc 4 2 to 5 5v vss 0v at topr 20 to 85 c/ 40to85 c f (bclk) 20mhz unless otherwise speci f ied i oh =-5ma i oh =-200a v cc -2.0 v cc -0.3 v cc v cc v cc v cc i ol =5ma i ol =200a low output voltage low output voltage p1 5 to p1 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p10 0 to p10 7 p1 5 to p1 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p10 0 to p10 7 p1 5 to p1 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p10 0 to p10 7 p1 5 to p1 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p10 0 to p10 7 p1 5 to p1 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p10 0 to p10 7, x in , reset, cnvss p1 5 to p1 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p10 0 to p10 7 hysteresis v t+- v t- 0.2 0.8 v x in v cc = 5v note 1: referenced to vcc=4.2 to 5.5v, vss=0v at topr = -20 to 85
18. electrical characteristics (m16c/26a) page 262 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m v cc = 5v table 18.9. electrical characteristics (2) (note 1 ) s y m b o l standard t y p . u n i t measuring condition m i n .m a x . p a r a m e t e r i c c p o w e r s u p p l y c u r r e n t ( v c c = 4 . 0 t o 5 . 5 v ) t h e o u t p u t p i n s a r e o p e n a n d o t h e r p i n s a r e v s s m a i n c l o c k , n o d i v i s i o n ma 1 6 f(bclk)=20mhz, f l a s h m e m o r y ma f l a s h m e m o r y p r o g r a m v cc =5.0v f(bclk)=10mhz, ma f l a s h m e m o r y e r a s e v cc =5.0v f(bclk)=10mhz, t opr =25 c 3 a stop mode, f ( b c l k )=3 2 k h z , wait mode (note 2), oscillation capacity high a 0 . 8 a m a s k r o m o r f l a s h m e m o r y note 1: referenced to v cc =4.2 to 5.5v, v ss =0v at topr = -20 to 85 c / -40 to 85 c, f(x in )=20mhz unless otherwise specified. note 2: with one timer operated using f c32 . note 3: this indicates the memory in which the program to be executed exists. note 4: idet is dissipation current when the following bit is set to ??(detection circuit enabled). idet4: vc27 bit in the vcr2 register idet3: vc26 bit in the vcr2 register note 5: with one timer operated. ma f(bclk)=1mhz, wait mode(note 5) a low power dissipation mode, ram(note 3) f ( b c l k ) = 3 2 k h z a low power dissipation mode, flash memory(note 3) f(bclk)=32khz, a f l a s h m e m o r y on-chip oscillation, f2(roc), f(bclk)=32khz, wait mode(note 2), oscillation capacity low i d e t 4 v o l t a g e d o w n d e t e c t i o n d i s s i p a t i o n c u r r e n t ( n o t e 4 ) a i d e t 3 r e s e t a r e a d e t e c t i o n d i s s i p a t i o n c u r r e n t ( n o t e 4 ) a on-chip oscillation f 2 (roc) selected, f(bclk)=1mhz 1 9 1 1 1 1 2 2 5 4 5 0 5 0 1 0 3 0 . 7 4 8 1.2 m a i n c l o c k , n o d i v i s i o n f(bclk)=20mhz, m as k rom on-chip oscillation f 2 (roc) selected, f(bclk)=1mhz ma 1 2 ma 1 7 1 . 5 low power dissipation mode, rom(note 3) f(bclk)=32khz, a 2 5 m as k rom o n - c h i p o s c i l l a t i o n f 2 ( r o c ) s e l e c t e d , f ( b c l k ) = 1 m h z i n w a i t m o d e ( n o t e 5 ) a 3 0
18. electrical characteristics (m16c/26a) page 263 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m v cc = 5v timing requirements (v cc = 5v, v ss = 0v, at topr = 20 to 85 o c / 40 to 85 o c unless otherwise specified) table 18.10. external clock input (x in input) max. external clock rise time ns t r min. external clock input cycle time external clock input high pulse width external clock input low pulse width external clock fall time ns ns ns ns t c t w(h ) t w(l) t f parameter symbol unit standard 50 20 20 9 9
18. electrical characteristics (m16c/26a) page 264 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m v cc = 5v timing requirements (v cc = 5v, v ss = 0v, at topr = 20 to 85 o c / 40 to 85 o c unless otherwise specified) table 18.12. timer a input (gating input in timer mode) table 18.13. timer a input (external trigger input in one-shot timer mode) table 18.14. timer a input (external trigger input in pulse width modulation mode) table 18.15. timer a input (counter increment/decrement input in event counter mode) table 18.11. timer a input (counter input in event counter mode) table 18.16. timer a input (two-phase pulse input in event counter mode) standard max. ns tai in input low pulse width t w(tal) min. ns ns unit tai in input high pulse width t w(tah) parameter symbol t c(ta) tai in input cycle time 40 100 40 standard max. min. ns ns ns unit tai in input cycle time tai in input high pulse width tai in input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter 400 200 200 standard max. min. ns ns ns unit tai in input cycle time tai in input high pulse width tai in input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter 200 100 100 standard max. min. ns ns unit t w(tah) t w(tal) symbol parameter tai in input high pulse width tai in input low pulse width 100 100 standard max. min. ns ns ns unit ns ns symbol parameter tai out input cycle time tai out input high pulse width tai out input low pulse width tai out input setup time tai out input hold time t c(up) t w(uph) t w(upl) t su(up-t in ) t h(t in- up) 2000 1000 1000 400 400 standard max. min. ns ns ns unit symbol parameter tai in input cycle time tai out input setup time tai in input setup time t c(ta) t su(ta in -ta out ) t su(ta out -ta in ) 800 200 200
18. electrical characteristics (m16c/26a) page 265 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m timing requirements (v cc = 5v, v ss = 0v, at topr = 20 to 85 o c / 40 to 85 o c unless otherwise specified) table 18.17. timer b input (counter input in event counter mode) table 18.18. timer b input (pulse period measurement mode) table 18.19. timer b input (pulse width measurement mode) table 18.20. a/d trigger input table 18.21. serial i/o _______ table 18.22. external interrupt inti input v cc = 5v ns ns ns ns ns ns ns standard max. min. tbi in input cycle time (counted on one edge) tbi in input high pulse width (counted on one edge) tbi in input low pulse width (counted on one edge) ns ns ns t c(tb) t w(tbh) t w(tbl) parameter symbol unit t c(tb) t w(tbl) t w(tbh) ns ns ns tbi in input high pulse width (counted on both edges) tbi in input low pulse width (counted on both edges) tbi in input cycle time (counted on both edges) standard max. min. ns ns t c(tb) t w(tbh) symbol parameter unit t w(tbl) ns tbi in input high pulse width tbi in input cycle time tbi in input low pulse width standard max. min. ns ns t c(tb) symbol parameter unit t w(tbl) ns t w(tbh) tbi in input cycle time tbi in input high pulse width tbi in input low pulse width standard max. min. ns ns t c(ad) t w(adl) symbol parameter unit ad trg input cycle time (trigger able minimum) ad trg input low pulse width standard max. min. ns ns t w(inh) t w(inl) symbol parameter unit inti input low pulse width inti input high pulse width standard max. min. clki input cycle time clki input high pulse width clki input low pulse width t c(ck) t w(ckh) t w(ckl) parameter symbol unit t d(c-q) t su(d-c) t h(c-q) txdi hold time rxdi input setup time txdi output delay time t h(c-d) rxdi input hold time 100 40 40 80 80 200 400 200 200 400 200 200 1000 125 250 250 200 100 100 0 90 80
18. electrical characteristics (m16c/26a) page 266 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m v cc = 5v taiin input taiout input during event counter mode tbiin input adtrg input t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) t h(tin-up) t su(up-tin) taiin input (when count on falling edge is selected) taiin input (when count on rising edge is selected) taiout input (up/down input) taiin input two-phase pulse input in event counter mode t c(ta) t su(tain-taout) t su(taout-tain) t su(tain-taout) t su(taout-tain) taiout input xin input t w(h) t w(l) t r t f t c figure 18.1. timing diagram (1)
18. electrical characteristics (m16c/26a) page 267 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m v cc = 5v figure 18.2. timing diagram (2) t su(d C c) clki txdi rxdi t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) t d(c C q) t h(c C d) t h(c C q) inti input
18. electrical characteristics (m16c/26a) page 268 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m v cc = 3v table 18.23. electrical characteristics ( note 1) s y m b o l v o h h i g h o u t p u t v o l t a g e v o h v o l l o w o u t p u t v o l t a g e v o l h i g h o u t p u t v o l t a g e s t a n d a r d t y p . unit measuring condition v v x out v v x o u t 0 . 5 0 . 5 m i n .m a x . v cc - 0.5 p a r a m e t e r i o h = - 1 m a i o h = - 0 . 1 m a i o h = - 5 0 a i o l = 1 m a i o l = 0 . 1 m a i o l = 5 0 a h i g h p o w e r l o w p o w e r h i g h p o w e r l o w p o w e r h i g h p o w e r l o w p o w e r x c o u t with no load applied w i t h n o l o a d a p p l i e d 2.5 1.6 v h y s t e r e s i s h y s t e r e s i s h i g h i n p u t c u r r e n t i ih l o w i n p u t c u r r e n t i i l v ram r a m r e t e n t i o n v o l t a g e v t + - v t - v t + - v t - 0 . 8v 1 . 8v 4.0 a a a t s t o p m o d e2 . 0v r e s e t x i n , r e s e t , c n v s s v i = 3 v v i = 0 v - 4 . 0 r fxin r f x c i n feedback resistance x in f e e d b a c k r e s i s t a n c ex c i n 2 5 3.0 m ? m ? r p u l l u p pull-up resistance 1 0 0k ? v x c o u t 0 0 w i t h n o l o a d a p p l i e d w i t h n o l o a d a p p l i e d h i g h p o w e r l o w p o w e r v i = 0 v 5 05 0 0 c l k 0 t o c l k 2 , t a 2 o u t t o t a 4 o u t , t a 0 i n t o t a 4 i n , t b 0 i n t o t b 2 i n , a d t r g , c t s 0 t o c t s 2 , i n t 0 t o i n t 5 , n m i , ki 0 to ki 3 , rxd 0 to rxd 2 x in , reset, cnvss v cc - 0.5 v cc - 0.5 n o t e 1 : r e f e r e n c e d t o v c c = 2 . 7 t o 3 . 6 v , v s s = 0 v a t t o p r = - 2 0 t o 8 5 c / - 4 0 t o 8 5 c , f ( b c l k ) = 1 0 m h z u n l e s s o t h e r w i s e s p e c i f i e d . v cc v cc v cc 0 . 5 h i g h o u t p u t v o l t a g e l o w o u t p u t v o l t a g e l o w o u t p u t v o l t a g e p1 5 to p1 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p10 0 to p10 7 p1 5 to p1 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p10 0 to p10 7 p1 5 to p1 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p10 0 to p10 7 p 1 5 t o p 1 7 , p 6 0 t o p 6 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p 9 0 t o p 9 3 , p 1 0 0 t o p 1 0 7 p1 5 to p1 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p10 0 to p10 7 h y s t e r e s i s v t + - v t - 0. 8v x i n
18. electrical characteristics (m16c/26a) page 269 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m table 18.24. electrical characteristics (2) ( note 1) v cc = 3v symbol standard typ. unit measuring condition min. max. parameter the output pins are open and other pins are v ss main clock, no division ma f(bclk)=10mhz, 12 flash memory i cc power supply current (v cc =2.7 to 3.6v) t opr =25 c 3 a stop mode, f(bclk)=32khz, wait mode (note 2), oscillation capacity high a 0.7 a mask rom ps flash memory note 1: referenced to v cc =2.7 to 3.6v, v ss =0v at topr = -20 to 85 c / -40 to 85 c, f(bclk)=10mhz unless otherwise specified. note 2: with one timer operated using f c32 . note 3: this indicates the memory in which the program to be executed exists. note 4: idet is dissipation current when the following bit is set to 1 (detection circuit enabled). idet4: vc27 bit in the vcr2 register idet3: vc26 bit in the vcr2 register note 5: with one timer o p erated. f(bclk)=1mhz, wait mode a low power dissipation mode, ram(note 3) f(bclk)=32khz, a low power dissipation mode, flash memory(note 3) f(bclk)=32khz, a flash memory on-chip oscillation, f2(roc) f(bclk)=32khz, wait mode (note 2), oscillation capacity low idet4 voltage down detection dissipation current (note 4) a 0.6 idet3 reset level detection dissipation current (note 4) a 7 vcc=3.0v ma flash memory f(bclk)=10mhz, program vcc=3.0v ma flash memory f(bclk)=10mhz, erase 1 4 5 10 11 25 450 45 10 3 main clock, no division ma f(bclk)=10mhz, 10 mask rom 7 mask rom low power dissipation mode, rom(note 3) f(bclk)=32khz, a 25 1 on-chip oscillation, f 2 (roc) selected, f(bclk)=1mhz ma on-chip oscillation, f 2 (roc) selected, f(bclk)=1mhz 1 on-chip oscillation, f 2 (roc) selected, f(bclk)=1mhz in wait mode (note 5) a 25 ma
18. electrical characteristics (m16c/26a) page 270 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m v cc = 3v timing requirements (v cc = 3v, v ss = 0v, at topr = 20 to 85 o c / 40 to 85 o c unless otherwise specified) table 18.25. external clock input (x in input) max. external clock rise time ns t r min. external clock input cycle time external clock input high pulse width external clock input low pulse width external clock fall time ns ns ns ns t c t w(h ) t w(l) t f parameter symbol unit standard 100 40 40 18 18
18. electrical characteristics (m16c/26a) page 271 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m v cc = 3v timing requirements (v cc = 3v, v ss = 0v, at topr = 20 to 85 o c / 40 to 85 o c unless otherwise specified) table 18.26. timer a input (counter input in event counter mode) table 18.27. timer a input (gating input in timer mode) table 18.28. timer a input (external trigger input in one-shot timer mode) table 18.29. timer a input (external trigger input in pulse width modulation mode) table 18.30. timer a input (counter increment/decrement input in event counter mode) table 18.31. timer a input (two-phase pulse input in event counter mode) standard max. ns tai in input low pulse width t w(tal) min. ns ns unit tai in input high pulse width t w(tah) parameter symbol t c(ta) tai in input cycle time 60 150 60 standard max. min. ns ns ns unit tai in input cycle time tai in input high pulse width tai in input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter 600 300 300 standard max. min. ns ns ns unit tai in input cycle time tai in input high pulse width tai in input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter 300 150 150 standard max. min. ns ns unit t w(tah) t w(tal) symbol parameter tai in input high pulse width tai in input low pulse width 150 150 standard max. min. ns ns ns unit ns ns symbol parameter tai out input cycle time tai out input high pulse width tai out input low pulse width tai out input setup time tai out input hold time t c(up) t w(uph) t w(upl) t su(up-t in ) t h(t in- up) 3000 1500 1500 600 600 standard max. min. s ns ns unit symbol parameter tai in input cycle time tai out input setup time tai in input setup time t c(ta) t su(ta in -ta out ) t su(ta out -ta in ) 2 500 500
18. electrical characteristics (m16c/26a) page 272 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m v cc = 3v table 18.32. timer b input (counter input in event counter mode) table 18.33. timer b input (pulse period measurement mode) table 18.34. timer b input (pulse width measurement mode) table 18.35. a/d trigger input table 18.36. serial i/o _______ table 18.37. external interrupt inti input timing requirements (v cc = 3v, v ss = 0v, at topr = 20 to 85 o c / 40 to 85 o c unless otherwise specified) ns ns ns ns ns ns ns standard max. min. tbi in input cycle time (counted on one edge) tbi in input high pulse width (counted on one edge) tbi in input low pulse width (counted on one edge) ns ns ns t c(tb) t w(tbh) t w(tbl) parameter symbol unit t c(tb) t w(tbl) t w(tbh) ns ns ns tbi in input high pulse width (counted on both edges) tbi in input low pulse width (counted on both edges) tbi in input cycle time (counted on both edges) standard max. min. ns ns t c(tb) t w(tbh) symbol parameter unit t w(tbl) ns tbi in input high pulse width tbi in input cycle time tbi in input low pulse width standard max. min. ns ns t c(tb) symbol parameter unit t w(tbl) ns t w(tbh) tbi in input cycle time tbi in input high pulse width tbi in input low pulse width standard max. min. ns ns t c(ad) t w(adl) symbol parameter unit ad trg input cycle time (trigger able minimum) ad trg input low pulse width standard max. min. ns ns t w(inh) t w(inl) symbol parameter unit inti input low pulse width inti input high pulse width standard max. min. clki input cycle time clki input high pulse width clki input low pulse width t c(ck) t w(ckh) t w(ckl) parameter symbol unit t d(c-q) t su(d-c) t h(c-q) txdi hold time rxdi input setup time txdi output delay time t h(c-d) rxdi input hold time 150 60 60 120 120 300 600 300 300 600 300 300 1500 200 380 380 300 150 150 0 90 160
18. electrical characteristics (m16c/26a) page 273 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m v cc = 3v figure 18.3. timing diagram (1) taiin input taiout input during event counter mode tbiin input adtrg input t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) t h(tin-up) t su(up-tin) taiin input (when count on falling edge is selected) taiin input (when count on rising edge is selected) taiout input (up/down input) taiin input two-phase pulse input in event counter mode t c(ta) t su(tain-taout) t su(taout-tain) t su(tain-taout) t su(taout-tain) taiout input xin input t w(h) t w(l) t r t f t c
18. electrical characteristics (m16c/26a) page 274 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m v cc = 3v figure 18.4. timing diagram (2) t su(d C c) clki txdi rxdi t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) t d(c C q) t h(c C d) t h(c C q) inti input
18. electrical characteristics (m16c/26t) page 275 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 18.2. t version table 18.38. absolute maximum ratings operating ambient temperature parameter unit input voltage analog supply voltage supply voltage output voltage v o -0.3 to v cc +0.3 -0.3 to v cc +0.3 p d power dissipation storage temperature rated value v v v condition v i av cc v cc t stg t opr symbol mw v p1 5 to p1 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p10 0 to p10 7 , x in , v ref , reset, cnv ss v cc =av cc v cc =av cc -0.3 to 6.5 -0.3 to 6.5 -65 to 150 300 -40 to 85 c -40 c topr 85 c c p1 5 to p1 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p10 0 to p10 7 , x out when the microcomputer is operating flash program erase c 0 to 60 program area (block 0 to block 3) data area (block a, block b) -40 to 85 c < = < =
18. electrical characteristics (m16c/26t) page 276 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m table 18.39. recommended operating conditions (note 1) 3.0 5.5 typ. max. unit parameter v cc supply voltage symbol min. standard analog supply voltage v cc avcc v v 0 0 analog supply voltage supply voltage v ih i oh (avg) high average output current ma ma vss avss 0.7v cc v v v v cc 0.3v cc 0 low input voltage i oh (peak) high peak output current high input voltage -5.0 -10.0 low peak output current 10.0 5.0 ma f (x in ) main clock input oscillation frequency (note 3) low average output current i ol (peak) ma i ol (avg) v v il 0 mhz 20 f (x cin ) sub-clock oscillation frequency khz 50 32.768 note 1: referenced to v cc = 3.0 to 5.5v at topr = -40 to 85 c unless otherwise specified. note 2: the mean output current is the mean value within 100ms. note 3: relationship between main clock oscillation frequency, pll clock oscillation frequency and supply voltage. note 4: the total iol(peak) for all ports must be 80ma max. the total ioh(peak) for all ports must be -80ma max. f 1 (roc) on-chip oscillation frequency 1 mhz 1 f (pll) pll clock oscillation frequency (note 3) 10 mhz 20 f (bclk) cpu operation clock 0 mhz 20 t su (pll) pll frequency synthesizer stabilization wait time v cc =5.0v v cc =3.0v 50 20 ms ms p1 5 to p1 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p10 0 to p10 7 f 2 (roc) on-chip oscillation frequency 2 f 3 (roc) on-chip oscillation frequency 3 mhz 2 mhz 16 p1 5 to p1 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p10 0 to p10 7 p1 5 to p1 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p10 0 to p10 7 p1 5 to p1 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p10 0 to p10 7 p1 5 to p1 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p10 0 to p10 7 p1 5 to p1 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p10 0 to p10 7 0.5 2 1 4 8 26 x in , reset, cnv ss x in , reset, cnv ss v ih high input voltage low input voltage v il 0.8v cc v v cc v 0.2v cc 0 main clock input oscillation frequency 20.0 0.0 f(x in ) operating maximum frequency [mh z ] v cc [v] (main clock: no division) 5.5 3.0 10.0 2.7 aaaaa aaaaa aaaaa aaaaa aaaaa aaaaa 20mh z pll clock oscillation frequency 20.0 0.0 f(pll) operating maximum frequency [mh z ] v cc [v] (pll clock oscillation) 5.5 10.0 aaaaa aaaaa aaaaa 3.0 20mh z
18. electrical characteristics (m16c/26t) page 277 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m table 18.40. a/d conversion characteristics (note 1) standard min. typ. max. C inl resolution integral non- linearity error bits v ref =v cc 10 symbol parameter measuring condition unit lsb 3 lsb v ref =v cc =3.3v, 5v 8 bit 2 r ladder t conv ladder resistance conversion time(10bit), sample & hold function available reference voltage analog input voltage k ? s v v ia v ref v 0 2.0 10 v cc v ref 40 3.3 conversion time(8bit), sample & hold function available 2.8 t conv v ref =v cc v ref =v cc =5v, ? ad =10mhz v ref =v cc =5v, ? ad =10mhz dnl differential non-linearity error offset error gain error C C lsb lsb lsb 1 3 3 note 1: referenced to v cc =av cc =v ref =3.3 to 5.5v, v ss =av ss =0v at topr = -40 to 85 c unless otherwise specified. note 2: ad operation clock frequency ( ? ad frequency) must be 10 mhz or less. and divide the f ad if v cc is less than 4.2v, and make ? ad frequency equal to or lower than f ad /2. note 3: a case without sample & hold function turn ? ad frequency into 250 khz or more in addition to a limit of note 2. a case with sample & hold function turn ? ad frequency into 1mhz or more in addition to a limit of note 2. note 4: a case with sample & hold function the sampling time is 3/ ? ad . a case without sam p le & hold function the sam p lin g time is 2/ ? ad . 10 bit lsb 5 lsb 3 lsb v ref =v cc =3.3v, 5v 8 bit 2 lsb 5 C absolute accuracy v ref =v cc =3.3v v ref =v cc =5v 10 bit v ref =v cc =3.3v v ref =v cc =5v
18. electrical characteristics (m16c/26t) page 278 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m table 18.41. flash memory version electrical characteristics (note 1) for 100 e/w cycle products / 1,000 e/w cycle products note 1: when not otherwise specified, vcc = 3.0 to5.5v; topr = 0 to 60 c. note 2: vcc = 5v; topr = 25 c. note 3: program and erase endurance refers to the number of times a block erase can be performed. if the program and erase endurance is n (n=100, 1,000, 10,000), each block can be erased n times. for example, if a 2kbytes block a is erased after writing 1 word data 1,024 times, each to a different address, this counts as one program and erase endurance. data cannot be written to the same address more than once without erasing the block. (rewrite prohibited) note 4: maximum number of e/w cycles for which opration is guaranteed. note 5: topr = 55 c. note 6: when not otherwise specified, vcc = 3.0 to 5.5v; topr = -40 to 85 c. note 7: this is a standard when program or erase endurance exceeds over 1,000 times. word program time or block erase time up to 1,000 times is the same as program area. note 8: to reduce the number of program and erase endurance when working with systems requiring numerous rewrites, write to unused word adresses within the block instead of rewrite. erase block only after all prossible addresses are used. for example, an 8-word program can be written 256 times maximum before erase becomes necessary. maintaining an equal number of erasure between block a and block b will also improve efficiency. it is improtant to track the total number of times erasure is used. note 9: should erase error occur during block erase, attempt to execute clear status register command, then clock erase command at least three times until erase error disappears. note 10: when block a or b e/w cycles exceed 1,000 (option), select one wait state per block access. when bit 7 in flash memory control register 1(fmr17 in address 01b5 16 ) is set to "1", one wait state is inserted per access to block a or b - regardless of the value of pm17. wait state insertion during access to all other blocks, as well as to internal ram, is controlled by pm17 - regardless of the setting of fmr17. note 11: customers desiring erase/write cycle information should contact their renesas technical support representative. note 12: customers desiring e/w failure rate information should contact their renesas technical support representative. w o r d p r o g r a m t i m e ( v c c = 5 . 0 v , t o p r = 2 5 c ) block erase time 7 5 0.2 60 0 9 s s p a r a m e t e r s t a n d a r d min. t y p . ( n o t e 2 ) m a x unit s y m b o l C C C C t i m e d e l a y f r o m s u s p e n d r e q u e s t u n t i l e r a s e s u s p e n d data retention time (note 5) m s y e a r 8 20 w o r d p r o g r a m t i m e ( v c c = 5 . 0 v , t o p r = 2 5 c ) b l o c k e r a s e t i m e ( v c c = 5 . 0 v , t o p r = 2 5 c ) 1 0 0 s parameter s t a n d a r d min. t y p . ( n o t e 2 ) m a x unit symbol C C C t i m e d e l a y f r o m s u s p e n d r e q u e s t u n t i l e r a s e s u s p e n d m s 8 t ps flash memory circuit stabilization wait time s 15 C erase suspend request (interrupt request) fmr46 td(sr-es)
18. electrical characteristics (m16c/26t) page 279 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m table 18.43. power supply circuit timing characteristics symbol standard typ. unit measuring condition min. max. parameter 2 v cc =3.0 to 5.5v 150 td(r-s) stop release time ms td(p-r) time for internal power supply stabilization during powering-on td(w-s) low power dissipation mode wait mode release time (note 2) 150 s td(roc) time for internal on-chip oscillator stabilization during powering-on 40 s s cpu clock t d(r-s) (a) (b) t d(w-s) t d(p-r) time for internal power supply stabilization during powering-on t d(r-s) stop release time t d(w-s) low power dissipation mode wait mode release time interrupt for (a) stop mode release or (b) wait mode release roc reset vcc td(p-r) td(roc) t d(r 0$ ) time for internal 0odijq 0tdjmmbups stabilization during powering-on
18. electrical characteristics (m16c/26t) page 280 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m v cc = 5v table 18.44. electrical characteristics (note 1 ) symbol v oh v oh high output voltage v oh v ol low output voltage low output voltage v ol v ol high output voltage high output voltage standard typ. unit measuring condition v v v x out v 2.0 0.45 v v x out 2.0 2.0 min. max. parameter i oh =-1ma i oh =-0.5ma i ol =1ma i ol =0.5ma highpower lowpower highpower lowpower highpower lowpower high output voltage x cout with no load applied with no load applied 2.5 1.6 v hysteresis hysteresis high input current i ih low input current i il v ram ram retention voltage v t+- v t- v t+- v t- clk 0 to clk 2 ,ta2 out to ta4 out , 0.2 1.0 v 0.2 2.5 v 5.0 a a at stop mode 2.0 v reset ta0 in to ta4 in , tb0 in to tb2 in , ad trg , cts 0 to cts 2 , v i =5v v i =0v -5.0 r fxin r fxcin feedback resistance x in feedback resistance x cin 15 1.5 m ? m ? p1 5 to p1 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p10 0 to p10 7, x in , reset, cnvss r pullup pull-up resistance 50 k ? int 0 to int 5 , nmi, v x cout 0 0 with no load applied with no load applied highpower lowpower v i =0v 30 170 ki 0 to ki 3 , rxd 0 to rxd 2 v cc -2.0 v cc -2.0 note 1: re f erencedtov cc =42to55v v ss =0vattopr= 40to85 c f (bclk)=20mhz unless otherwise speci f ied i oh =-5ma i oh =-200a v cc -2.0 v cc -0.3 v cc v cc v cc v cc i ol =5ma i ol =200a low output voltage low output voltage p1 5 to p1 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p10 0 to p10 7 p1 5 to p1 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p10 0 to p10 7 p1 5 to p1 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p10 0 to p10 7 p1 5 to p1 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p10 0 to p10 7 p1 5 to p1 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p10 0 to p10 7 p1 5 to p1 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p10 0 to p10 7, x in , reset, cnvss hysteresis v t+- v t- x in 0.2 0.8 v note 1: referenced to vcc=4.2 to 5.5v, vss=0v at topr = -40 to 85
18. electrical characteristics (m16c/26t) page 281 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m v cc = 5v table 18.45. electrical characteristics (2) (note 1 ) s y m b o l standard typ. u n i t measuring condition min. max. p a r a m e t e r i c c p o w e r s u p p l y c u r r e n t ( v c c = 4 . 0 t o 5 . 5 v ) the output pins are open and other pins are v ss ma 1 6 f(bclk)=20mhz, main clock, no division f l a s h m e m o r y ma f l a s h m e m o r y p r o g r a m v cc =5.0v f(bclk)=10mhz, ma f l a s h m e m o r y e r a s e v cc =5.0v f(bclk)=10mhz, t opr =25 c 3 a s t o p m o d e , f ( b c l k )=3 2 k h z , wait mode (note 2), oscillation capacity high a 0 . 8 a note 1: referenced to v cc =4.2 to 5.5v, v ss =0v at topr = -40 to 85 c, f(x in )=20mhz unless otherwise specified. note 2: with one timer operated using f c32 . note 3: this indicates the memory in which the program to be executed exists. note 4: with one timer operated. ma a low power dissipation mode, ram(note 3) f ( b c l k ) = 3 2 k h z a low power dissipation mode, flash memory(note 3) f(bclk)=32khz, a fl as h memory o n - c h i p o s c i l l a t i o n , f 2 ( r o c ) s e l e c t e d , f ( b c k ) = 1 m h z , w a i t m o d e ( n o t e 4 ) f(bclk)=32khz, wait mode(note 2), oscillation capacity low on-chip oscillation f 2(roc) selected, f(bck)=1mhz 19 1 11 1 2 25 4 5 0 5 0 1 0 3
18. electrical characteristics (m16c/26t) page 282 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m v cc = 5v timing requirements (v cc = 5v, v ss = 0v, at topr = 40 to 85 o c unless otherwise specified) table 18.46. external clock input (x in input) max. external clock rise time ns t r min. external clock input cycle time external clock input high pulse width external clock input low pulse width external clock fall time ns ns ns ns t c t w(h ) t w(l) t f parameter symbol unit standard 50 20 20 9 9
18. electrical characteristics (m16c/26t) page 283 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m v cc = 5v timing requirements (v cc = 5v, v ss = 0v, at topr = 40 to 85 o c unless otherwise specified) table 18.48. timer a input (gating input in timer mode) table 18.49. timer a input (external trigger input in one-shot timer mode) table 18.50. timer a input (external trigger input in pulse width modulation mode) table 18.51. timer a input (counter increment/decrement input in event counter mode) table 18.47. timer a input (counter input in event counter mode) table 18.52. timer a input (two-phase pulse input in event counter mode) standard max. ns tai in input low pulse width t w(tal) min. ns ns unit tai in input high pulse width t w(tah) parameter symbol t c(ta) tai in input cycle time 40 100 40 standard max. min. ns ns ns unit tai in input cycle time tai in input high pulse width tai in input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter 400 200 200 standard max. min. ns ns ns unit tai in input cycle time tai in input high pulse width tai in input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter 200 100 100 standard max. min. ns ns unit t w(tah) t w(tal) symbol parameter tai in input high pulse width tai in input low pulse width 100 100 standard max. min. ns ns ns unit ns ns symbol parameter tai out input cycle time tai out input high pulse width tai out input low pulse width tai out input setup time tai out input hold time t c(up) t w(uph) t w(upl) t su(up-t in ) t h(t in- up) 2000 1000 1000 400 400 standard max. min. ns ns ns unit symbol parameter tai in input cycle time tai out input setup time tai in input setup time t c(ta) t su(ta in -ta out ) t su(ta out -ta in ) 800 200 200
18. electrical characteristics (m16c/26t) page 284 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m timing requirements (v cc = 5v, v ss = 0v, at topr = 40 to 85 o c unless otherwise specified) table 18.53. timer b input (counter input in event counter mode) table 18.54. timer b input (pulse period measurement mode) table 18.55. timer b input (pulse width measurement mode) table 18.56. a/d trigger input table 18.57. serial i/o _______ table 18.58. external interrupt inti input v cc = 5v ns ns ns ns ns ns ns standard max. min. tbi in input cycle time (counted on one edge) tbi in input high pulse width (counted on one edge) tbi in input low pulse width (counted on one edge) ns ns ns t c(tb) t w(tbh) t w(tbl) parameter symbol unit t c(tb) t w(tbl) t w(tbh) ns ns ns tbi in input high pulse width (counted on both edges) tbi in input low pulse width (counted on both edges) tbi in input cycle time (counted on both edges) standard max. min. ns ns t c(tb) t w(tbh) symbol parameter unit t w(tbl) ns tbi in input high pulse width tbi in input cycle time tbi in input low pulse width standard max. min. ns ns t c(tb) symbol parameter unit t w(tbl) ns t w(tbh) tbi in input cycle time tbi in input high pulse width tbi in input low pulse width standard max. min. ns ns t c(ad) t w(adl) symbol parameter unit ad trg input cycle time (trigger able minimum) ad trg input low pulse width standard max. min. ns ns t w(inh) t w(inl) symbol parameter unit inti input low pulse width inti input high pulse width standard max. min. clki input cycle time clki input high pulse width clki input low pulse width t c(ck) t w(ckh) t w(ckl) parameter symbol unit t d(c-q) t su(d-c) t h(c-q) txdi hold time rxdi input setup time txdi output delay time t h(c-d) rxdi input hold time 100 40 40 80 80 200 400 200 200 400 200 200 1000 125 250 250 200 100 100 0 70 90 80
18. electrical characteristics (m16c/26t) page 285 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m v cc = 5v taiin input taiout input during event counter mode tbiin input adtrg input t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) t h(tin-up) t su(up-tin) taiin input (when count on falling edge is selected) taiin input (when count on rising edge is selected) taiout input (up/down input) taiin input two-phase pulse input in event counter mode t c(ta) t su(tain-taout) t su(taout-tain) t su(tain-taout) t su(taout-tain) taiout input xin input t w(h) t w(l) t r t f t c figure 18.5. timing diagram (1)
18. electrical characteristics (m16c/26t) page 286 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m v cc = 5v figure 18.6. timing diagram (2) t su(d C c) clki txdi rxdi t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) t d(c C q) t h(c C d) t h(c C q) inti input
18. electrical characteristics (m16c/26t) page 287 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m v cc = 3v table 18.59. electrical characteristics ( note) s y m b o l v o h h i g h o u t p u t v o l t a g e v o h v o l l o w o u t p u t v o l t a g e v o l h i g h o u t p u t v o l t a g e standard typ. u n i t measuring condition v v x o u t v v x o u t 0.5 0.5 m i n .m a x . v c c - 0 . 5 p a r a m e t e r i oh = - 1ma i oh = - 0.1ma i oh = - 50 a i ol =1ma i ol =0.1ma i ol =50 a h i g h p o w e r l o w p o w e r h i g h p o w e r l o w p o w e r h i g h p o w e r lowpower x c o u t with no load applied with no load applied 2.5 1 . 6 v h y s t e r e s i s h y s t e r e s i s h i g h i n p u t c u r r e n t i i h l o w i n p u t c u r r e n t i il v ram ram retention voltage v t + - v t - v t + - v t - 0.8 v 1 . 8v 4.0 a a at stop mode 2.0 v r e s e t x in , reset, cnvss v i =3v v i =0v - 4 . 0 r fxin r fxcin feedback resistance x in feedback resistance x cin 25 3.0 m ? m ? r p u l l u p pull-up resistance 1 0 0k ? v x c o u t 0 0 with no load applied with no load applied h i g h p o w e r l o w p o w e r v i =0v 5 05 0 0 c l k 0 t o c l k 2 , t a 2 o u t t o t a 4 o u t , t a 0 i n t o t a 4 i n , t b 0 i n t o t b 2 i n , a d t r g , c t s 0 t o c t s 2 , i n t 0 t o i n t 5 , n m i , k i 0 t o k i 3 , r x d 0 t o r x d 2 x i n , r e s e t , c n v s s v c c - 0 . 5 v c c - 0 . 5 note 1 : referenced to v cc =3.0 to 3.3v, v ss =0v at topr = -40 to 85 c, f(bclk)=20mhz unless otherwise specified. v c c v c c v c c 0.5 h i g h o u t p u t v o l t a g e l o w o u t p u t v o l t a g e l o w o u t p u t v o l t a g e p 1 5 t o p 1 7 , p 6 0 t o p 6 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p 9 0 t o p 9 3 , p 1 0 0 t o p 1 0 7 p 1 5 t o p 1 7 , p 6 0 t o p 6 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p 9 0 t o p 9 3 , p 1 0 0 t o p 1 0 7 p1 5 to p1 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p10 0 to p10 7 p1 5 to p1 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p10 0 to p10 7 p1 5 to p1 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 3 , p10 0 to p10 7 hysteresis v t+- v t- 0.8 v x i n
18. electrical characteristics (m16c/26t) page 288 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m table 18.60. electrical characteristics (2) ( note 1) v cc = 3v s y m b o l s t a n d a r d t y p . unit m e a s u r i n g c o n d i t i o n m i n .max. p a r a m e t e r th e o u t p u t p i n s a r e o p e n a n d o t h e r p i n s a r e v s s main clock, no division m a f ( b c l k ) = 1 0 m h z , 1 2 f l a s h m e m o r y i c c p o w e r s u p p l y c u r r e n t ( v c c = 3 . 0 t o 3 . 6 v ) t opr =25 c 3 a stop mode, f(bclk)=32khz, w a i t m o d e ( n o t e 2 ) , o s c i l l a t i o n c a p a c i t y h i g h a 0 . 7 a n o t e 1 : r e f e r e n c e d t o v c c = 3 . 0 t o 3 . 3 v , v s s = 0 v a t t o p r = - 4 0 t o 8 5 c , f ( b c l k ) = 2 0 m h z u n l e s s o t h e r w i s e s p e c i f i e d . n o t e 2 : w i t h o n e t i m e r o p e r a t e d u s i n g f c 3 2 . n o t e 3 : t h i s i n d i c a t e s t h e m e m o r y i n w h i c h t h e p r o g r a m t o b e e x e c u t e d e x i s t s . n o t e 4 : w i t h o n e t i m e r o p e r a t e d . a low power dissipation mode, ram(note 3) f ( b c l k ) = 3 2 k h z , a l o w p o w e r d i s s i p a t i o n m o d e , f l a s h m e m o r y ( n o t e 3 ) f(bclk)=32khz, a f l a s h m e m o r y on-chip oscillation, f 2(roc) selected, f(bck)=1mhz,wait mode (note 4) f(bclk)=32khz, wait mode (note 2), oscillation capacity low 7 v c c= 3 . 0 v m a fl as h memory f(bclk)=10mhz, p rogram v c c= 3 . 0 v m a fl as h memory f(bclk)=10mhz, e rase 1 0 1 1 25 4 5 0 4 5 1 0 3 1 on-chip oscillation, f 2(roc) selected, f(bck)=1mhz m a
18. electrical characteristics (m16c/26t) page 289 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m timing requirements (v cc = 3v, v ss = 0v, at topr = 40 to 85 o c unless otherwise specified) table 18.61. external clock input (x in input) max. external clock rise time ns t r min. external clock input cycle time external clock input high pulse width external clock input low pulse width external clock fall time ns ns ns ns t c t w(h ) t w(l) t f parameter symbol unit standard 100 40 40 18 18 v cc = 3v
18. electrical characteristics (m16c/26t) page 290 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m v cc = 3v timing requirements (v cc = 3v, v ss = 0v, at topr = 40 to 85 o c unless otherwise specified) table 18.62. timer a input (counter input in event counter mode) table 18.63. timer a input (gating input in timer mode) table 18.64. timer a input (external trigger input in one-shot timer mode) table 18.65. timer a input (external trigger input in pulse width modulation mode) table 18.66. timer a input (counter increment/decrement input in event counter mode) table 18.67. timer a input (two-phase pulse input in event counter mode) standard max. ns tai in input low pulse width t w(tal) min. ns ns unit tai in input high pulse width t w(tah) parameter symbol t c(ta) tai in input cycle time 60 150 60 standard max. min. ns ns ns unit tai in input cycle time tai in input high pulse width tai in input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter 600 300 300 standard max. min. ns ns ns unit tai in input cycle time tai in input high pulse width tai in input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter 300 150 150 standard max. min. ns ns unit t w(tah) t w(tal) symbol parameter tai in input high pulse width tai in input low pulse width 150 150 standard max. min. ns ns ns unit ns ns symbol parameter tai out input cycle time tai out input high pulse width tai out input low pulse width tai out input setup time tai out input hold time t c(up) t w(uph) t w(upl) t su(up-t in ) t h(t in- up) 3000 1500 1500 600 600 standard max. min. s ns ns unit symbol parameter tai in input cycle time tai out input setup time tai in input setup time t c(ta) t su(ta in -ta out ) t su(ta out -ta in ) 2 500 500
18. electrical characteristics (m16c/26t) page 291 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m v cc = 3v table 18.68. timer b input (counter input in event counter mode) table 18.69. timer b input (pulse period measurement mode) table 18.70. timer b input (pulse width measurement mode) table 18.71. a/d trigger input table 18.72. serial i/o _______ table 18.73. external interrupt inti input timing requirements (v cc = 3v, v ss = 0v, at topr = 40 to 85 o c unless otherwise specified) ns ns ns ns ns ns ns standard max. min. tbi in input cycle time (counted on one edge) tbi in input high pulse width (counted on one edge) tbi in input low pulse width (counted on one edge) ns ns ns t c(tb) t w(tbh) t w(tbl) parameter symbol unit t c(tb) t w(tbl) t w(tbh) ns ns ns tbi in input high pulse width (counted on both edges) tbi in input low pulse width (counted on both edges) tbi in input cycle time (counted on both edges) standard max. min. ns ns t c(tb) t w(tbh) symbol parameter unit t w(tbl) ns tbi in input high pulse width tbi in input cycle time tbi in input low pulse width standard max. min. ns ns t c(tb) symbol parameter unit t w(tbl) ns t w(tbh) tbi in input cycle time tbi in input high pulse width tbi in input low pulse width standard max. min. ns ns t c(ad) t w(adl) symbol parameter unit ad trg input cycle time (trigger able minimum) ad trg input low pulse width standard max. min. ns ns t w(inh) t w(inl) symbol parameter unit inti input low pulse width inti input high pulse width standard max. min. clki input cycle time clki input high pulse width clki input low pulse width t c(ck) t w(ckh) t w(ckl) parameter symbol unit t d(c-q) t su(d-c) t h(c-q) txdi hold time rxdi input setup time txdi output delay time t h(c-d) rxdi input hold time 150 60 60 120 120 300 600 300 300 600 300 300 1500 200 380 380 300 150 150 0 100 90 160
18. electrical characteristics (m16c/26t) page 292 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m v cc = 3v figure 18.7. timing diagram (1) taiin input taiout input during event counter mode tbiin input adtrg input t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) t h(tin-up) t su(up-tin) taiin input (when count on falling edge is selected) taiin input (when count on rising edge is selected) taiout input (up/down input) taiin input two-phase pulse input in event counter mode t c(ta) t su(tain-taout) t su(taout-tain) t su(tain-taout) t su(taout-tain) taiout input xin input t w(h) t w(l) t r t f t c
18. electrical characteristics (m16c/26t) page 293 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m v cc = 3v figure 18.8. timing diagram (2) t su(d C c) clki txdi rxdi t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) t d(c C q) t h(c C d) t h(c C q) inti input
page 294 19. usage precaution 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 19. usage precaution 19.1 sfr 19.1.1 precaution for 48 pin version set the ifsr20 bit in the ifsr2a register to "1" after reset and set the pacr2 to pacr0 bits in the pacr register to "100 2 ". 19.1.2 precaution for 42 pin version set the ifsr20 bit in the ifsr2a register to "1" after reset and set the pacr2 to pacr0 bits in the pacr register to "001 2 ".
page 295 19. usage precaution 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 19.2 pll frequency synthesizer stabilize supply voltage so that the standard of the power supply ripple is met. 10 typ. max. unit parameter f (ripple) power supply ripple allowable frequency(v cc ) symbol min. standard khz power supply ripple allowabled amplitude voltage power supply ripple rising/falling gradient (v cc =5v) (v cc =3v) (v cc =5v) (v cc =3v) v p-p(ripple) v cc(| ? v/ ? t|) 0.5 0.3 0.3 0.3 v v/ms v/ms v v p-p(ripple) f (ripple) v cc f (ripple) power supply ripple allowable frequency (v cc ) v p-p(ripple) power supply ripple allowable amplitude voltage figure 19.1 timing of voltage fluctuation
page 296 19. usage precaution 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 19.3 power control 1. when exiting stop mode by hardware reset, the device will startup using the on-chip oscillator. 2. set the mr0 bit in the taimr register(i=0 to 4) to 0 (pulse is not output) to use the timer a to exit stop mode. 3. when entering wait mode, insert a jmp.b instruction before a wait instruction. do not excute any instructions which can generate a write to ram between the jmp.b and wait instructions. disable the dma transfers, if a dma transfer may occur between the jmp.b and wait instructions. after the wait instruction, insert at least 4 nop instructions. when entering wait mode, the instruction queue reads ahead the instructions following wait, and depending on timing, some of these may execute before the microcomputer enters wait mode. program example when entering wait mode program example: jmp.b l1 ; insert jmp.b instruction before wait instruction l1: fset i ; wait ; enter wait mode nop ; more than 4 nop instructions nop nop nop 4. when entering stop mode, insert a jmp.b instruction immediately after executing an instruction which sets the cm10 bit in the cm1 register to 1 , and then insert at least 4 nop instructions. when entering stop mode, the instruction queue reads ahead the instructions following the instruction which sets the cm10 bit to 1 (all clock stops), and, some of these may execute before the microcomputer enters stop mode or before the interrupt routine for returning from stop mode. program example when entering stop mode program example: fset i bset cm10 ; enter stop mode jmp.b l1 ; insert jmp.b instruction l1: nop ; more than 4 nop instructions nop nop nop
page 297 19. usage precaution 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 5. wait until the main clock oscillation stabilization time, before switching the cpu clock source to the main clock. similarly, wait until the sub clock oscillates stably before switching the cpu clock source to the sub clock. 6. suggestions to reduce power consumption (a) ports the processor retains the state of each i/o port even when it goes to wait mode or to stop mode. a current flows in active i/o ports. a dash current may flow through the input ports in high impedance state, if the input is floating. when entering wait mode or stop mode, set non-used ports to input and stabilize the potential. (b) a/d converter when a/d conversion is not performed, set the vcut bit in the adcon1 register to 0 (no v ref connection). when a/d conversion is performed, start the a/d conversion at least 1 s or longer after setting the vcut bit to 1 (v ref connection). (c) stopping peripheral functions use the cm02 bit in the cm0 register to stop the unnecessary peripheral functions during wait mode. however, because the peripheral function clock (f c32 ) generated from the sub-clock does not stop, this measure is not conducive to reducing the power consumption of the chip. if low speed mode or low power dissipation mode is to be changed to wait mode, set the cm02 bit to 0 (do not stop peripheral function clocks in wait mode), before changing wait mode. (d) switching the oscillation-driving capacity set the driving capacity to low when oscillation is stable.
page 298 19. usage precaution 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 19.4 protect set the prc2 bit to 1 (write enabled) and then write to any address, and the prc2 bit will be cleared to 0 (write protected). the registers protected by the prc2 bit should be changed in the next instruction after setting the prc2 bit to 1 . make sure no interrupts or dma transfers will occur between the instruction in which the prc2 bit is set to 1 and the next instruction.
page 299 19. usage precaution 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 19.5 interrupts 19.5.1 reading address 00000 16 do not read the address 00000 16 in a program. when a maskable interrupt request is accepted, the cpu reads interrupt information (interrupt number and interrupt request priority level) from the address 00000 16 during the interrupt sequence. at this time, the ir bit for the accepted interrupt is cleared to 0 . if the address 00000 16 is read in a program, the ir bit for the interrupt which has the highest priority among the enabled interrupts is cleared to 0 . this causes a problem that the interrupt is canceled, or an unexpected interrupt request is generated. 19.5.2 setting the sp set any value in the sp(usp, isp) before accepting an interrupt. the sp(usp, isp) is cleared to 0000 16 after reset. therefore, if an interrupt is accepted before setting any value in the sp(usp, isp), the pro- gram may go out of control. _______ 19.5.3 the nmi interrupt _______ _______ 1. the nmi interrupt is invalid after reset. the nmi interrupt becomes effective by setting to 1 the pm24 bit in the pm2 register. once enabled, it stays enabled until a reset is applied. _______ 2. the input level of the nmi pin can be read by accessing the p8_5 bit in the p8 register. note that the _______ p8_5 bit can only be read when determining the pin level in nmi interrupt routine. _______ _______ 3. when selecting nmi function, stop mode cannot be entered into while input on the nmi pin is low. this _______ is because while input on the nmi pin is low the cm10 bit in the cm1 register is fixed to 0 . _______ _______ 4. when selecting nmi function, do not go to wait mode while input on the nmi pin is low. this is because _______ when input on the nmi pin goes low, the cpu stops but cpu clock remains active; therefore, the current consumption in the chip does not drop. in this case, normal condition is restored by an interrupt gener- ated thereafter. _______ _______ 5. when selecting nmi function, the low and high level durations of the input signal to the nmi pin must each be 2 cpu clock cycles + 300 ns or more. _______ 6. when using the nmi interrupt for exiting stop mode, set the nddr register to ff 16 (disable digital debounce filter) before entering stop mode.
page 300 19. usage precaution 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 19.5.4 changing the interrupt generation factor if the interrupt generate factor is changed, the ir bit in the interrupt control register for the changed interrupt may inadvertently be set to 1 (interrupt requested). if you changed the interrupt generate factor for an interrupt that needs to be used, be sure to clear the ir bit for that interrupt to 0 (interrupt not requested). changing the interrupt generate factor referred to here means any act of changing the source, polarity or timing of the interrupt assigned to each software interrupt number. therefore, if a mode change of any peripheral function involves changing the generate factor, polarity or timing of an interrupt, be sure to clear the ir bit for that interrupt to 0 (interrupt not requested) after making such changes. refer to the description of each peripheral function for details about the interrupts from peripheral functions. figure 19.2 shows the procedure for changing the interrupt generate factor. figure 19.2. procedure for changing the interrupt generate factor changing the interrupt source disable interrupts (note 2, note 3) use the mov instruction to clear the ir bit to 0 (interrupt not requested) (note 3) change the interrupt generate factor (including a mode change of peripheral function) enable interrupts (note 2, note 3) end of change ir bit: a bit in the interrupt control register for the interrupt whose interrupt generate factor is to be changed note 1: the above settings must be executed individually. do not execute two or more settings simultaneously (using one instruction). note 2: use the i flag for the inti interrupt (i = 0 to 5). for the interrupts from peripheral functions other than the inti interrupt, turn off the peripheral function that is the source of the interrupt in order not to generate an interrupt request before changing the interrupt generate factor. in this case, if the maskable interrupts can all be disabled without causing a problem, use the i flag. otherwise, use the corresponding ilvl2 to ilvl0 bit for the interrupt whose interrupt generate factor is to be changed. note 3: refer to section 1.5.6, rewrite the interrupt control register for details about the instructions to use and the notes to be taken for instruction execution.
page 301 19. usage precaution 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m ______ 19.5.5 int interrupt 1. either an l level of at least t w ( inh ) or an h level of at least t w ( inl ) width is necessary for the signal _______ _______ input to pins int 0 through int 5 regardless of the cpu operation clock. 2. if the pol bit in the int0ic to int5ic registers or the ifsr7 to ifsr0 bits in the ifsr register are changed, the ir bit may inadvertently set to 1 (interrupt requested). be sure to clear the ir bit to 0 (interrupt not requested) after changing any of those register bits. 3. when using the int 5 interrupt for exiting stop mode, set the p17ddr register to ff 16 (disable digital debounce filter) before entering stop mode. 19.5.6 rewrite the interrupt control register (1) the interrupt control register for any interrupt should be modified in places where no requests for that interrupt may occur. otherwise, disable the interrupt before rewriting the interrupt control register. (2) to rewrite the interrupt control register for any interrupt after disabling that interrupt, be careful with the instruction to be used. changing any bit other than the ir bit if while executing an instruction, a request for an interrupt controlled by the register being modified occurs, the ir bit in the register may not be set to 1 (interrupt requested), with the result that the interrupt request is ignored. if such a situation presents a problem, use the instructions shown below to modify the register. usable instructions: and, or, bclr, bset changing the ir bit depending on the instruction used, the ir bit may not always be cleared to 0 (interrupt not re- quested). therefore, be sure to use the mov instruction to clear the ir bit. (3) when using the i flag to disable an interrupt, refer to the sample program fragments shown below as you set the i flag. (refer to (2) for details about rewrite the interrupt control registers in the sample program fragments.) examples 1 through 3 show how to prevent the i flag from being set to 1 (interrupts enabled) before the interrupt control register is rewritten, due to the internal bus and the instruction queue buffer timing.
page 302 19. usage precaution 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 19.5.7 watchdog timer interrupt initialize the watchdog timer after the watchdog timer interrupt occurs. example 1:using the nop instruction to keep the program waiting until the interrupt control register is modified int_switch1: fclr i ; disable interrupts. and.b #00h, 0055h ; set the ta0ic register to 00 16 . nop ; nop fset i ; enable interrupts. the number of nop instruction is 2. example 2:using the dummy read to keep the fset instruction waiting int_switch2: fclr i ; disable interrupts. and.b #00h, 0055h ; set the ta0ic register to 00 16 . mov.w mem, r0 ; dummy read. fset i ; enable interrupts. example 3:using the popc instruction to changing the i flag int_switch3: pushc flg fclr i ; disable interrupts. and.b #00h, 0055h ; set the ta0ic register to 00 16 . popc flg ; enable interrupts.
page 303 19. usage precaution 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 19.6 dmac 19.6.1 write to dmae bit in dmicon register when both of the conditions below are met, follow the steps below. conditions ? the dmae bit is set to 1 again while it remains set (dmai is in an active state). ? a dma request may occur simultaneously when the dmae bit is being written. step 1: write 1 to the dmae bit and dmas bit in dmicon register simultaneously (*1) . step 2: make sure that the dmai is in an initial state (*2) in a program. if the dmai is not in an initial state, the above steps should be repeated. notes: *1. the dmas bit remains unchanged even if 1 is written. however, if 0 is written to this bit, it is set to 0 (dma not requested). in order to prevent the dmas bit from being modified to 0 , 1 should be written to the dmas bit when 1 is written to the dmae bit. in this way the state of the dmas bit immediately before being written can be maintained. similarly, when writing to the dmae bit with a read-modify-write instruction, 1 should be written to the dmas bit in order to maintain a dma request which is generated during execution. *2. read the tcri register to verify whether the dmai is in an initial state. if the read value is equal to a value which was written to the tcri register before dma transfer start, the dmai is in an initial state. (if a dma request occurs after writing to the dmae bit, the value written to the tcri register is 1 .) if the read value is a value in the middle of transfer, the dmai is not in an initial state.
page 304 19. usage precaution 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 19.7 timer 19.7.1 timer a 19.7.1.1 timer a (timer mode) 1. the timer remains idle after reset. set the mode, count source, counter value, etc. using the taimr (i = 0 to 4) register and the tai register before setting the tais bit in the tabsr register to 1 (count starts). always make sure the taimr register is modified while the tais bit remains 0 (count stops) regardless whether after reset or not. 2. while counting is in progress, the counter value can be read out at any time by reading the tai register. however, if the tai register is read at the same time the counter is reloaded, the read value is always ffff 16 . if the tai register is read after setting a value in it, but before the counter starts counting, the read value is the one that has been set in the register. _____ 3. if a low-level signal is applied to the sd pin when the ivpcr1 bit in the tb2sc register is set to 1 _____ (three-phase output forcible cutoff by input on sd pin enabled), the ta1 out , ta2 out and ta4 out pins go to a high-impedance state.
page 305 19. usage precaution 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 19.7.1.2 timer a (event counter mode) 1. the timer remains idle after reset. set the mode, count source, counter value, etc. using the taimr (i = 0 to 4) register, the tai register, the udf register, the tazie, ta0tgl and ta0tgh bits in the onsf register and the trgsr register before setting the tais bit in the tabsr register to 1 (count starts). always make sure the taimr register, the udf register, the tazie, ta0tgl and ta0tgh bits and the trgsr register are modified while the tais bit remains 0 (count stops) regardless whether after reset or not. 2. while counting is in progress, the counter value can be read out at any time by reading the tai register. however, if the tai register is read at the same time the counter is reloaded, the read value is always ffff 16 when the timer counter underflows and 0000 16 when the timer counter over- flows. if the tai register is read after setting a value in it, but before the counter starts counting, the read value is the one that has been set in the register. _____ 3. if a low-level signal is applied to the sd pin when the ivpcr1 bit in the tb2sc register is set to 1 _____ (three-phase output forcible cutoff by input on sd pin enabled), the ta1 out , ta2 out and ta4 out pins go to a high-impedance state.
page 306 19. usage precaution 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 19.7.1.3 timer a (one-shot timer mode) 1. the timer remains idle after reset. set the mode, count source, counter value, etc. using the taimr (i = 0 to 4) register, the tai register, the ta0tgl and ta0tgh bits in the onsf register and the trgsr register before setting the tais bit in the tabsr register to 1 (count starts). always make sure the taimr register, the ta0tgl and ta0tgh bits and the trgsr register are modified while the tais bit remains 0 (count stops) regardless whether after reset or not. 2. when setting tais bit to 0 (count stop), the following occur: ? the counter stops counting and the content of reload register is reloaded. ? tai out pin outputs l . ? after one cycle of the cpu clock, the ir bit in the taiic register is set to 1 (interrupt request). 3. output in one-shot timer mode synchronizes with a count source internally generated. when the external trigger has been selected, a maximun delay of one cycle of the count source occurs be- tween the trigger input to tai in pin and output in one-shot timer mode. 4. the ir bit is set to 1 when timer operation mode is set with any of the following procedures: ? select one-shot timer mode after reset. ? change the operation mode from timer mode to one-shot timer mode. ? change the operation mode from event counter mode to one-shot timer mode. to use the timer ai interrupt (the ir bit), set the ir bit to 0 after the changes listed above have been made. 5. when a trigger occurs while the timer is counting, the counter reloads the reload register value, and continues counting after a second trigger is generated and the counter is decremented once. to generate a trigger while counting, space more than one cycle of the timer count source from the first trigger and generate again. 6. when selecting the external trigger for the count start conditions in timer a one-shot timer mode, do generate an external trigger 300ns before the count value of timer a is set to 0000 16 . the one-shot timer does not continue counting and may stop. _____ 7. if a low-level signal is applied to the sd pin when the ivpcr1 bit in the tb2sc register is set to 1 _____ (three-phase output forcible cutoff by input on sd pin enabled), the ta1 out , ta2 out and ta4 out pins go to a high-impedance state.
page 307 19. usage precaution 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 19.7.1.4 timer a (pulse width modulation mode) 1. the timer remains idle after reset. set the mode, count source, counter value, etc. using the taimr (i = 0 to 4) register, the tai register, the ta0tgl and ta0tgh bits in the onsf register and the trgsr register before setting the tais bit in the tabsr register to 1 (count starts). always make sure the taimr register, the ta0tgl and ta0tgh bits and the trgsr register are modified while the tais bit remains 0 (count stops) regardless whether after reset or not. 2. the ir bit is set to 1 when setting a timer operation mode with any of the following procedures: ? select the pwm mode after reset. ? change an operation mode from timer mode to pwm mode. ? change an operation mode from event counter mode to pwm mode. to use the timer ai interrupt (interrupt request bit), set the ir bit to 0 by program after the above listed changes have been made. 3. when setting tais register to 0 (count stop) during pwm pulse output, the following action occurs: ? stop counting. ? when tai out pin is output h , output level is set to l and the ir bit is set to 1 . ? when tai out pin is output l , both output level and the ir bit remains unchanged. _____ 4. if a low-level signal is applied to the sd pin when the ivpcr1 bit in the tb2sc register is set to 1 _____ (three-phase output forcible cutoff by input on sd pin enabled), the ta1 out , ta2 out and ta4 out pins go to a high-impedance state.
page 308 19. usage precaution 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 19.7.2 timer b 19.7.2.1 timer b (timer mode) 1. the timer remains idle after reset. set the mode, count source, counter value, etc. using the tbimr (i = 0 to 2) register and tbi register before setting the tbis bit in the tabsr register to 1 (count starts). always make sure the tbimr register is modified while the tbis bit remains 0 (count stops) regardless whether after reset or not. 2. the counter value can be read out at any time by reading the tbi register. however, if this register is read at the same time the counter is reloaded, the read value is always ffff 16 . if the tbi register is read after setting a value in it but before the counter starts counting, the read value is the one that has been set in the register.
page 309 19. usage precaution 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 19.7.2.2 timer b (event counter mode) 1. the timer remains idle after reset. set the mode, count source, counter value, etc. using the tbimr (i = 0 to 2) register and tbi register before setting the tbis bit in the tabsr register to 1 (count starts). always make sure the tbimr register is modified while the tbis bit remains 0 (count stops) regardless whether after reset or not. 2. the counter value can be read out at any time by reading the tbi register. however, if this register is read at the same time the counter is reloaded, the read value is always ffff 16 . if the tbi register is read after setting a value in it but before the counter starts counting, the read value is the one that has been set in the register.
page 310 19. usage precaution 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 19.7.2.3 timer b (pulse period/pulse width measurement mode) 1. the timer remains idle after reset. set the mode, count source, etc. using the tbimr (i = 0 to 2) register before setting the tbis bit in the tabsr register to 1 (count starts). always make sure the tbimr register is modified while the tbis bit remains 0 (count stops) regardless whether after reset or not. to clear the mr3 bit to 0 by writing to the tbimr register while the tbis bit is set to 1 (count starts), be sure to set the tm0d0, tm0d1, mr0, mr1, tck0 and tck1 bits to the same value as previously written and the mr2 bit to "0". 2. the ir bit in the tbiic register (i=0 to 2) goes to 1 (interrupt request), when an effective edge of a measurement pulse is input or timer bi is overflowed. the factor of interrupt request can be determined by use of the mr3 bit in the tbimr register within the interrupt routine. 3. if the source of interrupt cannot be identified by the mr3 bit such as when the measurement pulse input and a timer overflow occur at the same time, use another timer to count the number of times timer b has overflowed. 4. to set the mr3 bit to 0 (no overflow), set tbimr register with setting the tbis bit to 1 and counting the next count source after setting the mr3 bit to 1 (overflow). 5. use the ir bit in the tbiic register to detect only overflows. use the mr3 bit only to determine the interrupt factor within the interrupt routine. 6. when the count is started and the first effective edge is input, an indeterminate value is transferred to the reload register. at this time, timer bi interrupt request is not generated. 7. the value of the counter is indeterminate at the beginning of a count. mr3 may be set to 1 and timer bi interrupt request may be generated between the count start and an effective edge input. 8. for pulse width measurement, pulse widths are successively measured. use program to check whether the measurement result is an h level width or an l level width.
page 311 19. usage precaution 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 19.8 serial i/o (clock-synchronous serial i/o) 19.8.1 transmission/reception _______ ________ 1. with an external clock selected, and choosing the rts function, the output level of the rtsi pin goes to l when the data-receivable status becomes ready, which informs the transmission side that the ________ reception has become ready. the output level of the rtsi pin goes to h when reception starts. so if ________ ________ the rtsi pin is connected to the ctsi pin on the transmission side, the circuit can transmit and receive _______ data with consistent timing. with the internal clock, the rts function has no effect. _____ 2. if a low-level signal is applied to the sd pin when the ivpcr1 bit in the tb2sc register is set to 1 _____ _________ (three-phase output forcible cutoff by input on sd pin enabled), the p7 3 /rts 2 /txd1(when the u1map bit in pacr register is 1 ) and clk 2 pins go to a high-impedance state.
page 312 19. usage precaution 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 19.8.2 transmission when an external clock is selected, the conditions must be met while if the ckpol bit in the uic0 register is set to 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the external clock is in the high state; if the ckpol bit in the uic0 register is set to 1 (transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state. ? the te bit in the uic1 register is set to 1 (transmission enabled) ? the ti bit in the uic1 register is set to 0 (data present in uitb register) _______ _______ ? if cts function is selected, input on the ctsi pin is l
page 313 19. usage precaution 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 19.8.3 reception 1. in operating the clock-synchronous serial i/o, operating the transmitter generates a clock for the re- ceiver shift register. fix settings for transmission even when using the device only for reception. dummy data is output to the outside from the txdi pin when receiving data. 2. when an internal clock is selected, set the te bit in the uic1 register (i = 0 to 2) to 1 (transmission enabled) and write dummy data to the uitb register, and the clock for the receiver shift register will thereby be generated. when an external clock is selected, set the te bit to "1" and write dummy data to the uitb register, and the clock for the receiver shift register will be generated when the external clock is fed to the clki input pin. 3. when successively receiving data, if all bits of the next receive data are prepared in the uarti receive register while the re bit in the uic1 register (i = 0 to 2) is set to 1 (data present in the uirb register), an overrun error occurs and the oer bit in the uirb register is set to 1 (overrun error occurred). in this case, because the content of the uirb register is indeterminate, a corrective measure must be taken by programs on the transmit and receive sides so that the valid data before the overrun error occurred will be retransmitted. note that when an overrun error occurred, the ir bit in the siric register does not change state. 4. to receive data in succession, set dummy data in the lower-order byte of the uitb register every time reception is made. 5. when an external clock is selected, make sure the external clock is in high state if the ckpol bit is set to 0 , and in low state if the ckpol bit is set to 1 before the following conditions are met: ? set the re bit in the uic1 register to 1 (reception enabled) ? set the te bit in the uic1 register to 1 (transmission enabled) ? set the ti bit in the uic1 register to 0 (data present in the uitb register)
page 314 19. usage precaution 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 19.9 serial i/o (uart mode) 19.9.1 special mode 1 (i 2 c bus mode) when generating start, stop and restart conditions, set the stspsel bit in the u2smr4 register to 0 and wait for more than half cycle of the transfer clock before setting each condition generate bit (stareq, rstareq and stpreq) from 0 to 1 . 19.9.2 special mode 2 _______ _____ if a low-level signal is applied to the p8 5 /nmi/sd pin when the ivpcr1 bit in the tb2sc register is set to _____ "1" (three-phase output forcible cutoff by input on sd pin enabled), the p7 3 /rts 2 /txd1(when the u1map bit in pacr register is 1 ) and clk 2 pins go to a high-impedance state. 19.9.3 special mode 4 (sim mode) a transmit interrupt request is generated by setting the u2irs bit in the u2c1 register to 1 (transmission complete) and u2ere bit to 1 (error signal output) after reset. therefore, when using sim mode, be sure to clear the ir bit to 0 (no interrupt request) after setting these bits.
page 315 19. usage precaution 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 19.10 a/d converter 1. set adcon0 (except bit 6), adcon1 and adcon2 registers when a/d conversion is stopped (before a trigger occurs). 2. when the vcut bit in the adcon1 register is changed from 0 (vref not connected) to 1 (vref connected), start a/d conversion after waiting 1 s or longer. 3. to prevent noise-induced device malfunction or latchup, as well as to reduce conversion errors, insert capacitors between the av cc , v ref , and analog input pins (an i (i=0 to 7),an 24 ,an 3i (i=0 to 2)) each and the av ss pin. similarly, insert a capacitor between the v cc pin and the v ss pin. figure 19.4 is an example connection of each pin. 4. make sure the port direction bits for those pins that are used as analog inputs are set to 0 (input mode). also, if the tgr bit in adcon0 register is set to "1" (external trigger), make sure the port ___________ direction bit for the ad trg pin is set to 0 (input mode). 5. when using key input interrupts, do not use any of the four an 4 to an 7 pins as analog inputs. (a key input interrupt request is generated when the a/d input voltage goes low.) 6. the ad frequency must be 10 mhz or less. without sample-and-hold function, limit the ad frequency to 250kh z or more. with the sample and hold function, limit the ad frequency to 1mh z or more. 7. when changing an a/d operation mode, select analog input pin again in the ch2 to ch0 bits in the adcon0 register and the scan1 to scan0 bits in the adcon1 register. figure 19.3. use of capacitors to reduce noise microcomputer note 1: c1 0.47f, c2 0.47f, c3 100pf, c4 0.1f (reference) note 2: use thick and shortest possible wiring to connect capacitors. v cc v ss av cc av ss v ref an i c4 c1 c2 c3 an i : an i (i=0 to 7), an 24 , and an 3i (i=0 to 2) v cc v cc
page 316 19. usage precaution 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 8. if the cpu reads the a/d register i (i = 0 to 7) at the same time the conversion result is stored in the a/ d register i after completion of a/d conversion, an incorrect value may be stored in the a/d register i. this problem occurs when a divide-by-n clock derived from the main clock or a subclock is selected for cpu clock. ? when operating in one-shot mode, single-sweep mode, simultaneous sample sweep mode, delayed trigger mode 0 or delayed trigger mode 1 check to see that a/d conversion is completed before reading the target a/d register i. (check the ir bit in the adic register to see if a/d conversion is completed.) ? when operating in repeat mode or repeat sweep mode 0 or 1 use the main clock for cpu clock directly without dividing it. 9. if a/d conversion is forcibly terminated while in progress by setting the adst bit in the adcon0 register to 0 (a/d conversion halted), the conversion result of the a/d converter is indeterminate. the contents of a/d register i irrelevant to a/d conversion may also become indeterminate. if while a/d conversion is underway the adst bit is cleared to 0 in a program, ignore the values of all a/d register i. 10.when setting the adst bit in the adcon register to "0" to terminate a conversion forcefully by the program in single sweep conversion mode, a/d delayed trigger mode 0 and a/d delayed trigger mode 1 during a/d conversion operation, the a/d interrupt request may be generated. if this causes a prob- lem, set the adst bit to "0" after the interrupt is disabled.
page 317 19. usage precaution 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 19.11 programmable i/o ports _____ 1. if a low-level signal is applied to the sd pin when the ivpcr1 bit in the tb2sc register is set to 1 _____ (three-phase output forcible cutoff by input on sd pin enabled), the p7 2 to p7 5 , p8 0 and p8 1 pins go to a high-impedance state. 2. the input threshold voltage of pins differs between programmable input/output ports and peripheral functions. therefore, if any pin is shared by a programmable input/output port and a peripheral function and the input level at this pin is outside the range of recommended operating conditions v ih and v il (neither high nor low ), the input level may be determined differently depending on which side the program- mable input/output port or the peripheral function is currently selected. 3. when the inv03 bit in the invc0 register is "1"(three-phase motor control timer output enabled), an "l" _______ _____ input on the p8 5 /nmi/sd pin, has the following effect: ? when the ivpcr1 bit in the tb2sc register is set to 1 (three-phase output forcible cutoff by input _____ __ __ ___ on the sd pin enabled), the u/ u/ v/ v/ w/ w pins go to a high-impedance state. _____ ? when the ivpcr1 bit is set to 0 (three-phase output forcible cutoff by input on sd pin __ __ ___ disabled), the u/ u/ v/ v/ w/ w pins go to a normal port. therefore, the p8 5 pin can not be used as programmable i/o port when the inv03 bit is set to "1". _____ _______ _____ when the sd function isn't used, set pd8 5 to 0 (input) and pull the p8 5 /nmi/sd pin to h externally.
page 318 19. usage precaution 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 19.12 electric characteristic differences between mask rom and flash memory version microcomputers flash memory version and mask rom version may have different characteristics, operating margin, noise tolerated dose, noise width dose in electrical characteristics due to internal rom, different layout pattern, etc. when switching to the mask rom version, conduct equivalent tests as system evaluation tests con- ducted in the flash memory version. 19.13 mask rom version 19.13.1 internal rom area when using the masked rom version, write nothing to internal rom area. 19.13.2 reserve bit the b3 to b0 in address 0fffff 16 are reserved bits. set these bits to 1111 2 .
page 319 19. usage precaution 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 19.14 flash memory version 19.14.1 functions to inhibit rewriting flash memory id codes are stored in addresses 0fffdf 16 , 0fffe3 16 , 0fffeb 16 , 0fffef 16 , 0ffff3 16 , 0ffff7 16 , and 0ffffb 16 . if wrong data is written to these addresses, the flash memory cannot be read or written in standard serial i/o mode. the romcp register is mapped in address 0fffff 16 . if wrong data is written to this address, the flash memory cannot be read or written in parallel i/o mode. in the flash memory version of microcomputer, these addresses are allocated to the vector addresses (h) of fixed vectors.the b3 to b0 in address 0fffff 16 are reserved bits. set these bits to 1111 2 . 19.14.2 stop mode when the microcomputer enters stop mode, execute the instruction which sets the cm10 bit to 1 (stop mode) after setting the fmr01 bit to 0 (cpu rewrite mode disabled) and disabling the dma transfer. 19.14.3 wait mode when the microcomputer enters wait mode, excute the wait instruction after setting the fmr01 bit to 0 (cpu rewrite mode disabled). 19.14.4 low power dissipation mode, on-chip oscillator low power dissipation mode if the cm05 bit is set to 1 (main clock stop), the following commands must not be executed. ? program ? block erase 19.14.5 writing command and data write the command code and data at even addresses. 19.14.6 program command write xx40 16 in the first bus cycle and write data to the write address in the second bus cycle, and an auto program operation (data program and verify) will start. make sure the address value specified in the first bus cycle is the same even address as the write address specified in the second bus cycle. 19.14.7 operation speed when cpu clock source is main clock, before entering cpu rewrite mode (ew0 or ew1 mode), select 10 mhz or less for bclk using the cm06 bit in the cm0 register and the cm17 to cm16 bits in the cm1 register. also, when cpu clock is f 3 (roc) on-chip oscillator clock, before entering cpu rewrite mode (ew0 or ew1 mode), set the rocr3 to rocr2 bits in the rocr register to divied by 4 or divide by 8 . on both cases, set the pm17 bit in the pm1 register to 1 (with wait state).
page 320 19. usage precaution 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 19.14.8 instructions prohibited in ew0 mode the following instructions cannot be used in ew0 mode because the flash memory s internal data is referenced: und instruction, into instruction, jmps instruction, jsrs instruction, and brk instruction 19.14.9 interrupts ew0 mode ? any interrupt which has a vector in the variable vector table can be used, providing that its vector is transferred into the ram area. _______ ? the nmi and watchdog timer interrupts can be used because the fmr0 register and fmr1 regis- ter are initialized when one of those interrupts occurs. the jump addresses for those interrupt service routines should be set in the fixed vector table. _______ because the rewrite operation is halted when a nmi or watchdog timer interrupt occurs, the rewrite program must be executed again after exiting the interrupt service routine. ? the address match interrupt cannot be used because the flash memory s internal data is refer- enced. ew1 mode ? make sure that any interrupt which has a vector in the variable vector table or address match interrupt will not be accepted during the auto program or auto erase period. ? avoid using watchdog timer interrupts. _______ ? the nmi interrupt can be used because the fmr0 register and fmr1 register are initialized when this interrupt occurs. the jump address for the interrupt service routine should be set in the fixed vector table. _______ because the rewrite operation is halted when a nmi interrupt occurs, the rewrite program must be executed again after exiting the interrupt service routine. 19.14.10 how to access to set the fmr01, fmr02, fmr11 or fmr16 bit to 1 , set the subject bit to 1 immediately after setting to 0 . do not generate an interrupt or a dma transfer between the instruction to set the bit to 0 and the _______ instruction to set the bit to 1 . set the bit while either the pm24 bit in the pm2 register is set to 0 (nmi _______ _______ disable) or the pm24 bit is set to 1 (nmi funciton) and a high-level ( h ) signal is applied to the nmi pin. 19.14.11 writing in the user rom area ew0 mode ? if the power supply voltage drops while rewriting any block in which the rewrite control program is stored, a problem may occur that the rewrite control program is not correctly rewritten and, conse- quently, the flash memory becomes unable to be rewritten thereafter. in this case, standard serial i/o or parallel i/o mode should be used. ew1 mode ? avoid rewriting any block in which the rewrite control program is stored. 19.14.12 dma transfer in ew1 mode, make sure that no dma transfers will occur while the fmr00 bit in the fmr0 register is set to "0" (during the auto program or auto erase period).
page 321 19. usage precaution 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 19.14.13 regarding programming/erasure times and execution time as the number of programming/erasure times increases, so does the execution time for software com- mands (program, and block erase). _______ the software commands are aborted by hardware reset 1, hardware reset 2, nmi interrupt, and watchdog timer interrupt. if a software command is aborted by such reset or interrupt, the affected block must be erased before reexecuting the aborted command. 19.14.14 definition of programming/erasure times "number of programs and erasure" refers to the number of erasure per block. if the number of program and erasure is n (n=100 1,000 10,000) each block can be erased n times. for example, if a 2k byte block a is erased after writing 1 word data 1024 times, each to a different address, this is counted as one program and erasure. however, data cannot be written to the same adrress more than once without erasing the block. (rewrite prohibited) 19.14.15 flash memory version electrical characteristics 10,000 e/w cycle products (u7, u9) when block a or b e/w cycles exceed 100, select one wait state per block access. when fmr17 is set to "1", one wait state is inserted per access to block a or b - regardless of the value of pm17. wait state insertion during access to all other blocks, as well as to internal ram, is controlled by pm17 - regardless of the setting of fmr17. to use the limited number of erasure efficiently, write to unused address within the block instead of rewite. erase block only after all possible address are used. for example, an 8-word program can be written 128 times before erase becomes necessary. maintaining an equal number of erasure between block a and b will also improve efficiency. we recommend keeping track of the number of times erasure is used. 19.14.16 boot mode an indeterminate value is sometimes output in the i/o port until the internal power supply becomes stable _____________ when "h" is applied to the cnv ss pin and "l" is applied to the reset pin. when setting the cnv ss pin to "h", the following procedure is required: ____________ (1) apply an "l" signal to the reset pin and the cnv ss pin. (2) bring v cc to more than 2.7v, and wait at least 2msec. (internal power supply stable waiting time) (3) apply an "h" signal to the cnv ss pin. ____________ (4) apply an "h" signal to the reset pin. when the cnv ss pin is h and reset pin is l , p6 7 pin is connected to the pull-up resister.
page 322 19. usage precaution 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 19.15 noise connect a bypass capacitor (approximately 0.1 f) across the v cc and v ss pins using the shortest and thicker possible wiring. figure 19.4 shows the bypass capacitor connection. m16c/26a group (m16c/26a, m16c/26t) bypass capacitor connecting pattern connecting pattern vss vcc figure 19.4 bypass capacitor connection
page 323 19. usage precaution 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m 19.16 instruction for a device use when handling a device, extra attention is necessary to prevent it from crashing during the electrostatic discharge period.
appendix 1. package dimensions page 324 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m appendix 1. package dimensions lqfp48-p-77-0.50 weight(g) jedec code eiaj package code lead material cu alloy 48p6q-a plastic 48pin 7 ? 7mm body lqfp 0.1 0.2 symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.225 i 2 1.0 m d 7.4 m e 7.4 8 0 0.1 1.0 0.65 0.5 0.35 9.2 9.0 8.8 9.2 9.0 8.8 0.5 7.1 7.0 6.9 7.1 7.0 6.9 0.175 0.125 0.105 0.27 0.22 0.17 1.4 0 1.7 e e e h e 1 48 37 24 25 36 12 13 h d d m d m e a f y b 2 i 2 recommended mount pad a 1 a 2 l 1 l detail f lp a3 c lp 0.45 0.6 0.25 0.75 0.08 x a3 e b x m recommended ssop42-p-450-0.80 weight(g) CC jedec code eiaj package code lead material cu alloy+42 alloy 42p2r-e plastic 42pin 450mil ssop symbol min nom max a a 2 b c d e l l 1 y dimension in millimeters h e a 1 i 2 C C .25 0 .05 0 .13 0 .3 17 .2 8 C .63 11 .3 0 C C C .27 1 C C .0 2 .3 0 .15 0 .5 17 .4 8 .8 0 .93 11 .5 0 .765 1 C .43 11 C .4 2 C C .4 0 .2 0 .7 17 .6 8 C .23 12 .7 0 C .15 0 C b 2 C .5 0 C C 0 C 10 e e 1 e b 2 e 1 i 2 recommended mount pad C C z 1 0.75 C C 0.9 z recommended 42 22 21 1 h e e e y f a a 2 a 1 l 1 l c detail f g b d detail g z z 1
appendix 2. functional difference page 325 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m appendix 2. functional difference appendix 2.1 differences between m16c/26a and m16c/26t item m16c/26a m16c/26t main clock during oscillating stoped and after reset (default value 0 while and after the (default value 1 while and after the cm05 bit is reset.) cm05 bit is reset.) voltage detection available not available circuit (vcr1 register, vcr2 register, (reserve register) (function of 0019 16 , d4int register) 001a 16 , 001f 16 ) cold start/warm start available not available detection function wdc5 bit in thewdc register package 48p6q, 42p2r 48p6q note. since the emulator between the m16c/26a and m16c/29 group are same, all functions of m16c/29 are built in the emulator. when evaluating m16c/26a group, do not access to the sfr which is not built in m16c/26a group. refer to hardware manual about detail and electrical characteristics.
appendix 2. functional difference page 326 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m appendix 2.2 differences between m16c/26a and m16c/26 item m16c/26a m16c/26 clock generation 4 circuits (main clock oscillation circuit, 3 circuits (main clock oscillation circuit, circuit sub clock oscillation circuit, sub clock oscillation circuit, on-chip oscillator, on-chip oscillator) pll frequency synthesizer) system clock on-chip oscillator main clock source after reset (initial value "1" of cm21 bit) (initial value "0" of cm21 bit) (initial value of the cm21 bit in the cm2 register) on-chip oscillator clock selectable (8mhz/1mhz/500khz) fixed (1mhz) pacr2 to pacr0 in necessary to set after reset no pacr register the pacr register 48pin:"100 2 ", 42pin:"001 2 " ifsr20 bit in the necessary to set to "1" after reset no ifsr2a register ifsr2a register external interrupt ________ 8 causes (int2 added) 7 causes 13 pin (48-pin version) ________ p8 4 /int2/zp iv cc function p7 0 , p7 1 n-ch open drain output and cmos n-ch open drain output output are selectable by s/w a/d input pin 12 channels 8 channels (48-pin version) a/d operation mode 8 modes (single, repeat, single sweep, 5 modes (single, repeat, single sweep, repeat sweep mode 0, repeat sweep repeat sweep mode 0, repeat sweep mode 1, simultaneous sampling, mode 1) delayed trigger mode 0, delayed trigger mode 1) 1 shunt current measurement function is available timer b operation 5 modes (timer, event counter, pulse 4 modes (timer, event counter, pulse mode periods measurement, pulse width periods measurement, pulse width measurment, a/d trigger) measurment) 1 shunt current measurement function is available crc calculation available (compatible to crc-ccitt not available and crc-16 methods) three-phase motor ? waveform output/switching port output ? waveform output/switching port output control by software is enabled by software is disabled ? position data retention function ? no position data retention function digital debounce _______ _____ this function is in the nmi/sd pin and not available function ________ int5 pin 3 pin (48-pin version) p9 0 /clk out /tb0 in /an3 0 p9 0 /tb0 in function (clk out : f1, f8, f32, and f c output) uart1 compatible switching to p6 4 to p6 7 or p7 0 to p7 3 p6 4 to p6 7 pin is enabled flash memory protection to blocks 0, 1 by fmr02 bit protection to blocks 0,1 by fmr02 bit protect function protection to the blocks 0 to 3 by fmr16 bit package 48p6q, 42p2r 48p6q note. since the emulator between the m16c/26a and m16c/29 group are same, all functions of m16c/29 are built in the emulator. when evaluating m16c/26a group, do not access to the sfr which is not built in m16c/26a group. refer to hardware manual about detail and electrical characteristics.
register index page 327 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m register index a ad0 to ad7 179 adcon0 to adcon2 177, 182, 184, 186, 188, 190, 192 adstat0 179 adtrgcon 178, 193, 199, 205 aier 73 c cm0 34 cm1 35 cm2 36 cpsrf 91 , 105 crcd 209 crcin 209 crcmr 209 crcsar 209 d d4int 26 dar0 81 dar1 81 dm0con 80 dm0sl 79 dm1con 80 dm1sl 80 dtt 116 f fmr0 236 fmr1 236 fmr4 237 i icctb2 116 ictb2 117 idb 116 idb0 116 ifsr 62 , 70 ifsr2a 62 interrupt control 61 invc0 114 invc1 115 n nddr and p17ddr 222 o onsf 91 p p0 to p13 219 pacr 134 , 221 pclkr 37 pcr 221 pd0 to pd13 218 pdrf 124 pfcr 126 plc0 38 pm0 31 pm1 31 pm2 37 prcr 54 pur0 to pur2 220 r rmad0 73 rmad1 73 rocr 35 romcp 231 s sar0 81 sar1 81 t ta0 to ta4 90 ta0mr to ta4mr 89 ta11 117 ta1mr 120 ta2 117 ta21 117 ta2mr 120 ta2mr to ta4mr 96 ta4 117 ta41 117 ta4mr 120
register index page 328 8 2 3 f o 5 0 0 2 , 5 1 . r a m 0 0 . 1 . v e r 0 0 1 0 - 2 0 2 0 b 9 0 j e r ) t 6 2 / c 6 1 m , a 6 2 / c 6 1 m ( p u o r g a 6 2 / c 6 1 m tabsr 90 , 105 , 119 taimr 94 , 101 tb0 to tb5 105 tb0mr to tb5mr 104 tb2 119 tb2mr 120 tb2sc 118, 180 tcr0 81 tcr1 81 timer ai mode 92 tprc 126 trgsr 91, 119 u u0brg to u2brg 131 u0c0 to u2c0 133 u0c1 to u2c1 134 u0mr to u2mr 132 u0rb to u2rb 131 u0tb to u2tb 131 u2smr 135 u2smr2 135 u2smr3 136 u2smr4 136 ucon 133 udf 90 v vcr1 26 vcr2 26 w wdc 75 wdts 75
revision history m16c/26a hardware manual rev. date description page summary c-1 0.51 feb/ 01/ 04 2 note 2 in table 1.1 is revised. 3 note 2 in table 1.2 is revised. 10 table 1.6 is revised. 39 the section ?.3 ring oscillator clock?is revised. 58 the section ?.3 interrupt control?is revised. 60 figure 9.3.2 is added. ifsr2a register is revised. 68 ______ the section ?.6 int interrupt?is revised. ifsr2a register in figure 9.6.1 is deleted. 69 _______ the section ?.7 nmi interrupt?is revised. 72 the section ?0. watchdog timer?is revised. 81 table 11.2.2 is revised. 100 the section ?2.2 timer b?is revised. figure 12.2.2 is revised. 102 figure 12.2.2.1 is revised. 107 figure 12.2.4.2 is revised. 114 figure 12.3.6 is revised. 122 the section ?3. serial i/o?is revised. 124 figure 13.1.2 is revised. 149 table 13.1.3.3 is revised. 161 table 13.1.5.1 is revised. 168 to 201 the chapter 14 is revised. 202 the section 15 is revised. 205 the section ?6. programmable i/o port?is revised. 206 the section ?6.6 digital debounce function?is revised. 216 figure 16.6.1 is revised. 222 table 17.4 and note 5, 7 are revised. 241 table 17.41 and note 5, 7 are revised. 260 table 17.78 and note 5, 7 are revised. 271 the section 18.2 is revised. 277 note 2 in table 18.4.1 is revised. 297 figure 18.9.3 is revised. 302 the chapter 20 is revised. 0.51a mar/09/04 120 figure 12.3.1.2.1 and the section 12.3.1.2.4 are partly revised. 0.70 april/08/04 1 the section ?. overview?is partly revised. 2,3 table 1.1 and 1.2 are partly revised. 6 the section ?.4 product list?is partly revised. 8,9 figure 1.3 to 1.5 are partly revised. 11 table 1.7 is partly revised. 14 the chapter ?. memory?is partly revised. note 2 in figure 3.1 is added. 15 the chapter ?. special function register?is partly revised.
revision history m16c/26a hardware manual rev. date description page summary c-2 24 the section ?.5 voltage detection curcuit?is partly revised. figure 5.5.1 and 5.5.2 are partly revised. 25 vcr1 register and vcr2 register in figure 5.5.3 are partly revised. 26 figure 5.5.4 is partly revised. 27 the section ?.5.1 voltage detection interrupt?is partly revised. 28 figure 5.5.1.1.2.1 is partly revised. 29 figure 6.2 is partly revised. 32 figure 7.2 is partly revised. 33 figure 7.3 is partly revised. 34 figure 7.5 is partly revised. 35 processer mode register 2 in figure 7.6 is partly revised. 37 the section ?.1 main clock?is partly revised. 40 figure 7.4.1 is partly revised. 41 the section ?.5 cpu clock and peripheral function clock?and ?.5.2 peripheral function clock?are partly revised. 49 the section ?.7 system clock protective function?and ?.8 oscillation stop and re-oscillation detect function?are partly revised. 60 ifsr2a register in figure 9.3.2 is partly revised. 62 the section ?.4 interrupt sequence?is partly revised. 63 the section ?.4.1 interrupt response time?and figure 9.4.1.1 are partly revised. 89 table 12.1.1.1 is partly revised. 97 table 12.1.4.1 is partly revised. 100 setction 12.2. timer b?is partly revised. 101 the timer bi register in figure 12.2.3 is partly revised. 106 the section ?2.2.4 a-d trigger mode?and table 12.2.4.1 are partly revised. 107 figure 12.2.4.1 and 12.2.4.2 are partly revised. 110 figure 12.3.2 is partly revised. 112 ?timer b2 interrupt occurrences frequency set counter?in figure 12.3.4 is partly revised. 114 figure 12.3.6 is partly revised. 117 figure 12.3.9 pfcr register and tprc register is deleted. 121 the section ?3.3.2 three-phase/port output switch function? figure ?2.3.2.1 usage example of three-phse/port output switch function?and figure ?2.3.2.2 pfcr register and tprc register?are added. 130 ?art 2 special mode register 2?in figure 13.1.8 is partly revised. 131 ?art 2 special mode register 3?in figure 13.1.9 is partly revised. 134 table 13.1.1.2 is partly revised. 141 table 13.1.2.2 is partly revised. 149 figure 13.1.3.1 is partly revised.
revision history m16c/26a hardware manual rev. date description page summary c-3 169 table 14.1 is partly revised. 172 figure 14.4 is partly revised. 173 figure 14.5 is partly revised. 178 the section ?4.1.3. single sweep mode?is partly revised. 184 the section ?4.1.6 simultaneous sample sweep mode?is partly revised. 187 the section ?4.1.7 delayed trigger mode 0?and table 15.1.7.1 are partly revised. 188 figure 14.1.7.1 is revised. 189, 190 figure 14.1.7.2 and 14.1.7.3 are revised 191 figure 14.1.7.3 is deleted. 192 figure 14.1.7.6 is partly revised. 193 the section ?4.1.8 delayed trigger mode 1?and table 15.1.8.1 are partly revised. 195, 196 figure 14.1.8.2 and 14.1.8.3 are partly revised. 200 figure 14.5.1 is partly revised. 202 the chapter ?5. crc calculation circuit?is partly revised. 204 figure 15.3 is partly revised. 205 the chapter ?6. programmable i/o ports?is partly revised. 206 the section ?6.5 pin assignment control register(pacr)?is partly revised. 214 ?ull-up control register 2?in figure 16.3.1 is partly revised. 222 table 17.4 and 17.5 are revised partly revised. note 6 and 10 are partly revised. 223 note 3 in table 17.6 is added. 241 table 17.41 and 17.42 are revised partly revised. note 10 is partly revised. 242 note 3 in table 17.43 is added. 257 to 268 the section ?7.3 v version?is deleted. 269 table 18.1 is partly revised. 270 to 227 setction ?8.2. memory map?and figure18.2.3 and 18.2.4 are revised. 280 ?fmr17 bit?in the section 18.5.2 is partly revised. 269 to 300 chapter ?8. flash memory version?is revised. 302 capter ?0 difference between m16c/26a and m16c/27?is partly revised. 1.00 mar/15/05 all pages word standardized (on-chip oscillator, a/d) 1 m16c/26t?in ?. overview?is added. 2,3 table 1.1 and table 1.2 are revised. 6 ?.4 product list?and table 1.3 to 1.5 are revised. 7 ?om/ram capacity?and ?roduct code? in figure 1.3 are partly revised. table 1.6 is added. 8 figure 1.4 marking diagram?is added. 9, 10 the 24 and 25 pin in figure 1.5 and the 27 and 28 pin in figure 1.6 are revised. 11 ?ower supply input?in talbe 1.6 is revised. ?/o port p6?and /o port p7?are partly revised. 12 ?/o prot p9?is partly revised.
revision history m16c/26a hardware manual rev. date description page summary c-4 15 ?. memoty?is partly revised. the size of internal rom in figure 3.1 is revised. 16 to 21 ?. special function register?is change from ??to ?? 16 register name of d4int register is revised. note 2 and 3 in table 4.1 are revised. 19 the after reset of idb0 and icb1 register are revised. 21 the after reset of adtrgcon and pd9 are revised. 22 ?.1.2 hardware reset 2?is added ?ote? and partly revised. 23 ?.4 oscillation stop detection reset?is partly revised. 25 ?.5 voltage detection circuit?is added ?ote? and partly revised. figure 5.5.1 is revised. figure ?dc register?is deleted. 26 the vc25 bit in ?cr2 register?in figure 5.5.2 is deleted. 27 figure 5.5.3 is revised. 28 to 30 ?.5.1 voltage down detection interrupt? ?.5.2 limitations on exiting stop mode and ?.5.3 limitations exiting wait mode?are revised. 31 figure 6.2 is partly revised. 32 ?scillator status after reset?in table 7.1 is partly revised. 33 figure 7.1 is partly revised. 34 the after reset value of ?m0 register?is revised. 35 the bit 7 to 4 in figure 7.4 is revised. 37 note 2 and note 4 in pm2 register is revised. 39 7 line in ?.1 main clock?is added. 41 ?.3 on-chip oscillator clock?is revised. 42 figure 7.4.1 is partly revised. 45 ?.6.1.6 on-chip oscillator mode?is partly revised. 46 table 7.6.2.3.1 is added. 48 figure 7.6.1 is partly revised. 49 notes in figure 7.6.1.1 is revised. 54 note in ?. protection?is added. ?ddr register?in ?. protection?and figure 8.1 is added. 55 note in ?. interrupt?is added. 58 note 2 in table 9.2.1.1 is added. 64 note 2 in figure 9.4.1 is added. 68 ?atchdog timer?in figure 9.5.1 is added. 74 ?0. watchdog timer?is partly revised. figure 10.1 is partly revised. 75 note 3 of wdc register in figure 10.2 is added. 76 ?0.2 cold start/warm start?is added. 77 note in ?1. dmac?is added. 83 figure 11.1.1 is partly revised. 87 note in ?2. timers?is added. 91 trgsr register in figure 12.1.4 is revised. 94 ?ormal processing operation?in table 12.1.2.2 is partly revised.
revision history m16c/26a hardware manual rev. date description page summary c-5 100 ?ount start condition?in table 12.1.4.1 is patly revised. 112 ?otes?of table 12.3.1 is revised. 113 figure 12.3.1 is partly revised. 114 the function of inv00 bit and note 1,3, 5, 6 in figure 12.3.2 are partly revised. 115 the function in inv13 bit is revised. note 2 is added. 116 reset value of ?hree-phase output buffer register?in figure 12.3.4 is revised. 117 note 6 in figure 12.3.5 is revised. 120 figure 12.3.9 is partly revised. 125 note in figure 12.3.2.1 is added. 127 note in ?3. serial i/o?is added. ?3.1 uarti(i=0 to 2)?is partly revised. 128 to 130 figure 13.1.1 to figure 13.1.3 are partly revised. 131 note 2 in uirb register and note 1 in uibrg register are revised. 132 function of smd2 to smd0 bits and note 3 in u2mr register are revised. 133 note 5 and 6 in uic0 register are added. note 2 in ucon register is added. 134 pacr register is added in figure 13.1.7. 137 ?ransfer clock?in table 13.1.1.1 is partly revised. ?art 1 pin remapping selection?in select function is added. 138 function of rcsp bit in table 13.1.1.2 is partly revised. 139 ?xdi?in table 13.1.1.3 is partly revised. note 1 in table 13.1.1.3 and table 13.1.1.4 are added. 140 the comment of fext in figure 13.1.1.1 is added. 141 ?3.1.1.1 counter measure for communication error occurs?is added. 143 note 2 in figure 13.1.1.6.1 is added. 144 note 1 in figure 13.1.1.7.1 is added. 145 ?ransfer clock?in table 13.1.2.1 is partly revised. ?art 1 pin remapping selection?in select function is added. 146 function of rcsp bit in table 13.1.2.2 is partly revised. 147 ?xdi?in table 13.1.2.3 is partly revised. note 1 in table 13.1.2.3 and table 13.1.2.4 are added. 149,150 ?3.1.2.1 bit rates?and ?3.1.2.2 counter measure for communication error occurs?is added. 152 note 1 in figure 13.1.2.6.1 is added. 153 ?ransfer clock?in table 13.1.3.1 is partly revised. 163 ?ransfer clock?in table 13.1.4.1 is partly revised. 165 ?form?in table 13.1.4.2 is revised. 169 figure 13.1.5.1 is partly revised. 170 ?ransfer clock?in table 13.1.6.1 is partly revised. 175 note in ?4. a/d converter?is added.?ntegral nonlinearity error?in table 14.1 is partly revised. 206 ?4.2 sample and hold?is partly revised. 206, 207 ?4.5 analog input pin and external sensor equivalent circuit example?and ?4.6 precautions of using a/d converter?are deleted. ?4.5 output impedance of sensor under a/d conversion?is added.
revision history m16c/26a hardware manual rev. date description page summary c-6 209 ?fter reset?of crcsar register in figure 15.2 is revised. 211 note in ?6. programmable i/o ports?is added. 211 ?6.3 pull-up control register 0 to pull-up control register 2?is added p6 7 . 212 ?6.5 pin assignment cotrol register?is added ?16c/26t? prc2 bit is revised. ?6.6 digital debounce function?is partly revised. (inpc17 is added.) 214 p77, p90 to p92 in figure 16.2 is partly revised. 218 the after reset of pd9 register in figure 16.1.1 is revised. 221 note 1 in figure 16.5.1 is revised. 222 note in nddr register and p17ddr register is added. 224 note 5 in table 16.1 is added. 225 to 293 ?lash memory version?and ?lectrical characteristics?are exchanged. 225 ?rase block?and ?rogream/erase endurance?in table 17.1 are revised. 227 ?7.2 memory map?is partly revised. 232 ?7.4 cpu rewrite mode?is partly revised. note2 in table 17.4.1 is partly revised. 234 ?7.5.1 flash memory control register 0?is partly revised. 236 the after reset of fmr0 register and note 3 of fmr1 register in figure 17.5.1 is revised. 239 figure 17.5.1.3 is partly revised. 240 the fmr16 bit in ?7.6.4 how to access?is added. 241 ?7.6.9 stop mode?is partly revised. 244 ?7.7.6 block erase?is partly revised. 250 table 17.9.1 and note 2 is partly revised. 251, 252 figure 17.9.1 and figure 17.9.2 are partly revised. 253, 254 figure 17.9.2.1 and figure 17.9.2.2 are partly revised. 256 the condition of ?d?in table 18.1 is revised. flash program erase of ?opr?is added. 257 table 18.2 is modified. 258 measuring condition in table 18.3 is partly revised. 259 table 18.4 and table 18.5 are added ? ps ?and ?d(sr-es)? note 3 and note 8 are revised. 260 table 18.6, table 18.7 and ?ower supply circuit timing diagram? are modified. 261 the ?ysteresis x in ?in table 18.8 is added. 262 table 18.9 is revised. 266 ?in input?in figure 18.1 is added. 268 the ?ysteresis x in ?in table 18.23 is added. note 1 is partly revised. 269 table 18.24 is revised. 273 ?in input?in figure 18.3 is added. 275 the condition of ?d?in table 18.38 is revised. flash program erase of ?opr?is added. 276 table 18.39 is partly revised. 277 ?olerance level impedance?in table 18.40 is added. 278 table 18.41 and table 18.42 are added ? ps ?and ?d(sr-es)? note 3 and 8 are revised. 279 table 18.43 and ?ower supply circuit timing diagram? are revised.
revision history m16c/26a hardware manual rev. date description page summary c-7 280 the ?ysteresis x in ?in table 18.44 is added. note 1 is partly revised. 281 table 18.45 is revised. 285 ?in input?in figure 18.5 is added. 287 the ?ysteresis x in ?in table 18.59 is added. note 1 is partly revised. 288 table 18.60 is revised. 292 ?in input?in figure 18.7 is added. 294 to 323 chapter ?9. usage precaution?is added. 296 the title of figure 19.2 is partly revised. 297, 298 ths subsection 3, 4, 5 and 6(a) are revised. 300 _______ the subsection 1 in ?9.6.3 the nmi interrupt?is partly revised. 301 the title of ?9.6.4?is partly revised. 302 the last 2 lines in ?9.6.6 rewrite the interrupt control register?is partly revised. 305, 306 the subsection 2 in ?9.8.1.1 timer a (timer mode)?and ?9.8.1.2 timer a (event counter mode)?are revised. 307 ?9.8.1.3 timer a (one-shot timer mode)?is partly revised. 309, 310 the subsection 2 in ?9.8.2.1 timer b (timer mode)?and ?9.8.2.2 timer b (event counter mode)?are revised. 311 the subsection 6 and 7 in ?9.8.2.3 timer b ( pulse period/pulse width measurement mode ) are partly revised. 312 the subsection 1 in ?9.9.1 transmission/reception?is partly revised. 314 the subsection 1, 2 and 5 in ?9.9.3 reception?is partly revised. 316, 317 the subsection 2 and 10 in ?9.11 a/d converter?are partly revised. 318 the subsection 3 in ?9.12 programmalbe i/o ports?is partly revised. 319 ?9.13 electric characteristic differences between mask rom and flash memory version microcomputers and ?9.14.2 reserve bit are partly revised. 320 ?9.15.1 function to inhibit rewriting flash memory?is partly revised. 321 the title of ?9.15.8?is revised. ?9.15.10 how to access?is revised. 322 ?9.15.13 regarding programming/erasure times and execution time? ?9.15.14 definition of programming/erasure times?and ?9.15.16 boot mode?are partly revised. 325 ?ppendix 2.1 differences between m16c/26a and m16c/26t?is added. 275 ?perating ambient temperature?in table 18.38 is revised. 276, 277 table 18.39 and 18.40 are partly revised. 278 table 18.41 and 18.42 are partly revised. 279 figure of timing is revised. 281 table 18.45 is partly revised. 284 table 18.57 is partly revised. 287, 288 table 18.59 and 18.60 are partly revised.
revision history m16c/26a hardware manual rev. date description page summary c-8 288 tabl 18.60 is revised. 294 table 18.72 is partly revised. 296 the max values of ?ower supply ripple rising/falling gradient?are revised.
m16c/26a group(m16c/26a,m16c/26t) hardware manual publication data : rev.0.51 feb 01, 2004 rev.1.00 mar 15, 2005 published by : sales strategic planning div. renesas technology corp. ? 2005. renesas technology corp., all rights reserved. printed in japan.
m16c/26a group (m16c/26a,m16c/26t) hardware manual 2-6-2, ote-machi, chiyoda-ku, tokyo, 100-0004, japan

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