32 mega bit cmos sram dp3s1mx32py5 ad vanced in for ma tion de scrip tion: the dp3s1mx32py5 is a 1m x 32 sram module that utilizes the new and innovative space saving tsop stacking technology. the module is constructed of two 1m x 16 sram?s that are configured as a 1m x 32. the dp3s1mx32py5 module features high speed access times with common data inputs and outputs. fea tures: ? organizations available: 1m x 32 ? access times: 10*, 12, 15, 20ns ? 3.3 0.3** volt power requirement ? fully static operation - no clock or refresh required ? ttl-compatible inputs and outputs ? 80-pin surface mount lp-stack ? * 0-70 only. ** 5% for 10ns only. 1 30a244-00 rev. a pin-out di a gram func tional block di a gram pin names a0 - a19 address inputs i/o0 - i/o31 data input/output cs stack enable we write enable oe output enable bs 0 byte select i/o0 - i/o7 bs 1 byte select i/o8 - i/o15 bs 2 byte select i/o16 - i/o23 bs 3 byte select i/o24 - i/o31 v dd power (+3.3v) v ss ground nu. not usable 2mx8/1mx16/512kx32, 12 - 20ns, surface mount 30a244-00 a this document contains information on a product under consideration for development at dense-pac microsystems, inc. dense-pac reserves the right to change or discontinue information on this product without prior notice.
dp3s1mx32py5 dense-pac microsystems, inc. ad vanced in for ma tion 2 30a244-00 rev. a recommended operating range 4 symbol characteristic min. typ. max. unit v dd supply voltage 10ns 3.135 3.3 3.465 v 12, 15, 20ns 3.0 3.3 3.6 v ih input high voltage 2.0 v dd +0.3 3 v v il input low voltage -0.3 2 0.8 v t a operating temperature c 0 +25 +70 o c ci -40 +25 +85 dc output characteristics symbol parameter conditions min. max. unit v oh high voltage i oh = -2ma 2.4 v v ol low voltage i ol =+2ma 0.4 v absolute maximum ratings 4 symbol parameter value unit t stc storage temperature -55 to +125 c t bias temperature under bias -55 to +125 c v dd supply voltage 1 -0.5 to +4.6 v v i/o input/output voltage 1 -0.5 to +4.6 v dc operating characteristics: over operating ranges symbol characteristics test conditions min. max. unit i in input leakage current v in = 0v to v dd , v dd = max. -2 +2 m a i out output leakage current v i/o = 0v to v dd , v dd = max., ce = v ih -1 +1 m a i cc dynamic operating current ce = v il , v dd = max. i out = 0ma, f = f max. 900 ma i sb1 full standby supply current (cmos) f = 0, v in 3 v dd -0.2v or v in v ss +0.2v, ce 3 v dd -0.2v 8 ma i sb2 standby current ( ttl ) ce = v ih , f = f max. 210 ma v ol output low voltage i out = +2.0ma 0.4 v v oh output high voltage i out = -2.0ma 2.4 v capacitance 5 : t a = 25 c, f = 1.0mhz symbol parameter max. unit condition c adr address input 20 pf v in 2 = 0v c ce chip enable 20 c bs byte select 15 c we write enable 20 c oe output enable 20 c i/o data input/output 15 +3.3v 780 w 1200 w c l ** d out figure 1. output load ** including probe and jig capacitance. output load load c l parameters measured 1 30pf except t lz , t hz , t ohz , t olz , and t whz 2 5pf t lz , t hz , t ohz , t olz , and t whz ac test conditions input pulse levels 0v to 3.0v input pulse rise and fall times 2ns input and output timing reference levels 1.5v
dense-pac microsystems, inc. dp3s1mx32py5 ad vanced in for ma tion 3 30a244-00 rev. a ac operating conditions and characteristics - read cycle: over operating ranges no. symbol parameter 10ns 12ns 15ns 20ns unit min. max. min. max. min. max. min. max. 1 t rc read cycle time 10 12 15 20 ns 2 t aa address access time 10 12 15 20 ns 3 t co ce to output valid 10 12 15 20 ns 4 t oe output enable to output valid 5 6 8 9 ns 5 t ba byte enable access time 5 6 8 9 ns 6 t lz ce to output in low-z 5, 6 3 3 3 3 ns 7 t olz output enable to output in low-z 5, 6 1 1 1 1 ns 8 t blz byte enable to output in low-z 1 1 1 1 ns 9 t hz ce to output in high-z 5, 6 6 7 8 9 ns 10 t ohz output enable to output in high-z 5, 6 6 7 8 9 ns 11 t bhz byte enable to output in high-z 6 7 8 9 ns 12 t oh output hold from address change 3 3 3 3 ns truth table mode cs oe we bs 0 bs 1 bs 2 bs 3 i/o0- i/o7 i/o8- i/o15 i/o16- i/o23 i/o24- i/o31 supply current read l l h l l l l d out d out d out d out active h l l l high-z d out d out d out l h l l d out high-z d out d out l l h l d out d out high-z d out l l l h d out d out d out high-z write l x l l l l l d in d in d in d in active h l l l high-z d in d in d in l h l l d in high-z d in d in l l h l d in d in high-z d in l l l h d in d in d in high-z output data l h h x x x x high-z high-z high-z high-z active l x x h h h h high-z high-z high-z high-z standby h x x x x x x high-z high-z high-z high-z standby h = high l = low x = don?t care ac operating conditions and characteristics - write cycle 7, 8 : over operating ranges no. symbol parameter 10ns 12ns 15ns 20ns unit min. max. min. max. min. max. min. max. 13 t wc write cycle time 10 12 15 20 ns 14 t aw address valid to end of write 8.5 9 11 15 ns 15 t cw chip enable to end of write 8.5 9 11 15 ns 16 t bw byte enable to end of write 8.5 9 11 15 ns 17 t as address set-up time * 0 0 0 0 ns 18 t wp write pulse width ( oe high) 7 8 10 12 ns 19 t wr write recovery time, ce , we 0 0 0 0 ns 20 t whz write enable to output in high-z 5, 6 6 7 8 10 ns 21 t dw data to write time overlap 6 7 8 10 ns 22 t dh data hold from write time 0 0 0 0 ns 23 t ow output active from end of write 1 1 1 1 ns * valid for both read and write cycles.
dp3s1mx32py5 dense-pac microsystems, inc. ad vanced in for ma tion 4 30a244-00 rev. a write cycle 1: we con trolled. read cycle address ce oe bs 0 - bs 3 data out address we ce bs 0 - bs 3 data in data out
dense-pac microsystems, inc. dp3s1mx32py5 ad vanced in for ma tion 5 30a244-00 rev. a write cycle 2: ce con trolled. write cycle 3: ub , lb con trolled. address we ce bs 0 - bs 3 data in data out address we ce bs 0 - bs 3 data in data out
dp3s1mx32py5 dense-pac microsystems, inc. ad vanced in for ma tion 6 30a244-00 rev. a me chan i cal drawing or dering in for ma tion dense-pac microsystems, inc. 7321 lincoln way, garden grove, california 92841-1431 (714) 898-0007 u (800) 642-4477 u fax: (714) 897-1772 u http :// www .dense-pac.com notes: 1. all voltages are with respect to v ss . 2. -1.5v min. (pulse width 4ns) for i 20ma. 3. v ih (max.)=v dd +1.5vdc (pulse width 4ns) for i 20ma. 4. stresses greater than those under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 5. this parameter is guaranteed and not 100% tested. 6. transition is measured at the point of 500mv from steady state voltage. 7. when oe and ce are low and we is high, i/o pins are in the output state,and input signals of opposite phase to the outputs must not be applied. 7. the outputs are in a high impedance state when we is low. 9. chip enable and write enable can initiate and terminate write cycle.
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