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im[s/h]h1gp03a1f1c im[s/h]h2gp[13/02]a1f1c im[s/h]h4gp[23/12]a1f1c 240-pin ddr3 registered modules with parity bit 1gbyte, 2gbyte and 4gbyte rohs compliant advance internet data sheet rev. 0.51 january 2008
advance internet data sheet ddr3 registered dimm im[s/h]h[1g/2g/4g]pxxa1f1c qag_techdoc_a4, 4.20, 2008-01-25 2 12122007-wj2l-rgdp we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc@qimonda.com im[s/h]h1gp03a1f1c, im[s/h]h2gp[13/ 02]a1f1c, im[s/h]h4gp[23/12]a1f1c revision history: 2008-01, rev. 0.51 page subjects (major chang es since last revision) all added product types and related information for modules with heat spreader. previous revision: 2007-12, rev. 0.5 all data sheet for 1gb, 2gb and 4gb registered me mory modules with parity bit product family. ddr3 registered dimm im[s/h]h[1g/2g/4g]pxxa1f1c advance internet data sheet rev. 0.51, 2008-01 3 12122007-wj2l-rgdp 1overview this chapter gives an overview of the 240?pin registered ddr3 dual-in-line memory modules product family with parity bit for address and control bus and describes its main characteristics. 1.1 features ? 240-pin 8-byte ddr3 sdram registered dual-in-line memory modules with parity bit for address and control bus. ? module organization: one rank ? 128m 72, 256m 72, two rank ? 256m 72, 512m 72 , four rank ? 512m 72 chip organization: 128m 8, 256m 4 ? pc3-10600, pc3-8500 and pc3-6400 module speed grades. ? 4gb, 2gb, 1gb modules built with 1gb ddr3 sdrams in packages pg-tfbga-78 ? ddr3 sdrams with a single 1.5 v ( 0.075 v) power supply. ? asynchronous reset. ? programmable cas latency, cas write latency, additive latency, burst length and burst type. ? on-die-termination (odt) and dynamic odt for improved signal integrity. ? refresh. self refresh and power down modes. ? zq calibration for output driver and odt. ? system level timing calibration support via write leveling and multi purpose register (mpr) read pattern. ? serial presence detect with eeprom. ? on-dimm thermal sensor. ? rdimm dimensions: 133.35 mm x 30 mm. ? based on standard reference raw ca rds: 'a', 'b', 'c', 'e' and 'h' ? rohs compliant products 1) . table 1 performance table for ddr3?1600 and ddr3?1333 1) rohs compliant product: restriction of the use of certain hazar dous substances (rohs) in el ectrical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include m ercury, lead, cadmium, hexavalent chromium, polybro minated biphenyls and polybrominated biphenyl ethers. qimonda speed code ?13g ?13h unit note 1) 1) the available cl and cwl settings depend on t he sdram device speed bin. the cl setti ng and cwl setting result in maximum but also minimum clock frequency re quirements. when making a selecti on of operating clock frequency, bot h need to be fulfilled: requirem ents from cl setting as well as requirements from cwl setting. for details, refer to chapter 4.1 speed bins. module speed bin pc3 ?10600g ?10600h device speed bin ddr3 ?1333g ?1333h cl- n rcd - n rp 8-8-8 9-9-9 cl and cwl settings for maximum clock frequency cl = 8 cwl = 7 cl = 9 cwl = 7 mhz maximum clock frequency and data rate with above cl and cwl settings 667 1333 667 1333 mhz mb/s minimum clock frequency and data rate with above cl and cwl settings 533 1066 533 1066 mhz mb/s ddr3 registered dimm im[s/h]h[1g/2g/4g]pxxa1f1c advance internet data sheet rev. 0.51, 2008-01 4 12122007-wj2l-rgdp table 2 performance table for ddr3?1066 and ddr3?800 qimonda speed code ?10f ?10g ?08d ?08e unit note 1) 1) the available cl and cwl settings depend on t he sdram device speed bin. the cl setti ng and cwl setting result in maximum but also minimum clock frequency re quirements. when making a selecti on of operating clock frequency, bot h need to be fulfilled: requirem ents from cl setting as well as requirements from cwl setting. for details, refer to chapter 4.1 speed bins. module speed bin pc3 ?8500f ?8500g ?6400d ?6400e device speed bin ddr3 ?1066f ?1066g ?800d ?800e cl- n rcd - n rp 7-7-7 8-8-8 5-5-5 6-6-6 cl and cwl settings for maximum clock frequency cl = 7 cwl = 6 cl = 8 cwl = 6 cl = 5 cwl = 5 cl = 6 cwl = 5 mhz maximum clock frequency and data rate with above cl and cwl settings 533 1066 533 1066 400 800 400 800 mhz mb/s minimum clock frequency and data rate with above cl and cwl settings 400 800 400 800 300 600 300 600 mhz mb/s ddr3 registered dimm im[s/h]h[1g/2g/4g]pxxa1f1c advance internet data sheet rev. 0.51, 2008-01 5 12122007-wj2l-rgdp 1.2 description the qimonda im[s/h]h[1 g/2g/4g]pxxa1f1c are registered dimm (pdimm) family with parity bit for address and control bus and 30 mm height based on ddr3 sdram technology. dimms are available in 128m 72 (1gb), 256m 72 (2gb), 512m 72 (4gb) organization and density, intended for mounting into 240 pin connector sockets. the memory array is designed with 1gb double data rate (ddr3) synchronous drams. all control and address signals are re-driven on the di mm using register devices and a pll for the clock distribution. this reduces capacitive loading to the system bus, bu t adds one cycle to the sdram timing. de-coupling capacitors, stub resistors, calibration resistors and termination resistors are mounted on the pcb board. the dimms feature serial presence detect based on a 256 byte serial eeprom device using the 2-pin i2c protocol. the first 176 bytes are programmed with module specific spd data. table 3 product information for modules without heat spreader qimonda part number compliance code description 1024 mbyte registered dimm imsh1gp03a1f1c imsh1gp03a1f1c?08d 1gb 1r8 pc3?6400p?5-xx?a0 2 40-pin 1024 mbyte ddr3 registered dimm with one rank and on-dimm thermal sensor. the memory rank consists of nine ddr3 components in x8 organization. standard reference card a is used on this assembly used ddr3 sdram component part number: idsh1g-03a1f1c density: 1 gbit organization: 128mbit 8 address bits (row/column/bank): 14/10/3 imsh1gp03a1f1c?08e 1gb 1r8 pc3?6400p?6-xx?a0 imsh1gp03a1f1c?10f 1gb 1r8 pc3?8500p?7-xx?a0 imsh1gp03a1f1c?10g 1gb 1r8 pc3?8500p?8-xx?a0 imsh1gp03a1f1c?13g 1gb 1r8 pc3?10600p?8-xx?a0 imsh1gp03a1f1c?13h 1gb 1r8 pc3?10600p?9-xx?a0 2048 mbyte registered dimm imsh2gp13a1f1c imsh2gp13a1f1c?08d 2gb 2r8 pc3?6400p?5-xx?b0 2 40-pin 2048 mbyte ddr3 registered dimm with two ranks and on-dimm thermal sensor. each memory rank consists of nine ddr3 components in x8 organization. standard reference card b is used on this assembly used ddr3 sdram component part number: idsh1g-03a1f1c density: 1 gbit organization: 128mbit 8 address bits (row/column/bank): 14/10/3 imsh2gp13a1f1c?08e 2gb 2r8 pc3?6400p?6-xx?b0 imsh2gp13a1f1c?10f 2gb 2r8 pc3?8500p?7-xx?b0 imsh2gp13a1f1c?10g 2gb 2r8 pc3?8500p?8-xx?b0 imsh2gp13a1f1c?13g 2gb 2r8 pc3?10600p?8-xx?b0 imsh2gp13a1f1c?13h 2gb 2r8 pc3?10600p?9-xx?b0 2048 mbyte registered dimm imsh2gp02a1f1c imsh2gp02a1f1c?08d 2gb 1r4 pc3?6400p?5-xx?c0 2 40-pin 2048 mbyte ddr3 registered dimm with one rank and on-dimm thermal sensor. the memory rank consists of eighteen ddr3 components in x4 organization. standard reference card c is used on this assembly used ddr3 sdram component part number: idsh1g-02a1f1c density: 1 gbit organization: 256mbit 4 address bits (row/column/bank): 14/11/3 imsh2gp02a1f1c?08e 2gb 1r4 pc3?6400p?6-xx?c0 imsh2gp02a1f1c?10f 2gb 1r4 pc3?8500p?7-xx?c0 imsh2gp02a1f1c?10g 2gb 1r4 pc3?8500p?8-xx?c0 imsh2gp02a1f1c?13g 2gb 1r4 pc3?10600p?8-xx?c0 imsh2gp02a1f1c?13h 2gb 1r4 pc3?10600p?9-xx?c0 ddr3 registered dimm im[s/h]h[1g/2g/4g]pxxa1f1c advance internet data sheet rev. 0.51, 2008-01 6 12122007-wj2l-rgdp table 4 product information for modules with heat spreader 4096 mbyte registered dimm imsh4gp23a1f1c imsh4gp23a1f1c?08d 4gb 4r8 pc3?6400p?5-xx?h0 2 40-pin 4096 mbyte ddr3 registered dimm with four ranks and on-dimm thermal sensor. each memory rank consists of nine ddr3 components in x4 organization. standard reference card h is used on this assembly used ddr3 sdram component part number: idsh1g-03a1f1c density: 1 gbit organization: 128mbit 8 address bits (row/column/bank): 14/10/3 imsh4gp23a1f1c?08e 4gb 4r8 pc3?6400p?6-xx?h0 imsh4gp23a1f1c?10f 4gb 4r8 pc3?8500p?7-xx?h0 imsh4gp23a1f1c?10g 4gb 4r8 pc3?8500p?8-xx?h0 imsh4gp23a1f1c?13g 4gb 4r8 pc3?10600p?8-xx?h0 imsh4gp23a1f1c?13h 4gb 4r8 pc3?10600p?9-xx?h0 4096 mbyte registered dimm imsh4gp12a1f1c imsh4gp12a1f1c?08d 4gb 2r4 pc3?6400p?5-xx?e0 2 40-pin 4096 mbyte ddr3 registered dimm with two ranks and on-dimm thermal sensor. each memory rank consists of eighteen ddr3 components in x4 organization. standard reference card e is used on this assembly used ddr3 sdram component part number: idsh1g-02a1f1c density: 1 gbit organization: 256mbit 4 address bits (row/column/bank): 14/11/3 imsh4gp12a1f1c?08e 4gb 2r4 pc3?6400p?6-xx?e0 imsh4gp12a1f1c?10f 4gb 2r4 pc3?8500p?7-xx?e0 imsh4gp12a1f1c?10g 4gb 2r4 pc3?8500p?8-xx?e0 imsh4gp12a1f1c?13g 4gb 2r4 pc3?10600p?8-xx?e0 imsh4gp12a1f1c?13h 4gb 2r4 pc3?10600p?9-xx?e0 qimonda part number compliance code description 1024 mbyte registered dimm imhh1gp03a1f1c imhh1gp03a1f1c?08d 1gb 1r8 pc3?6400p?5-xx?a0 240-pin 1024 mbyte ddr3 registered dimm with one rank and on-dimm thermal sensor. the memory rank consists of nine ddr3 components in x8 organization. standard reference card a is used on this assembly used ddr3 sdram component part number: idsh1g-03a1f1c density: 1 gbit organization: 128mbit 8 address bits (row/column/bank): 14/10/3 imhh1gp03a1f1c?08e 1gb 1r8 pc3?6400p?6-xx?a0 imhh1gp03a1f1c?10f 1gb 1r8 pc3?8500p?7-xx?a0 imhh1gp03a1f1c?10g 1gb 1r8 pc3?8500p?8-xx?a0 imhh1gp03a1f1c?13g 1gb 1r8 pc3?10600p?8-xx?a0 imhh1gp03a1f1c?13h 1gb 1r8 pc3?10600p?9-xx?a0 2048 mbyte registered dimm imhh2gp13a1f1c imhh2gp13a1f1c?08d 2gb 2r8 pc3?6400p?5-xx?b0 240-pin 2048 mbyte ddr3 registered dimm with two ranks and on-dimm thermal sensor. each memory rank consists of nine ddr3 components in x8 organization. standard reference card b is used on this assembly used ddr3 sdram component part number: idsh1g-03a1f1c density: 1 gbit organization: 128mbit 8 address bits (row/column/bank): 14/10/3 imhh2gp13a1f1c?08e 2gb 2r8 pc3?6400p?6-xx?b0 imhh2gp13a1f1c?10f 2gb 2r8 pc3?8500p?7-xx?b0 imhh2gp13a1f1c?10g 2gb 2r8 pc3?8500p?8-xx?b0 imhh2gp13a1f1c?13g 2gb 2r8 pc3?10600p?8-xx?b0 imhh2gp13a1f1c?13h 2gb 2r8 pc3?10600p?9-xx?b0 qimonda part number compliance code description ddr3 registered dimm im[s/h]h[1g/2g/4g]pxxa1f1c advance internet data sheet rev. 0.51, 2008-01 7 12122007-wj2l-rgdp 2048 mbyte registered dimm imhh2gp02a1f1c imhh2gp02a1f1c?08d 2gb 1r4 pc3?6400p?5-xx?c0 240-pin 2048 mbyte ddr3 registered dimm with one rank and on-dimm thermal sensor. the memory rank consists of eighteen ddr3 components in x4 organization. standard reference card c is used on this assembly used ddr3 sdram component part number: idsh1g-02a1f1c density: 1 gbit organization: 256mbit 4 address bits (row/column/bank): 14/11/3 imhh2gp02a1f1c?08e 2gb 1r4 pc3?6400p?6-xx?c0 imhh2gp02a1f1c?10f 2gb 1r4 pc3?8500p?7-xx?c0 imhh2gp02a1f1c?10g 2gb 1r4 pc3?8500p?8-xx?c0 imhh2gp02a1f1c?13g 2gb 1r4 pc3?10600p?8-xx?c0 imhh2gp02a1f1c?13h 2gb 1r4 pc3?10600p?9-xx?c0 4096 mbyte registered dimm imhh4gp23a1f1c imhh4gp23a1f1c?08d 4gb 4r8 pc3?6400p?5-xx?h0 240-pin 4096 mbyte ddr3 registered dimm with four ranks and on-dimm thermal sensor. each memory rank consists of nine ddr3 components in x4 organization. standard reference card h is used on this assembly used ddr3 sdram component part number: idsh1g-03a1f1c density: 1 gbit organization: 128mbit 8 address bits (row/column/bank): 14/10/3 imhh4gp23a1f1c?08e 4gb 4r8 pc3?6400p?6-xx?h0 imhh4gp23a1f1c?10f 4gb 4r8 pc3?8500p?7-xx?h0 imhh4gp23a1f1c?10g 4gb 4r8 pc3?8500p?8-xx?h0 imhh4gp23a1f1c?13g 4gb 4r8 pc3?10600p?8-xx?h0 imhh4gp23a1f1c?13h 4gb 4r8 pc3?10600p?9-xx?h0 4096 mbyte registered dimm imhh4gp12a1f1c imhh4gp12a1f1c?08d 4gb 2r4 pc3?6400p?5-xx?e0 240-pin 4096 mbyte ddr3 registered dimm with two ranks and on-dimm thermal sensor. each memory rank consists of eighteen ddr3 components in x4 organization. standard reference card e is used on this assembly used ddr3 sdram component part number: idsh1g-02a1f1c density: 1 gbit organization: 256mbit 4 address bits (row/column/bank): 14/11/3 imhh4gp12a1f1c?08e 4gb 2r4 pc3?6400p?6-xx?e0 imhh4gp12a1f1c?10f 4gb 2r4 pc3?8500p?7-xx?e0 imhh4gp12a1f1c?10g 4gb 2r4 pc3?8500p?8-xx?e0 imhh4gp12a1f1c?13g 4gb 2r4 pc3?10600p?8-xx?e0 imhh4gp12a1f1c?13h 4gb 2r4 pc3?10600p?9-xx?e0 qimonda part number compliance code description ddr3 registered dimm im[s/h]h[1g/2g/4g]pxxa1f1c advance internet data sheet rev. 0.51, 2008-01 8 12122007-wj2l-rgdp 2 configuration 2.1 pin configuration table 5 pin configuration of ddr3 rdimm - 240 pins pin name eda signal name 1) pin no. pin type buffer type function clock signals ck0 ck0_t 184 i sstl differnetial clock inputs [1:0] ck0 ck0_c 185 i sstl ck1 ck1_t 63 i sstl ck1 ck1_c 64 i sstl control signals cke0 cke0 50 i sstl clock enable [1:0] cke1/nc cke1 169 i sstl odt0 odt0 195 i sstl on-die termination [1:0] odt1/nc odt1 77 i s0 s0_n 193 i sstl chip select [3:0] s1 s1_n 76 i sstl s2 s2_n 79 i sstl s3 s3_n 198 i sstl command signals ras ras_n 192 i sstl row address strobe cas cas_n 74 i sstl column address strobe we we_n 73 i sstl write enable bank address signals ba0 ba0 71 i sstl bank address bus[2:0] ba1 ba1 190 i sstl ba2 ba2 52 i sstl address signals a0 a0 188 i sstl address bus [15:0] a1 a1 181 i sstl a2 a2 61 i sstl a3 a3 180 i sstl a4 a4 59 i sstl ddr3 registered dimm im[s/h]h[1g/2g/4g]pxxa1f1c advance internet data sheet rev. 0.51, 2008-01 9 12122007-wj2l-rgdp a5 a5 58 i sstl address bus [15:0] a6 a6 178 i sstl a7 a7 56 i sstl a8 a8 177 i sstl a9 a9 175 i sstl a10/ap a10 70 i sstl a11 a11 55 i sstl a12/bc a12 174 i sstl a13 a13 196 i sstl a14 a14 172 i sstl a15 a15 171 i sstl data signals dq0 dq0 3 i/o sstl data bus [63:0] dq1 dq1 4 i/o sstl dq2 dq2 9 i/o sstl dq3 dq3 10 i/o sstl dq4 dq4 122 i/o sstl dq5 dq5 123 i/o sstl dq6 dq6 128 i/o sstl dq7 dq7 129 i/o sstl dq8 dq8 12 i/o sstl dq9 dq9 13 i/o sstl dq10 dq10 18 i/o sstl dq11 dq11 19 i/o sstl dq12 dq12 131 i/o sstl dq13 dq13 132 i/o sstl dq14 dq14 137 i/o sstl dq15 dq15 138 i/o sstl dq16 dq16 21 i/o sstl dq17 dq17 22 i/o sstl dq18 dq18 27 i/o sstl dq19 dq19 28 i/o sstl dq20 dq20 140 i/o sstl dq21 dq21 141 i/o sstl dq22 dq22 146 i/o sstl dq23 dq23 147 i/o sstl dq24 dq24 30 i/o sstl dq25 dq25 31 i/o sstl dq26 dq26 36 i/o sstl dq27 dq27 37 i/o sstl pin name eda signal name 1) pin no. pin type buffer type function ddr3 registered dimm im[s/h]h[1g/2g/4g]pxxa1f1c advance internet data sheet rev. 0.51, 2008-01 10 12122007-wj2l-rgdp dq28 dq28 149 i/o sstl data bus [63:0] dq29 dq29 150 i/o sstl dq30 dq30 155 i/o sstl dq31 dq31 156 i/o sstl dq32 dq32 81 i/o sstl dq33 dq33 82 i/o sstl dq34 dq34 87 i/o sstl dq35 dq35 88 i/o sstl dq36 dq36 200 i/o sstl dq37 dq37 201 i/o sstl dq38 dq38 206 i/o sstl dq39 dq39 207 i/o sstl dq40 dq40 90 i/o sstl dq41 dq41 91 i/o sstl dq42 dq42 96 i/o sstl dq43 dq43 97 i/o sstl dq44 dq44 209 i/o sstl dq45 dq45 210 i/o sstl dq46 dq46 215 i/o sstl dq47 dq47 216 i/o sstl dq48 dq48 99 i/o sstl dq49 dq49 100 i/o sstl dq50 dq50 105 i/o sstl dq51 dq51 106 i/o sstl dq52 dq52 218 i/o sstl dq53 dq53 219 i/o sstl dq54 dq54 224 i/o sstl dq55 dq55 225 i/o sstl dq56 dq56 108 i/o sstl dq57 dq57 109 i/o sstl dq58 dq58 114 i/o sstl dq59 dq59 115 i/o sstl dq60 dq60 227 i/o sstl dq61 dq61 228 i/o sstl dq62 dq62 233 i/o sstl dq63 dq63 234 i/o sstl pin name eda signal name 1) pin no. pin type buffer type function ddr3 registered dimm im[s/h]h[1g/2g/4g]pxxa1f1c advance internet data sheet rev. 0.51, 2008-01 11 12122007-wj2l-rgdp cb0 cb0 39 i/o sstl check bit [7:0] check bit input/output pin cb1 cb1 40 i/o sstl cb2 cb2 45 i/o sstl cb3 cb3 46 i/o sstl cb4 cb4 158 i/o sstl cb5 cb5 159 i/o sstl cb6 cb6 164 i/o sstl cb7 cb7 165 i/o sstl dqs0 dqs0_t 7 i/o sstl data strobe signals [8:0] differential data strobe input/output pins. dqs0 dqs0_c 6 i/o sstl dqs1 dqs1_t 16 i/o sstl dqs1 dqs1_c 15 i/o sstl dqs2 dqs2_t 25 i/o sstl dqs2 dqs2_c 24 i/o sstl dqs3 dqs3_t 34 i/o sstl dqs3 dqs3_c 33 i/o sstl data strobe signals [8:0] differential data strobe input/output pins. dqs4 dqs4_t 85 i/o sstl dqs4 dqs4_c 84 i/o sstl dqs5 dqs5_t 94 i/o sstl dqs5 dqs5_c 93 i/o sstl dqs6 dqs6_t 103 i/o sstl dqs6 dqs6_c 102 i/o sstl dqs7 dqs7_t 112 i/o sstl dqs7 dqs7_c 111 i/o sstl dqs8 dqs8_t 43 i/o sstl dqs8 dqs8_c 42 i/o sstl (t)dqs9 dqs9_t 125 i/o sstl data strobe signals [17:9] (t)dqs9 dqs9_c 126 i/o sstl (t)dqs10 dqs10_t 134 i/o sstl (t)dqs10 dqs10_c 135 i/o sstl (t)dqs11 dqs11_t 143 i/o sstl (t)dqs11 dqs11_c 144 i/o sstl (t)dqs12 dqs12_t 152 i/o sstl (t)dqs12 dqs12_c 153 i/o sstl (t)dqs13 dqs13_t 203 i/o sstl (t)dqs13 dqs13_c 204 i/o sstl (t)dqs14 dqs14_t 212 i/o sstl (t)dqs14 dqs14_c 213 i/o sstl (t)dqs15 dqs15_t 221 i/o sstl (t)dqs15 dqs15_c 222 i/o sstl pin name eda signal name 1) pin no. pin type buffer type function ddr3 registered dimm im[s/h]h[1g/2g/4g]pxxa1f1c advance internet data sheet rev. 0.51, 2008-01 12 12122007-wj2l-rgdp (t)dqs16 dqs16_t 230 i/o sstl data strobe signals [17:9] (t)dqs16 dqs16_c 231 i/o sstl (t)dqs17 dqs17_t 161 i/o sstl (t)dqs17 dqs17_c 162 i/o sstl eeprom and thermal sensor scl scl 118 i cmos serial bus clock sda sda 238 i/o od serial data bus sa0 sa0 117 i cmos serial address select bus [2:0] sa1 sa1 237 i cmos sa2 sa2 119 i cmos power supply v dd vdd 51, 54, 57, 60, 62, 65, 66, 69, 72, 75, 78, 170, 173, 176, 179, 182, 183, 186, 189, 191, 194, 197 pwr - power supply v ss vss 2, 5, 8, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 44, 47, 80, 83, 86, 89,92, 95, 98, 101, 104, 107, 110, 113, 116, 121, 124, 127, 130, 133, 136, 139, 142, 145, 148, 151, 154, 157, 160, 163, 166, 199, 202, 205, 208, 211, 214, 217, 220, 223, 226, 229, 232, 235, 239 gnd - ground v ref.dq vrefdq 1 ai - reference voltage v ref.ca vrefca 67 ai - reference voltage v tt vtt 48, 49, 120 , 240 pwr - termination voltage v ddspd vddspd 236 - eeprom and thermal se nsor power supply other pins reset reset_n 168 i asynchronous reset err_out err_out_n 53 o od err_out par_in par_in 68 i par_in event event_n 187 o od event nc nc 79, 126, 135, 144, 153, 162, 167, 198, 204, 213, 222, 231, -- not connected 1) the eda (electronic design automation) signal name is used in qimonda simulation models such as ebd (electronic board descrip tion). pin name eda signal name 1) pin no. pin type buffer type function ddr3 registered dimm im[s/h]h[1g/2g/4g]pxxa1f1c advance internet data sheet rev. 0.51, 2008-01 13 12122007-wj2l-rgdp table 6 abbreviations for pin type table 7 abbreviations for buffer type abbreviation description i standard input pin only. digital levels. o standard output pin only - digital levels. i/o i/o is a bidirectional input/output signal. ai input - analog levels. pwr power gnd ground nc not connected abbreviation description sstl serial stub terminated logic cmos cmos levels od open drain. the corresponding pin has 2 oper ational states, active low and tri-state, and allows multiple devices to share as a wire-or. ddr3 registered dimm im[s/h]h[1g/2g/4g]pxxa1f1c advance internet data sheet rev. 0.51, 2008-01 14 12122007-wj2l-rgdp figure 1 pin configuration rdimm - 240 pin 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 9 5 ( ) ' 4 ' 4 9 6 6 ' 4 6 ' 4 9 6 6 ' 4 ' 4 6 9 6 6 ' 4 9 6 6 ' 4 ' 4 6 9 6 6 ' 4 ' 4 9 6 6 ' 4 6 ' 4 9 6 6 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q ' 4 ' 4 6 9 6 6 ' 4 ' 4 9 6 6 ' 4 6 ' 4 9 6 6 & |