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4 - bit single chip microcomputers mc40p5x01 series user`s manual ? MC40P5001 ? mc40p5101 ? mc40p5201 ? mc40p5301 mar. 2009 rev. 1.5 www.datasheet.co.kr datasheet pdf - http://www..net/
introduction we hereby introduce the manual for cmos 4 - bit microcomputer mc40p5x01 series. this manual is prepared for the users who should understand fully the functions and features of mc40p5x01 series so that you can utilize this product to its fullest capacity. a detailed explana - tions of the specifications and applications regard - ing the hardware is hereby provided. the contents of this user`s manual are subject to change for the reasons of later improvement of the features. the information, diagrams, and other data in this user`s manual are correct and reliable; however, abov semiconductor inc. is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual revision history ver. 1.5 (mar. 2009) added details of instruction system.(page 33~48) modified pin assignment.(page 7) deleted details of spgm.(page 49) ver. 1.4 (feb. 2008) added the i ol capability of built in transistor for i.r led drive.(page 2) added remdrv port i ol4 and v ol4 parameter data at electrical characteristics.(page 15) added remdrv i ol4 vs v ol4 characteristic graph.(page 17) added the pin description of mc40p5101d.(page 11) added remout port structure.(page 12) added chpater 5 circuit diagram.(page 64,65) modified characteristic graph location and note(page 15, 16, 17) modified the remout port of MC40P5001d & mc40p5201d to remdrv.(page 3, 5, 10) ver. 1.3 modified some errata. ver. 1.2 modified pin assignment.(page 7) ver. 1.1 added lvd parameter data at electrical characteristics.(page 15) ver. 1.0 (agu. 2007) first edition. www.datasheet.co.kr datasheet pdf - http://www..net/
table of contents table of contents chapter 1 introduction ................................................................... 1 outline of characteristics ................................... 2 block diagram ....................................................... 3 pin assignment and dimension ............................... 7 pin description and circuit ...................................... 8 electrical characteristics ............ 14 chapter 2 architecture .................................................................. 16 program memory (rom) ......................................... 17 eprom address register ........................................ 20 data memory (ram) ................................................ 21 x - register (x) .......................................................... 21 y - register (y) .......................................................... 22 accumulator (acc) ................................................... 22 state counter (sc) .................................................. 23 clock generator ..................................................... 24 pulse generator ..................................................... 25 reset operation ..................................................... 26 built - in power on reset .......................................... 26 built - in low vdd reset circuit ................................ 27 watch dog timer (wdt) ......................................... 27 stop function ......................................................... 28 port operation ......................................................... 28 chapter 3 instruction ..... 29 instruction format .. 30 instruction table ... 31 details of instruction system 33 www.datasheet.co.kr datasheet pdf - http://www..net/
table of contents chapter 4 spgm .......................................................................... 48 i2c bus protocol .................................................... 49 summary of protocol .............................................. 49 chapter 5 circuit diagram ..................................................... 51 MC40P5001d with built - in tr circuit diagram ...... 52 mc40p5101d without built - in tr circuit diagram .. 53 www.datasheet.co.kr datasheet pdf - http://www..net/
1 /53 introduction 1 architecture 2 instruction 3 spgm 4 circuit diagrm 5 www.datasheet.co.kr datasheet pdf - http://www..net/
2 /53 chapter 1. introduction outline of characteristics the mc 40 p 5 x 01 d series is 4 - bit remote control mcu which uses cmos technology and the 1 k bytes eprom version . this enables transmission code outputs of different configurations, multiple custom code output, and double push key output for easy fabrication . the mc 40 p 5 x 01 d series is suitable for remote control of tv, vcr, fans, air - conditioners, audio equipments, toys, games etc . characteristics ? program memory : 1,024 bytes ? data memory : 32 4 bits ? 43 types of instruction set ? 3 levels of subroutine nesting ? operating frequency : 2.4mhz ~ 4mhz ? instruction cycle : f osc /48 ? cmos process (single 3.0v power supply) ? stop mode (through internal instruction) ? released stop mode by key input ? built in power - on reset circuit ? built in transistor for i.r led drive (MC40P5001d, mc40p5201d) - i ol =250ma at v dd =3v and v o =0.3v - i ol =500ma at v dd =3v and v o =0.52v ? built in low voltage reset circuit ? built in a watch dog timer (wdt) ? low operating voltage : 2.0 ~ 3.6v ? 20/24 pin sop package chapter 1. introduction www.datasheet.co.kr datasheet pdf - http://www..net/
3 /53 block diagram fig 1 - 1 block diagram ( MC40P5001d, 20 pins ) ram 16word x 2page x 4bit ram word selector y - reg acc st r - latch x - reg mux mux alu 2 3 4 5 6 9 19 7 8 10 11 12 13 14 15 16 17 18 instruction decoder program counter 3 - level stack power - on reset watchdog timer 20 1 10 10 8 eprom 64word 16page 8bit 8 4 4 2 4 10 4 10 4 4 4 16 4 4 4 4 4 osc1 osc2 k0 ~ k3 r0 ~ r3 d0 remdrv vdd gnd osc control signal pulse generator d - latch d1 d2 d3 d4 d5 pgnd i.r.led drive tr. chapter 1. introduction www.datasheet.co.kr datasheet pdf - http://www..net/
4 /53 fig 1 - 2 block diagram ( mc40p5101d, 20 pins ) ram 16word x 2page x 4bit ram word selector y - reg acc st r - latch x - reg mux mux alu 2 3 4 5 6 9 19 7 8 10 11 12 13 14 15 16 17 18 instruction decoder program counter 3 - level stack power - on reset watchdog timer 20 1 10 10 8 eprom 64word 16page 8bit 8 4 4 2 4 10 4 10 4 4 4 16 4 4 4 4 4 osc1 osc2 k0 ~ k3 r0 ~ r3 d0 remout vdd gnd osc control signal pulse generator d - latch d1 d2 d3 d4 d5 d6 chapter 1. introduction www.datasheet.co.kr datasheet pdf - http://www..net/
5 /53 ram 16word x 2page x 4bit ram word selector y - reg acc st r - latch x - reg mux mux alu 2 3 4 5 6 9 19 7 8 10 11 18 instruction decoder program counter 3 - level stack power - on reset watchdog timer 24 1 10 10 8 eprom 64word 16page 8bit 8 4 4 2 4 10 4 10 4 4 4 16 4 4 4 4 4 vdd gnd osc control signal pulse generator d - latch i.r.led drive tr. 21 4 13 14 2 3 5 6 7 10 23 8 9 11 12 15 16 17 18 19 22 osc1 osc2 k0 ~ k3 r0 ~ r3 d0 remdrv d1 d2 d3 d4 d5 pgnd d6 d7 d8 d9 fig 1 - 3 block diagram ( mc40p5201d, 24 pins ) chapter 1. introduction 20 www.datasheet.co.kr datasheet pdf - http://www..net/
6 /53 ram 16word x 2page x 4bit ram word selector y - reg acc st r - latch x - reg mux mux alu 2 3 4 5 6 9 19 7 8 10 11 instruction decoder program counter 3 - level stack power - on reset watchdog timer 24 1 10 10 8 eprom 64word 16page 8bit 8 4 4 2 4 10 4 10 4 4 4 16 4 4 4 4 4 vdd gnd osc control signal pulse generator d - latch 21 4 13 14 2 3 5 6 7 10 23 8 9 11 12 15 16 17 18 19 22 osc1 osc2 k0 ~ k3 r0 ~ r3 d0 remout d1 d2 d3 d4 d5 nc d6 d7 d8 d9 fig 1 - 4 block diagram ( mc40p5301d, 24 pins ) chapter 1. introduction 20 www.datasheet.co.kr datasheet pdf - http://www..net/
7 /53 pin assignment chapter 1. introduction fig 1 - 5 MC40P5001d pin assignment (20 pin) vdd remdrv pgnd d5 d4 d3 d2 d1 d0 r3 gnd osc1 osc2 sda/k0 scl/k1 k2 vpp/k3 r0 r1 r2 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 fig 1 - 7 mc40p5201d pin assignment (24 pin) vdd remdrv pgnd d6 d5 d4 d3 d2 d1 d0 gnd osc1 osc2 d7 sda/k0 scl/k1 vpp/k2 k3 r0 r1 1 2 3 4 5 6 7 8 9 10 24 23 22 21 20 19 18 17 16 15 d9 d8 r2 r3 11 12 14 13 remdrv : open drain output vpp : k2 (port no. 7) fig 1 - 6 mc40p5101d pin assignment (20 pin) vdd remout d6 d5 d4 d3 d2 d1 d0 r3 gnd osc1 osc2 sda/k0 scl/k1 k2 vpp/k3 r0 r1 r2 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 remdrv : open drain output vpp : k3 ( port no.7) remout : push pull output vpp : k3 ( port no.7) fig 1 - 8 mc40p5301d pin assignment (24 pin) vdd remout nc d6 d5 d4 d3 d2 d1 d0 gnd osc1 osc2 d7 sda/k0 scl/k1 vpp/k2 k3 r0 r1 1 2 3 4 5 6 7 8 9 10 24 23 22 21 20 19 18 17 16 15 d9 d8 r2 r3 11 12 14 13 remout : push pull output vpp : k2 (port no. 7) www.datasheet.co.kr datasheet pdf - http://www..net/
8 /53 pin dimension chapter 1. introduction fig 1 - 7. 20sop (209mil) unit : inch 0.512 0.4961 0.050 bsc 0.020 0.013 0.104 0.093 0.0118 0.004 0.208 0.200 0.328 0.307 0 - 8 0.042 0.016 0.0125 0.0091 fig 1 - 8. 20sop (300mil) unit : inch 0.512 0.4961 0.050 bsc 0.020 0.013 0.104 0.093 0.0118 0.004 0.299 0.291 0.419 0.398 0 - 8 0.042 0.016 0.0125 0.0091 www.datasheet.co.kr datasheet pdf - http://www..net/
9 /53 pin dimension chapter 1. introduction fig 1 - 9. 24sop (300mil) unit : inch 0.614 0.598 0.050 bsc 0.019 0.0138 0.104 0.093 0.0118 0.004 0.299 0.291 0.419 0.398 0 - 8 0.042 0.016 0.0125 0.0091 www.datasheet.co.kr datasheet pdf - http://www..net/
10 /53 pin description and circuit pin description ( MC40P5001d, 20 pins) pin function i/o connected to 2.0~ 3.6v power supply connected to 0v power supply. 4 - bit input port with built in pull - up resistor. stop mode is released by "l" input of each pin. k0 ~ k3 input gnd - vdd - each can be set and reset independently. the output is the structure of n - channel - open - drain. 2 - bit i/o port with built in pull - up resistor. input mode is set only when each of them output "h". in outputting, each can be set and reset independently(or at once.) the output is in the form of c - mos. stop mode is released by "l" input of each pin. high current output port for driving i.r.led. the output is in the form n - channel open drain. d0 ~ d5 output r2 ~ r3 i/o remdrv output oscillator input. input to the oscillator circuit and connection point for ceramic resonator. a feedback resistor is connected between this pin and osc2. connect a resonator between this pin and osc1. osc1 input osc2 output ground pin for internal high current n - channel transistor. (connected to gnd) pgnd - 2 - bit input port with built in pull - up resistor. stop mode is released by "l" input of each pin. r0 ~ r1 input chapter 1. introduction www.datasheet.co.kr datasheet pdf - http://www..net/
11 /53 pin description and circuit pin description ( mc40p5101d, 20 pins) pin function i/o connected to 2.0~ 3.6v power supply connected to 0v power supply. 4 - bit input port with built in pull - up resistor. stop mode is released by "l" input of each pin. k0 ~ k3 input gnd - vdd - each can be set and reset independently. the output is the structure of n - channel - open - drain. 2 - bit i/o port with built in pull - up resistor. input mode is set only when each of them output "h". in outputting, each can be set and reset independently(or at once.) the output is in the form of c - mos. stop mode is released by "l" input of each pin. output port for driving i.r.led. the output is push - pull. d0 ~ d6 output r2 ~ r3 i/o remout output oscillator input. input to the oscillator circuit and connection point for ceramic resonator. a feedback resistor is connected between this pin and osc2. connect a resonator between this pin and osc1. osc1 input osc2 output 2 - bit input port with built in pull - up resistor. stop mode is released by "l" input of each pin. r0 ~ r1 input chapter 1. introduction www.datasheet.co.kr datasheet pdf - http://www..net/
12 /53 pin circuit (MC40P5001d & mc40p5101d, 20pins) pin i/o note i/o circuit pull - up - cmos output. - "h" output at reset. - built in mos tr for pull - up, about 140 ? . r2 ~ r3 i/o pull - up - built in mos tr for pull - up, about 140 ? . k0 ~ k3 i - open drain output. - "l" output at reset. - d0~d3 are l output at stop mode. - d4 ~d5 keep before stop mode at stop mode . - d0~d6 : mc40p5101 d0 ~ d5 (d0 ~ d6) o - open drain output - output tr. disable at reset. remdrv (MC40P5001d) o remdrv pgnd pull - up - built in mos tr for pull - up, about 140 ? . r0 ~ r1 i chapter 1. introduction - push pull output. remout (mc40p5101d) o www.datasheet.co.kr datasheet pdf - http://www..net/
13 /53 pin i/o note i/o circuit osc2 rf osc1 stop - built in feedback - resistor about 1 ? i osc2 osc1 o optional features the MC40P5001d is offered to the following option (otp). you can set up on mask ? i/o terminals having pull - up resistor : r2 ~ r3 ? input terminals having stop release mode : k0 ~ k3, r0 ~ r3 ? output form at stop mode : d0 ~d3 pins are changed low by force ? output form at stop mode : d4 ~d5 pins keep the status before stop mode chapter 1. introduction note : at 24 pins, d0 ~d5 is changed to d0 ~ d9 (mc40p5201d, 24pins) d8, d9 pin is automatically outputted l at stop mode. there is remdrv at mc40p5201d and remout at mc40p5301d. www.datasheet.co.kr datasheet pdf - http://www..net/
14 /53 parameter supply voltage power dissipation storage temperature range input voltage output voltage unit v mw v v electrical characteristics absolute maximum ratings (ta = 25 symbol v dd p d tstg v in v out max. rating - 0.3 ~ 5.0 700 * - 55 ~ 125 - 0.3 ~ v dd +0.3 - 0.3 ~ v dd +0.3 * thermal derating above 25 : 6mw per degree rise in temperature. recommended operating condition parameter supply voltage unit v rating 2.0 ~ 3.6 condition 2.4mhz ~ 4mhz symbol v dd topr operating temperature - - 20 ~ +70 chapter 1. introduction www.datasheet.co.kr datasheet pdf - http://www..net/
15 /53 f osc electrical characteristics (ta=25 dd = 3v) *1 refer to fig.1 - 11 < i ol2 vs. v ol2 graph> *2 refer to fig.1 - 12 < i ol1 vs. v ol1 graph> *3 refer to fig.1 - 13 < i ol4 vs. v ol4 graph> *4 refer to fig.1 - 10 < i oh1 vs. v oh1 graph> *5 i dd1 , i dd2 , is measured at reset mode. parameter symbol limits unit condition min. typ. max. input h current r pull - up resistance v ih1 r pu1 i ih 2.1 70 - - 140 - - 300 1 v ? ua - vi=gnd vi=v dd k pull - up resistance r pu2 70 140 300 ? vi=gnd, output off current on stop mode operating supply current i dd2 *5 i stp - - 0.5 - 1.5 1 ma ua f osc =4mhz at stop mode remout leakage current i olk1 - - 1 ua v 0ut =v dd , output off osc2 output l voltage osc2 output h voltage v oh3 v ol3 2.1 - 2.5 0.4 - 0.9 v v i oh = - 150ua i ol =150ua d. r output l voltage v ol2 *1 - 0.15 0.4 v i ol =3ma k, r input h voltage k, r input l voltage v il1 - - 0.9 v - f osc /48 system clock frequency 2.4 - 4 mhz mhz version remout output l current i ol1 *2 0.5 1.1 3 ma v ol1 =0.4v d, r output leakage current i olk2 - - 1 ua v 0ut =v dd , output off feedback resistance r fd 0.3 1.0 3.0 ? v osc1 =gnd, v osc2 =vdd remout output h current i oh1 *4 - 5 - 15 - 30 ma v oh1 =2v chapter 1. introduction remdrv output l current i ol4 *3 - 250 520 - ma v ol4 =0.3v v ol4 =0.52v low voltage reset voltage v lvr - 1.5 - v www.datasheet.co.kr datasheet pdf - http://www..net/
16 /53 fig 1 - 11. i ol2 vs. v ol2 graph. ( d, r port ) chapter 1. introduction ` ta = 25 0 4 8 12 16 20 24 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 vol2 (v) iol2 (ma) vcc = 3.0v fig 1 - 10. i oh1 vs v oh1 graph (remout port) ta = 25 -35 -30 -25 -20 -15 -10 -5 0 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 voh1 (v) ioh1 (ma) vcc = 3.0v vcc = 3.6v vcc = 2.2v www.datasheet.co.kr datasheet pdf - http://www..net/
17 /53 chapter 1. introduction fig 1 - 12. i ol1 vs v ol1 graph (remout without built - in transistor of mc40p5101d and mc40p5301d ) fig 1 - 13. i ol4 vs. v ol4 graph. ( remout port with built - in transistor of MC40P5001d and mc40p5201d ) ` ta = 25 0 100 200 300 400 500 600 0.0 0. 1 0. 2 0 . 3 0 . 4 0.5 0.6 0.7 0.8 0.9 1.0 vol 4 (v) iol 4 (ma) vcc = 3.0v 800 700 ta = 25 0 1 2 3 4 5 6 7 8 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 vol1 (v) iol1 (ma) vcc = 3.0v vcc = 3.6v vcc = 2.2v www.datasheet.co.kr datasheet pdf - http://www..net/
18 /53 introduction 1 architecture 2 instruction 3 spgm 4 circuit diagrm 5 www.datasheet.co.kr datasheet pdf - http://www..net/
19 /53 chapter 2. architecture block description program memory (eprom) the mc 40 p 5 x 01 d series can incorporate maximum 1 , 024 words ( 64 words x 6 page x 8 bits) for program memory . program counter pc (a 0 ~a 5 ) and page address register (a6~a9) are used to address the whole area of program memory having an instruction ( 8 bits) to be next executed . the program memory consists of 64 words on each page, and thus each page can hold up to 64 steps of instructions . he program memory is composed as shown below chapter 2. architecture 0 1 2 4 5 6 3 8 7 63 page 0 program counter (pc) page buffer (pb) 0 a0~a5 a6~a9 page 1 page 2 page 15 page address register (pa) 1 15 2 (sr) (psr) stack register (level 1 ) program capacity (pages) 4 6 4 (level 2 ) (level 3 ) fig 2 - 1 configuration of program memory : www.datasheet.co.kr datasheet pdf - http://www..net/
20 /53 eprom address register the following registers are used to address the eprom . df ? page address register (pa) holds eproms page number ( 0 ~fh) to be addressed . ? page buffer register (pb) value of pb is loaded by an lpbi command when newly addressing a page . then it is shifted into the pa when rightly executing a branch instruction (br) and a subroutine call (cal) . ? program counter (pc) available for addressing word on each page . ? stack register (sr) stores returned - word address in the subroutine call mode . ( 1 ) page address register and page buffer register : address one of pages # 0 to # 15 in the eprom by the 4 - bit binary counter . unlike the program counter, the page address register is usually unchanged so that the program will repeat on the same page unless a page changing command is issued . to change the page address, take two steps such as ( 1 ) writing in the page buffer what page to jump (execution of lpbi) and ( 2 ) execution of br or cal, because instruction code is of eight bits so that page and word can not be specified at the same time . in case a return instruction (rtn) is executed within the subroutine that has been called in the other page, the page address will be changed at the same time . ( 2 ) program counter : this 6 - bit binary counter increments for each fetch to address a word in the currently addressed page having an instruction to be next executed . for easier programming, at turning on the power, the program counter is reset to the zero location . the pa is also set to " 0 " . then the program counter specifies the next eprom address in random sequence . when br, cal or rtn instructions are decoded, the switches on each step are turned off not to update the address . then, for br or cal, address data are taken in from the instruction operands (a 0 to a 5 ), or for rtn, and address is fetched from stack register no . 1 . ( 3 ) stack register : this stack register provides two stages each for the program counter ( 6 bits) and the page address register ( 4 bits) so that subroutine nesting can be made on two levels . chapter 2. architecture www.datasheet.co.kr datasheet pdf - http://www..net/
21 /53 data memory (ram) up to 32 nibbles ( 16 words x 2 pages x 4 bits) is incorporated for storing data . the whole data memory area is indirectly specified by a data pointer (x,y) . page number is specified by zero bit of x register, and words in the page by 4 bits in y - register . data memory is composed in 16 nibbles/page . figure 2 - 2 shows the configuration . chapter 2. architecture x - register (x) x - register is consist of 2bit, x0 is a data pointer of page in the ram, x1 is only used for selecting of d8~d9 with value of y - register 1 1 0 2 3 15 page 1 page 0 0 y - register (y) x - register (x) 4 2 data memory page (0~1) output port d0 remout d9 r0 r3 a0~a3 4 fig 2 - 2 configuration of data memory table 2 - 1 mapping table between x and y register x1=0 x1=1 y=0 d0 d8 y=1 d1 d9 www.datasheet.co.kr datasheet pdf - http://www..net/
22 /53 y - register (y) y - register has 4 bits . it operates as a data pointer or a general - purpose register . y - register specifies and address (a 0 ~a 3 ) in a page of data memory, as well as it is used to specify an output port . further it is used to specify a mode of carrier signal outputted from the remout port . it can also be treated as a general - purpose register on a program . accumulator (acc) the 4 - bit register for holding data and calculation results. arithmetic and logic unit (alu) in this unit, 4bits of adder/comparator are connected in parallel as it's main components and they are combined with status latch and status logic (flag.) (1) operation circuit (alu) : the adder/comparator serves fundamentally for full addition and data comparison. it executes subtraction by making a complement by processing an inversed output of acc (acc +1) (2) status logic : this is to bring an st, or flag to control the flow of a program. it occurs when a specified instruction is executed in three cases such as overflow or underflow in operation and two inputs unequal. chapter 2. architecture www.datasheet.co.kr datasheet pdf - http://www..net/
23 /53 state counter (sc) a fundamental machine cycle timing chart is shown below . every instruction is one byte length . its execution time is the same . execution of one instruction takes 48 clocks for fetch cycle and 48 clocks for execute cycle ( 96 clocks in total) . virtually these two cycles proceed simultaneously, and thus it is apparently completed in 48 clocks (one machine cycle) . exceptionally br, cal and rtn instructions is normal execution time since they change an addressing sequentially . therefore, the next instruction is prefetched so that its execution is completed within the fetch cycle . chapter 2. architecture fig 2 - 3 fundamental timing chart t1 t2 t47 t48 t1 t2 t47 t48 fetch cycle n fetch cycle n - 1 execute cycle n - 1 execute cycle n machine cycle machine cycle phase i phase ii phase iii www.datasheet.co.kr datasheet pdf - http://www..net/
24 /53 clock generator the oscillator circuit is designed to operate with an external ceramic resonator. oscillator circuit is able to organize by connecting ceramic resonator to outside. * it is necessary to connect capacitor to outside in order to change ceramic resonator, you must refer to a manufacturer`s resonator matching guide. chapter 2. architecture figure 2 - 4 oscillator circuit with external capacitor c2 port no.2 port no.3 c1 osc 1 osc 2 note matching test results are below. maker device names test result baotong rt3.640mg matched chequers ztt3.64mgw ztt3.84mgw ztt4.0mgw matched tdk fcr3.64mc5 fcr4.0mc5 matched table 2 - 2 matching test results www.datasheet.co.kr datasheet pdf - http://www..net/
25 /53 pulse generator the following frequency and duty ratio are selected for carrier signal outputted from the remout port depending on a pmr (pulse mode register) value set in a program. pmr remout signal 0 t=1/f pul = 96/f osc , t1/t = 1/2 1 t=1/f pul = 96/f osc , t1/t = 1/3 2 t=1/f pul = 64/f osc , t1/t = 1/2 3 t=1/f pul = 64/f osc , t1/t = 1/4 4 t=1/f pul = 88/f osc , t1/t = 4/11 5 no pulse (same to d0~d9) 6 t=1/f pul = 96/f osc , t1/t =1/4 7 t= 1/ f pul = 8/ f osc , t1/t = 1/2 *default value is 0 * f pul = pulse frequency, f osc = oscillation frequency table 2 - 3 pmr selection table chapter 2. architecture t1 t t1 t (mc40p5101d, mc40p5301d) (MC40P5001d, mc40p5201d) www.datasheet.co.kr datasheet pdf - http://www..net/
26 /53 chapter 2. architecture vcc gnd 3pf counter (wdt) 1 ? vcc system resetb t reset about 108msec at fosc = 3.64mhz system resetb fig2 - 5 power C on reset circuit and timing chart reset operation mc40p5x01d series have three reset sources. one is a built - in power - on reset circuit, another is a built - in low vdd detection circuit, the other is the overflow of watch dog timer (wdt). all reset operations are internal in the MC40P5001d, mc40p5201d built - in power on reset circuit mc40p5x01d series has a built - in power - on reset circuit consisting of an about 1 ? resistor and a 3pf capacitor. when the power - on reset pulse occurs, system reset signal is latched and wdt is cleared. after the overflow time of wdt (213 x system clock time), system reset signal is released. www.datasheet.co.kr datasheet pdf - http://www..net/
27 /53 chapter 2. architecture binary counter (14 steps) reset (edge - trigger) f osc/48 reset by instruction power C on reset low vdd detection vdd reset voltage internal resetb about 108msec at fosc = 3.64mhz fig2 - 6 low voltage detection timing chart watch dog timer (wdt) watch dog timer is organized binary of 14 steps . the signal of f osc / 48 cycle comes in the first step of wdt after wdt reset . if this counter was overflowed, reset signal automatically come out so that internal circuit is initialized . the overflow time is 8 x 6 x 2 13 /f osc ( 108 . 026 ms at f osc = 3 . 64 mhz) normally, the binary counter must be reset before the overflow by using reset instruction (wdtr), power - on reset pulse or low vdd detection pulse . * it is constantly reset in stop mode. when stop is released, counting is restarted. (refer to page 29 stop operation>) built - in low vdd reset circuit mc40p5x01d series have a low vdd detection circuit. if vdd become reset voltage of low vdd detection circuit at a active status, system reset occur and wdt is cleared. after vdd is increased upper reset voltage again, wdt is re - counted and if wdt is overflowed, system reset is released. www.datasheet.co.kr datasheet pdf - http://www..net/
28 /53 stop operation stop mode can be achieved by stop instructions . in stop mode : 1 . oscillator is stopped, the operating current is low . 2 . watch dog timer is reset, d 8 ~d 9 output and remout output are "l" . 3 . part of output pin other than wdt,d 0 ~d 3 , d 8 ~d 9 output and remout output have a value before come into stop mode . stop mode is released when one of k or r input is going to "l" . 1 . state of d 0 ~d 7 output and remout output is return to state of before stop mode is achieved . 2 . after 1 , 024 x 8 enable clocks for stable oscillating, first instruction start to operate . 3 . in return to normal operation, wdt is counted from zero again . but, at executing stop instruction, if one of k or r input is chosen to "l", stop instruction is same to nop (no operation) instruction . port operation port operation is defined by value of x,y register value of x - reg value of y - reg operation 0 or 1 0 ~ 7 so : d(y) 1, ro : d(y) 0 0 or 1 8 remout port repeats "h" and "l" in pulse frequency. (when pmr = 5, it is fixed at "h") so : remout(pmr) 1 ro : remout(pmr) 0 0 or 1 9 so : d0 ~ d9 1 (high - z) ro : d0 ~ d9 0 0 or 1 a ~ d so : r(y - ah) 1 ro : r(y - ah) 0 0 or 1 e so : r0 ~ r3 1 ro : r0 ~ r3 0 0 or 1 f so : d0 ~ d9 1, r0 ~ r3 1 ro : d0 ~ d9 0, r0 ~ r3 0 2 or 3 0 so : d(8) 1 ro : d(8) 0 2 or 3 1 so : d(9) 1 ro : d(9) 0 chapter 2. architecture www.datasheet.co.kr datasheet pdf - http://www..net/
29 /53 introduction 1 architecture 2 instruction 3 spgm 4 circuit diagrm 5 www.datasheet.co.kr datasheet pdf - http://www..net/
30 /53 chapter 3. instruction chapter 3. instruction instruction format all of the 43 instruction in mc40p5x01d series is format in two fields of op code and operand which consist of eight bits. the following formats are available with different types of operands. *format all eight bits are for op code without operand. *format two bits are for operand and six bits for op code. two bits of operand are used for specifying bits of ram and x - register (bit 1 and bit 7 are fixed at 0) *format four bits are for operand and the others are op code. four bits of operand are used for specifying a constant loaded in ram or y - register, a comparison value of compare command, or page addressing in rom. *format six bits are for operand and the others are op code. six bits of operand are used for word addressing in the rom. www.datasheet.co.kr datasheet pdf - http://www..net/
31 /53 instruction table the mc40p5x01d series provides the following 43 basic instructions. category mnemonic function st *1 1 register to register lay a y s 2 lya y a s 3 laz a 0 s 4 ram to register lma m(x,y) a s 5 lmaiy m(x,y) a, y y+1 s 6 lym y m(x,y) s 7 lam a m(x,y) s 8 xma a ? m(x,y) s 9 immediate lyi i y i s 10 lmiiy i m(x,y) i, y y+1 s 11 lxi n x n s 12 ram bit manipulation sem n m(n) 1 s 13 rem n m(n) 0 s 14 tm n test m(n) 1 e 15 rom address br a if st = 1 then branch s 16 cal a if st = 1 then subroutine call s 17 rtn return from subroutine s 18 lpbi i pb i s 19 arithmetic am a a + m(x,y) c 20 sm a m(x,y) C a b 21 im a m(x,y) + 1 c 22 dm a m(x,y) C 1 b 23 ia a a + 1 s 24 iy y y + 1 c 25 da a a - 1 b chapter 3. instruction www.datasheet.co.kr datasheet pdf - http://www..net/
32 /53 category mnemoni c function st *1 26 arithmetic dy y y C 1 b 27 eorm a a m(x,y) s 28 nega a a + 1 z 29 comparison alem test a m(x,y) e 30 alem i test a i e 31 mnez test m(x,y) 0 n 32 ynea test y a n 33 ynei i test y i n 34 knez test k 0 n 35 rnez test r 0 n 36 input/ output lak a k s 37 lar a r s 38 so output(y) 1 *2 s 39 ro output(y) 0 *2 s 40 control wdtr watch dog timer reset s 41 stop stop operation s 42 lpy pmr y s 43 nop no operation s note) i = 0~f, n = 0~3, a = 6bit pc address *1 column st indicates conditions for changing status. symbols have the following meanings s : on executing an instruction, status is unconditionally set. c : status is only set when carry or borrow has occurred in operation. b : status is only set when borrow has not occurred in operation. e : status is only set when equality is found in comparison. n : status is only set when equality is not found in comparison. z : status is only set when the result is zero. *2 operation is settled by a value of y - register.. chapter 3. instruction www.datasheet.co.kr datasheet pdf - http://www..net/
33 /53 chapter 3. instruction details of instruction system all 43 basic instructions of the mc40p5x01d series are one by one described in detail below. description form each instruction is headlined with its mnemonic symbol according to the instructions table given earlier. then, for quick reference, it is described with basic items as shown below. after that, detailed comment follows. ? items : - naming : full spelling of mnemonic symbol - status : check of status function - format : categorized into to - operand : omitted for format - function www.datasheet.co.kr datasheet pdf - http://www..net/
34 /53 chapter 3. instruction (1) lay naming : load accumulator from y - register status : set format : i function : a y data of four bits in the y - register is unconditionally transferred to the accumulator. data in the y - register is left unchanged. (2) lya naming : load y - register from accumulator status : set format : i function : y a load y - register from accumulator (3) laz naming : clear accumulator status : set format : i function : a 0 data in the accumulator is unconditionally reset to zero. (4) lma naming : load memory from accumulator status : set format : i function : m(x,y) a data of four bits from the accumulator is stored in the ram location addressed by the x - register and y - register. such data is left unchanged. (5) lmaiy naming : load memory from accumulator and increment y - register status : set format : i function : m(x,y) a, y y+1 data of four bits from the accumulator is stored in the ram location addressed by the x - register and y - register. such data is left unchanged. www.datasheet.co.kr datasheet pdf - http://www..net/
35 /53 chapter 3. instruction (6) lym naming : load y - register form memory status : set format : i function : y m(x,y) data from the ram location addressed by the x - register and y - register is loaded into the y - register. data in the memory is left unchanged. (7) lam naming : load accumulator from memory status : set format : i function : a m(x,y) data from the ram location addressed by the x - register and y - register is loaded into the y - register. data in the memory is left unchanged. (8) xma naming : exchanged memory and accumulator status : set format : i function : m(x,y) ? a data from the memory addressed by x - register and y - register is exchanged with data from the accumulator. for example, this instruction is useful to fetch a memory word into the accumulator for operation and store current data from the accumulator into the ram. the accumulator can be restored by another xma instruction. (9) lyi i naming : load y - register from immediate status : set format : operand : constant 0 i 15 function : y i to load a constant in y - register. it is typically used to specify y - register in a particular ram word address, to specify the address of a selected output line, to set y - register for specifying a carrier signal outputted from out port, and to initialize y - register for loop control. the accumulator can be restored by another xma instruction. data of four bits from operand of instruction is transferred to the y - register. www.datasheet.co.kr datasheet pdf - http://www..net/
36 /53 chapter 3. instruction (10) lmiiy i naming : load memory from immediate and increment y - register status : set format : operand : constant 0 i 15 function : m(x,y) i, y y + 1 data of four bits from operand of instruction is stored into the ram location addressed by the x - register and y - register. then data in the y - register is incremented by one. (11) lxi n naming : load x - register from immediate status : set format : operand : x file address 0 n 3 function : x n a constant is loaded in x - register. it is used to set x - register in an index of desired ram page. operand of 1 bit of command is loaded in x - register. (12) sem n naming : set memory bit status : set format : operand : bit address 0 n 3 function : m(x,y,n) 1 depending on the selection in operand of operand, one of four bits is set as logic 1 in the ram memory addressed in accordance with the data of the x - register and y - register. (13) rem n naming : reset memory bit status : set format : operand : bit address 0 n 3 function : m(x,y,n) 0 depending on the selection in operand of operand, one of four bits is set as logic 0 in the ram memory addressed in accordance with the data of the x - register and y - register. www.datasheet.co.kr datasheet pdf - http://www..net/
37 /53 chapter 3. instruction (14) tm n naming : test memory bit status : comparison results to status format : operand : bit address 0 n 3 function : m(x,y,n) 1? st 1 when m(x,y,n)=1, st 0 when m(x,y,n)=0 a test is made to find if the selected memory bit is logic. 1 status is set depending on the result. (15) br a naming : branch on status 1 status : conditional depending on the status format : operand : branch address a (addr) function : when st =1 , pa pb, pc a(addr) when st = 0, pc pc + 1, st 1 note : pc indicates the next address in a fixed sequence that is actually pseudo - random count. for some programs, normal sequential program execution can be change. a branch is conditionally implemented depending on the status of results obtained by executing the previous instruction. ? branch instruction is always conditional depending on the status. a. if the status is reset (logic 0), a branch instruction is not rightly executed but the next instruction of the sequence is executed. b. if the status is set (logic 1), a branch instruction is executed as follows. ? branch is available in two types - short and long. the former is for addressing in the current page and the latter for addressing in the other page. which type of branch to exeute is decided according to the pb register. to execute a long branch, data of the pb register should in advance be modified to a desired page address through the lpbi instruction. www.datasheet.co.kr datasheet pdf - http://www..net/
38 /53 chapter 3. instruction (16) cal a naming : subroutine call on status 1 status : conditional depending on the status format : operand : subroutine code address a(addr) function : when st =1 , pc a(addr) pa pb sr1 pc + 1, psr1 pa sr2 sr1 psr2 psr1 sr3 sr2 psr3 psr2 when st = 0 pc pc + 1 pb ps st 1 note : pc actually has pseudo - random count against the next instruction. ? in a program, control is allowed to be transferred to a mutual subroutine. since a call instruction preserves the return address, it is possible to call the subroutine from different locations in a program, and the subroutine can return control accurately to the address that is preserved by the use of the call return instruction (rtn). such calling is always conditional depending on the status. a. if the status is reset, call is not executed. b. if the status is set, call is rightly executed. the subroutine stack (sr) of three levels enables a subroutine to be manipulated on three levels. besides, a long call (to call another page) can be executed on any level. ? for a long call, an lpbi instruction should be executed before the cal. when lpbi is omitted (and when pa=pb), a short call (calling in the same page) is executed. www.datasheet.co.kr datasheet pdf - http://www..net/
39 /53 chapter 3. instruction (17) rtn naming : return from subroutine status : set format : function : pc sr1 pa, pb psr1 sr1 sr2 psr1 psr2 sr2 sr3 psr2 psr3 sr3 sr3 psr3 psr2 st 1 control is returned from the called subroutine to the calling program. control is returned to its home routine by transferring to the pc the data of the return address that has been saved in the stack register (sr1). at the same time, data of the page stack register (psr1) is transferred to the pa and pb. (18) lpbi i naming : load page buffer register from immediate status : set format : operand : rom page address 0 i 15 function : pb i a new rom page address is loaded into the page buffer register (pb). this loading is necessary for a long branch or call instruction. the pb register is loaded together with three bits from 4 bit operand. (19) am naming : add accumulator to memory and status 1 on carry status : carry to status format : function : a m(x,y)+a, st 1(when total>15), st 0 (when total 15) data in the memory location addressed by the x and y - register is added to data of the accumulator. results are stored in the accumulator. carry data as results is transferred to status. when the total is more than 15, a carry is caused to put 1 in the status. data in the memory is not changed. www.datasheet.co.kr datasheet pdf - http://www..net/
40 /53 chapter 3. instruction (20) sm naming : subtract accumulator to memory and status 1 not borrow status : carry to status format : function : a m(x,y) - a st 1(when a m(x,y)) st 0(when a > m(x,y)) data of the accumulator is, through a 2`s complemental addition, subtracted from the memory word addressed by the y - register. results are stored in the accumulator. if data of the accumulator is less than or equal to the memory word, the status is set to indicate that a borrow is not caused. if more than the memory word, a borrow occurs to reset the status to 0. (21) im naming : increment memory and status 1 on carry status : carry to status format : function : a m(x,y) + 1 st 1(when m(x,y) 15) st 0(when m(x,y) < 15) data of the memory addressed by the x and y - register is fetched. adding 1 to this word, results are stored in the accumulator. carry data as results is transferred to the status. when the total is more than 15, the status is set. the memory is left unchanged. (22) dm naming : decrement memory and status 1 on not borrow status : carry to status format : function : a m(x,y) - 1 st 1(when m(x,y) 1) st 0 (when m(x,y) = 0) data of the memory addressed by the x and y - register is fetched, and one is subtracted from this word (addition of fh)> results are stored in the accumulator. carry data as results is transferred to the status. if the data is more than or equal to one, the status is set to indicate that no borrow is caused. the memory is left unchanged. www.datasheet.co.kr datasheet pdf - http://www..net/
41 /53 chapter 3. instruction (23) ia naming : increment accumulator status : set format : function : a a+1 data of the accumulator is incremented by one. results are returned to the accumulator. a carry is not allowed to have effect upon the status. (24) iy naming : increment y - register and status 1 on carry status : carry to status format : function : y y + 1 st 1 (when y = 15) st 0 (when y < 15) data of the y - register is incremented by one and results are returned to the y - register. carry data as results is transferred to the status. when the total is more than 15, the status is set. (25) da naming : decrement accumulator and status 1 on borrow status : carry to status format : function : a a - 1 st 1(when a 1) st 0 (when a = 0) data of the accumulator is decremented by one. as a result (by addition of fh), if a borrow is caused, the status is reset to 0 by logic. if the data is more than one, no borrow occurs and thus the status is set to 1. www.datasheet.co.kr datasheet pdf - http://www..net/
42 /53 chapter 3. instruction (26) dy naming : decrement y - register and status 1 on not borrow status : carry to status format : function : y y - 1 st 1 (when y 1) st 0 (when y = 0) data of the y - register is decremented by one. data of the y - register is decremented by one by addition of minus 1 (fh). carry data as results is transferred to the status. when the results is equal to 15, the status is set to indicate that no borrow has not occurred. (27) eorm naming : exclusive or memory and accumulator status : set format : function : a m(x,y) + a data of the accumulator is, through a exclusive or, subtracted from the memory word addressed by x and y - register. results are stored into the accumulator. (28) nega naming : negate accumulator and status 1 on zero status : carry to status format : function : a a + 1 st 1(when a = 0) st 0 (when a != 0) the 2`s complement of a word in the accumulator is obtained. the 2`s complement in the accumulator is calculated by adding one to the 1`s complement in the accumulator. results are stored into the accumulator. carry data is transferred to the status. when data of the accumulator is zero, a carry is caused to set the status to 1. www.datasheet.co.kr datasheet pdf - http://www..net/
43 /53 chapter 3. instruction (29) alem naming : accumulator less equal memory status : carry to status format : function : a m(x,y) st 1 (when a m(x,y)) st 0 (when a > m(x,y)) data of the accumulator is, through a complemental addition, subtracted from data in the memory location addressed by the x and y - register. carry data obtained is transferred to the status. when the status is 1, it indicates that the data of the accumulator is less than or equal to the data of the memory word. neither of those data is not changed. (30) alei naming : accumulator less equal immediate status : carry to status format : function : a i st 1 (when a i) st 0 (when a > i) data of the accumulator and the constant are arithmetically compared. data of the accumulator is, through a complemental addition, subtracted from the constant that exists in 4bit operand. carry data obtained is transferred to the status. the status is set when the accumulator value is less than or equal to the constant. data of the accumulator is left unchanged. (31) mnez naming : memory not equal zero status : comparison results to status format : function : m(x,y) 0 st 1(when m(x,y) 0) st 0 (when m(x,y) = 0) a memory word is compared with zero. data in the memory addressed by the x and y - register is logically compared with zero. comparison data is transferred to the status. unless it is zero, the status is set. www.datasheet.co.kr datasheet pdf - http://www..net/
44 /53 chapter 3. instruction (32) ynea naming : y - register not equal accumulator status : comparison results to status format : function : y a st 1 (when y a) st 0 (when y = a) data of y - register and accumulator are compared to check if they are not equal. data of the y - register and accumulator are logically compared. results are transferred to the status. unless they are equal, the status is set. (33) ynei naming : y - register not equal immediate status : comparison results to status format : operand : constant 0 i 15 function : y i st 1 (when y i) st 0 (when y = i) the constant of the y - register is logically compared with 4bit operand. results are transferred to the status. unless the operand is equal to the constant, the status is set. (34) knez naming : k not equal zero status : the status is set only when not equal format : function : when k 0, st 1 a test is made to check if k is not zero. data on k are compared with zero. results are transferred to the status. for input data not equal to zero, the status is set. (35) rnez naming : r not equal zero status : the status is set only when not equal format : function : when r 0, st 1 a test is made to check if r is not zero. data on r are compared with zero. results are transferred to the status. for input data not equal to zero, the status is set. www.datasheet.co.kr datasheet pdf - http://www..net/
45 /53 chapter 3. instruction (36) lak naming : load accumulator from k status : set format : function : a k data on k are transferred to the accumulator (37) lar naming : load accumulator from r status : set format : function : a r data on r are transferred to the accumulator (38) so naming : set output register latch status : set format : function : d(y) 1 0 y 7 remout 1(pmr=5) y = 8 d0~d9 1 (high - z) y = 9 r(y) 1 ah y dh r 1 y = eh d0~d9, r 1 y = fh a single d output line is set to logic 1, if data of y - register is between 0 to 7. carrier frequency come out from remout port, if data of y - register is 8. all d output line is set to logic 1, if data of y - register is 9. it is no operation, if data of y - register between 10 to 15. when y is between ah and dh, one of r output lines is set at logic 1. when y is eh, the output of r is set at logic 1. when y is fh, the output d0~d9 and r are set at logic 1. data of y - register is between 0 to 7, selects appropriate d output. data of y - register is 8, selects remout port. data of y - register is 9, selects all d port. data in y - register, when between ah and dh, selects an appropriate r output (r0~r3). data in y - register, when it is eh, selects all of r0~r3. data in y - register, when it is fh, selects all of d0~d9 and r0~r3. www.datasheet.co.kr datasheet pdf - http://www..net/
46 /53 chapter 3. instruction (39) ro naming : reset output register latch status : set format : function : d(y) 0 0 y 7 remout 0 y = 8 d0~d9 0 y = 9 r(y) 0 ah y dh r 0 y = eh d0~d9, r 0 y = fh a single d output line is set to logic 0, if data of y - register is between 0 to 9. remout port is set to logic 0, if data of y - register is 9. all d output line is set to logic 0, if data of y - register is 9. when y is between ah and dh, one of r output lines is set at logic 0. when y is eh, the output of r is set at logic 0 when y is fh, the output d0~d9 and r are set at logic 1. data of y - register is between 0 to 7, selects appropriate d output. data of y - register is 8, selects remout port. data of y - register is 9, selects d port. data in y - register, when between ah and dh, selects an appropriate r output (r0~r3). data in y - register, when it is eh, selects all of r0~r3. data in y - register, when it is fh, selects all of d0~d9 and r0~r3. (40) wdtr naming : watch dog timer reset status : set format : function : reset watch dog timer (wdt) normally, you should reset this counter before overflowed counter for dc watch dog timer. this instruction controls this reset signal. www.datasheet.co.kr datasheet pdf - http://www..net/
47 /53 chapter 3. instruction (41) stop naming : stop status : set format : function : operate the stop function stopped oscillator, and little current. (see 1 - 12 page, stop function.) (42) lpy naming : pulse mode set status : set format : function : pmr y selects a pulse signal outputted from remout port. (43) nop naming : no operation status : set format : function : no operation assembler macro (44) call a (2byte) : long_call macro page call (2byte) : lpbi i ; i = low_page address(4bits), pb3~0(low_page address) < -- i cal a ; see you "cal" instruction. (45) bl a (2byte) : long_branch macro page branch (2byte) : lpbi i ; i = low_ page address(4bits), pb0~3(low_page address) < -- i br a ; see you "br" instruction. www.datasheet.co.kr datasheet pdf - http://www..net/
48 /53 introduction 1 architecture 2 instruction 3 spgm 4 circuit diagrm 5 www.datasheet.co.kr datasheet pdf - http://www..net/
49 /53 spgm(serial program) the i 2 c bus protocol the i 2 c bus protocol is a method of communication . it physically consists of 2 active wires . the active wires, called scl and sda, are both bi - directional . scl is the serial clock line . it is used to synchronize all data transfers over the i 2 c bus . and sda is the serial data line . the scl & sda lines are connected to all devices on the i 2 c bus . summary of protocol ? necessary pins (5pins) - serial data (sda) : k0 - serial clock (scl) : k1 - vpp : k3 (20pin) : k2 (24pin) - vdd - vss chapter 4. spgm www.datasheet.co.kr datasheet pdf - http://www..net/
50 /53 ? lock program / read data format id6 id5 id4 id3 id2 id1 id0 lock tail ? id6 C id0 : it can be treated as user id. MC40P5001d id: 1000 000xb mc40p5101d id: 1001 000xb mc40p5201d id: 1010 000xb mc40p5301d id: 1011 000xb for protection the written program code, in other words it can not be read, you have to clear the lock bit to 0, and for this, you have to write the lock register to 1111_1110b. in this time, id6 C id0 keep the existing value without any effect chapter 4. spgm www.datasheet.co.kr datasheet pdf - http://www..net/
51 /53 introduction 1 architecture 2 instruction 3 spgm 4 circuit diagrm 5 www.datasheet.co.kr datasheet pdf - http://www..net/
52 /53 MC40P5001d with built - in tr circuit diagram k0 k1 k2 k3 r0 r1 r2 r3 d0 d1 d2 d3 d4 d5 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 4 5 6 7 8 9 10 11 12 13 14 15 16 3 2 19 20 1 vdd gnd rem drv osc2 osc1 MC40P5001 + 17 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f pgnd 18 chapter 5. circuit diagrm www.datasheet.co.kr datasheet pdf - http://www..net/
53 /53 mc40p5101d without built - in tr circuit diagram k0 k1 k2 k3 r0 r1 r2 r3 d0 d1 d2 d3 d4 d5 d6 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 4 5 6 7 8 9 10 11 12 13 14 15 16 3 2 19 20 1 vdd gnd rem out osc2 osc1 mc40p5101 + 17 20 21 22 23 24 25 26 27 18 28 29 2a 2b 2c 2d 2e 2f 30 32 32 33 34 35 36 37 chapter 5. circuit diagrm www.datasheet.co.kr datasheet pdf - http://www..net/

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