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2303n0docdat10a-0899 1 pc-tel, inc. ! ! the leader in host signal processing (hsp) modem technology ! ! the leader in host signal processing (hsp) modem technology PCT2303N for amr & mdc motherboard integration of the modem subsystem has been problematic to date, in large part due to fcc and other international telecom certification processes that delay the introduction of a motherboard when the modem?s analog i/o (codec and daa) circuitry was physically soldered to the board. resolving homologation/ certification issues for oems is one of the key objectives of the amr/mdc specification. with an open, industry-standard riser solution, a system manufacturer is free to implement audio and/or modem functions on the motherboard at a lower bill of materials (bom) cost than would be possible by deploying these functions in either industry-standard expansion slots or in a proprietary method. pc-tel has streamlined the traditional modem into the host signal processing (hsp) solution. operating with the pentium class processors, hsp becomes part of the host computer?s system software. it requires less power to operate and less physical space than standard modem solutions. pc-tel?s hsp modem is an easily integrated, cost-effective communications solution that is flexible enough to carry you into the future. the PCT2303N chip set is an integrated direct access arrangement (daa) and codec that provides a programmable line interface to meet requirements. thepct 2303n chip set is available in two 16-pin small outline packages (ac?97 interface on pct303a and phone-line interface on pct303l). the chip set eliminates the need for an afe, an isolation transformer, relays, opto-isolators, and 2- to 4-wire hybrid. the PCT2303N chip set dramatically reduces the number of discrete components and cost required to achieve compliance with regulatory requirements. the pct303a complies with ac?97 interface specification rev. 2.1. ac ?97 digital controller mdc 30-pin connector modem daughter card integrated daa/codec chip set ac ?97 audio codec rj11 rj11 amr 46-pin connector ac ?97 digital controller integrated chipset daa/ codec ac ?97 audio codec PCT2303N chip mdc i/f 30-pin 27*45mm mobile daughter card modem riser card intel amr i/f PCT2303N chip set 68mm 60mm codec/daa features s ac?97 rev 2.1 compliant s 86db dynamic range tx/rx paths s 2-4-wire hybrid s integrated ring detector s high voltage isolation of 2000v s support for ?caller id? s compliant with fcc part15b/part 68 s low power standby s low profile soic package 10x3x1.55mm s low power consumption 10ma @ 3.3v operation 1ma @ 3.3v power down s integrated modem codec standard features data s itu-t v.90, v.34, v.32bis, v.32, v.22bis, v.22, v.21, v.23, bell 212a, bell 103 s data compression itu-t v.42bis mnp class 5 s error correction itu-t v.42 lapm mnp 2-4 fax s itu-t v. 17, v.29, v.27ter, v.21 channel 2 group 3 eia class i operating systems s windows 95/98, nt 4.0, windows 2000, and linux
pc-tel, inc. 2 2303n0docdat10a-0899 PCT2303N data sheet ! ! f e a t u r e s complete daa includes: ? ac?97 2.1 compliant ? international line interface ? compliant with fcc part 68 ? 86 db dynamic range tx/rx paths ? 3.3 to 5v power supply ? integrated ring detector ? 2000 v isolation ? low profile soic packages ? integrated analog front end (afe) ? low-power standby mode ? support for caller id a p p l i c a t i o n s ? audio/modem riser card (amr) ? mobile daughter card (mdc) ? mini pci f u n c t i o n a l d e s c r i p t i o n the PCT2303N is an integrated direct access arrangement (daa) chipset that provides a digital, low- cost, solid-state interface to a telephone line. the PCT2303N chipset is available in two 16-pin small outline packages (ac?97 interface on pct303a and phone-line interface on pct303l). the chipset eliminates the need for an afe, an isolation transformer, relays, opto-isolators, and 2- to 4-wire hybrid. the PCT2303N chipset dramatically reduces the number of discrete components and cost required to achieve compliance with fcc part 68. the pct303a complies with ac?97/mc?97 interface specification rev. 2.1. \ f u n c t i o n a l b l o c k d i a g r a m PCT2303N chip set isolation interface out in hybrid ring detect off-hook tx rx dct vreg rext ignd rng1 rng2 qb qe dc termination hybd pct303a pct303l digital interface control interface bit_clk sync sdata_in ac?97 id0 id1 gpioa gpiob clock xout mclk/xin sdata_out reset isolation interface
pc-tel, inc. 3 2303n0docdat10a-0899 PCT2303N data sheet ! ! c o n t e n t s PCT2303N f o r amr & mdc . . . . . . . . . . . . . . 1 codec/daa features . . . . . . . . . . . . . . . . . . 1 standard features . . . . . . . . . . . . . . . . . . . . 1 operating systems . . . . . . . . . . . . . . . . . . . . 1 ptt approved countries . . . . . . . . . . . . . . . . . . . 1 f e a t u r e s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 a p p l i c a t i o n s . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 f u n c t i o n a l d e s c r i p t i o n . . . . . . . . . . . . . . . . . . . 2 f u n c t i o n a l b l o c k d i a g r a m . . . . . . . . . . . . . . . . 2 p i n o u t s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 pct303a pinout . . . . . . . . . . . . . . . . . . . . . . . . . 5 pct303l pinout . . . . . . . . . . . . . . . . . . . . . . . . . 5 p i n d e s c r i p t i o n s . . . . . . . . . . . . . . . . . . . . . . . . 6 pct303a pin description . . . . . . . . . . . . . . . . . . 6 pct303l pin descriptions . . . . . . . . . . . . . . . . . 7 f u n c t i o n a l d e s c r i p t i o n . . . . . . . . . . . . . . . . . . . 8 isolation barrier . . . . . . . . . . . . . . . . . . . . . . . . . . 8 off-hook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ring detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 lightning test . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 safety and isolation . . . . . . . . . . . . . . . . . . . . . . . 8 digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . 8 pct303a as secondary device . . . . . . . . . . 8 pct303a as primary mc?97 codec . . . . . . 9 pct303a connection to ac?97 controller . . 9 clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 resetting the PCT2303N . . . . . . . . . . . . . . . 9 ac-link digital serial interface protocol . . . . . . . 9 audio output frame (sdata_out) . . . . . . 10 variable sample rate signaling protocol . . 11 audio input frame (sdata_in) . . . . . . . . . 13 ac-link low power mode . . . . . . . . . . . . . . . . . 14 analog output . . . . . . . . . . . . . . . . . . . . . . . . . . 15 on-hook line monitor (cid) . . . . . . . . . . . . . . . . 15 loop current monitor . . . . . . . . . . . . . . . . . . . . . 15 gain control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 filter selection . . . . . . . . . . . . . . . . . . . . . . . . . . 15 charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 in-circuit testing . . . . . . . . . . . . . . . . . . . . . . . . 16 c o n t r o l r e g i s t e r s . . . . . . . . . . . . . . . . . . . . . 17 e l e c t r i c a l c h a r a c t e r i s t i c s . . . . . . . . . . . . . . 26 recommended operating conditions . . . . . . . . 26 absolute maximum ratings . . . . . . . . . . . . . . . . 26 loop characteristics . . . . . . . . . . . . . . . . . . . . . . 27 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . 28 v d = 5v . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 v d = 3.3v . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . 29 ac-l i n k c h a r a c t e r i s t i c s . . . . . . . . . . . . . . . . 30 cold reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 warm reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 data setup and hold . . . . . . . . . . . . . . . . . . . . . 32 rise and fall times . . . . . . . . . . . . . . . . . . . . . . 32 low power mode . . . . . . . . . . . . . . . . . . . . . . . . 33 ate test mode . . . . . . . . . . . . . . . . . . . . . . . . . 33 d i g i t a l f i l t e r c h a r a c t e r i s t i c s . . . . . . . . . . . 34 digital fir filter characteristics . . . . . . . . . . . . . 34 digital iir filter characteristics . . . . . . . . . . . . . 34 filter plot diagrams . . . . . . . . . . . . . . . . . . . . . . 35 m e c h a n i c a l d i m e n s i o n s . . . . . . . . . . . . . . . . . . 38 m a n u f a c t u r e d u n d e r o n e o r m o r e o f t h e f o l l o w i n g p a t e n t s : . . . . . . . . . . . . . . . . . . . . 39 c o m p a n y l o c a t i o n s . . . . . . . . . . . . . . . . . . . . . 40 o r d e r i n g i n f o r m a t i o n . . . . . . . . . . . . . . . . . . . 40
pc-tel, inc. 4 2303n0docdat10a-0899 PCT2303N data sheet ! ! f i g u r e s figure 1 pct303a 16-pin soic . . . . . . . . . . . . . . . . 5 figure 2 pct303l 16-pin soic . . . . . . . . . . . . . . . . 5 figure 3 PCT2303N chipset connection to ac?97 con- troller (primary device configuration) . . . . . . . . . . . 9 figure 4 standard bidirectional audio frame . . . . . 10 figure 5 ac-link audio output frame . . . . . . . . . . . 11 figure 6 start of an audio output frame . . . . . . . . . 11 figure 7 ac-link audio input frame . . . . . . . . . . . . 13 figure 8 ac-link power-down timing . . . . . . . . . . . 14 figure 9 typical lcs transfer function . . . . . . . . . 15 figure 10 loopback points . . . . . . . . . . . . . . . . . . . 23 figure 11 cold reset timing diagram . . . . . . . . . . . 30 figure 12 warm reset timing diagram . . . . . . . . . . 30 figure 13 clocks timing diagram . . . . . . . . . . . . . . 31 figure 14 data setup and hold timing diagram . . . 32 figure 15 signal rise and fall timing diagram . . . . 32 figure 16 low power mode timing diagram . . . . . . 33 figure 17 ate test mode timing diagram . . . . . . . 33 figure 18 test circuit for loop characteristics . . . . 34 figure 19 fir receive filter response . . . . . . . . . . 35 figure 20 fir receive filter passband ripple . . . . . 35 figure 21 fir transmit filter response . . . . . . . . . . 35 figure 22 fir transmit filter passband ripple . . . . 35 figure 23 iir receive filter response . . . . . . . . . . . 36 figure 24 iir receive filter passband ripple . . . . . 36 figure 25 iir transmit filter response . . . . . . . . . . 36 figure 26 iir transmit filter passband ripple . . . . . 36 figure 27 iir receive group delay . . . . . . . . . . . . . 37 figure 28 iir transmit group delay . . . . . . . . . . . . . 37 figure 29 16-pin soic package . . . . . . . . . . . . . . . . 38 t a b l e s table 1 pct303a pin description . . . . . . . . . . . . . . . 6 table 2 pct303l pin descriptions . . . . . . . . . . . . . . 7 table 3 device id configuration . . . . . . . . . . . . . . . . 8 table 4 slot 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 5 sample rates for line 1 and line 2 . . . . . . . 18 table 6 recommended operating conditions . . . . . 26 table 7 absolute maximum ratings . . . . . . . . . . . . 26 table 8 loop characteristics . . . . . . . . . . . . . . . . . . 27 table 9 dc characteristics, v d = +5v . . . . . . . . . . 28 table 10 dc characteristics, v d = +3.3v . . . . . . . . 28 table 11 ac characteristics . . . . . . . . . . . . . . . . . . 29 table 12 timing characteristics?cold reset . . . . . 30 table 13 timing characteristics?warm reset . . . . 30 table 14 timing characteristics?clocks . . . . . . . . . 31 table 15 timing characteristics?data setup and hold 32 table 16 timing?rise and fall times . . . . . . . . . . . 32 table 17 timing characteristics?low power mode 33 table 18 timing characteristics?ate test mode . . 33 table 19 digital fir filter characteristics?transmit and receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 20 digital iir filter characteristics?transmit and receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 21 soic mechanical dimensions . . . . . . . . . . 38
pc-tel, inc. 5 2303n0docdat10a-0899 PCT2303N data sheet p i n o u t s ! ! p i n o u t s pct303a pinout figure 1 pct303a 16-pin soic pct303l pinout figure 2 pct303l 16-pin soic 1 2 3 4 5 6 7 8 9 10 11 12 13 16 15 14 gpio_a cpio_b id1 v a gnd c1a id0 aout mclk/xin xout bit_clk v d sdata_in sdata_out sync reset 1 2 3 4 5 6 7 8 9 10 11 12 13 16 15 14 tx nc rx rext dct hybd nc vreg tsta tstb ignd c1b rng1 rng2 qb qe
pc-tel, inc. 6 2303n0docdat10a-0899 PCT2303N data sheet p i n d e s c r i p t i o n s ! ! p i n d e s c r i p t i o n s pct303a pin description table 1 pct303a pin description name number i/o description serial interface bit_clk 3 i/o serial port bit clock output/input. controls the serial data on sdata_in and latches the data on sdata_out. output when configured as primary device. input when configured as secondary device. sdata_in 5 o serial port data out. serial communication and status data that is provided by the pct303a to the ac?97 digital controller. sdata_out 6 i serial port data in. serial communication and control data that is generated by the ac?97 digital controller and presented as an input to the pct303a. sync 7 i frame sync input. data framing signal that is used to indicate the start and stop of a communication data frame. reset 8 i reset input. an active-low input that is used to reset all control registers to a defined, initialized state. also used to bring the PCT2303N out of sleep mode. miscellaneous signals id0 10 i device id bit 0. bit 0 of the device configuration. id1 14 i device id bit 1. bit 1 of the device configuration. aout 9 o analog speaker output. provides an analog output signal for driving a call progress speaker. c1a 11 i/o isolation capacitor 1a. connects to one side of the isolation capacitor c1. mclk/xin 1 i master clock input/crystal input. xout 2 o crystal output. gpio_a 16 i/o general-purpose i/o a. programmable through registers 4ch?54h. default input. gpio_b 15 i/o general-purpose i/o b. programmable through registers 4ch?54h. default input. power signals v d 4 i digital supply voltage. provides the digital supply voltage to the pct303a. nomi- nally either 3.3v or 5v. v a 13 i analog supply voltage. provides the analog supply voltage to the pct303a. nom- inally 5v. gnd 12 i ground. connects to the system digital ground. also connects to capacitor c2.
pc-tel, inc. 7 2303n0docdat10a-0899 PCT2303N data sheet p i n d e s c r i p t i o n s ! ! pct303l pin descriptions table 2 pct303l pin descriptions name number i/o description line interface tx 16 o transmit output. provides the output, through an ac termination impedance, to the telephone network. rx 14 i receive input. serves as the receive side input from the telephone network. dct 12 dc termination. provides dc termination to the telephone network. rext 13 external resistor. connects to an external resistor. rng1 5 i ring 1 input. connects through a capacitor to the ?tip? lead of the telephone line. pro- vides the ring and caller id signals to the PCT2303N. rng2 6 i ring 2 input. connects through a capacitor to the ?ring? lead of the telephone line. pro- vides the ring and caller id signals to the PCT2303N. qb 7 transistor base. connects to the base of the hookswitch transistor. qe 8 transistor emitter. connects to the emitter of the hookswitch transistor. hybd 11 o hybrid node output. balancing capacitor connection used for jate out-of-band noise support. isolation c1b 4 isolation capacitor 1b. connects to one side of isolation capacitor c1. ignd 3 isolated ground. connects to ground on the line-side interface. also connects to capac- itor c2. miscellaneous signals vreg 9 voltage regulator. connects to an external capacitor to provide bypassing for an inter- nal voltage regulator. tsta 1 i test input a. allows access to test modes, which are reserved for factory use. this pin has an internal pull-up and should be left as a no-connect for normal operation. tstb 2 i test input b. allows access to test modes, which are reserved for factory use. this pin has an internal pull-up and should be left as a no-connect for normal operation. nc 10,15 no connection. this is an unused pin and must be left floating.
pc-tel, inc. 8 2303n0docdat10a-0899 PCT2303N data sheet f u n c t i o n a l d e s c r i p t i o n ! ! f u n c t i o n a l d e s c r i p t i o n the PCT2303N is an integrated chipset that provides a low-cost, isolated, silicon-based mc97-compliant interface to the telephone line. the PCT2303N saves cost and board area by eliminating the need for a modem afe or serial codec. it also eliminates the need for an isolation transformer, relays, opto-isolators, and a 2- to 4-wire hybrid. the PCT2303N solution complies with ac?97/mc?97 interface specification rev. 2.1. see ac-link ac-link is a bidirectional, fixed rate, serial pcm digital stream. it handles multiple input and output audio streams and control register accesses employing a time division multiplexed (tdm) scheme. the ac-link architecture divides each audio frame into 12 outgoing and 12 incoming data streams, each with 20-bit sample resolution. the ac-link serial interconnect defines a digital data and control pipe between the controller and the codec. the ac-link supports 12 20-bit slots at 48 khz on sdata_in and sdata_out. the tdm ?slot-based? architecture supports a per-slot valid tag infrastructure that is the source of each slot?s data sets or clears to indicate the validity of the slot data within the current audio frame. for modem afe, data streams at a variety of required sample rates can be supported. isolation barrier the PCT2303N achieves an isolation barrier through a low-cost, high-voltage capacitor in conjunction with pc- tel?s proprietary signal processing techniques. these techniques eliminate any signal degradation due to capacitor mismatches, common mode interference, or noise coupling. all transmit, receive, and control data are communicated through this barrier. off-hook the communication system generates an off-hook command by writing a logic 1 to bit 0 (line 1) or bit 10 (line 2) of slot 12. the off-hook state is used to seize the line for an outgoing call and can also be used for pulse dialing. when the part is not in the off-hook state, negligible dc current flows through the hookswitch. in the off-hook state, the hookswitch transistor pair, q1 & q2, turn on. ring detect the ring signal enters the pct303l through low-value capacitors connected to tip and ring. the integrated ring detect of the PCT2303N allows it to present the ring signal to the ac?97 controller through the serial port with no additional signaling required. the signal sent to the ac?97 controller is a clipped version of the original ring signal. the system can detect a ring occurring by the status of the rdt bit of slot 12. this bit is a read-only bit that is set when the line-side device detects a ring signal at rng1 and rng2. when this state occurs, the line-side chip draws a small amount of dc current from the line to provide the digitized line data to the ac?97 controller. this bit clears either when the system goes off-hook or four to eight seconds after the last ring is detected. lightning test the PCT2303N meets the lightning test requirements of fcc part 68. safety and isolation the PCT2303N meets the requirements of fcc part 68 and ul. digital interface the id pins configure the pct303a as a primary or secondary ac?97 device as shown in table 3. the following sections describe pct303a operation. pct303a as secondary device the pct303a can operate as a secondary device, which allows up to two pct303as to exist on the ac-link along with a primary device. the primary device can be an ac?97 rev. 2.1-compatible codec or a pct303a configured as the primary device. when configured as a secondary device, the pct303a?s bit_clk becomes an input and is used as the master clock. therefore, xin is not used and should be grounded. table 3 device id configuration id1 id0 description 1 1 primary device 1 0 secondary device #1 0 1 secondary device #2 0 0 factory test
pc-tel, inc. 9 2303n0docdat10a-0899 PCT2303N data sheet f u n c t i o n a l d e s c r i p t i o n ! ! pct303a as primary mc?97 codec the PCT2303N can operate as a primary ac?97 rev 2.1 compatible codec. however, when there is an audio ac?97 codec present on the ac-link, the PCT2303N should be configured as a secondary codec, and the audio ac?97 codec should be configured as the primary. when the pct303a is configured as a primary device, it requires a 24.576 mhz crystal across the xin and xout pins. an external 24.576 mhz master clock can also be applied to xin. pct303a connection to ac?97 controller the pct303a communicates with its companion ac?97 controller through a digital serial link called the ac-link . all digital audio streams, optional modem line codec streams, and command/status information is communicated over this point to point serial interconnect. figure 3 illustrates the breakout of the connecting signals. figure 3 PCT2303N chipset connection to ac?97 controller (primary device configuration) clocking the pct303a derives its internal clock, when primary, from the 24.576 mhz clock and drives a buffered and divided down (1/2) clock to its digital companion controller over the ac-link through the bit_clk signal. clock jitter at the dacs and adcs is a fundamental impediment to high quality output, and the internally generated clock provides the pct303a with a clean clock that is independent of the physical proximity of the pct303a?s companion ac?97 controller. the beginning of all audio sample packets, or audio frames, transferred over the ac-link is synchronized to the rising edge of the sync signal. sync is driven by the ac?97 controller. the ac?97 controller takes bit_clk as an input and generates sync by dividing bit_clk by 256 and applying some conditioning to tailor its duty cycle. this yields a 48-khz sync signal whose period defines an audio frame. data is transitioned on the ac-link on each rising edge of bit_clk, and subsequently sampled on the receiving side of the ac-link on each immediately following falling edge of bit_clk. resetting the PCT2303N there are three types of reset: ? cold reset ?initializes all pct2 303n logic (registers included) to its default state. initiated by bringing reset low at least 1 s when bit_clk is inactive. ? warm reset ?leaves the register contents unaltered. initiated by bringing sync high for at least 1 s in the absence of bit_clk. ? register reset ?initializes only the registers to their default states. initiated by a write to register 3ch. after signaling a reset to the PCT2303N, the ac?97 controller should not attempt to play or capture modem data until it has sampled a codec ready indication from the PCT2303N. ac-link digital serial interface protocol the pct303a incorporates a 5-pin digital serial interface that links it to the ac?97 controller. the ac-link is a bidirectional, fixed rate, serial pcm digital stream. it handles multiple input and output audio streams (including modems), as well as control register digital ac?97 controller pct303a sync bit_clk sdata_out sdata_in reset
pc-tel, inc. 10 2303n0docdat10a-0899 PCT2303N data sheet f u n c t i o n a l d e s c r i p t i o n ! ! accesses employing a tdm scheme. the ac-link architecture divides each audio frame into 12 outgoing and 12 incoming data streams, each with 20-bit sample resolution. in primary device mode, the pct303a data streams are as follows: ? control ?control register write port; two output slots. ? status ?control register read port; two input slots. ? modem line codec output ?modem line codec dac input stream; one output slot per line. ? modem line codec input ?modem line codec adc output stream; one input slot per line. ? i/o control ?daa control and gpio; one output slot. ? i/o status ?daa status and gpio; one input slot. synchronization of all ac-link data transactions is signaled by the ac?97 controller. the pct303a drives the serial bit clock onto the ac-link, which the ac?97 controller then qualifies with a synchronization signal to construct audio frames. the sync signal, fixed at 48 khz, is derived by dividing down the serial bit clock (bit_clk). bit_clk, fixed at 12.288 mhz, provides the necessary clocking granularity to support 12 20-bit outgoing and incoming time slots. ac-link serial data is transitioned on each rising edge of bit_clk. the receiver of ac-link data, the pct303a for outgoing data and the ac?97 controller for incoming data, samples each serial bit on the falling edges of bit_clk. the ac-link protocol provides for a special 16-bit time slot (slot 0) wherein each bit conveys a valid tag for its corresponding time slot within the current audio frame. a 1 in a given bit position of slot 0 indicates that the corresponding time slot within the current audio frame has been assigned to a data stream and contains valid data. if a slot is tagged invalid, it is the responsibility of the data source (the pct303a for the input stream, the ac?97 controller for the output stream) to populate all bit positions with 0s during that slot?s active time. sync remains high for a total duration of 16 bit_clks at the beginning of each audio frame. the portion of the audio frame where sync is high is called the tag phase. the remainder of the audio frame where sync is low is called the data phase. additionally, for power savings, all clock, sync, and data signals can be halted. the PCT2303N maintains its register contents intact when entering a power-savings mode. figure 4 standard bidirectional audio frame audio output frame (sdata_out) the audio output frame data streams correspond to the multiplexed bundles of all digital output data targeting the PCT2303N?s dac inputs and control registers. each audio output frame supports up to 12 20-bit outgoing data time slots. slot 0 is a special reserved time slot containing 16 bits used for ac-link protocol infrastructure. within slot 0, the first bit is a global bit (sdata_out slot 0, bit 15) which flags the validity for the entire audio frame. if the valid frame bit is a 1, the current audio frame contains at least one slot time of valid data. the next 12 bit positions sampled by the pct303a indicate which of the corresponding 12 time slots contain valid data. in this way, data streams of differing sample rates can be transmitted across the ac-link at its fixed 48-khz audio frame rate. figure 5 illustrates the time slot-based ac-link protocol. slot # 0 1 2 3 4 5 6 7 8 9 10 11 12 tag cmd addr cmd data pcm l pcm r line 1 dac pcm center pcm l surr pcm r surr pcm lfe line 2 dac hset dac io ctrl pcm l (n+1) pcm r (n+1) pcm c (n+1) tag status addr status data pcm l pcm r line 1 adc mic adc rsrvd rsrvd rsrvd line 2 adc hset adc io status slotreq 3-12 codec id sync sdata_out sdata_in
pc-tel, inc. 11 2303n0docdat10a-0899 PCT2303N data sheet f u n c t i o n a l d e s c r i p t i o n ! ! figure 5 ac-link audio output frame a new audio output frame begins with a low to high transition of sync. sync is synchronous to the rising edge of bit_clk. on the immediately following falling edge of bit_clk, the pct303a samples the assertion of sync. this falling edge marks the time when both sides of the ac-link are aware of the start of a new audio frame. on the next rising of bit_clk, the ac?97 controller transitions sdata_out into the first bit position of slot 0 (valid frame bit). each new bit position is presented to the ac-link on a rising edge of bit_clk, and subsequently sampled by the pct303a on the following falling edge of bit_clk. this sequence ensures that data transitions and subsequent sample points for both incoming and outgoing data streams are time aligned. see figure 6. figure 6 start of an audio output frame sdata_out?s composite stream is msb justified (msb first) with all non-valid slots? bit positions padded with 0s by the ac?97 controller. in the event that there are less than 20 valid bits within an assigned and valid time slot, the ac?97 controller always pads all trailing non-valid bit positions of the 20- bit slot with 0s. variable sample rate signaling protocol for variable sample rate output, the codec examines its sample rate control registers, the state of its fifos, and the incoming sdata_out tag bits at the beginning of each audio output frame to determine which slotreq bits (bit 4 or 9 in input slot 1) to set active (low). slotreq bits asserted during the current audio input frame signal which active output slots require data from the ac?97 digital controller in the next audio output frame. an active output slot is defined as any slot supported by the codec that is not in a power-down state. slot 1: command address port the command address port controls features and monitors status (see audio input frame slots 1 and 2) for PCT2303N functions including, but not limited to, sample rate, afe configuration, and power management. the control interface architecture supports up to 64 16-bit read/write registers addressable on even byte boundaries. only the even registers (00h, 02h, etc.) are valid; odd register (01h, 03h, etc.) writes are ignored and reads return 0. note that shadowing of the control register file on the ac?97 controller is an option left open to the implementation of the ac?97 controller. the PCT2303N?s control register file is readable as well as writable to provide more robust testability. audio output frame slot 1 communicates control register address and write/read command information to the PCT2303N. command address port bit assignments: ? bit 19?read/write command (1=read, 0=write) ? bits 18:12?control register index (64 16-bit locations, addressed on even byte boundaries) ? bits 11:0?reserved (padded with 0s)
pc-tel, inc. 12 2303n0docdat10a-0899 PCT2303N data sheet f u n c t i o n a l d e s c r i p t i o n ! ! the first bit (msb) sampled by the pct303a indicates whether the current control transaction is a read or a write operation. the following seven bit positions communicate the targeted control register address. the trailing 12 bit positions within the slot are reserved and must be padded with 0s by the ac?97 controller. slot 2: command data port the command data port delivers 16-bit control register write data in the event that the current command port operation is a write cycle as indicated by slot 1, bit 19. command data port bit assignments: ? bits 19:4?control register write data (padded with 0s if the current operation is a read) ? bits 3:0?reserved (padded with 0s) slot 5: modem line 1 codec modem output frame slot 5 contains the msb justified modem dac input data for phone line #1. the PCT2303N?s modem dac input resolution is 16 bits. slot 10: modem line 2 dac line 2 is assigned to slot 10. the leading 16 bits of each slot must contain valid sample data (msb bit 19, lsb4). slot 12: modem gpio control slot 12 contains latency critical signals for the pct303l and the gpio of the pct303a. see table 4. slots 3, 4, 6?9, 11: not used the PCT2303N always pads audio output frame slots 3, 4, 6?9, and 11 with 0s. table 4 slot 12 gpio name sense description gpio15 line2_gpio_b in/out gpio pin b, line 2 gpio14 line2_gpio_a in/out gpio pin a, line 2 gpio13 line2_dlcs in delta loop current sense, line 2 gpio12 line2_cid out caller id path enable, line 2 gpio11 line2_ri in ring detect, line 2 gpio10 line2_oh out off hook, line 2 gpio[9:6] reserved gpio5 line1_gpio_b in/out gpio pin b, line 1 gpio4 line1_gpio_a in/out gpio pin a, line 1 gpio3 line1_dlcs in delta loop current sense, line 1 gpio2 line1_cid out caller id path enable, line 1 gpio1 line1_ri in ring detect, line 1 gpio0 line1_oh out off hook, line 1 vendor optional bit 3 reserved bit 2 line2_fdt in frame detect, line 2 bit 1 line1_fdt in frame detect, line 1 bit 0 gpio_int in gpio state change
pc-tel, inc. 13 2303n0docdat10a-0899 PCT2303N data sheet f u n c t i o n a l d e s c r i p t i o n ! ! audio input frame (sdata_in) the audio input frame data streams correspond to the multiplexed bundles of all digital input data targeting the ac?97 controller. this is the case with the audio output frame; each ac-link audio input frame consists of 12 20-bit time slots. slot 0 is a special reserved time slot containing 16 bits that are used by the ac-link protocol infrastructure. within slot 0, the first bit is a global bit (sdata_in slot 0, bit 15) that flags whether the pct303a is in the codec ready state or not. if the codec ready bit is a 0, the pct303a is not ready for normal operation. this condition is normal following the deassertion of reset (e.g., while the pct303a?s voltage references settle). when the ac-link codec ready indicator bit is a 1, the ac-link and pct303a control and status registers are in a fully operational state. the ac?97 controller must further probe the power-down control/status register to determine exactly which subsections, if any, are ready. before any attempts to put the PCT2303N into operation, the ac?97 controller must poll the first bit in the audio input frame (sdata_in slot 0, bit 15) for an indication that the pct303a is codec ready. when the pct303a is sampled codec ready, then the next 12 bit positions sampled by the ac?97 controller indicate which of the corresponding 12 time slots are assigned to input data streams, and that they contain valid data. figure 7 illustrates the time slot-based ac-link protocol. figure 7 ac-link audio input frame a new audio input frame begins with a low to high transition of sync. sync is synchronous to the rising edge of bit_clk. on the immediately following falling edge of bit_clk, the pct303a samples the assertion of sync. this falling edge marks the time when both sides of the ac-link are aware of the start of a new audio frame. on the next rising of bit_clk, the pct303a transitions sdata_in into the first bit position of slot 0 (codec ready bit). each new bit position is presented to the ac-link on a rising edge of bit_clk and subsequently sampled by the ac?97 controller on the following falling edge of bit_clk. this sequence ensures that data transitions and subsequent sample points for both incoming and outgoing data streams are time aligned. sdata_in?s composite stream is msb justified (msb first) with all non-valid bit positions (for assigned and unassigned time slots) padded with 0s by the pct303a. sdata_in data is sampled on the falling edges of bit_clk by the ac?97 controller. slot 1: status address port the status address port monitors status for pct303a functions including, but not limited to, line-side configuration. audio input frame slot 1?s stream echoes the control register index, for historical reference, for the data to be returned in slot 2. (assuming that slots 1 and 2 had been tagged ?valid? by the pct303a during slot 0). status address port bit assignments: ? bit 19?reserved (padded with 0) ? bits 18:12?control register index (echo of register index for which data is being returned) ? bits 11:2?slotreq bits, bit 9 for line 1 and bit 4 for line 2. (see ? variable sample rate signaling protocol ? on page11 for more details). ? bits 1:0?reserved (padded with 0s) the first bit (msb) generated by the pct303a is always padded with a 0. the following seven bit positions communicate the associated control register address and the trailing 12 bit positions are padded with 0s by the pct303a.
pc-tel, inc. 14 2303n0docdat10a-0899 PCT2303N data sheet f u n c t i o n a l d e s c r i p t i o n ! ! slot 2: status data port the status data port delivers 16-bit control register read data. status data port bit assignments: ? bits 19:4?control register read data (padded with 0s if tagged invalid by the pct303a) ? bits 3:0?reserved (padded with 0s) if slot 2 is tagged invalid by the pct303a, then the entire slot is padded with 0s by the pct303a. slot 5: modem line 1 codec audio input frame slot 5 contains msb-justified modem adc output data for phone line #1 (id = 0 or 1). the modem adc output resolution is 16bits. the PCT2303N ships out its adc output data (msb first), and pads any trailing non-valid bit positions with 0s to fill out its 20-bit time slot. slot 10: modem line 2 code audio input frame for line 2. slot 12: modem gpio status slot 12 contains latency critical signals for pct303l and the gpio of the pct303a. slot 12 also reflects the status of the link between the pct303a and pct303l. table4 on page12. ac-link low power mode the ac-link signals can be placed in a low-power mode. when ac?97?s power-down register is programmed to the appropriate value, both bit_clk and sdata_in are brought to, and held, at a logic low voltage level. figure 8 ac-link power-down timing bit_clk and sdata_in are transitioned low immediately following the decode of the write to the register 56h with mlnk. when the ac?97 controller driver is at the point where it is ready to program the ac-link into its low-power mode, slots 1 and 2 are assumed to be the only valid stream in the audio output frame. the ac?97 controller should also drive sync and sdata_out low after programming the PCT2303N to this low-power mode. when the PCT2303N has been instructed to halt bit_clk, a special wake up protocol must be used to bring the ac-link to the active mode because normal audio output and input frames cannot be communicated in the absence of bit_clk. note: the pct 2303n ?s pll must be initialized before being placed in sleep mode. pll is initialized by writing a sample rate in register 40h (42h). waking up the ac-link there are two methods for bringing the ac-link out of a low-power, halted mode. regardless of the method, the ac?97 controller performs the wake-up task. ac-link protocol provides for a cold reset and a warm reset. the current power down state ultimately dictates which form of reset is appropriate. unless a cold or register reset (a write to the reset register) is performed, wherein the registers are initialized to their default values, registers are required to keep state during all power-down modes. when powered down, reactivation of the ac-link through reassertion of the sync signal must not occur for a minimum of four audio frame times following the frame in which the power down was triggered. when the ac-link powers up, the pct303a indicates readiness through the codec ready bit (input slot 0, bit 15). the PCT2303N can be enabled to indicate a power management event has occurred (e.g., ring detection) while in low-power mode. see ? gpio pin wake-up mask (register 52h, r/w) ? on page21 for more details. PCT2303N cold reset a cold reset is achieved by asserting reset for the minimum specified time. by driving reset low, bit_clk and sdata_out are activated, or re- activated, and all PCT2303N control registers are initialized to their default power on reset values. it should be noted that while reset is low, the PCT2303N remains active. upon the rising edge of reset the pct303a performs a cold reset. reset is an asynchronous pct303a input. PCT2303N warm reset a warm reset reactivates the ac-link without altering the current PCT2303N register values. a warm reset is signaled by driving sync high for a minimum of 1 s in the absence of bit_clk.
pc-tel, inc. 15 2303n0docdat10a-0899 PCT2303N data sheet f u n c t i o n a l d e s c r i p t i o n ! ! within normal audio frames, sync is a synchronous pct303a input. however, in the absence of bit_clk, sync is treated as an asynchronous input used in the generation of a warm reset to the PCT2303N. the primary ac?97 codec does not respond with the activation of bit_clk until sync has been sampled low again by ac?97. this precludes the false detection of a new audio frame. analog output the pct303a supports an analog output (aout) for driving the call progress speaker found with most of today?s modems. aout is an analog signal comprised of a mix of the transmit and receive signals. the receive portion of this mixed signal has a 0 db gain while the transmit signal has a gain of ?20 db. the transmit and receive portions of the aout signal have independent mute controls found in register 5ch. developer?s kit application schematics illustrate a recommended application circuit. note that in the configuration shown, the lm386 provides a gain of 26 db. make additional gain adjustments by varying r1. on-hook line monitor (cid) the PCT2303N allows the user to detect line activity when the device is in an on-hook state. when the system is on-hook, the line data can be passed to the ac?97 controller across the serial port while drawing a small amount of dc current from the line. this process is identical to the passing of line information while on-hook following a ring signal detection. to activate this feature, set the line1_cid/line2_cid bit in slot 12. loop current monitor when the system is in an off-hook state, the lcs bits of register 5ch indicate the approximate amount of dc loop current that is flowing in the loop. the lcs is a 4-bit value ranging from zero to fifteen. each unit represents approximately 6 ma of loop current from lcs codes 1-14. the typical lcs transfer function is shown in figure 9. figure 9 typical lcs transfer function an lcs value of zero means the loop current is less than required for normal operation and the system should be on-hook. typically, an lcs value of 15 means the loop current is greater than 120ma. the lcs detector has a built-in hysteresis of 2 ma of current. this allows for a stable lcs value when the loop current is near a transition level. the lcs value is a rough approximation of the loop current, and the designer is advised to use this value in a relative means rather than an absolute value. this feature enables the modem to determine if an additional line has ?picked up? while the modem is transferring information. in the case of a second phone going off-hook, the loop current falls approximately 50% and is reflected in the value of the lcs bits. gain control the PCT2303N supports multiple gain and attenuation settings in register 46h/48h for the receive and transmit paths, respectively. the receive path can support gains of 0, 3, 6, 9, and 12 db. the gain is selected by bits 3:1 (adc3:1). the receive path can also be muted by setting bit 7. the transmit path can support attenuations of 0, 3, 6, 9, and 12 db. the attenuation is selected by bits 11:9 (dac3:1). the transmit path can also be muted by setting bit 15. filter selection the pct303a supports additional filter selections for the receive and transmit signals. the iire bit of register 5ch, when set, enables the iir filters. this filter provides a much lower, however non-linear, group delay than the default fir filters. 15 0 0 5 10 6 12 66 60 54 48 42 36 30 24 18 72 78 84 90 96 140 lcs bit loop current (ma)
pc-tel, inc. 16 2303n0docdat10a-0899 PCT2303N data sheet f u n c t i o n a l d e s c r i p t i o n ! ! charge pump the pct303a has an integrated charge pump for 3.3v- only operation. the isocap requires a 5v supply that can come from either the v a pin or the internal charge pump. for 3.3v-only operation, r3 must not be installed. the charge pump by default is set to be the 5v supply after the sample rate register is programmed. to use a separate 5v supply, connect 5v through r3 and set register 5eh, bit 10 (pdc) to 1. the pdc must be set before the sample rate register is written. in-circuit testing the PCT2303N?s advanced design provides the modem manufacturer with increased ability to determine system functionality during production line tests, as well as user diagnostics. several loopback modes exist allowing increased coverage of system components. the loopback mode allows the data pump to provide a digital input test pattern on sdata_in and receive that digital test pattern back on sdata_out. to enable this mode, set l1b2:0(l2b2:0)=101 in register 56h. in this mode, the isolation barrier is actually being tested. the digital stream is delivered across the isolation capacitors, c1 and c2 to the line-side device and returned across the same barrier. the digital dac loopback mode allows data to be sent on the digital path from sdata_in to the digital section of dac to adc to sdata_out. this loopback mode is used when the line-side chip is in power-down mode. to enable this mode, set l1b2:0(l2b2:0) = 011 in register56h. the remote analog loopback mode allows an external device to drive the receive pins of the line-side chip and receive the signal from the transmit pins. this mode allows testing of external components connecting the rj-11 jack (tip and ring) to the line side of the pct303l. to enable this mode, set l1b2:0(l2b2:0) = 100 in register 56h. the adc loopback mode allows an external device to drive the receive pins of the pct303l. the signal is then digitized on the pct303l and sent to the pct303a, which sends the data back to the pct303l. the signal is then converted back to analog. the external device receives the signal on the transmit pins. this mode allows testing of the PCT2303N?s converters and external devices between the pct303l and rj-11 jack. to enable this mode, set the l1b2:0(l2b2:0) = 001. the final two testing modes, local analog loopback and external analog loopback, allow the system to test the basic operation of the converters on the line side and the functionality of the external components. in local analog loopback mode, the ac?97 controller provides a digital test waveform on sdata_in. this data is passed across the isolation barrier, converted to analog, internally looped to the receive path, converted to digital, passed back across the isolation barrier, and presented to the ac?97 controller. to enable local and analog loopback, set l1b2:0 (l2b2:0) = 010. external analog loopback mode allows the system to test external components by passing converted data (from sdata_in) to the transmit pin, which is looped externally to the receive pin. to enable external analog loopback, set l1b2:0 (l2b2:0) = 110. both analog loopback modes require power, which is typically supplied by the loop current from tip and ring.
pc-tel, inc. 17 2303n0docdat10a-0899 PCT2303N data sheet c o n t r o l r e g i s t e r s ! ! c o n t r o l r e g i s t e r s any register not listed here is reserved and should not be written. undefined/unimplemented registers return 0. extended modem id (register 3ch, r/w) reset settings (dependent on pins id1 and id0 ) = 0001h; 8002h; 4001h; cxxxh bit definitions: extended modem status and control (register 3eh, r/w) reset settings = ff00h bits 13:8 are read/write and control modem afe subsystem power-down. when these bits are all set to 1, the pct303l is powered down. bits 7:0 are read-only; 1 indicates modem afe subsystem readiness. bit definitions: id[1:0] reserved lin2 lin1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bits name description 15:14 id[1:0] indicates codec configuration . 13:2 reserved reserved. 1 lin2 1 = 2nd line is supported; id[1:0] = 10. codec data is transferred in slot 10. 0 lin1 1 = 1st line is supported; id[1:0] = 01. codec data is transferred in slot 5. reserved prf pre prd prc prb pra reserved dac2 adc2 dac1 adc1 mref gpio 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 id[1:0] description 00 primary 01 secondary 10 secondary 11 factory test bits name description 15:14 reserved reserved. 13 prf 1 = modem line 2 dac off. 12 pre 1 = modem line 2 adc off. 11 prd 1 = modem line 1 dac off. 10 prc 1 = modem line 1 adc off. 9 prb reserved for future use. 8 pra 1 = gpio power-down. 7:6 reserved reserved. 5 dac2 read-only. 1 = modem line 2 dac ready. 4 adc2 read-only. 1 = modem line 2 adc ready. 3 dac1 read-only. 1 = modem line 1 dac ready. 2 adc1 read-only. 1 = modem line 1 adc ready. 1 mref read-only. 1 = modem vrefs up to nominal level. 0 gpio read-only. 1 = gpio ready.
pc-tel, inc. 18 2303n0docdat10a-0899 PCT2303N data sheet c o n t r o l r e g i s t e r s ! ! line 1 dac/adc rate (register 40h, r/w) reset settings = 0000h each dac/adc pair is governed by a read/write modem sample rate control register that contains a 16-bit unsigned value between 0 and 65535, representing the rate of operation in hz. a number written over 2ee0h causes the sample rate to 13.714 khz. for all rates, if the value written to the register is supported, that value is echoed back when read, otherwise the closest rate supported is returned. when set to zero, the internal pll is disabled. the pll should be programmed before the line-side (pct303l) is activated through clearing any pr bit in register 3eh. sleep mode is not supported when the pll is disabled. line 2 dac/adc rate (register 42h, r/w) reset settings = 0000h sample rates for line 2 are the same as for line 1, refer to table 5. sr[15:0] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 table 5 sample rates for line 1 and line 2 sample rate d[15:0] 7200 1c20h 8000 1f40h 8228.57 (57600/7) 2024h 8400 20d0h 9000 2328h 9600 2580h 10285.71 (72000/7) 282dh 12000 2ee0h 13714.28 (96000/7) 3592h sr[15:0] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
pc-tel, inc. 19 2303n0docdat10a-0899 PCT2303N data sheet c o n t r o l r e g i s t e r s ! ! line 1 dac/adc level (register 46h, r/w) reset settings = 8080h this read/write register controls the modem afe dac and adc levels. the default value after cold register reset for this register (8080h) corresponds to 0 db dac attenuation with mute on and 0 db adc gain with mute on. bit definitions: mute reserved dac[3:1] r mute reserved adc[3:1] r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bits name description 15 mute transmit mute. 1 = mute on. 14:12 reserved reserved. 11:9 dac[3:1] analog transmit attenuation. 8 reserved reserved. 7 mute receive mute. 1 = mute on. 6:4 reserved reserved. 3:1 adc[3:1] analog receive gain. 0 reserved reserved. dac[3:1] description 000 0db attenuation. 001 3db attenuation. 010 6db attenuation. 011 9db attenuation. 1xx 12db attenuation. adc[3:1] description 000 0db gain. 001 3db gain. 010 6db gain. 011 9db gain. 1xx 12db gain.
pc-tel, inc. 20 2303n0docdat10a-0899 PCT2303N data sheet c o n t r o l r e g i s t e r s ! ! line 2 dac/adc level (register 48h, r/w) reset settings = 8080h this read/write register controls the modem afe dac and adc levels. the default value after cold register reset for this register (8080h) corresponds to 0 db dac attenuation with mute on and 0 db adc gain with mute on. bit definitions: gpio pin configuration (register 4ch, r/w) reset setting for line 1 device = 003fh reset setting for line 2 device = fc00h the gpio pin configuration register is read/write for configuring slot 12 i/o. these pins are digital commands (virtual pins). this register specifies whether a gpio pin is configured for input (1) or output (0). the digital controller sends the desired gpio pin value over output slot 12 in the outgoing stream of the ac-link before configuring any of these bits for output. mute reserved dac[3:1] r mute reserved adc[3:1] r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bits name description 15 mute transmit mute. 1 = mute on. 14:12 reserved reserved. 11:9 dac[3:1] analog transmit attenuation. 8 reserved reserved. 7 mute receive mute. 1 = mute on. 6:4 reserved reserved. 3:1 adc[3:1] analog receive gain. 0 reserved reserved. read returns zero. gc[15:10] reserved gc[5:0] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dac[3:1] description 000 0db attenuation. 001 3db attenuation. 010 6db attenuation. 011 9db attenuation. 1xx 12db attenuation. adc[3:1] description 000 0db gain. 001 3db gain. 010 6db gain. 011 9db gain. 1xx 12db gain.
pc-tel, inc. 21 2303n0docdat10a-0899 PCT2303N data sheet c o n t r o l r e g i s t e r s ! ! gpio pin polarity and type (register 4eh, r/w) reset settings = ffffh the gpio pin polarity and type register is read/write for selecting the polarity and type for slot 12 i/o. this register defines gpio input polarity (0 = low; 1 = high active) when a gpio pin is configured as an input. it defines gpio output type (0 = cmos; 1 = open-drain) when a gpio pin is configured as an output. the default value after soft reset (ffffh) is all pins active-high. unimplemented gpio pins always return 1s. gpio pin sticky (register 50h, r/w) reset settings = 0000h the gpio pin sticky register is a read/write register. it defines the gpio input type (0 = non-sticky; 1 = sticky) when a gpio pin (defined in slot 12 i/o) is configured as an input. this applies to ring detect, delta loop current sense, and gpio_a bits. gpio inputs configured as sticky are cleared only by writing a 0 to the corresponding bit of the gpio pin status register 54h, and by reset. the default value after cold register reset (0000h) is all pins non-sticky. unimplemented gpio pins always return zeros. sticky is defined as edge-sensitive; non-sticky is defined as level-sensitive. gpio pin wake-up mask (register 52h, r/w) reset settings = 0000h the gpio pin wake-up mask register is a read/write register that provides a mask for determining if an input gpio change will generate a wake-up or gpio_int (0 = no; 1 = yes). when the ac-link is powered down, a wake-up event triggers the assertion of sdata_in. when the ac-link is powered up, a wake-up event appears as gpio_int = 1 on bit 0 of input slot 12. ring-detection wake-up can be enabled or disabled. an ac-link wake-up interrupt is defined as a 0-to-1 transition on sdata_in when the ac-link is powered down. gpio bits that have been programmed as inputs, sticky, and pin wake-up, upon transition (either high-to-low or low- to-high) depending on pin polarity, cause an ac-link wake-up event, if the ac-link was powered down. the default value after cold register reset (0000h) defaults to all 0s specifying no wake-up event. this applies to ring detect, delta loop current sense, gpio_a, and gpio_b bits. unimplemented gpio pins always return 0s. gp[15:10] reserved gp[5:0] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 gs[15:13] r gs11 reserved gs[5:3] r gs1 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 gw[15:10] reserved gw[5:0] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
pc-tel, inc. 22 2303n0docdat10a-0899 PCT2303N data sheet c o n t r o l r e g i s t e r s ! ! gpio pin status (register 54h, r/w) reset settings = xxxxh the gpio status register is a read/write register that reflects the state of all gpio pins (inputs and outputs) on slot 12. the value of all gpio pin inputs and outputs comes from each frame on slot 12, but is also available for reading as gpio pin status through the standard slot 1 and 2 command address/data protocols. gpio inputs configured as sticky are cleared by writing a 0 to the corresponding bit of this register. this should be the last event before setting the ac?97 mlnk bit. bits corresponding to unimplemented gpio pins should be forced to zero in this register and input slot 12. gpio bits that have been programmed as inputs and sticky, upon transition (high-to-low or low-to-high), cause the individual gi bit to go asserted to 1, and remain asserted until a write of 0 to that bit. the only way to set the desired value of a gpio output pin is to set the control bit in output slot 12. if configured as an input, the default value after register reset is always the state of the gpio pin. gi[15:10] reserved gi[5:0] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
pc-tel, inc. 23 2303n0docdat10a-0899 PCT2303N data sheet c o n t r o l r e g i s t e r s ! ! miscellaneous modem afe status and control (register 56h, r/w) reset settings = 0000h this read/write register defines the loopback modes available for the modem line adcs/dacs. the default value after cold register reset (0000h) is all loopbacks disabled. bit definitions: figure 10 loopback points reserved mlnk reserved l2b[2:0] r l1b[2:0] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bits name description 15:13 reserved reserved. read returns zero. 12 mlnk controls an mc?97?s ac-link status. 1 = sets the mc?97 ac-link to off (sleep). 0 = sets the mc?97 ac-link to on (active). 11:7 reserved reserved. read returns zero. 6:4 l2b[2:0] line 2 loopback modes. 3 reserved reserved. read returns zero. 2:0 l1b[2:0] line 1 loopback modes. l2b[2:0] description 000 disabled (default). 001 adc loopback (i ? b). 010 local analog loopback (f ? m). 011 digital dac loopback (c ? j). 100 remote analog loopback (m? ? f). 101 isolation cap loopback (d ? k). 110 external analog loopback (g ? n). 111 reserved. l1b[2:0] description 000 disabled (default). 001 adc loopback (i ? b). 010 local analog loopback (f ? m). 011 digital dac loopback (c ? j). 100 remote analog loopback (m ? f). 101 isolation cap loopback (d ? k). 110 external analog loopback (g ? n). 111 reserved. 303a 303l a b c e f h i j l m ac link digital filter digital filter analog dac analog adc i/o pad i/o pad dac adc k d output input n g note: for all loopback modes except 011, line side must be powered on and off-hook.
pc-tel, inc. 24 2303n0docdat10a-0899 PCT2303N data sheet c o n t r o l r e g i s t e r s ! ! chip id and revision (register 5ah, r) reset settings = n/a note: the line side must be activated through the pr bits before valid read. bit definitions: line-side configuration 1 (register 5ch, r/w) reset settings = f010h shaded bit descriptions are for international line-side support only. bit definitions: reserved cbid revb[3:0] reva[3:0] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bits name description 15:9 reserved reserved. read returns zero. 8 cbid chip b (line-side) id. 1 = line side has international support. 0 = line side is domestic. 7:4 revb[3:0] chip revision. four-bit value indicates the pct303l (line-side) silicon revision. 3:0 reva[3:0] chip revision. four-bit value indicates the pct303a silicon revision. arm[1:0] atm[1:0] iire resereved reserved rt 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bits name description 15:14 arm[1:0] analog (call progress) receive path mute. 13:12 atm[1:0] analog (call progress) transmit path mute. 11 iire iir filter enable. 1 = transmit and receive filters are realized with an iir filter characteristic. 2:1 reserved reserved. read returns zero. arm[1:0] description 00 0db 01 ?6db 10 ?12db 11 mute arm[1:0] description 00 0db 01 ?6db 10 ?12db 11 mute
pc-tel, inc. 25 2303n0docdat10a-0899 PCT2303N data sheet c o n t r o l r e g i s t e r s ! ! line-side configuration 2 (register 5eh, r/w) reset settings = 0000h note: the line side must be activated through the pr bits before valid read/write. shaded bit descriptions are for international line-side support only. bit definitions: vendor id (register 7ch, r/w) vendor id (register 7eh, r/w) reset settings = n/a these registers are for specific vendor identification. the id method is microsoft?s plug and play vendor id code with f7..0 being the first character of that id, s7..0 being the second character, and t7..0 the third character. these three characters are ascii encoded. reserved pdc reserved cle fdt lcs[3:0] reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bits name description 15:11 reserved reserved. read returns zero. 10 pdc charge pump disable. this bit disables the internal charge pump when set. 7 cle com link error. 1 = a communication problem exists between the pct303a and the pct303l. when this bit goes high, it remains high until a logic 0 is written to it. 6 fdt frame detect. 1 = isolation cap frame lock has been established. 0 = isolation cap communication has not established frame lock. 5:2 lcs[3:0] loop current sense. four-bit value returning the loop current in 6 ma increments. f[7:0] s[7:0] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 t[7:0] rev[7:0] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lcs[3:0] description 0 loop current < 6 ma. 1111 loop current >120 ma.
pc-tel, inc. 26 2303n0docdat10a-0899 PCT2303N data sheet e l e c t r i c a l c h a r a c t e r i s t i c s ! ! e l e c t r i c a l c h a r a c t e r i s t i c s recommended operating conditions absolute maximum ratings permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 6 recommended operating conditions parameter a symbol test condition min b typ max b unit ambient temperature t a k-grade 0 25 70 c ambient temperature t a b-grade 0 25 90 c pct303a supply voltage, analog v a 4.50 5.0 5.50 v pct303a supply voltage, digital c v d 3.0 3.3/5.0 5.50 v a. the PCT2303N chipset specifications are guaranteed when the typical application circuit (including component tolerance) and any pct303a and pct303l are used. b. all minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. typical values apply at nominal supply voltages and an operating temperature of 25c unless otherwise stated. c. the digital supply, v d , can operate from either 3.3v or 5.0v. the pct303a supports interface to 3.3v logic when operating from 3.3v. the 3.3v operation applies to both the serial port and the digital signals reset , id0, and id1. table 7 absolute maximum ratings parameter symbol value unit dc supply voltage v d , v a ?0.5 to +6.0 v input current, pct303a digital input pins i in 10 ma digital input voltage v ind ?0.3 to (v d +0.3) v operating temperature range t a ?10 to +100 c storage temperature range t stg ?40 to +150 c
pc-tel, inc. 27 2303n0docdat10a-0899 PCT2303N data sheet e l e c t r i c a l c h a r a c t e r i s t i c s ! ! loop characteristics given values are: v a = charge pump, v d = +3.3 v 5%; t a = 0 c to 70 c for k-grade, ?40 c to +85 c for b-grade; refer to figure18 on page 34. table 8 loop characteristics parameter symbol test condition min typ max unit dc termination voltage v dct i l = 20ma 7.7 v dc termination voltage v dct i l = 120ma 12 v dc ring current i rdc 720 a ac termination impedance z act 600 w operating loop current i lp 8 120 ma ring voltage detect v rd 13 18 26 v rms ring frequency f r 15 68 hz on-hook leakage current i lk v bat = ?48v 1 a ringer equivalence number ren 1.2
pc-tel, inc. 28 2303n0docdat10a-0899 PCT2303N data sheet e l e c t r i c a l c h a r a c t e r i s t i c s ! ! dc characteristics v d = 5v given values are: v a = +5 v 5%; v d = +3.3 v 5%; t a = 0 c to 70 c for k-grade, ?40 c to +85 c for b-grade. v d = 3.3v given values are: v a = charge pump; v d = +3.3 v 5%; t a = 0 c to 70 c for k-grade, ?40 c to +85 c for b-grade. table 9 dc characteristics, v d = +5v parameter symbol test condition min typ max unit high-level input voltage v ih 3.2 v low-level input voltage v il 0.8 v high-level output voltage v oh i o = ?2ma 2.4 v low-level output voltage v ol i o = +2ma 0.4 v input leakage current i l 10 a power supply current, analog i a v a pin 3 6 ma power supply current, digital i d v d pin 13 17 ma total supply current, sleep mode 1.5 ma table 10 dc characteristics, v d = +3.3v parameter symbol test condition min typ max unit high-level input voltage v ih 2.4 v low-level input voltage v il 0.8 v high-level output voltage v oh i o = ?2ma 2.4 v low-level output voltage v ol i o = +2ma 0.35 v input leakage current i l 10 a power supply current, analog i a v a pin 1 6 ma power supply current, digital i d v d pin 8 11 ma total supply current, sleep mode 1.5 ma
pc-tel, inc. 29 2303n0docdat10a-0899 PCT2303N data sheet e l e c t r i c a l c h a r a c t e r i s t i c s ! ! ac characteristics given values are: v a = charge pump, v d = +3.3 v 5%; t a = 0 c to 70 c for k-grade, ?40 c to +85 c for b-grade. table 11 ac characteristics parameter symbol test condition min typ max unit freq response, transmit a , b a. these characteristics are determined by external components. b. sample rate = 8 khz. f rt low ?3db corner 33 hz freq response, transmit a,b f rt 300hz ?0.2 0 db freq response, transmit b f rt 3400hz ?0.2 0 db transmit full scale level c (0db gain) c. parameter measured at tip and ring. v tx 0.98 v peak freq response, receive a,b f rr low ?3db corner 33 hz freq response, receive a,b f rr 300hz ?0.01 0 db freq response, receive b f rr 3400hz ?0.2 0 db receive full scale level c , d (0db gain) d. receive full scale level produces ?0.9dbfs at sdata_in. v rx 0.98 v peak dynamic range e e. dr = 60db + 20 log (rms signal/rms noise). applies to both the transmit and receive paths. measurement bandwidth is 10hz to 3400hz. valid sample rate range is between 7200hz and 11025hz. dr vin = 1khz, ?60db 84 db total harmonic distortion f f. thd = 20 log (rms distortion/rms signal). applies to both the transmit and receive paths. valid sample rate range is between 7200hz and 11025hz. thd vin = 1khz, ?3db ?84 db gain drift at vin = 1khz 0.002 db/c dynamic range (call progress aout) dr ao vin = 1khz 60 db thd (call progress aout) thd ao vin = 1khz 1.0 % aout full scale level 0.75v d v p-p aout output impedance 10 k w mute level (call progress aout) ?90 db dynamic range (caller id mode) dr cid vin = 1khz, ?60db 60 db caller id full scale level (0db gain) c v cid 0.8 v peak
pc-tel, inc. 30 2303n0docdat10a-0899 PCT2303N data sheet ac-l i n k c h a r a c t e r i s t i c s ! ! ac-l i n k c h a r a c t e r i s t i c s cold reset given values are: v a = charge pump, v d = +3.3v 5%; t a = 25 c; c l = 50 pf. figure 11 cold reset timing diagram warm reset given values are: v a = charge pump, v d = +3.3v 5%; t a = 25 c; c l = 50 pf. figure 12 warm reset timing diagram table 12 timing characteristics?cold reset parameter symbol min typ max unit reset active-low pulse width t rst_low 1.0 s reset inactive to bit_clk startup delay t rst2clk 162.8 ns t rst_low t rst2clk reset# bit_clk table 13 timing characteristics?warm reset parameter symbol min typ max unit sync active-high pulse width t sync_high 1.0 s sync inactive to bit_clk startup delay t sync2clk 162.8 ns t sync_high t sync2clk sync bit_clk
pc-tel, inc. 31 2303n0docdat10a-0899 PCT2303N data sheet ac-l i n k c h a r a c t e r i s t i c s ! ! clocks given values are: v a = charge pump, v d = +3.3v 5%; t a = 25 c; c l = 50 pf. figure 13 clocks timing diagram table 14 timing characteristics?clocks parameter symbol min typ max unit bit_clk frequency 12.288 mhz bit_clk period t clk_period 81.4 ns bit_clk output jitter 750 ps bit_clk high pulse width a a. worst case duty cycle restricted to 45/55. t clk_high 36 40.7 45 ns bit_clk low pulse width a t clk_low 36 40.7 45 ns sync frequency 48.0 khz sync period t sync_period 20.8 s sync high pulse width t sync_high 1.3 s sync low pulse width t sync_low 19.5 s bit_clk sync t clk_low t clk_period t clk_high t sync_low t sync_period t sync_high
pc-tel, inc. 32 2303n0docdat10a-0899 PCT2303N data sheet ac-l i n k c h a r a c t e r i s t i c s ! ! data setup and hold given values are: v a = charge pump, v d = +3.3v 5%; t a = 25 c; c l = 50 pf. figure 14 data setup and hold timing diagram rise and fall times given values are: v a = charge pump, v d = +3.3v 5%; t a = 25 c; c l = 50 pf. figure 15 signal rise and fall timing diagram table 15 timing characteristics?data setup and hold parameter symbol min typ max unit setup to falling edge of bit_clk t setup 15.0 ns hold from falling edge of bit_clk t hold 5.0 ns t setup t hold bit_clk sync sdata_out sdata_in table 16 timing?rise and fall times parameter symbol min typ max unit bit_clk rise time trise clk 2 6 ns bit_clk fall time tfall clk 2 6 ns sync rise time trise sync 2 6 ns sync fall time tfall sync 2 6 ns sdata_in rise time trise din 2 6 ns sdata_in fall time tfall din 2 6 ns sdata_out rise time trise dout 2 6 ns sdata_out fall time tfall dout 2 6 ns sync trise sync tfall sync sdata_out trise dout tfall dout bit_clk trise clk tfall clk sdata_in trise din tfall din
pc-tel, inc. 33 2303n0docdat10a-0899 PCT2303N data sheet ac-l i n k c h a r a c t e r i s t i c s ! ! low power mode given values are: v a = charge pump, v d = +3.3v 5%; t a = 25 c; c l = 50 pf. figure 16 low power mode timing diagram ate test mode given values are: v a = charge pump, v d = +3.3v 5%; t a = 25 c; c l = 50 pf. figure 17 ate test mode timing diagram table 17 timing characteristics?low power mode parameter symbol min typ max unit end of slot 2 to bit_clk, sdata_in low t s2_pdown 1.0 s note: bit_clk not to scale slot 1 slot 2 sync bit_clk sdata_out sdata_in write to 0x56 data mlnk don?t care t s2_pdown table 18 timing characteristics?ate test mode parameter a , b a. all ac-link signals are normally low through the trailing edge of reset . bringing sdata_out high for the trailing edge of reset causes ac?97 ac-link outputs to go high impedance, which is suitable for ate in circuit testing. b. when the test mode has been entered, ac?97 must be issued another reset with all ac-link signals low to return to the normal operating mode. symbol min typ max unit setup to rising edge of reset (also applies to sync) t setup2rst 15.0 ns rising edge of reset to hi-z delay t off 25.0 ns t setup2rst hi-z t off reset# sdata_out sdata_in, bit_clk
pc-tel, inc. 34 2303n0docdat10a-0899 PCT2303N data sheet d i g i t a l f i l t e r c h a r a c t e r i s t i c s ! ! d i g i t a l f i l t e r c h a r a c t e r i s t i c s digital fir filter characteristics given values are: v a = charge pump, v d = +3.3 v 5%; sample rate = 8 khz; t a = 70 c for k-grade, 85 c for b-grade. typical fir filter characteristics for fs = 8000hz are shown in figures 19, 20, 21, and 22. digital iir filter characteristics given values are: v a = charge pump, v d = +3.3 v 5%; sample rate = 8 khz; t a = 70 c for k-grade, 85 c for b-grade. typical iir filter characteristics for fs = 8000 hz are shown in figures 23, 24, 25, and 26. figures 27 and 28 show group delay versus input frequency. figure 18 test circuit for loop characteristics table 19 digital fir filter characteristics?transmit and receive parameter symbol min typ max unit passband (0.1db) f (0.1db) 0 3.3 khz passband (3db) f (3db) 0 3.6 khz passband ripple peak-to-peak ?0.1 0.1 db stopband 4.4 khz stopband attenuation ?74 db group delay t gd 12/fs sec table 20 digital iir filter characteristics?transmit and receive parameter symbol min typ max unit passband (3db) f (3db) 0 3.6 khz passband ripple peak-to-peak ?0.2 0.2 db stopband 4.4 khz stopband attenuation ?40 db group delay t gd 1.6/fs sec pct303l tip ring 10 f 600 w note: the remainder of the circuit is identical to the one shown in the application program. i l
pc-tel, inc. 35 2303n0docdat10a-0899 PCT2303N data sheet d i g i t a l f i l t e r c h a r a c t e r i s t i c s ! ! filter plot diagrams for figures 19, 20, 21, and 22, all filter plots apply to a sample rate of fs = 8 khz. the filters scale with the sample rate as follows: f (0.1 db) = 0.4125 fs f (? 3 db) = 0.45 fs where fs is the sample frequency. s figure 19 fir receive filter response figure 20 fir receive filter passband ripple figure 21 fir transmit filter response figure 22 fir transmit filter passband ripple input frequency - khz a t t e n u a t i o n - d b input frequency - khz a t t e n u a t i o n - d b a t t e n u a t i o n - d b input frequency - khz input frequency - khz a t t e n u a t i o n - d b
pc-tel, inc. 36 2303n0docdat10a-0899 PCT2303N data sheet d i g i t a l f i l t e r c h a r a c t e r i s t i c s ! ! for figures 23, 24, 25, and 26, all filter plots apply to a sample rate of fs = 8 khz. the filters scale with the sample rate as follows: f (? 3 db) = 0.45 fs where fs is the sample frequency. figure 23 iir receive filter response figure 24 iir receive filter passband ripple figure 25 iir transmit filter response figure 26 iir transmit filter passband ripple input frequency - khz a t t e n u a t i o n - d b input frequency - khz a t t e n u a t i o n - d b input frequency - khz a t t e n u a t i o n - d b input frequency - khz a t t e n u a t i o n - d b
pc-tel, inc. 37 2303n0docdat10a-0899 PCT2303N data sheet d i g i t a l f i l t e r c h a r a c t e r i s t i c s ! ! figure 27 iir receive group delay figure 28 iir transmit group delay input frequency - khz d e l a y - s input frequency - khz d e l a y - s
pc-tel, inc. 38 2303n0docdat10a-0899 PCT2303N data sheet m e c h a n i c a l d i m e n s i o n s ! ! m e c h a n i c a l d i m e n s i o n s figure 29 16-pin soic package 16 9 1 8 e h b 0 0.010" gauge plane detail f l d e a 2 a a 1 seating plane c l1 see detail f table 21 soic mechanical dimensions (controlling dimension: millimeters) symbol millimeters inches min max min max a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 a2 1.30 1.50 0.051 0.059 b 0.330 0.51 0.013 0.020 c 0.19 0.25 0.007 0.010 d 9.80 10.01 0.386 0.394 e 3.80 4.00 0.150 0.157 e 1.27 bsc 0.050 bsc h 5.80 6.20 0.228 0.244 l 0.40 1.27 0.016 0.050 l1 1.07 bsc 0.042 bsc g 0.10 0.004 q 0 8 0 8
pc-tel, inc. 39 2303n0docdat10a-0899 PCT2303N data sheet m a n u f a c t u r e d u n d e r o n e o r m o r e o f t h e f o l l o w i n g p a t e n t s : ! ! m a n u f a c t u r e d u n d e r o n e o r m o r e o f t h e f o l l o w i n g p a t e n t s : 4,290,139 4,471,489 4,394,767 4,694,450 4,817,147 4,922,534 4,827,431 4,856,031 4,811,360 4,841,561 4,809,300 4,845,735 4,891,823 5,146,472 5,048,056 5,113,412 5,260,971 5,265,151 5,317,594 5,291,520 5,394,440 5,486,825 5,465,273 5,822,371 5,787,305 5,721,830 5,765,021 5,825,816 5,825,823 5,838,724 5,862,184
pc-tel, inc. 40 2303n0docdat10a-0899 PCT2303N data sheet c o m p a n y l o c a t i o n s ! ! c o m p a n y l o c a t i o n s us headquarters 70 rio robles drive san jose, ca 95134, usa tel: +1-408-965-2100 fax: +1-408-383-0455 http://www.pctel.com japan office yoshida bldg. 501 4-1-31, kudankita, chiyoda-yu, tokyo 102-0073 tel: +81-3-3288-2410 fax: +81-3-3288-2375 taiwan office 10f-2, 160, sec 6, minchuan e. road taipei, taiwan, r. o. c. tel: +886-2-2793-9908 fax: +886-2-2791-8543 europe office 26 rue des sources 91530 sermaise, france tel: +33-1-6459-6464 fax: +33-1-6459-3859 communications systems division 61 mattatuck heights road waterbury, ct 06705 usa tel: +1-203-591-1122 fax: +1-203-574-0635 o r d e r i n g i n f o r m a t i o n kit p/n driver parts k2303n-d-01 v.90/k56flex pct303a, pct303l k2303n-v-01 v.90 pct303a, pct303l

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