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general description the ds5003 secure microprocessor incorporates sophisticated security features including an array of mechanisms that are designed to resist all levels of threat, including observation, analysis, and physical attack. as a result, a massive effort is required to obtain any information about its memory contents. furthermore, the ?oft?nature of the ds5003 allows fre- quent modification of the secure information, thereby minimizing the value of any secure information obtained by such a massive effort. the device is an enhanced version of the ds5002fp secure microprocessor chip with additional scratchpad ram. differences from the ds5002fp the ds5003 implements only one additional feature from the ds5002fp: it adds 128 bytes of internal scratchpad memory (for a total of 256 bytes) similar to that used in 8032/8052 architectures. this additional memory is accessible through indirect addressing 8051 instructions such as ?ov a, @r1,?where r1 now can have a value between 0 and 255. it is also usable as stack space for pushes, pops, calls, and returns. register indirect addressing is used to access the scratchpad ram locations above 7fh. it can also be used to reach the lower ram (0h?fh) if needed. the address is supplied by the contents of the working reg- ister specified in the instruction. thus, one instruction can be used to reach many values by altering the con- tents of the designated working register. note that only r0 and r1 can be used as pointers. an example of reg- ister indirect addressing is as follows: anl a, @r0 ;logical and the accumulator with the contents of ;the register pointed to by the value stored in r0 applications pin pads gaming machines any application requiring software protection features ? 8051-compatible microprocessor for secure/sensitive applications access 32kb, 64kb, or 128kb of nonvolatile sram for program and/or data storage 128 bytes of ram 128 bytes of indirect scratchpad ram in-system programming through on-chip serial port can modify its own program or data memory in the end system ? firmware security features memory stored in encrypted form encryption using on-chip 64-bit key automatic true random-key generator self-destruct input (sdi) top coating prevents microprobing protects memory contents from piracy ? crash-proof operation maintains all nonvolatile resources for over 10 years (at room temperature) in the absence of power power-fail reset early warning power-fail interrupt watchdog timer ds5003 secure microprocessor chip ________________________________________________________________ maxim integrated products 1 rev 0; 3/08 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. pin configuration appears at end of data sheet. ordering information + denotes a lead-free/rohs-compliant package. part temp range internal micro probe shield pin- package DS5003FPM-16+ 0 c to +70 c yes 80 mqfp
ds5003 secure microprocessor chip 2 _______________________________________________________________________________________ absolute maximum ratings dc characteristics (v cc = 5v ?0%, t a = 0? to +70?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on any pin relative to ground..................................-0.3v to (v cc + 0.5v) voltage range on v cc relative to ground ..........................................................-0.3v to +6.0v operating temperature range.............................40? to +85? storage temperature* .......................................-55? to +125? soldering temperature...........................refer to the ipc/jedec j-std-020 specification. parameter symbol conditions min typ max units operating voltage v cc (note 1) v ccmin 5.5 v minimum operating voltage v ccmin 0c to +70c (note 1) 4.00 4.12 4.25 v power-fail warning voltage v pfw 0c to +70c (note 1) 4.25 4.37 4.50 v lithium supply voltage v li (note 1) 2.5 4.0 v operating current at 16mhz i cc (note 2) 36 ma idle-mode current at 12mhz i idle 0c to +70c (note 3) 7.0 ma stop-mode current i stop (note 4) 80 a pin capacitance c in (note 5) 10 pf output supply voltage (v cco ) v cco1 (notes 1, 2) v cc - 0.45 v output supply battery-backed mode (v cco , ce1 C ce4 , pe1 , pe2 ) v cco2 0c to +70c (notes 1, 6) v li - 0.65 v output supply current (note 7) i cco1 v cco = v cc - 0.45v 75 ma lithium-backed quiescent current (note 8) i li 0c to +70c 5 75 na bat = 3.0v (0c to +70c) (note 1) 4.00 4.25 reset trip point in stop mode bat = 3.3v (0c to +70c) (note 1) 4.40 4.65 v input low voltage v il (note 1) -0.3 +0.8 v input high voltage v ih1 (note 1) 2.0 v cc + 0.3 v input high voltage (rst, xtal1, prog ) v ih2 (note 1) 3.5 v cc + 0.3 v output low voltage at i ol = 1.6ma (ports 1, 2, 3, pf ) v ol1 (notes 1, 9) 0.15 0.45 v *storage temperature is defined as the temperature of the device when v cc = 0v and v li = 0v. in this state, the contents of sram are not battery backed and are undefined. note: the ds5003 adheres to all ac and dc electrical specifications published for the ds5002fp.
ds5003 secure microprocessor chip _______________________________________________________________________________________ 3 ac characteristics?di pin (v cc = 0v to 5v, t a = 0? to +70?.) parameter symbol conditions min typ max units 4.5v < v cc < 5.5v 1.3 sdi pulse reject (note 11) t spr v cc = 0v, v bat = 2.9v 4 s 4.5v < v cc < 5.5v 10 sdi pulse accept (note 11) t spa v cc = 0v, v bat = 2.9v 50 s dc characteristics (continued) (v cc = 5v ?0%, t a = 0? to +70?.) parameter symbol conditions min typ max units output low voltage at i ol = 3.2ma (p0.0Cp0.7, ale, ba0Cba14, bd0Cbd7, r/ w , ce1n , ce1 C ce4 , pe1 C pe4 , vrst ) v ol2 (note 1) 0.15 0.45 v output high voltage at i oh = -80a (ports 1, 2, 3) v oh1 (note 1) 2.4 4.8 v output high voltage at i oh = -400a (p0.0Cp0.7, ale, ba0Cba14, bd0Cbd7, r/ w , ce1n , ce1 C ce4 , pe1 C pe4 , vrst ) v oh2 (note 1) 2.4 4.8 v input low current, v in = 0.45v (ports 1, 2, 3) i il -50 a transition current 1 to 0, v in = 2.0v (ports 1, 2, 3) i tl -500 a sdi input low voltage v ils (note 1) 0.4 v sdi input high voltage v ihs (notes 1, 10) 2.0 v cco v sdi pulldown resistor r sdi 25 60 k input leakage (p0.0Cp0.7, msel) i il 0.45 < v in < v cc +10 a rst pulldown resistor r re 0c to +70c 40 150 k vrst pullup resistor r vr 4.7 k prog pullup resistor r pr 40 k
ds5003 secure microprocessor chip 4 _______________________________________________________________________________________ ac characteristics?xpanded bus-mode timing specifications (v cc = 5v ?0%, t a = 0? to +70?.) (figures 1, 2) parameter symbol conditions min max units oscillator freq uency 1/t clk 1.0 16.0 mhz ale pulse width t alpw 2t clk - 40 ns address valid to ale low t avall t clk - 40 ns address hold after ale low t avaav t clk - 35 ns rd pulse width t rdpw 6t clk - 100 ns wr pulse width t wrpw 6t clk - 100 ns 12mhz 5t clk - 165 rd low to valid data in t rdldv 16mhz 5t clk - 105 ns data hold after rd high t rdhdv 0 ns data float after rd high t rdhdz 2t clk - 70 ns 12mhz 8t clk - 150 ale low to valid data in t allvd 16mhz 8t clk - 90 ns 12mhz 9t clk - 165 valid address to valid data in t avdv 16mhz 9t clk - 105 ns ale low to rd or wr low t allrdl 3t clk - 50 3t clk + 50 ns address valid to rd or wr low t avrdl 4t clk - 130 ns data valid to wr going low t dvwrl t clk - 60 ns 12mhz 7t clk - 150 data valid to wr high t dvwrh 16mhz 7t clk - 90 ns data valid after wr high t wrhdv t clk - 50 ns rd low to address float t rdlaz 0 ns rd or wr high to ale high t rdhalh t clk - 40 t clk + 50 ns ac characteristics?xternal clock drive (v cc = 5v ?0%, t a = 0? to +70?.) (figure 3) parameter symbol conditions min max units 12mhz 20 external clock high time t clkhpw 16mhz 15 ns 12mhz 20 external clock low time t clklpw 16mhz 15 ns 12mhz 20 external clock rise time t clkr 16mhz 15 ns 12mhz 20 external clock fall time t clkf 16mhz 15 ns
ds5003 secure microprocessor chip _______________________________________________________________________________________ 5 ac characteristics?ower-cycle time (v cc = 5v ?0%, t a = 0? to +70?.) (figure 4) parameter symbol min max units slew rate from v ccmin to v li t f 130 s crystal startup time t csu (note 12) power-on reset delay t por 21,504 t clk ac characteristics?erial port timing (mode 0) (v cc = 5v ?0%, t a = 0? to +70?.) (figure 5) parameter symbol min max units serial port clock cycle time t spclk 12t clk s output data setup to rising clock edge t doch 10t clk - 133 ns output data hold after rising clock edge t chdo 2t clk - 117 ns clock rising edge to input data valid t chdv 10t clk - 133 ns input data hold after rising clock edge t chdiv 0 ns ac characteristics?yte-wide address/data bus timing (v cc = 5v ?0%, t a = 0? to +70?.) (figure 6) parameter symbol min max units delay to byte-wide address valid from ce1 , ce2 , or ce1n low during op code fetch t ce1lpa 30 ns pulse width of ce1 C ce4 , pe1 C pe4 , or ce1n t cepw 4t clk - 35 ns byte-wide address hold after ce1 , ce2 , or ce1n high during op code fetch t ce1hpa 2t clk - 20 ns byte-wide data setup to ce1 , ce2 , or ce1n high during op code fetch t ovce1h 1t clk + 40 ns byte-wide data hold after ce1 , ce2 , or ce1n high during op code fetch t ce1hov 0 ns byte-wide address hold after ce1 C ce4 , pe1 C pe4 , or ce1n high during movx t cehda 4t clk - 30 ns delay from byte-wide address valid ce1 C ce4 , pe1 C pe4 , or ce1n low during movx t celda 4t clk - 35 ns byte-wide data setup to ce1 C ce4 , pe1 C pe4 , or ce1n high during movx (read) t daceh 1t clk + 40 ns byte-wide data hold after ce1 C ce4 , pe1 C pe4 , or ce1n high during movx (read) t cehdv 0 ns byte-wide address valid to r/ w active during movx (write) t avrwl 3t clk - 35 ns
ds5003 secure microprocessor chip 6 _______________________________________________________________________________________ ac characteristics?yte-wide address/data bus timing (continued) (v cc = 5v ?0%, t a = 0? to +70?.) (figure 6) parameter symbol min max units delay from r/ w low to valid data out during movx (write) t rwldv 20 ns valid data out hold time from ce1 C ce4 , pe1 C pe4 , or ce1n high t cehdv 1t clk - 15 ns valid data out hold time from r/ w high t rwhdv 0 ns write pulse width (r/ w low time) t rwlpw 6t clk - 20 ns rpc ac characteristics?bb read (v cc = 5v ?0%, t a = 0? to +70?.) (figure 7) parameter symbol min max units cs , a0 setup to rd t ar 0 ns cs , a0 hold after rd t ra 0 ns rd pulse width t rr 160 ns cs , a0 to data out delay t ad 130 ns rd to data out delay t rd 0 130 ns rd to data float delay t rdz 85 ns rpc ac characteristics?bb write (v cc = 5v ?0%, t a = 0? to +70?.) (figure 7) parameter symbol min max units cs , a0 setup to wr t aw 0 ns cs hold after wr t wa 0 ns a0 hold after wr t wa 20 ns wr pulse width t ww 160 ns data setup to wr t dw 130 ns data hold after wr t wd 20 ns ac characteristics?ma (v cc = 5v ?0%, t a = 0? to +70?.) parameter symbol min max units dack to wr or rd t acc 0 ns rd or wr to dack t cac 0 ns dack to data valid t acd 0 130 ns rd or wr to drq cleared t crq 110 ns
ds5003 secure microprocessor chip _______________________________________________________________________________________ 7 ac characteristics prog (v cc = 5v ?0%, t a = 0? to +70?.) parameter symbol min max units prog low to active t pra 48 clocks prog high to inactive t pri 48 clocks note 1: all voltages are referenced to ground. note 2: maximum operating i cc is measured with all output pins disconnected; xtal1 driven with t clkr , t clkf = 10ns, v il = 0.5v; xtal2 disconnected; rst = port 0 = v cc , msel = v ss . note 3: idle mode, i idle , is measured with all output pins disconnected; xtal1 driven with t clkr , t clkf = 10ns, v il = 0.5v; xtal2 disconnected; port 0 = v cc , rst = msel = v ss . note 4: stop mode, i stop , is measured with all output pins disconnected; port 0 = v cc ; xtal2 not connected; rst = msel = xtal1 = v ss . note 5: pin capacitance is measured with a test frequency: 1mhz, t a = +25?. this specification is characterized but not produc- tion tested. note 6: v cco2 is measured with v cc < v li and a maximum load of 10? on v cco . note 7: i cco1 is the maximum average operating current that can be drawn from v cco in normal operation. note 8: i li is the current drawn from the v li input when v cc = 0v and v cco is disconnected. battery-backed mode is 2.5v v bat 4.0; v cc v bat ; v sdi should be v ils for i bat max. note 9: pf pin operation is specified with v bat 3.0v. note 10: v ihs minimum is 2.0v or v cco , whichever is lower. note 11: sdi is deglitched to prevent accidental destruction. the pulse must be longer than t spr to pass the deglitcher, but sdi is not guaranteed unless it is longer than t spa . note 12: crystal startup time is the time required to get the mass of the crystal into vibrational motion from the time that power is first applied to the circuit until the first clock pulse is produced by the on-chip oscillator. the user should check with the crystal vendor for a worst-case specification on this time. ale t alpw t avdv t rdpw t allrdl t rdhalh t allvd t rdldv t avall t avrdl t avaav t rdlaz t rdhdv t rdhdz port 0 a7?0 (rn or dpl) p2.7?2.0 or a15?8 from dph a15?8 from pch data in a7?0 (pcl) instr in port 2 rd figure 1. expanded data memory read cycle
ds5003 secure microprocessor chip 8 _______________________________________________________________________________________ ale t wrpw t allrdl t rdhalh t avall t avrdl t dvwrh t avaav t wrhdv t dvwrl port 0 a7?0 (rn or dpl) p2.7?2.0 or a15?8 from pdh a15?8 from pch data out a7?0 (pcl) instr in port 2 wr figure 2. expanded data memory write cycle t clkhpw t clklpw 1/t clk t clkf t clkr figure 3. external clock timing
ds5003 secure microprocessor chip _______________________________________________________________________________________ 9 interrupt service routine clock osc internal reset lithium current v cc v pfw v ccmin v li t f t csv t por figure 4. power-cycle timing
ds5003 secure microprocessor chip 10 ______________________________________________________________________________________ 0 ale clock data out write to sbuf register input data 1 2 3 4 5 6 7 8 clear ri valid 01234567 t spclk t chdiv t doch t chdo t chdv valid valid valid valid valid valid set ri set ti figure 5. serial port timing (mode 0) 1 xtal2 ale ba0?a14 pc out data in data in data in data data out pc out pc out pc out dpl and (dph or p2 sfr out) dpl and (dph or p2 sfr out) bd0?d7 ce1, ce2, or ce1n ce1, ce2, ce3, ce4, pe1, pe2, pe3, pe4, or ce1n r/w 2 3 4 5 6 1 2 3 4 5 6 6 1 2 3 4 5 6 machine cycle machine cycle machine cycle t cel1lpa t ovce1h t daceh t ce1hov t cehdv t rwldv t rwhdv t cehdv t cel1hpa t celda t cehda t avrwl t rwlpw t cehda t celda t cepw t cepw figure 6. byte-wide bus timing
ds5003 secure microprocessor chip ______________________________________________________________________________________ 11 read operation data valid t ar t rr t rd t ad t ra t rdz cs or a0 rd data write operation data valid t aw t ww t wd t dw t wa cs or a0 data wr rd dma t acd t acc t acc t crq t crq t cac t cac data valid valid drq dack wr figure 7. rpc timing mode
ds5003 secure microprocessor chip 12 ______________________________________________________________________________________ pin description pin name function power pins 13 v cc power supply, +5v 12 v cco v cc output. this is switched between v cc and v li by internal circuits based on the level of v cc . when power is above the lithium input, power is drawn from v cc . the lithium cell remains isolated from a load. when v cc is below v li , v cco switches to the v li source. v cco should be connected to the v cc pin of an sram. 54 v li lithium voltage input. connect to a lithium cell greater than v limin and no greater than v limax as shown in the electrical specifications. nominal value is +3v. 52 gnd logic ground general-purpose i/o pins 11 p0.0/ad0 9 p0.1/ad1 7 p0.2/ad2 5 p0.3/ad3 1 p0.4/ad4 79 p0.5/ad5 77 p0.6/ad6 75 p0.7/ad7 general-purpose i/o port 0. this port is open drain and cannot drive a logic 1. it requires external pullups. port 0 is also the multiplexed expanded address/data bus. when used in this mode, it does not require pullups. 15 p1.0 17 p1.1 19 p1.2 21 p1.3 25 p1.4 27 p1.5 29 p1.6 31 p1.7 general-purpose i/o port 1 49 p2.0/a8 50 p2.1/a9 51 p2.2/a10 56 p2.3/a11 58 p2.4/a12 60 p2.5/a13 64 p2.6/a14 66 p2.7/a15 general-purpose i/o port 2. also serves as the msb of the expanded address bus. 36 p3.0/rxd general-purpose i/o port pin 3.0. also serves as the receive signal for the on-board uart. this pin should not be connected directly to a pc com port. 38 p3.1/txd general-purpose i/o port pin 3.1. also serves as the transmit signal for the on-board uart. this pin should not be connected directly to a pc com port. 39 p3.2/ int0 general-purpose i/o port pin 3.2. also serves as the active-low external interrupt 0. 40 p3.3/ int1 general-purpose i/o port pin 3.3. also serves as the active-low external interrupt 1. 41 p3.4/t0 general-purpose i/o port pin 3.4. also serves as the timer 0 input. 44 p3.5/t1 general-purpose i/o port pin 3.5. also serves as the timer 1 input. 45 p3.6/ wr general-purpose i/o port pin 3.6. also serves as the write strobe for expanded bus operation. 46 p3.7/ rd general-purpose i/o port pin 3.7. also serves as the read strobe for expanded bus operation.
ds5003 secure microprocessor chip ______________________________________________________________________________________ 13 pin description (continued) pin name function byte-wide bus interface pins 37 ba0 35 ba1 33 ba2 30 ba3 28 ba4 26 ba5 24 ba6 20 ba7 6 ba8 4 ba9 76 ba10 80 ba11 18 ba12 8 ba13 16 ba14 byte-wide address bus bits 14C0. this bus is combined with the nonmultiplexed data bus (bd7Cbd0) to access external sram. decoding is performed using ce1 C ce4 . therefore, ba15 is not actually needed. read/write access is controlled by r/ w . ba14Cba0 connect directly to an 8kb, 32kb, or 128kb sram. if an 8kb sram is used, ba13 and ba14 are unconnected. if a 128kb sram is used, the microcontroller converts ce2 and ce3 to serve as a16 and a15, respectively. 55 bd0 57 bd1 59 bd2 61 bd3 65 bd4 67 bd5 69 bd6 71 bd7 byte-wide data bus bits 7C0. this 8-bit bidirectional bus is combined with the nonmultiplexed address bus (ba14Cba0) to access external sram. decoding is performed on ce1 and ce2 . read/write access is controlled by r/ w . d7Cd0 connect directly to an sram and optionally to a real-time clock or other peripheral. 70 ale address latch enable. used to demultiplex the multiplexed expanded address/data bus on port 0. this pin is normally connected to the clock input on a 373 type transparent latch. 10 r/ w read/write (active low). this signal provides the write enable to the srams on the byte-wide bus. it is controlled by the memory map and partition. the blocks selected as program (rom) are write protected. 74 ce1 active-low chip-enable 1. this is the primary decoded chip enable for memory access on the byte-wide bus. it connects to the chip-enable input of one sram. ce1 is lithium-backed. it remains in a logic-high inactive state when v cc falls below v li . 72 ce1n nonbattery-backed version of ce1. it is not generally useful because the ds5003 cannot be used with eprom due to its encryption. 2 ce2 active-low chip-enable 2. this chip enable is provided to access a second 32kb block of memory. it connects to the chip-enable input of one sram. when msel = 0, the microcontroller converts ce2 into a16 for a 128kb x 8 sram. ce2 is lithium-backed and remains at a logic-high when v cc falls below v li . 63 ce3 active-low chip-enable 3. this chip enable is provided to access a third 32kb block of memory. it connects to the chip-enable input of one sram. when msel = 0, the microcontroller converts ce3 into a15 for a 128kb x 8 sram. ce3 is lithium backed and remains at a logic-high when v cc falls below v li .
ds5003 secure microprocessor chip 14 ______________________________________________________________________________________ pin description (continued) pin name function 62 ce4 active-low chip-enable 4. this chip enable is provided to access a fourth 32kb block of memory. it connects to the chip-enable input of one sram. when msel = 0, this signal is unused. ce4 is lithium-backed and remains at a logic-high when v cc falls below v li . 78 pe1 active-low peripheral enable 1. accesses data memory between addresses 0000h and 3fffh when the pes bit is set to logic 1. commonly used to chip enable a byte-wide real-time clock such as the ds1283. pe1 is lithium backed and remains at a logic-high when v cc falls below v li . connect pe1 to battery-backed circuitry only. 3 pe2 active-low peripheral enable 2. accesses data memory between addresses 4000h and 7fffh when the pes bit is set to logic 1. pe2 is lithium backed and remains at a logic-high when v cc falls below v li . connect pe2 to battery-backed circuitry only. 22 pe3 active-low peripheral enable 3. accesses data memory between addresses 8000h and bfffh when the pes bit is set to a logic 1. pe3 is not lithium backed and can be connected to any type of peripheral function. if connected to a battery-backed chip, it needs additional circuitry to maintain the chip enable in an inactive state when v cc < v li . 23 pe4 active-low peripheral enable 4. accesses data memory between addresses c000h and ffffh when the pes bit is set to logic 1. pe4 is not lithium backed and can be connected to any type of peripheral function. if connected to a battery-backed chip, it needs additional circuitry to maintain the chip enable in an inactive state when v cc < v li . 14 msel memory select. this signal controls the memory size selection. when msel = +5v, the ds5003 expects to use 32kb x 8 srams. when msel = 0v, the ds5003 expects to use a 128kb x 8 sram. msel must be connected regardless of partition, mode, etc. clock pins 47, 48 xtal2, xtal1 crystal connections. used to connect an external crystal to the internal oscillator. xtal1 is the input to an inverting amplifier and xtal2 is the output. reset, status, and self-destruct pins 34 rst active-high reset i nput. a logic 1 applied to this pin activates a reset state. this pin is pulled down internally so this pin can be left unconnected if not used. an rc power-on reset circuit is not needed and is not recommended. 32 prog invokes the bootstrap loader on falling edge. this signal should be debounced so that only one edge is detected. if connected to ground, the microcontroller enters bootstrap loading on power-up. this signal is pulled up internally. 42 vrst reset state active due to low v cc . this i/o pin (open drain with internal pullup) indicates that the power supply (v cc ) has fallen below the v ccmin level and the microcontroller is in a reset state. when this occurs, the ds5003 drives this pin to logic 0. because the microcontroller is lithium backed, this signal is guaranteed even when v cc = 0v. because it is an i/o pin, it also forces a reset if pulled low externally. this allows multiple parts to synchronize their power- down resets. 43 pf lithium backup active. this output goes to a logic 0 to indicate that the microcontroller has switched to lithium backup. this corresponds to v cc < v li . because the microcontroller is lithium backed, this signal is guaranteed even when v cc = 0v. the normal application of this signal is to control lithium-powered current to isolate battery-backed functions from nonbattery- backed functions. 53 sdi self-destruct input. an active high on this pin causes an unlock procedure. this results in the destruction of vector sram, encryption keys, and the loss of power from v cco . this pin should be grounded if not used. miscellaneous pins 68, 73 n.c. no connection
detailed description the ds5003 implements a security system that loads and executes application software in encrypted form. up to 128kb of standard sram (64kb program + 64kb data) can be accessed by its byte-wide bus. this sram is converted by the ds5003 into lithium-backed nonvolatile storage for program and data. data can be maintained for up to 10 years at room temperature with a very small lithium cell. as a result, the contents of the sram and the execution of the software appear unintel- ligible to the outside observer. the encryption algorithm uses an internally stored and protected key. any attempt to discover the key value results in its erasure, rendering the encrypted contents of the sram useless. the secure microprocessor chip provides a strong soft- ware-encryption algorithm that incorporates elements of des encryption. the encryption is based on a 64-bit key word, and the key can only be loaded from an on- chip true random-number generator. as a result, the user never knows the true key value. a self-destruct input (sdi) pin is provided to interface to external tam- per-detection circuitry. with or without the presence of v cc , activation of the sdi pin has the same effect as resetting the security lock: immediate erasure of the key word and the 48-byte vector sram area. in addition, an optional top coating of the die prevents access of infor- mation using microprobing techniques. when implemented as a part of an overall secure sys- tem design, a system based on the ds5003 can typi- cally provide a level of security that requires more time and resources to defeat than necessary for unautho- rized individuals who have reason to try. figure 8 is a block diagram illustrating the internal architecture of the ds5003. the ds5003 operates in an identical fashion to the ds5002fp, except where noted in text. secure operation overview the ds5003 incorporates encryption of the activity on its byte-wide address/data bus to prevent unauthorized access to the program and data information contained in the external sram. loading an application program in this manner is performed by the bootstrap loader using the general sequence described as follows: 1) activate bootstrap loader by asserting the prog pin low for at least 48 clocks. 2) clear security lock. 3) set memory map configuration. these settings are identical to those used for ds5002fp-based designs. 4) load application software. 5) set security lock. 6) exit loader by taking the prog pin high again. loading of application software into the program/data sram is performed while the ds5003 is in its bootstrap load mode. loading is only possible when the security lock is clear. if the security lock was previously set, it must be cleared by issuing the u command from the bootstrap loader. clearing the security lock instantly clears the previous key word and the contents of the vector sram. in addition, the bootstrap rom writes zeros into the first 32kb of external sram. the user? application software is loaded into user-sup- plied external sram by the l command in ?crambled form through on-chip encryptor circuits. each external sram address is an encrypted representation of an on- chip logical address. thus, the sequential instructions of an ordinary program or data table are stored nonse- quentially in sram memory. the contents of the pro- gram/data sram are also encrypted. each byte in sram is encrypted by a key- and address-dependent encryptor circuit such that identical bytes are stored as different values in different memory locations. the encryption of the program/data sram is depen- dent on an on-chip 64-bit key word. the key is automat- ically generated by the rom firmware just prior to the time that the application software is loaded, and is retained as nonvolatile information in the absence of v cc by the lithium-backup circuits. after the application software loading is complete, the key is protected by setting the on-chip security lock, which is also retained as nonvolatile information in the absence of v cc . any attempt to tamper with the key word and, thereby, gain access to the true program/data sram contents results in the erasure of the key word as well as the sram contents. during execution of the application software, logical addresses on the ds5003 that are generated from the program counter or data pointer registers are encrypt- ed before they are presented on the byte-wide address bus. op codes and data are read back and decrypted before they are operated on by the cpu. similarly, data values written to the external nv sram storage during program execution are encrypted before they are pre- sented on the byte-wide data bus during the write oper- ation. this encryption/decryption process is performed in real time such that no execution time is lost, so the operation of the encryptor circuitry is transparent to the application software. the ds5003? security features are always enabled. ds5003 secure microprocessor chip ______________________________________________________________________________________ 15
ds5003 secure microprocessor chip 16 ______________________________________________________________________________________ timing and bus control address/ data encryptors byte- wide bus interface special function registers encryption keys data registers with enhanced indirect addressing (256 bytes) power monitor vector ram (48 bytes) cpu osc xtal1 r/w sdi ce1?e4 4 ba0?a14 bd0?d7 pe1?e4 xtal2 rst ale prog watchdog timer port 0 p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 v li port 1 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 port 2 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 port 3 p3.0 p3.1 p3.2 p3.3 p3.4 p3.5 p3.6 p3.7 4 16 8 address data bootstrap loader rom txd rxd timer 0 timer 1 int0 int1 vrst pf v cco v cc ds5003 figure 8. block diagram
security circuitry figure 9 shows the on-chip functions associated with the ds5003? software security feature. encryption logic consists of an address encryptor and a data encryptor. although each encryptor uses its own algorithm for encrypting data, both depend on the 64-bit key word that is contained in the encryption key registers. both the encryptors operate during loading of the application software and also during its execution. the address encryptor translates each logical address, i.e., the normal sequence of addresses that are gener- ated in the logical flow of program execution, into an encrypted address (or physical address) at which the byte is actually stored. each time a logical address is generated, either during program loading or during program execution, the address encryptor circuitry uses the value of the 64-bit key word and of the address itself to form the physical address, which are presented on the address lines of the sram. the encryption algorithm is such that there is one and only one physical address for every possible logical address. the address encryptor operates over the entire memory range, which is configured during boot- strap loading for access on the byte-wide bus. as bootstrap loading of the application software is per- formed, the data encryptor logic transforms the op code, operand, or data byte at any given memory loca- tion into an encrypted representation. as each byte is read back to the cpu during program execution, the internal data encryptor restores it to its original value. when a byte is written to the external nonvolatile pro- gram/data sram during program execution, that byte is stored in encrypted form as well. the data encryption logic uses the value of the 64-bit key, the logical address to which the data is being written, and the value of the data itself to form the encrypted data, which is written to the nonvolatile program/data sram. the encryption algorithm is repeatable, such that for a given data value, encryption key value, and logical address the encrypted byte is always the same. however, there are many possible encrypted data val- ues for each possible true-data value due to the algo- rithm? dependency on the values of the logical address and encryption key. ds5003 secure microprocessor chip ______________________________________________________________________________________ 17 bootstrap loader random- number generator address encryptor external byte-wide ram data encryptor security lock 64-bit encryption key secure internal address bus encrypted byte-wide address bus 16 secure internal data bus program counter data pointer encrypted byte-wide data bus 8 sdi (self-destruct input) figure 9. security circuitry
ds5003 when the application software is executed, the ds5003? internal cpu operates as normal. logical addresses are calculated for op code fetch cycles and also data read and write operations. the ds5003 can perform address encryption on logical addresses as they are generated internally during the normal course of program execution. in a similar fashion, data is manipulated by the cpu in its true representation. however, data is also encrypted when it is written to the external program/data sram, and is restored to its original value when it is read back. when an application program is stored in the previously described format, it is virtually impossible to disassem- ble op codes or to convert data back into its true repre- sentation. address encryption has the effect that the op codes and data are not stored in the contiguous form in which they were assembled, but rather in seemingly random locations in memory. this effect makes it virtu- ally impossible to determine the normal flow of the pro- gram. as an added protection measure, the address encryptor also generates dummy read-access cycles whenever time is available during program execution. dummy read cycles like the ds5002fp, the ds5003 generates a dummy read-access cycle to nonsequential addresses in exter- nal sram memory whenever time is available during program execution. this action further complicates the task of determining the normal flow of program execu- tion. during these pseudorandom dummy cycles, the sram is read to all appearances, but the data is not used internally. through the use of a repeatable exchange of dummy and true read cycles, it is impossi- ble to distinguish a dummy cycle from a real one. encryption algorithm the ds5003 incorporates a proprietary hardware algo- rithm that performs the scrambling of address and data on the byte-wide bus to the sram. improvements include the following: 64-bit encryption key (protected by the security lock function). incorporation of des-like operations to provide a greater degree of nonlinearity. customizable encryption. encryption key as previously described, the on-chip 64-bit encryption key is the basis of both the address and data encryptor circuits. when the loader is given certain commands, the key is generated from an on-chip hardware ran- dom-number generator. this action is performed just prior to actually loading the code into the external sram. this scheme prevents characterization of the encryption algorithm by continuously loading new, known keys. it also frees the user from the burden of protecting the key selection process. the random-number generator circuit uses the asyn- chronous frequency differences of two internal ring oscillators and the processor master clock (determined by xtal1 and xtal2). as a result, a true random num- ber is produced. vector ram a 48-byte vector ram area is incorporated on-chip, and is used to contain the reset and interrupt vector code in the ds5003. it is included in the architecture to help ensure the security of the application program. if reset and interrupt vector locations were accessed from the external nonvolatile program/data ram during the execution of the program, it would be possible to determine the encrypted value of known addresses. this could be done by forcing an interrupt or reset con- dition and observing the resulting addresses on the byte-wide address/data bus. for example, it is known that when a hardware reset is applied, the logical pro- gram address is forced to location 0000h and code is executed starting from this location. it would then be possible to determine the encrypted value (or physical address) of the logical address value 0000h by observ- ing the address presented to the external sram follow- ing a hardware reset. interrupt vector address relationships could be determined in a similar fashion. by using the on-chip vector ram to contain the inter- rupt and reset vectors, it is impossible to observe such relationships. the vector ram eliminates the unlikely possibility that an application program could be deci- phered by observing vector address relationships. note that the dummy accesses mentioned are conducted while fetching from vector ram. the vector ram is automatically loaded with the user? reset and interrupt vectors from the intel hex file during bootstrap loading. security lock once the application program has been loaded into the ds5003? external and vector ram, the security lock can be enabled by issuing the z command in the boot- strap loader. while the security lock is set, no further access to program/data information is possible by the on-chip rom. access is prevented by both the boot- strap loader firmware and the ds5003 encryptor cir- cuits. access to the sram can only be regained by clearing the security lock by the u command in the bootstrap secure microprocessor chip 18 ______________________________________________________________________________________
loader. this action triggers several events that defeat tampering. first, the encryption key is instantaneously erased. without the encryption key, the ds5003 can no longer decrypt the contents of the sram. therefore, the application software can no longer be correctly execut- ed, nor can it be read back in its true form by the boot- strap loader. second, the vector ram area is also instantaneously erased, so that the reset and vector information is lost. third, the bootstrap loader firmware sequentially erases the encrypted sram area. lastly, the loader creates and loads a new random key. the security lock bit is constructed using a multiple-bit latch that is interlaced for self-destruction in the event of tampering. the lock is designed to set up a ?omino effect?such that erasure of the bit results in an unstop- pable sequence of events that clears critical data including encryption key and vector ram. in addition, this bit is protected from probing by the top-coating feature. self-destruct input (sdi) the self-destruct input (sdi) pin is an active-high input that is used to reset the security lock in response to a variety of user-defined external events. the sdi input is intended to be used with external tamper-detection cir- cuitry. it can be activated with or without operating power applied to the v cc pin. activation of the sdi pin instantly resets the security lock and causes the same sequence of events previously described for this action. in addition, power is momentarily removed from the byte-wide bus interface including the v cc pin, resulting in the loss of data in external sram. top-layer coating the ds5003m is provided with a special top-layer coat- ing that is designed to prevent a probe attack. this coating is implemented with second-layer metal added through special processing of the microcontroller die. this additional layer is not a simple sheet of metal, but rather a complex layout that is interwoven with power and ground, which are in turn connected to logic for the encryption key and the security lock. as a result, any attempt to remove the layer or probe through it results in the erasure of the security lock and/or the loss of encryption key bits. bootstrap loading initial loading of application software into the ds5003 is performed by firmware within the on-chip bootstrap loader communicating with a pc by the on-chip serial port. table 1 summarizes the commands accepted by the bootstrap loader. when the bootstrap loader is invoked, portions of the 256-byte scratchpad ram area are automatically over- written with zeros and then used for variable storage for the bootstrap firmware. also, a set of 8 bytes is gener- ated using the random-number generator circuitry and saved as a potential word for the 64-bit encryption key. any read or write operation to the ds5003? external program/data sram can only take place if the security lock bit is in a cleared state. therefore, the first step in loading a program should be the clearing of the securi- ty lock bit through the u command. execution of certain bootstrap loader commands result in the loading of the newly generated 64-bit random number into the encryption key word. these commands are as follows: fill f load l dump d verify v crc c execution of the fill and load commands load the encrypted data into sram using encryption keys from the newly generated key word. the subsequent execu- tion of the dump command within the same bootstrap session causes the contents of the encrypted sram to ds5003 secure microprocessor chip ______________________________________________________________________________________ 19 command function c return crc-16 of the program/data sram. d dump ram memory specified by msl bit as intel hex format. f fill program/data sram. g get data from p0, p1, p2, and p3. l load intel hex file. n set freshness sealall program and data is lost. p put data into p0, p1, p2, and p3. r read status of sfrs (mcon, rpctl, msl). t trace (echo) incoming intel hex code. u clear security lock. v verify program/data memory with incoming intel hex data. w write special function registers (mcon, rpctl, msl). z set security lock. table 1. serial bootstrap loader commands
ds5003 be read out and transmitted back to the host pc in decrypted form. similarly, execution of the verify com- mand within the same bootstrap session causes the incoming absolute hex data to be compared against the true contents of the encrypted sram, and the crc command returns the crc value calculated from the true contents of the encrypted sram. as long as any of these commands are executed within the same boot- strap session , the loaded key value remains the same and the contents of the encrypted program/data sram can be read or written normally and freely until the security lock bit is set. when the security lock bit is set using the z command, no further access to the true sram contents is possible using any bootstrap command or by any other means. a more extensive explanation of the serial loader opera- tion can be found in the secure microcontroller user? guide ( www.maxim-ic.com/secureug ). instruction set the ds5003 executes an instruction set that is object- code compatible with the industry-standard 8051 microcontroller. as a result, software development packages such as assemblers and compilers that have been written for the 8051 are compatible with the ds5003. a complete description of the instruction set and operation is provided in the secure microcontroller user? guide . memory organization figure 10 illustrates the memory map accessed by the ds5003. the entire 64kb of program and 64kb of data are potentially available to the byte-wide bus. this pre- serves the i/o ports for application use. the user con- trols the portion of memory that is actually mapped to the byte-wide bus by selecting the program range and data range. any area not mapped into the sram is secure microprocessor chip 20 ______________________________________________________________________________________ program memory ffffh 64kb data range program range nv ram program nv ram data data memory (movx) 0000h legend: = byte-wide bus access (encrypted) = expanded bus (ports 0 and 2) = not available figure 10. memory map in nonpartitionable mode (pm = 1)
reached by the expanded bus on ports 0 and 2. an alternate configuration allows dynamic partitioning of a 64kb space as shown in figure 11. selecting pes = 1 provides another 64kb of potential data storage or memory-mapped peripheral space as shown in figure 12. these selections are made using special function registers. the memory map and its controls are cov- ered in detail in the secure microcontroller user? guide . figure 13 illustrates a typical memory connection for a system using a 128kb sram. note that in this configu- ration, both program and data are stored in a common sram chip. figure 14 shows a similar system with using two 32kb srams. the byte-wide address bus connects to the sram address lines. the bidirectional byte-wide data bus connects the data i/o lines of the sram. ds5003 secure microprocessor chip ______________________________________________________________________________________ 21 program memory ffffh partition nv ram program nv ram data data memory (movx) 0000h legend: = nv ram memory = expanded bus (ports 0 and 2) = not available figure 11. memory map in partitionable mode (pm = 0)
ds5003 secure microprocessor chip 22 ______________________________________________________________________________________ program memory ffffh 64kb 48kb 32kb 16kb partition nv ram program data memory (movx) 0000h 4000h legend: = byte-wide program (encrypted) = not accessible pe4 pe3 pe2 pe1 figure 12. memory map with pes = 1 ds5003 13 v cc 14 msel 54 v li 12 v cco 52 gnd bd7?d0 63 ce3 ba14?a0 2 ce2 74 ce1 10 r/w +5v +3v lithium port 0 port 1 port 2 port 3 32 v cc 16 gnd 29 we 22 cs1 2 a16 31 a15 128kb x 8 sram 24 oe 30 cs2 a14?0 d7?0 figure 13. connection to 128kb x 8 sram
power management the ds5003 monitors v cc to provide power-fail reset, early warning power-fail interrupt, and switchover to lithium backup. it uses an internal bandgap reference in determining the switch points. these are called v pfw , v ccmin , and v li , respectively. when v cc drops below v pfw , the ds5003 performs an interrupt and vectors to location 2bh if the power-fail warning was enabled. full processor operation continues regard- less. when power falls further to v ccmin , the ds5003 invokes a reset state. no further code execution is per- formed unless power rises back above v ccmin . all decoded chip enables and the r/ w signal go to an inactive (logic 1) state. v cc is still the power source at this time. when v cc drops further to below v li , internal circuitry switches to the lithium cell for power. the majority of internal circuits are disabled and the remain- ing nonvolatile states are retained. any devices con- nected to v cco are powered by the lithium cell at this time. v cco is at the lithium battery voltage minus approximately 0.45v (less a diode drop), depending on the load. low-power srams should be used for this reason. when using the ds5003, the user must select the appropriate battery to match the sram data-reten- tion current and the desired backup lifetime. note that the lithium cell is only loaded when v cc < v li . the secure microcontroller user? guide has more informa- tion on this topic. the trip points v ccmin and v pfw are listed in the electrical specifications. ds5003 secure microprocessor chip ______________________________________________________________________________________ 23 ds5003 13 v cc 14 msel 54 v li 12 v cco 52 gnd bd7?d0 ba14?a0 2 ce2 74 ce1 10 r/w +5v +5v +3v lithium port 0 port 1 port 2 port 3 28 v cc 14 gnd 27 we 20 cs 32kb x 8 sram 22 oe a14?0 d7?0 28 v cc 14 gnd 27 we 20 cs 32kb x 8 sram 22 oe a14?0 d7?0 figure 14. connection to 64kb x 8 sram package information (for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo .) package type package code document no. 80 mqfp 56-g4005-001
ds5003 secure microprocessor chip maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 24 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2008 maxim integrated products is a registered trademark of maxim integrated products, inc. 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ba11 p0.5/ad5 pe1 p0.6/ad6 ba10 p0.7/ad7 ce1 n.c. ce1n bd7 ale 64 p2.6/a14 ce3 ce4 bd3 p2.5/a13 bd2 p2.4/a12 bd1 p2.3/a11 bd0 v li sdi gnd p2.2/a10 p2.1/a9 p2.0/a8 xtal1 xtal2 p3.7/rd p3.6/wr p3.5/t1 pf vrst p3.4/t0 p0.4/ad4 ce2 pe2 ba9 p0.3/ad3 ba8 p0.2/ad2 ba13 p0.1/ad1 r/w p0.0/ad0 v cco v cc msel p1.0 ba14 p1.1 ba12 p1.2 ba7 p1.3 pe3 pe4 ba6 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 bd6 n.c. bd5 p2.7/a15 bd4 p1.4 ba5 p1.5 ba4 p1.6 ba3 p1.7 prog ba2 rst ba1 p3.0/rxd ba0 p3.1/txd p3.2/int0 p3.3/int1 mqfp ds5003 top view + pin configuration

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