hmpp-386x series minipak surface mount rf pin diodes data sheet description/applications these ultra-miniature products represent the blending of avago technologies proven semiconductor and the latest in leadless packaging technology. the hmpp-386x series of general purpose pin diodes are designed for two classes of applications. the frst is attenu - ators where current consumption is the most important design consideration. the second application for this series of diodes is in switches where low capacitance with no reverse bias is the driving issue for the designer. the low dielectric relaxation frequency of the hmpp-386x insures that low capacitance can be reached at zero volts reverse bias at frequencies above 1 ghz, making this pin diode ideal for hand held applications. low junction capacitance of the pin diode chip, combined with ultra low package parasitics, mean that these products may be used at frequencies which are higher than the upper limit for conventional pin diodes. note that avagos manufacturing techniques assure that dice packaged in pairs are taken from adjacent sites on the wafer, assuring the highest degree of match. minipak 1412 is a ceramic based package, while minipak qfn is a leadframe based package. package lead code identifcation (top view) features ? surface mount minipak package ? better thermal conductivity for higher power dissipa - tion ? single and dual versions ? matched diodes for consistent performance ? low capacitance at zero volts ? low resistance ? low fit (failure in time) rate* ? six-sigma quality level * for more information, see the surface mount schottky reliability data sheet. pin connections and package marking notes: 1. package marking provides orientation and identifcation. 2. see electrical specifcations for appropriate package marking. s i n g l e 3 2 4 1 # 0 a n t i - p a r a l l e l 3 2 4 1 # 2 p a r a l l e l 3 2 4 1 # 5 ( m i n i p a k 1 4 1 2 ) ( m i n i p a k 1 4 1 2 ) ( m i n i p a k 1 4 1 2 ) 3 2 p r o d u c t c o d e d a t e c o d e 4 a a 1
hmpp-386x series absolute maximum ratings [1] , t c = 5c minipak 141 / symbol parameter units minipak qfn i f forward current (1 s pulse) amp 1 p iv peak inverse voltage v 100 t j junction temperature c 150 t stg storage temperature c -65 to +150 jc thermal resistance [2] c/w 150 notes: 1. operation in excess of any one of these conditions may result in permanent dam - age to the device. 2. t c = +25c, where t c is defned to be the temperature at the package pins where contact is made to the circuit board. minipak141 electrical specifcations, t c = +5c, each diode part number package minimum breakdown typical series hmpp- marking code lead code confguration voltage (v) resistance (?) 3860 h 0 single 50 3.0/1.5* 3862 f 2 anti-parallel 3865 e 5 parallel test conditions v r = v br i f = 10 ma measure f = 100 mhz i r 10 a *i f = 100 ma esd warning: handling precautions should be taken to avoid static discharge. minipak141 typical parameters, t c = +5c part number total resistance carrier lifetime reverse recovery time total capacitance hmpp- r t (?) (ns) t rr (ns) c t (pf) 3860 22 500 80 0.20 3862 3865 test conditions i f = 1 ma i f = 50 ma v r = 10 v v r = 50v f = 100 mhz t r = 250 ma i f = 20 ma f = 1 mhz 90% recovery
3 minipak 141 hmpp-386x series typical performance t c = +25 c (unless otherwise noted), each diode figure 1. rf capacitance vs. reverse bias. 0.15 0.30 0.25 0.20 0.35 0 2 6 4 1 0 1 2 8 1 6 14 18 20 total capacitance (pf) reverse voltage (v) 1 ghz 100 mhz 1 mhz 120 11 5 11 0 105 100 95 90 85 1 1 0 3 0 i f ? forward bias current (ma) figure 3. 2nd harmonic input intercept point vs. forward bias current for switch diodes. input intercept point (dbm) diode mounted as a series switch in a 50 microstrip and t ested at 123 mhz forward current (ma) figure 4. reverse recovery time vs. forward current for various reverse voltages. t rr ? reverse recovery time (ns) 10 100 1000 10 20 30 v r = 5 v v r = 10 v v r = 20 v figure 2. typical rf resistance vs. forward bias current. 0.01 100 1000 1 10 rf resistance (ohms) bias current (ma) 10 100 1 0.1 t a = +85 c t a = +25 c t a = ? 55 c 100 10 1 0.1 0.01 0 0.2 0.4 0.6 0.8 1.0 1.2 i f ? forward current (ma) v f ? forward voltage (ma) figure 5. forward current vs. forward voltage. 125 c 25 c ? 50 c intercept point will be higher at higher frequencies
4 typical applications rf common rf 1 1 2 3 4 bias 1 rf 2 bias 2 rf common rf 2 bias rf 1 2 3 4 1 2 3 4 1 figure 6. simple spdt switch using only positive bias. figure 7. high isolation spdt switch using dual bias. figure 9. four diode attenuator. see an1048 for details. figure 10. high isolation spst switch (repeat cells as required). input rf in/out 1 2 4 3 3 4 2 1 figure 9. four diode p attenuator . see an1048 for details. fixed bias voltage variable bias bias 3 4 2 1 3 4 2 1 rf common rf 2 rf 1 bias 2 3 4 1 2 3 4 1 3 4 1 2 figure 8. very high isolation spdt switch, dual bias.
5 dielectric relaxation frequency and diode capacitance f dr (dielectric relaxation frequency) for a pin diode is given by the equation f dr = 1 2 ? where = bulk resistivity of the i-layer = 0 r = 10 -12 f/cm = bulk susceptance of silicon in the case of an epitaxial diode with a value for of 10?- cm, f dr will be in ku-band. for a bulk diode fabricated on very pure material, can be as high as 2000, resulting in a value of f dr of 80 mhz. the implications of a low f dr are very important in rf atten - uator and switch circuits. at operating frequencies below f dr , reverse bias (as much as 50v) is needed to minimize junction capacitance. at operating frequencies well above f dr , the curve of capacitance vs. reverse bias is fat. for the hmpp-386x family, f dr is around 500 mhz, resulting in very low capacitance at zero bias for frequencies above 1 ghz. see figure 1. diode lifetime and resistance the resistance of a pin diode is controlled by the con - ductivity (or resistivity) of the i layer. this conductivity is controlled by the density of the cloud of carriers (charges) in the i layer (which is, in turn, controlled by the dc bias). minority carrier lifetime, indicated by the greek symbol , is a measure of the time it takes for the charge stored in the i layer to decay, when forward bias is replaced with reverse bias, to some predetermined value. this lifetime can be short (35 to 200 nsec. for epitaxial diodes) or it can be relatively long (400 to 3000 nsec. for bulk diodes). lifetime has a strong infuence over a number of pin diode parameters, among which are distortion and basic diode behavior. to study the efect of lifetime on diode behavior, we frst defne a cutof frequency f c = 1/ . for short lifetime diodes, this cutof frequency can be as high as 30 mhz while for our longer lifetime diodes f c ? 400 khz. at frequencies which are ten times f c (or more), a pin diode does indeed act like a current controlled variable resistor. at frequen - cies which are one tenth (or less) of f c , a pin diode acts like an ordinary pn junction diode. finally, at 0.1f c f 10f c , the behavior of the diode is very complex. sufce it to mention that in this frequency range, the diode can exhibit very strong capacitive or inductive reactance it will not behave at all like a resistor. the hmpp-386x family features a typical lifetime of 300 to 500 ns, so 10f c for this part is 5 mhz. at any frequency over 5 mhz, the resistance of this diode will follow the curve given in figure 2. from this curve, it can be seen that the hmpp-386x family produces a lower resistance at a given value of bias current than most attenuator pin diodes, making it ideal for applications where current consump - tion is important.
6 figure 11. linear equivalent circuit of the minipak 141 pin diode. 30 ff 30 ff 20 ff 20 ff 1.1 nh single diode package (hmpp-3860) 2 3 1 4 30 ff 30 ff 20 ff 20 ff 12 ff 12 ff 0.5 nh anti-parallel diode package (hmpp-3862) 2 3 1 4 0.5 nh 0.05 nh 0.5 nh 0.05 nh 0.05 nh 0.5 nh 0.05 nh 30 ff 30 ff 20 ff 20 ff 0.5 nh 0.05 nh parallel diode package (hmpp-3865) 2 3 1 4 0.5 nh 0.05 nh 0.5 nh 0.05 nh 0.5 nh 0.05 nh linear equivalent circuit in order to predict the performance of the hmpp-386x as a switch or an attenuator, it is necessary to construct a model which can then be used in one of the several linear analysis programs presently on the market. such a model is given in figure 16, where r s + r j is given in figure 2 and c j is provided in figure 1. careful examination of figure 16 will reveal the fact that the package parasitics (inductance and capacitance) are much lower for the minipak than they are for leaded plastic packages such as the sot-23, sot- 323 or others. this will permit the hmpp-386x family to be used at higher frequencies than its conventional leaded counterparts.
7 minipak 141 outline drawing 1.44 (0.057) 1.40 (0.055) top view side view dimensions are in millimeters (inches) bottom view 1.20 (0.047) 1.16 (0.046) 0.70 (0.028 ) 0.58 (0.023) 1.12 (0.044) 1.08 (0.043) 0.82 (0.032) 0.78 (0.031) 0.32 (0.013) 0.28 (0.011) -0.07 (-0.003) -0.03 (-0.001) 0.00 -0.07 (-0.003) -0.03 (-0.001) 0.42 (0.017) 0.38 (0.015) 0.92 (0.036) 0.88 (0.035) 1.32 (0.052) 1.28 (0.050) 0.00
8 smt assembly reliable assembly of surface mount components is a complex process that involves many material, process, and equipment factors, including: method of heating (e.g., ir or vapor phase refow, wave soldering, etc.) circuit board material, conductor thickness and pattern, type of solder alloy, and the thermal conductivity and thermal mass of components. components with a low mass, such as the minipak package, will reach solder refow temperatures faster than those with a greater mass. after ramping up from room temperature, the circuit board with components attached to it (held in place with solder paste) passes through one or more preheat zones. the preheat zones increase the temperature of the board and components to prevent thermal shock and begin evapo - rating solvents from the solder paste. the refow zone briefy elevates the temperature sufciently to produce a refow of the solder. the rates of change of temperature for the ramp-up and cool-down zones are chosen to be low enough to not cause deformation of the board or damage to components due to thermal shock. the maximum temperature in the refow zone (t max ) should not exceed 260c. these parameters are typical for a surface mount assembly process for avago diodes. as a general guideline, the circuit board and components should be exposed only to the minimum temperatures and times necessary to achieve a uniform refow of solder. assembly information the minipak diode is mounted to the pcb or microstrip board using the pad pattern shown in figure 17. 0 . 4 0 . 4 0 . 3 0 . 5 0 . 3 0 . 5 2.60 0.40 0.20 0.40 mm via hole (4 places) 0.8 2.40 figure 1 . pcb pad layout, minipak (dimensions in mm). this mounting pad pattern is satisfactory for most ap - plications. however, there are applications where a high degree of isolation is required between one diode and the other is required. for such applications, the mounting pad pattern of figure 18 is recommended. figure 13. pcb pad layout, high isolation minipak (dimensions in mm). this pattern uses four via holes, connecting the crossed ground strip pattern to the ground plane of the board.
9 device orientation user feed direction cover tape carrier tape reel end vie w 8 mm 4 mm top view aa aa aa aa note: ?aa? represents package marking code. package marking is right side up with carrier tape perforations at top. conforms to electronic industries rs-481, ?taping of surface mounted components for automated placement.? standard quantity is 3,000 devices per reel. ordering information part number no. of devices container hmpp-386x-tr2 10000 13? reel hmpp-386x-tr1 3000 7? reel hmpp-386x-blk 100 antistatic bag
for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2008 avago technologies. all rights reserved. obsoletes 5989-3629en av02-0652en - november 24, 2008 tape dimensions and product orientation for outline 4t (minipak 141 ) p p 0 p 2 f w c d 1 d e a 0 5 m a x . t 1 ( c a r r i e r t a p e t h i c k n e s s ) t t ( c o v e r t a p e t h i c k n e s s ) 5 m a x . b 0 k 0 d e s c r i p t i o n l e n g t h w i d t h d e p t h p i t c h b o t t o m h o l e d i a m e t e r a 0 b 0 k 0 p d 1 1 . 4 0 0 . 0 5 1 . 6 3 0 . 0 5 0 . 8 0 0 . 0 5 4 . 0 0 0 . 1 0 0 . 8 0 0 . 0 5 0 . 0 5 5 0 . 0 0 2 0 . 0 6 4 0 . 0 0 2 0 . 0 3 1 0 . 0 0 2 0 . 1 5 7 0 . 0 0 4 0 . 0 3 1 0 . 0 0 2 c a v i t y d i a m e t e r p i t c h p o s i t i o n d p 0 e 1 . 5 0 0 . 1 0 4 . 0 0 0 . 1 0 1 . 7 5 0 . 1 0 0 . 0 6 0 0 . 0 0 4 0 . 1 5 7 0 . 0 0 4 0 . 0 6 9 0 . 0 0 4 p e r f o r a t i o n w i d t h t h i c k n e s s w t 1 8 . 0 0 + 0 . 3 0 - 0 . 1 0 0 . 2 5 4 0 . 0 2 0 . 3 1 5 + 0 . 0 1 2 - 0 . 0 0 4 0 . 0 1 0 0 . 0 0 1 c a r r i e r t a p e c a v i t y t o p e r f o r a t i o n ( w i d t h d i r e c t i o n ) c a v i t y t o p e r f o r a t i o n ( l e n g t h d i r e c t i o n ) f p 2 3 . 5 0 0 . 0 5 2 . 0 0 0 . 0 5 0 . 1 3 8 0 . 0 0 2 0 . 0 7 9 0 . 0 0 2 d i s t a n c e w i d t h t a p e t h i c k n e s s c t t 5 . 4 0 0 . 1 0 0 . 0 6 2 0 . 0 0 1 0 . 2 1 3 0 . 0 0 4 0 . 0 0 2 0 . 0 0 0 0 4 c o v e r t a p e s y m b o l s i z e ( m m ) s i z e ( i n c h e s )
|
