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ds07-16507-2ea fujitsu microelectronics data sheet copyright?2005-2008 fujitsu microelect ronics limited all rights reserved 2005.10 32 - bit proprietary microcontroller cmos fr60lite mb91260b series mb91263b/mb91264b/mb91f264b description the mb91260b series is a 32-bit risc microcontroller designed by fujitsu microelectronics for embedded control applications which require high-speed processing. the cpu is used the fr family and the compatibility of fr60lite. features ? fr60lite cpu ? 32-bit risc, load/store architecture with a five-stage pipeline ? maximum operating frequency : 33 mhz (oscillation fr equency 4.192 mhz, oscillati on frequency 8-multiplier (pll clock multiplication method) ? 16-bit fixed length instruct ions (basic instructions) ? execution speed of instructions : 1 instruction per cycle ? memory-to-memory transfer, bit handling, barrel shift instructions, etc. : instructions suitable for embedded applications ? function entry/exit instructions, mult iple-register load/store instructions : instructions adapted for c-language (continued) pac k ag e s 100-pin plastic qfp 100-pin plastic lqfp (fpt-100p-m06) (fpt-100p-m05)
mb91260b series 2 (continued) ? register interlock function : facilitates coding in assembler. ? built-in multiplier with instruction-level support ? 32 bit multiplication with sign : 5 cycles ? 16 bit multiplication with sign : 3 cycles ? interrupt (pc, ps save) : 6 cycles, 16 priority levels ? harvard architecture allowing program access and data access to be executed simultaneously ? fr family instruction compatible ? internal peripheral functions ? capacity of internal rom and rom type mask rom : 128 kbytes (mb91263 b)/256 kbytes (mb91264b) flash rom : 256 kbytes (mb91f264b) ? capacity of internal ram : 8 kbytes ? a/d converter (sequential comparison type) ? resolution : 10 bits : 2 channels 2 units, 8 channels 1 unit ? conversion time : 1.2 s (minimum conversion time system clock at 33 mhz) 1.35 s (minimum conversion time system clock at 20 mhz) ? external interrupt input : 10 channels ? bit search module (for realos) function for searching the msb in each word for the first 1-to-0 inverted bit position ? uart (full-duplex double buffer) : 3 channels selectable parity on/off asynchronous (start-stop synchronized) or clock-synchronous communications selectable internal timer for dedicated baud rate (u-timer) on each channel external clock can be used as transfer clock error detection function for parity, frame and overrun errors ? 8/16-bit ppg timer : 16 channels (at 8-bit) / 8 channels (at 16-bit) ? 16-bit reload timer : 3 channels (with cascade mode, without output of reload timer 0) ? 16-bit free-run timer : 1 channel ? 16-bit pwc timer : 2 channels ? input capture : 4 channels (interface with free-run timer) ? output compare : 6 channels (interface with free-run timer) ? waveform generator various waveforms which are generated by using output compare, 16-bit ppg timer 0 and 16-bit dead timer ?mac ram : instruction ram 256 16-bit xram 64 16-bit yram 64 16-bit execution of 1 cycle pr oduct addition (16-bit 16-bit + 40 bits) operation results are extracted rounded from 40 to 16 bits ? dmac (dma controller) : 5 channels operation of transfer and activation by internal peripheral interrupts and software ? watchdog timer ? low power consumption mode sleep/stop function ? other ? package : qfp-100, lqfp-100 ? technology : cmos 0.35 m ? power supply : 1-power supply [vcc = 4.0 v to 5.5 v]
mb91260b series 3 pin assignment (continued) p23/sin1 p24/sot1 p25/sck1 p26/int6 p27/int7 p50 p51/tin0 p52/tin1 p53/tin2 p54/int0 p55/int1 p56/int2 p57/int3 pg0/cki/int4 pg1/ppg0/int5 pg2 v cc v ss c pg3/sin2 pg4/sot2 pg5/sck2 p40 p41 p42 p43 p44 p45 p46 p47 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 p02/ppg3 p01/ppg2 p00/ppg1 init md0 md1 md2 nmi p77/adtg2 p76/adtg1 p75/adtg0 p74/pwi1 v ss v cc p73/pwi0 p72/dtti p71/tot2 p70/tot1 p63/int9 p62/int8 p61/ic3 p60/ic2 p37/ic1 p36/ic0 p35/rto5 p34/rto4 p33/rto3 p32/rto2 p31/rto1 p30/rto0 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 p22/sck0 p21/sot0 p20/sin0 p17 p16/ppg15 x0 x1 v ss v cc p15/ppg14 p14/ppg13 p13/ppg12 p12/ppg11 p11/ppg10 p10/ppg9 p07/ppg8 p06/ppg7 p05/ppg6 p04/ppg5 p03/ppg4 pe1/an11 pe0/an10 avrh2 acc av cc avrh1 av ss pd1/an9 pd0/an8 avrh0 pc7/an7 pc6/an6 pc5/an5 pc4/an4 pc3/an3 pc2/an2 pc1/an1 pc0/an0 v cc v ss 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 (top view) (fpt-100-m06)
mb91260b series 4 (continued) p25/sck1 p26/int6 p27/int7 p50 p51/tin0 p52/tin1 p53/tin2 p54/int0 p55/int1 p56/int2 p57/int3 pg0/cki/int4 pg1/ppg0/int5 pg2 v cc v ss c pg3/sin2 pg4/sot2 pg5/sck2 p40 p41 p42 p43 p44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 init md0 md1 md2 nmi p77/adtg2 p76/adtg1 p75/adtg0 p74/pwi1 v ss v cc p73/pwi0 p72/dtti p71/tot2 p70/tot1 p63/int9 p62/int8 p61/ic3 p60/ic2 p37/ic1 p36/ic0 p35/rto5 p34/rto4 p33/rto3 p32/rto2 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 p24/sot1 p23/sin1 p22/sck0 p21/sot0 p20/sin0 p17 p16/ppg15 x0 x1 v ss v cc p15/ppg14 p14/ppg13 p13/ppg12 p12/ppg11 p11/ppg10 p10/ppg9 p07/ppg8 p06/ppg7 p05/ppg6 p04/ppg5 p03/ppg4 p02/ppg3 p01/ppg2 p00/ppg1 p45 p46 p47 pe1/an11 pe0/an10 avrh2 acc av cc avrh1 av ss pd1/an9 pd0/an8 avrh0 pc7/an7 pc6/an6 pc5/an5 pc4/an4 pc3/an3 pc2/an2 pc1/an1 pc0/an0 v cc v ss p30/rto0 p31/rto1 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 (top view) (fpt-100-m05)
mb91260b series 5 pin description (continued) pin no. pin name circuit type description qfp lqfp 199 sin1 d uart1 data input pin. since this inpu t is used as required when uart1 is performing input operation, the port output must remain off unless used in- tentionally. p23 general-purpose i/o port. this port is enabled when uart1 data input is disabled. 2100 sot1 d uart1 data output pin. this function is enabled when uart1 data output is enabled. p24 general-purpose i/o port. this function is enabled when uart1 data out- put is disabled. 31 sck1 d uart1 clock input/output pin. this function is enabled when uart1 clock output is enabled. p25 general-purpose i/o port. this function is enabled when uart1 clock out- put is disabled. 42 int6 e external interrupt input pin. since this input is used as required when the corresponding external interrupt is enabled, the port output must remain off unless used intentionally. p26 general-purpose i/o port. this function is enabled when external interrupt input is disabled. 53 int7 e external interrupt input pin. since this input is used as required when the corresponding external interrupt is enabled, the port output must remain off unless used intentionally. p27 general-purpose i/o port. this function is enabled when external interrupt input is disabled. 6 4 p50 c general-purpose i/o port. this port is enabled in single-chip mode. 75 tin0 c reload timer 0 external trigger input pin. since this input is used as re- quired when trigger input is enabled, the port output must remain off unless used intentionally. p51 general-purpose i/o port. this function is enabled when reload timer 0 ex- ternal clock input is disabled. 86 tin1 c reload timer 1 external trigger input pin. since this input is used as re- quired when trigger input is enabled, the port output must remain off unless used intentionally. p52 general-purpose i/o port. this function is enabled when reload timer 1 ex- ternal clock input is disabled. 97 tin2 c reload timer 2 external trigger input pin. since this input is used as re- quired when trigger input is enabled, the port output must remain off unless used intentionally. p53 general-purpose i/o port. this function is enabled when reload timer 2 ex- ternal clock input is disabled.
mb91260b series 6 (continued) pin no. pin name circuit type description qfp lqfp 10 8 int0 e external interrupt input pin. since this input is used as required when the corresponding external interrupt is enabled, the port output must remain off unless used intentionally. p54 general-purpose i/o port. this function is enabled when external interrupt input is disabled. 11 9 int1 e external interrupt input pin. since this input is used as required when the corresponding external interrupt is enabled, the port output must remain off unless used intentionally. p55 general-purpose i/o port. this function is enabled when external interrupt input is disabled. 12 10 int2 e external interrupt input pin. since this input is used as required when the corresponding external interrupt is enabled, the port output must remain off unless used intentionally. p56 general-purpose i/o port. this function is enabled when external interrupt input is disabled. 13 11 int3 e external interrupt input pin. since this input is used as required when the corresponding external interrupt is enabled, the port output must remain off unless used intentionally. p57 general-purpose i/o port. this function is enabled when external interrupt input is disabled. 14 12 cki e free-running timer external clock input pin. since this input is used as re- quired when selected as the external cl ock input for the free-running timer, the port output must remain off unless used intentionally. int4 external interrupt input pin. since this input is used as required when the corresponding external interrupt is enabled, the port output must remain off unless used intentionally. pg0 general-purpose i/o port. this port is enabled when free-running timer ex- ternal clock input and external interrupt input are disabled. 15 13 ppg0 e ppg timer 0 output pin. this function is enabled when ppg timer 0 output is enabled. int5 external interrupt input pin. since this input is used as required when the corresponding external interrupt is enabled, the port output must remain off unless used intentionally. pg1 general-purpose i/o port. this port is enabled when ppg timer 0 output and external interrupt input are disabled. 16 14 pg2 c general-purpose i/o port. 20 18 sin2 d uart2 data input pin. since this inpu t is used as required when uart2 is performing input operation, the port output must remain off unless used in- tentionally. pg3 general-purpose i/o port. this port is enabled when uart2 data input is disabled.
mb91260b series 7 (continued) pin no. pin name circuit type description qfp lqfp 21 19 sot2 d uart2 data output pin. this function is enabled when uart2 data output is enabled. pg4 general-purpose i/o port. this port is enabled when uart2 data output is disabled. 22 20 sck2 d uart2 clock input/output pin. this function is enabled when uart2 clock output is enabled. pg5 general-purpose i/o port. this function is enabled when uart2 clock out- put is disabled. 23 21 p40 c general-purpose i/o port. 24 22 p41 c general-purpose i/o port. 25 23 p42 c general-purpose i/o port. 26 24 p43 c general-purpose i/o port. 27 25 p44 c general-purpose i/o port. 28 26 p45 c general-purpose i/o port. 29 27 p46 c general-purpose i/o port. 30 28 p47 c general-purpose i/o port. 31 29 an11 g a/d converter analog input pin. this function is enabled when the aicr2 register specifies analog input. pe1 general-purpose i/o port. this function is enabled when analog input is disabled. 32 30 an10 g a/d converter analog input pin. this function is enabled when the aicr2 register specifies analog input. pe0 general-purpose i/o port. this function is enabled when analog input is disabled. 38 36 an9 g a/d converter analog input pin. this function is enabled when the aicr1 register specifies analog input. pd1 general-purpose i/o port. this function is enabled when analog input is disabled. 39 37 an8 g a/d converter analog input pin. this function is enabled when the aicr1 register specifies analog input. pd0 general-purpose i/o port. this function is enabled when analog input is disabled. 41 39 an7 g a/d converter analog input pin. this function is enabled when the aicr0 register specifies analog input. pc7 general-purpose i/o port. this function is enabled when analog input is disabled.
mb91260b series 8 (continued) pin no. pin name circuit type description qfp lqfp 42 40 an6 g a/d converter analog input pin. this function is enabled when the aicr0 register specifies analog input. pc6 general-purpose i/o port. this function is enabled when analog input is disabled. 43 41 an5 g a/d converter analog input pin. this function is enabled when the aicr0 register specifies analog input. pc5 general-purpose i/o port. this function is enabled when analog input is disabled. 44 42 an4 g a/d converter analog input pin. this function is enabled when the aicr0 register specifies analog input. pc4 general-purpose i/o port. this function is enabled when analog input is disabled. 45 43 an3 g a/d converter analog input pin. this function is enabled when the aicr0 register specifies analog input. pc3 general-purpose i/o port. this function is enabled when analog input is disabled. 46 44 an2 g a/d converter analog input pin. this function is enabled when the aicr0 register specifies analog input. pc2 general-purpose i/o port. this function is enabled when analog input is disabled. 47 45 an1 g a/d converter analog input pin. this function is enabled when the aicr0 register specifies analog input. pc1 general-purpose i/o port. this function is enabled when analog input is disabled. 48 46 an0 g a/d converter analog input pin. this function is enabled when the aicr0 register specifies analog input. pc0 general-purpose i/o port. this function is enabled when analog input is disabled. 51 49 rto0 j multifunction timer waveform generator output pin. this pin outputs a spec- ified waveform to the waveform generato r. the waveform output is enabled when waveform generator output is enabled. p30 general-purpose i/o port. this function is enabled when waveform gener- ator output is disabled. 52 50 rto1 j multifunction timer waveform generator output pin. this pin outputs a spec- ified waveform to the waveform generato r. the waveform output is enabled when waveform generator output is enabled. p31 general-purpose i/o port. this function is enabled when waveform gener- ator output is disabled.
mb91260b series 9 (continued) pin no. pin name circuit type description qfp lqfp 53 51 rto2 j multifunction timer waveform generator output pin. this pin outputs a spec- ified waveform to the waveform generato r. the waveform output is enabled when waveform generator output is enabled. p32 general-purpose i/o port. this function is enabled when waveform gener- ator output is disabled. 54 52 rto3 j multifunction timer waveform generator output pin. this pin outputs a spec- ified waveform to the waveform generato r. the waveform output is enabled when waveform generator output is enabled. p33 general-purpose i/o port. this function is enabled when waveform gener- ator output is disabled. 55 53 rto4 j multifunction timer waveform generator output pin. this pin outputs a spec- ified waveform to the waveform generato r. the waveform output is enabled when waveform generator output is enabled. p34 general-purpose i/o port. this function is enabled when waveform gener- ator output is disabled. 56 54 rto5 j multifunction timer waveform generator output pin. this pin outputs a spec- ified waveform to the waveform generato r. the waveform output is enabled when waveform generator output is enabled. p35 general-purpose i/o port. this function is enabled when waveform gener- ator output is disabled. 57 55 ic0 d input capture 0 trigger input pin. the trigger can be input when the input capture trigger input and input port are set. since this input is used as re- quired when selected as the input capture input, the port output must re- main off unless us ed intentionally. p36 general-purpose i/o port. this function is enabled when input capture trig- ger input is disabled. 58 56 ic1 d input capture 1 trigger input pin. the trigger can be input when the input capture trigger input and input port are set. since this input is used as re- quired when selected as the input capture input, the port output must re- main off unless us ed intentionally. p37 general-purpose i/o port. this function is enabled when input capture trig- ger input is disabled. 59 57 ic2 d input capture 2 trigger input pin. the trigger can be input when the input capture trigger input and input port are set. since this input is used as re- quired when selected as the input capture input, the port output must re- main off unless us ed intentionally. p60 general-purpose i/o port. this function is enabled when input capture trig- ger input is disabled.
mb91260b series 10 (continued) pin no. pin name circuit type description qfp lqfp 60 58 ic3 d input capture 3 trigger input pin. the trigger can be input when the input capture trigger input and input port are set. since this input is used as re- quired when selected as the input capture input, the port output must re- main off unless us ed intentionally. p61 general-purpose i/o port. this function is enabled when input capture trig- ger input is disabled. 61 59 int8 e external interrupt input pin. since this input is used as required when the corresponding external interrupt is enabled, the port output must remain off unless used intentionally. p62 general-purpose i/o port. this function is enabled when external interrupt input is disabled. 62 60 int9 e external interrupt input pin. since this input is used as required when the corresponding external interrupt is enabled, the port output must remain off unless used intentionally. p63 general-purpose i/o port. this function is enabled when external interrupt input is disabled. 63 61 tot1 c reload timer 1 output pin. this func tion is enabled when reload timer out- put is enabled. p70 general-purpose i/o port. this function is enabled when reload timer out- put is disabled. 64 62 tot2 c reload timer 2 output pin. this func tion is enabled when reload timer out- put is enabled. p71 general-purpose i/o port. this function is enabled when reload timer out- put is disabled. 65 63 dtti d input signal for controlling multifunction timer wave form genera tor output pins rto0 to rto5. this function is enabled when dtti input is enabled. p72 general-purpose i/o port. this function is enabled when dtti input is dis- abled. 66 64 pwi0 d pwc timer 0 pulse width counter input pin. this function is enabled when pwc timer 0 pulse width counter input is enabled. p73 general-purpose i/o port. this function is enabled when pwc timer 0 pulse width counter input is disabled. 69 67 pwi1 d pwc timer 1 pulse width counter input pin. this function is enabled when pwc timer 1 pulse width counter input is enabled. p74 general-purpose i/o port. this function is enabled when pwc timer 1 pulse width counter input is disabled. 70 68 adtg0 c a/d converter 0 external trigger input pin. since this input is used as re- quired when selected as the a/d converter trigger source, the port output must remain off unless used intentionally. p75 general-purpose i/o port. this function is enabled when a/d converter 0 external trigger input is disabled.
mb91260b series 11 (continued) pin no. pin name circuit type description qfp lqfp 71 69 adtg1 c a/d converter 1 external trigger input pin. since this input is used as re- quired when selected as the a/d converter trigger source, the port output must remain off unless used intentionally. p76 general-purpose i/o port. this function is enabled when a/d converter 1 external trigger input is disabled. 72 70 adtg2 c a/d converter 2 external trigger input pin. since this input is used as re- quired when selected as the a/d converter trigger source, the port output must remain off unless used intentionally. p77 general-purpose i/o port. this function is enabled when a/d converter 2 external trigger input is disabled. 73 71 nmi h nmi (non maskable interrupt) input pin. 74 72 md2 k mode pin 2. the setting of this pin determines the basic operation mode. connect the pin to vcc or vss. 75 73 md1 k mode pin 1. the setting of this pin determines the basic operation mode. connect the pin to vcc or vss. 76 74 md0 k mode pin 0. the setting of this pin determines the basic operation mode. connect the pin to vcc or vss. 77 75 init i external reset input pin. 78 76 ppg1 c ppg timer 1 output pin. this function is enabled when ppg timer 1 output is enabled. p00 general-purpose i/o port. this function is enabled when ppg timer 1 out- put is disabled. 79 77 ppg2 c ppg timer 2 output pin. this function is enabled when ppg timer 2 output is enabled. p01 general-purpose i/o port. this function is enabled when ppg timer 2 out- put is disabled. 80 78 ppg3 c ppg timer 3 output pin. this function is enabled when ppg timer 3 output is enabled. p02 general-purpose i/o port. this function is enabled when ppg timer 3 out- put is disabled. 81 79 ppg4 c ppg timer 4 output pin. this function is enabled when ppg timer 4 output is enabled. p03 general-purpose i/o port. this function is enabled when ppg timer 4 out- put is disabled. 82 80 ppg5 c ppg timer 5 output pin. this function is enabled when ppg timer 5 output is enabled. p04 general-purpose i/o port. this function is enabled when ppg timer 5 out- put is disabled.
mb91260b series 12 (continued) pin no. pin name circuit type description qfp lqfp 83 81 ppg6 c ppg timer 6 output pin. this function is enabled when ppg timer 6 output is enabled. p05 general-purpose i/o port. this function is enabled when ppg timer 6 out- put is disabled. 84 82 ppg7 c ppg timer 7 output pin. this function is enabled when ppg timer 7 output is enabled. p06 general-purpose i/o port. this function is enabled when ppg timer 7 out- put is disabled. 85 83 ppg8 c ppg timer 8 output pin. this function is enabled when ppg timer 8 output is enabled. p07 general-purpose i/o port. this function is enabled when ppg timer 8 out- put is disabled. 86 84 ppg9 c ppg timer 9 output pin. this function is enabled when ppg timer 9 output is enabled. p10 general-purpose i/o port. this function is enabled when ppg timer 9 out- put is disabled. 87 85 ppg10 c ppg timer 10 output pin. this function is enabled when ppg timer 10 out- put is enabled. p11 general-purpose i/o port. this function is enabled when ppg timer 10 out- put is disabled. 88 86 ppg11 c ppg timer 11 output pin. this function is enabled when ppg timer 11 out- put is enabled. p12 general-purpose i/o port. this function is enabled when ppg timer 11 out- put is disabled. 89 87 ppg12 c ppg timer 12 output pin. this function is enabled when ppg timer 12 out- put is enabled. p13 general-purpose i/o port. this function is enabled when ppg timer 12 out- put is disabled. 90 88 ppg13 c ppg timer 13 output pin. this function is enabled when ppg timer 13 out- put is enabled. p14 general-purpose i/o port. this function is enabled when ppg timer 13 out- put is disabled. 91 89 ppg14 c ppg timer 14 output pin. this function is enabled when ppg timer 14 out- put is enabled. p15 general-purpose i/o port. this function is enabled when ppg timer 14 out- put is disabled. 94 92 x1 a clock (oscillation) output pin. 95 93 x0 a clock (oscillation) input pin.
mb91260b series 13 (continued) ? power supply and gnd pins pin no. pin name circuit type description qfp lqfp 96 94 ppg15 c ppg timer 15 output pin. this function is enabled when ppg timer 15 out- put is enabled. p16 general-purpose i/o port. this function is enabled when ppg timer 15 out- put is disabled. 97 95 p17 c general-purpose i/o port. 98 96 sin0 d uart0 data input pin. since this inpu t is used as required when uart0 is performing input operation, the port output must remain off unless used in- tentionally. p20 general-purpose i/o port. this port is enabled when uart0 data input is disabled. 99 97 sot0 d uart0 data output pin. this function is enabled when uart0 data output is enabled. p21 general-purpose i/o port. this port is enabled when uart0 data output is disabled. 100 98 sck0 d uart0 clock input/output pin. this function is enabled when uart0 clock output is enabled. p22 general-purpose i/o port. this function is enabled when uart0 clock out- put is disabled. pin no. pin name description qfp lqfp 18, 50, 68, 93 16, 48, 66, 91 vss gnd pins. us e all of these pins at equal potential. 17, 49, 67, 92 15, 47, 65, 90 vcc power-supply pins . use all of these pins at equal potential. 35 33 avcc analog power-supply pin for a/d converter 33 31 avrh2 analog reference power-supply pin for a/d converter 2 36 34 avrh1 analog reference power-supply pin for a/d converter 1 40 38 avrh0 analog reference power-supply pin for a/d converter 0 37 35 avss analog gnd pin for a/d converter 19 17 c capacitor coupling pin for internal regulator 34 32 acc analog capacitor coupling pin
mb91260b series 14 i/o circuit type (continued) type circuit type remarks a ? oscillation circuit ? oscillation feedback resistance : approx. 1 m c ? cmos level output ? cmos level input. ? with standby control ? with pull-up control ?i ol = 4 ma d ? cmos level output ? cmos level hysteresis input. ? with standby control ? with pull-up control ?i ol = 4 ma x1 x0 clock input standby control p-ch n-ch p-ch digital input pull-up control digital output digital output standby control p-ch p-ch n-ch digital input pull-up control digital output digital output standby control
mb91260b series 15 (continued) type circuit type remarks e ? cmos level output ? cmos level hysteresis input. ? without standby control ? with pull-up control ?i ol = 4 ma g ? analog/cmos level input/output pin ? cmos level output ? cmos level input. (attached with standby control) ? analog input (analog input is enabled when aicr register?s corresponding bit is set to ?1?.) ?i ol = 4 ma h ? cmos level hysteresis input. ? without standby control p-ch n-ch p-ch digital input digital output digital output pull-up control p-ch n-ch analog input digital input digital output digital output standby control n-ch p-ch digital input
mb91260b series 16 (continued) type circuit type remarks i ? cmos level hysteresis input. ? with pull-up resistor ? without standby control j ? cmos level output ? cmos level hysteresis input. ? with standby control ?i ol = 12 ma k ? cmos level input. ? without standby control p-ch p-ch n-ch digital input p-ch n-ch digital output digital output digital input standby control p-ch n-ch digital input
mb91260b series 17 handling devices preventing latch-up latch-up may occur in a cmos ic if a voltage greater than v cc or less than v ss is applied to an input or output pin or if an above-rating voltage is applied between v cc and v ss . a latch-up, if it occurs, significantly increases the power supply current and may cause thermal destruction of an element. when you use a cmos ic, be very careful not to exceed the absolute maximum rating. treatment of unused pins do not leave an unused input pin open, since it may cause a malfunction. handle by, for example, using a pull- up or pull-down resistor. about power supply pins in products with multiple v cc or v ss pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. however, you must connect the pins to external power supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. moreover, connect the current supply source with the v cc and v ss pins of this device at the low impedance. it is also advisable to connect a cera mic bypass capacitor of approximately 0.1 f between v cc and v ss near this device. about crystal oscillator circuit noise near the x0, x1, x0a and x1a pins may cause the de vice to malfunction. design the printed circuit board so that x0, x1, x0a and x1a the cryst al oscillator (or ceramic oscillator) , and the bypass ca pacitor to ground are located as close to the device as possible. it is strongly recommended to design the pc board artwork with the x0, x1, x0a and x1a pins surrounded by ground plane because stable operation can be expected with such a layout. please ask the crystal maker to evaluate the oscillati onal characteristics of the crystal and this device. about mode pins (md0 to md2) these pins should be connected directly to v cc or v ss . to prevent the device erroneously switching to test mode due to noise, design the printed circuit board such that the distance between the mode pins and v cc or v ss is as short as possible and th e connection impedance is low. operation at start-up be sure to execute setting in itialized reset (init) with init pin immediately after start-up. also, in order to provide the oscillation stabilization wait time for the oscilla tion circuit immediately after start-up, hold the ?l? level input to the init pin for the required stabilization wait time. (for init via the init pin, the oscillation stabilization wait time setting is initialized to the minimum value) . about oscillation input at power on when turning the power on, maintain cl ock input until the device is releas ed from the oscilla tion stabilization wait state.
mb91260b series 18 caution operation during pll clock mode even if the oscillator comes off or the clock input stops with the pll clock selected for this device, the device may continue to operate at the free -run frequency of the pll?s internal self-oscillating oscillator circuit. performance of this operation, however, cannot be guaranteed. external clock when external clock is selected, the opposite phase clock to x0 pin must be supplied to x1 pin simultaneously. if the stop mode (oscillation stop mo de) is used simultaneously, the x1 pi n is stopped with the "h" output. so, when stop mode is spec ified, approximately 1 k of resistance should be added externally to avoid the conflict of output. the following figure shows using an external clock. c pin a bypass capacitor of approximately 0.1 f should be connected the c pin for built-in regulator. acc pin a capacitor should be inserted between the acc pin and the avcc pin as this product has built-in regulator for a/d converter. x0 x1 using an external clock mb91260b series c 0.1 f gnd v ss mb91260b series acc 0.1 f av ss mb91260b series
mb91260b series 19 clock control block input the ?l? signal to the init pin to assure the clock oscillation stabilization wait time. switch shared port function to switch between the use as a port and the use as a dedicated pin, use the port function register (pfr) . low power consumption mode to enter the standby mode, use the synchronous standby mode (set with the syncs bit as bit 8 in the tbcr : timebase counter control register) and be sure to use the following sequence in addition, please set i flag, ilm, and icr to diverge to the interruption handler that is the return factor after the standby returns. ?please do not do the following when the monitor debugger is used. ? break point setting for above instruction lines ? step execution for above instruction lines notes on the ps register as the ps register is processed by some instructions in advance, exception handling below may cause the interrupt handling routine to break when the debugger is used or the display contents of flags in the ps register to be updated. as the microcontroller is designed to carry out reprocessing correctly upon returning from such an eit event, it performs operations before and after the eit as specified in either case. ? the following operations may be performed when the instruction immediately followed by a divou/divos instruction is (a) acceptance of a user interrupt, (b) si ngle-stepped, or (c) breaks in response to a data event or emulator menu : 1) the d0 and d1 flags are updated in advance. 2) an eit handling routine (user interrupt or emulator) is executed. 3) upon returning from the eit, the divou/divos instruction is executed, and the d0 and d1 flags are updated to the same values as in 1). ? the following operations are performed when the orccr/stilm/movri and ps instructions are executed to allow the interrupt. (ldi #value_of_standby, r0) : value_of standby is write data to stcr. (ldi #_stcr, r12) : _stcr is address (481h) of stcr. stb r0, @r12 : writing to st andby control register (stcr) ldub @r12, r0 : stcr read for synchronous standby ldub @r12, r0 : dummy re-read of stcr nop : nop 5 for arrangement of timing nop nop nop nop
mb91260b series 20 1) the ps register is updated in advance. 2) an eit handling routine (user interrupt) is executed. 3) upon returning from the eit, the above instructions are executed, and the ps register is updated to the same value as in 1). watchdog timer the watchdog timer built in this model monitors a program that it defers a reset within a certain period of time. the watchdog timer resets the cpu if the program runs out of controls, preventing the reset defer function from being executed. once the function of the watchdog timer is enabled, therefore, the watchdog timer keeps on operating programs until it resets the cpu. as an exception, the watchdog timer defers a reset automatically under the condition in which the cpu stops program execution. for those conditions to which this exception applies, see the function description of watchdog timer.
mb91260b series 21 note on debugger ? step execution of reti command if an interrupt occurs frequently during step execution, the corresponding interrupt handling routine is executed repeatedly after step execution. this will prevent the main routine and low-interrupt-level programs from being executed. do not execute step of reti instruction for escape. disable the corresponding interrupt and execute debugger when the corresponding interrupt handling routine no longer needs debugging. ? operand break do not apply a data event break to access to the area containing the address of a system stack pointer. ? execution in an unused area of flash memory accidentally executing an instruction in an unus ed area of flash memory (with data placed at 0xffff h ) prevents breaks from being accepted. to prevent this, the code event address mask function of the debugger should be used to cause a break when accessing an instruction in an unused area. ? power-on debugging all of the following three conditions must be satisfied when the power supply is turned off by power-on debugging. (1) the time for the user power to fall from 0.9 v cc to 0.5 v cc is 25 s or longer. note : in a dual-power system, vcc indicates the external i/o power supply voltage. (2) cpu operating frequency must be higher than 1 mhz. (3) during execution of user program ? interrupt handler for nmi request (tool) add the following program to the interrupt handler to prevent the device from malfunctioning in case the factor flag to be set only in response to a break request from the ice is set, for example, by an adverse effect of noise to the dsu pin while the ice is not connected. enable to use the ice while adding this program. additional location next interrupt handler additional program interrupt source : nmi request (tool) interrupt number : #13 (decimal) , 0d h (hexa decimal) offset : 3c8 h address tbr is default : 000fffc8 h stm (r0, r1) ldi #b00h, r0; : b00 h is the address of dsu break factor register. ldi #0, r1 stb r1, @r0 : clear the break factor register. ldm (r0, r1) reti
mb91260b series 22 block diagram ram 8 kbytes dmac 5 channels 3 channels uart x0, x1 md0 to md2 init int0 to int9 nmi sin0 to sin2 sot0 to sot2 sck0 to sck2 av cc adtg0 an0 to an7 avrh0 adtg1 avrh1 an8, an9 adtg2 avrh2 an10, an11 port tin0 to tin2 tot1, tot2 pwi0, pwi1 ppg0 to ppg15 cki ic0 to ic3 rto0 to rto5 dtti 32 32 16 32 rom 128 kbytes/ rom 256 kbytes/ flash 256 kbytes bit search mac clock control interrupt controller 10 channels external interrupt 3 channels u-timer fr60 lite cpu core bus converter port i/f 3 channels 16-bit reload timer 16/8 channels 8/16 ppg timer free-run timer 1 channel input capture 4 channels output compare 6 channels waveform generator multi-function timer 8 channels input 8/10-bit a/d converter 0 2 channels input 8/10-bit a/d converter 1 2 channels input 8/10-bit a/d converter 2 32 ? 16 adapter 2 channels 16-bit pwc timer
mb91260b series 23 memory space 1. memory space the fr family has 4 gbytes of logical address space (2 32 addresses) available to the cpu by linear access. ? direct addressing areas the following address space areas are used as i/o areas. these areas are called direct addressing areas, in whic h the address of an operand can be specified directly during an instruction. the size of directly addressable areas depends on the data size to be being accessed as follows. byte data access : 000 h to 0ff h half word data access : 000 h to 1ff h word data access : 000 h to 3ff h 2. memory map 000e 0000 h 0000 0000 h 0000 0400 h 0001 0000 h 0003 e000 h 0004 0000 h 0010 0000 h ffff ffff h i/o i/o single chip mode refer to ? i/o map?. direct addressing area access disallowed internal ram 8 kbytes access disallowed internal ram 128 kbytes access disallowed mb91263b 000c 0000 h 0000 0000 h 0000 0400 h 0001 0000 h 0003 e000 h 0004 0000 h 0010 0000 h ffff ffff h i/o i/o single chip mode refer to ? i/o map?. direct addressing area access disallowed internal ram 8 kbytes access disallowed internal ram 256 kbytes access disallowed mb91f264b/mb91264b
mb91260b series 24 mode settings the fr family uses mode pins (md2 to md0) and a mode data to set the operation mode. ? mode pins the md2 to md0 pins specify how the mode vector fetch and reset vector fetch is performed. setting is prohibited other than that shown in the following table. ? mode data data written to the internal mode register (modr) by a mode vector fetch is called mode data. after an operation mode has been set in the mode register, the device operates in the operation mode. the mode data is set by all reset source. user programs cannot set data to the mode register. details of mode data description bit31 to bit24 are all reserved bits. be sure to set this bit to ?00000111?. operation is not guaranteed when any value other than ?00000111? is set. note : mode data set in the mode vector must be placed as byte data at 0x000ffff8 h . use the highest byte from bit31 to bit24 for placemen t as the fr family uses the big endian for byte endian. mode pins mode name reset vector access area remarks md2 md1 md0 0 0 0 internal rom mode vector internal 0 0 1 external rom mode vector external not supported by this model. 31 bit 30 29 28 27 26 25 24 00000111 operation mode setting bits 31 bit 24 23 16 15 8 7 0 xxxxxxxx 0x000ffff8 h 0x000ffff8 h 0x000ffffc h xxxxxxxx xxxxxxxx mode data mode data reset vector xxxxxxxx xxxxxxxx xxxxxxxx incorrect correct
mb91260b series 25 i/o map [how to read the table] note : initial values of register bits are represented as follows : ? 1 ? : initial value ? 1 ? ? 0 ? : initial value ? 0 ? ? x ? : initial value ? undefined? ? - ? : no physical register at this location access is barred with an undefined data access attribute. address register block + 0 + 1 + 2 + 3 000000 h pdr0 [r/w] b xxxxxxxx pdr1 [r/w] b xxxxxxxx pdr2 [r/w] b xxxxxxxx pdr3 [r/w] b xxxxxxxx t-unit port data register read/write attribute access unit (b : byte, h : half word, w : word) initial value of re gister after reset register name (column 1 of the register is at address 4n, column 2 is at address 4n + 1...) leftmost register address (for word-length access, column 1 of the register becomes the msb of the data.)
mb91260b series 26 (continued) address register block + 0 + 1 + 2 + 3 000000 h pdr0 [r/w] b xxxxxxxx pdr1 [r/w] b xxxxxxxx pdr2 [r/w] b xxxxxxxx pdr3 [r/w] b xxxxxxxx port data register 000004 h pdr4 [r/w] b xxxxxxxx pdr5 [r/w] b xxxxxxxx pdr6 [r/w] b ----xxxx pdr7 [r/w] b xxxxxxxx 000008 h ? 00000c h pdrc [r/w] b xxxxxxxx pdrd [r/w] b ------xx pdre [r/w] b ------xx ? 000010 h pdrg [r/w] b --xxxxxx ?? ? 000014 h to 00003c h ? reserved 000040 h eirr0 [r/w] b, h, w 00000000 enir0 [r/w] b, h, w 00000000 elvr0 [r/w] b, h, w 00000000 00000000 external interrupt (int0 to int7) 000044 h dicr [r/w] b, h, w -------0 hrcl [r/w, r] b, h, w 0--11111 ?? delay interrupt/ hold request 000048 h tmrlr0 [w] h, w xxxxxxxx xxxxxxxx tmr0 [r] h, w xxxxxxxx xxxxxxxx reload timer 0 00004c h ? tmcsr0 [r/w, r] b, h, w ---00000 00000000 000050 h tmrlr1 [w] h, w xxxxxxxx xxxxxxxx tmr1 [r] h, w xxxxxxxx xxxxxxxx reload timer 1 000054 h ? tmcsr1 [r/w, r] b, h, w ---00000 00000000 000058 h tmrlr2 [w] h, w xxxxxxxx xxxxxxxx tmr2 [r] h, w xxxxxxxx xxxxxxxx reload timer 2 00005c h ? tmcsr2 [r/w, r] b, h, w ---00000 00000000 000060 h ssr0 [r/w, r] b, h, w 00001000 sidr0 [r]/sodr0[w] b, h, w xxxxxxxx scr0 [r/w] b, h, w 00000100 smr0 [r/w, w] b, h, w 00--0-0- uart0 000064 h utim0 [r] h / utimr0 [w] h 00000000 00000000 drcl0 [w] b -------- utimc0 [r/w] b 0--00001 u-timer 0 000068 h ssr1 [r/w, r] b, h, w 00001000 sidr1, sodr1 [r/w] b, h, w xxxxxxxx scr1 [r/w] b, h, w 00000100 smr1 [r/w] b, h, w 00--0-0- uart1 00006c h utim1 [r] h / utimr1 [w] h 00000000 00000000 drcl1 [w] b -------- utimc1 [r/w] b 0--00001 u-timer 1 000070 h ssr2 [r/w, r] b, h, w 00001000 sidr2, sodr2 [r/w] b, h, w xxxxxxxx scr2 [r/w] b, h, w 00000100 smr2 [r/w] b, h, w 00--0-0- uart2 000074 h utim2 [r] h / utimr2 [w] h 00000000 00000000 drcl2 [w] b -------- utimc2 [r/w] b 0--00001 u-timer 2
mb91260b series 27 (continued) address register block + 0 + 1 + 2 + 3 000078 h adch0 [r/w] b, h, w xx000000 admd0 [r/w] b, h, w 00001111 adcd01 [r] b, h, w xxxxxxxx adcd00 [r] b, h, w xxxxxxxx a/d converter 0/ aicr0 00007c h adcs0 [r/w, w] b, h, w 00000x00 ? aicr0 [r/w] b, h, w 00000000 ? 000080 h adch1 [r/w] b, h, w xxxx0xx0 admd1 [r/w] b, h, w 00001111 adcd11 [r] b, h, w xxxxxxxx adcd10 [r] b, h, w xxxxxxxx a/d converter 1/ aicr1 000084 h adcs1 [r/w, w] b, h, w 00000x00 ? aicr1 [r/w] b, h, w ------00 ? 000088 h adch2 [r/w] b, h, w xxxx0xx0 admd2 [r/w] b, h, w 00001111 adcd21 [r] b, h, w xxxxxxxx adcd20 [r] b, h, w xxxxxxxx a/d converter 2/ aicr2 00008c h adcs2 [r/w, w] b, h, w 00000x00 ? aicr2 [r/w] b, h, w ------00 ? 000090 h occpbh0, occpbl0[w]/ occph0, occpl0[r] h, w 00000000 00000000 occpbh1, occpbl1[w]/ occph1, occpl1 [r] h, w 00000000 00000000 16-bit output compare 000094 h occpbh2, occpbl2[w]/ occph2, occpl2 [r] h, w 00000000 00000000 occpbh3, occpbl3[w]/ occph3, occpl3 [r] h, w 00000000 00000000 000098 h occpbh4, occpbl4[w]/ occph4, occpl4 [r] h, w 00000000 00000000 occpbh5, occpbl5[w]/ occph5, occpl5 [r] h, w 00000000 00000000 00009c h ocsh1 [r/w] b, h, w x1100000 ocsl0 [r/w] b, h, w 00001100 ocsh3 [r/w] b, h, w x1100000 ocsl2 [r/w] b, h, w 00001100 0000a0 h ocsh5 [r/w] b, h, w x1100000 ocsl4 [r/w] b, h, w 00001100 ocmod [r/w] b, h, w xx000000 ? 0000a4 h cpclrbh, cpclrbl[w]/ cpclrh, cpclrl[r] h, w 11111111 11111111 tcdth, tcdtl [r/w] h, w 00000000 00000000 16-bit free-run timer 0000a8 h tccsh [r/w] b, h, w 00000000 tccsl [r/w] b, h, w 01000000 ? adtrgc [r/w] b, h, w xxxx0000 0000ac h ipcph0, ipcpl0 [r] h, w xxxxxxxx xxxxxxxx ipcph1, ipcpl1 [r] h, w xxxxxxxx xxxxxxxx 16-bit input capture 0000b0 h ipcph2, ipcpl2 [r] h, w xxxxxxxx xxxxxxxx ipcph3, ipcpl3 [r] h, w xxxxxxxx xxxxxxxx 0000b4 h picsh01 [w] b, h, w 000000-- picsl01 [r/w] b, h, w 00000000 icsh23 [r] b, h, w xxxxxx00 icsl23 [r/w] b, h, w 00000000 0000b8 h eirr1 [r/w] b, h, w ------00 enir1 [r/w] b, h, w ------00 elvr1 [r/w] b, h, w -------- ----0000 external interrupt (int8, int9)
mb91260b series 28 (continued) address register block + 0 + 1 + 2 + 3 0000bc h tmrrh0, tmrrl0 [r/w] h, w xxxxxxxx xxxxxxxx tmrrh1, tmrrl1 [r/w] h, w xxxxxxxx xxxxxxxx waveform generator 0000c0 h tmrrh2, tmrrl2 [r/w] h, w xxxxxxxx xxxxxxxx ?? 0000c4 h dtcr0 [r/w] b, h, w 00000000 dtcr1 [r/w] b, h, w 00000000 dtcr2 [r/w] b, h, w 00000000 ? 0000c8 h ? sigcr1 [r/w] b, h, w 10000000 ? sigcr2 [r/w] b, h, w xxxxxxx1 0000cc h adcomp0 [r/w] h, w 00000000 00000000 adcomp1 [r/w] h, w 00000000 00000000 a/d comp 0000d0 h adcomp2 [r/w] h, w 00000000 00000000 ? adcompc [r/w] b, h, w xxxxx000 0000d4 h to 0000dc h ? reserved 0000e0 h pwcsr0 [r/w, r] b, h, w 00000000 00000000 pwcr0 [r] h, w 00000000 00000000 pwc timer 0000e4 h pwcsr1 [r/w, r] b, h, w 00000000 00000000 pwcr1 [r] h, w 00000000 00000000 0000e8 h ? pdivr0 [r/w] b, h, w xxxxx000 ? pdivr1 [r/w] b, h, w xxxxx000 0000ec h to 000fc h ? reserved 000100 h prlh0 [r/w] b, h, w xxxxxxxx prll0 [r/w] b, h, w xxxxxxxx prlh1 [r/w] b, h, w xxxxxxxx prll1 [r/w] b, h, w xxxxxxxx ppg0 to ppg15 000104 h prlh2 [r/w] b, h, w xxxxxxxx prll2 [r/w] b, h, w xxxxxxxx prlh3 [r/w] b, h, w xxxxxxxx prll3 [r/w] b, h, w xxxxxxxx 000108 h ppgc0 [r/w] b, h, w 0000000x ppgc1 [r/w] b, h, w 0000000x ppgc2 [r/w] b, h, w 0000000x ppgc3 [r/w] b, h, w 0000000x 00010c h prlh4 [r/w] b, h, w xxxxxxxx prll4 [r/w] b, h, w xxxxxxxx prlh5 [r/w] b, h, w xxxxxxxx prll5 [r/w] b, h, w xxxxxxxx 000110 h prlh6 [r/w] b, h, w xxxxxxxx prll6 [r/w] b, h, w xxxxxxxx prlh7 [r/w] b, h, w xxxxxxxx prll7 [r/w] b, h, w xxxxxxxx 000114 h ppgc4 [r/w] b, h, w 0000000x ppgc5 [r/w] b, h, w 0000000x ppgc6 [r/w] b, h, w0000000x ppgc7 [r/w] b, h, w 0000000x 000118 h prlh8 [r/w] b, h, w xxxxxxxx prll8 [r/w] b, h, w xxxxxxxx prlh9 [r/w] b, h, w xxxxxxxx prll9 [r/w] b, h, w xxxxxxxx 00011c h prlh10 [r/w] b, h, w xxxxxxxx prll10 [r/w] b, h, w xxxxxxxx prlh11 [r/w] b, h, w xxxxxxxx prll11 [r/w] b, h, w xxxxxxxx 000120 h ppgc8 [r/w] b, h, w 0000000x ppgc9 [r/w] b, h, w 0000000x ppgc10 [r/w] b, h, w 0000000x ppgc11 [r/w] b, h, w 0000000x
mb91260b series 29 (continued) address register block + 0 + 1 + 2 + 3 000124 h prlh12 [r/w] b, h, w xxxxxxxx prll12 [r/w] b, h, w xxxxxxxx prlh13 [r/w] b, h, w xxxxxxxx prll13 [r/w] b, h, w xxxxxxxx ppg0 to ppg15 000128 h prlh14 [r/w] b, h, w xxxxxxxx prll14 [r/w] b, h, w xxxxxxxx prlh15 [r/w] b, h, w xxxxxxxx prll15 [r/w] b, h, w xxxxxxxx 00012c h ppgc12 [r/w] b, h, w 0000000x ppgc13 [r/w] b, h, w 0000000x ppgc14 [r/w] b, h, w 0000000x ppgc15 [r/w] b, h, w 0000000x 000130 h trg [r/w] b, h, w 00000000 00000000 ? gatec [r/w] b, h, w xxxxxx00 000134 h revc [r/w] b, h, w 00000000 00000000 ?? 000138 h to 0001fc h ? reserved 000200 h dmaca0 [r/w] b, h, w * 1 00000000 00000000 00000000 00000000 dmac 000204 h dmacb0 [r/w] b, h, w 00000000 00000000 00000000 00000000 000208 h dmaca1 [r/w] b, h, w* 1 00000000 00000000 00000000 00000000 00020c h dmacb1 [r/w] b, h, w 00000000 00000000 00000000 00000000 000210 h dmaca2 [r/w] b, h, w * 1 00000000 00000000 00000000 00000000 000214 h dmacb2 [r/w] b, h, w 00000000 00000000 00000000 00000000 000218 h dmaca3 [r/w] b, h, w * 1 00000000 00000000 00000000 00000000 00021c h dmacb3 [r/w] b, h, w 00000000 00000000 00000000 00000000 000220 h dmaca4 [r/w] b, h, w * 1 00000000 00000000 00000000 00000000 000224 h dmacb4 [r/w] b, h, w 00000000 00000000 00000000 00000000 000228 h to 00023c h ? reserved 000240 h dmacr [r/w] b 0xx00000 xxxxxxxx xxxxxxxx xxxxxxxx dmac 000244 h to 000398 h ? reserved
mb91260b series 30 (continued) address register block + 0 + 1 + 2 + 3 00039c h ?? ?? mac 0003a0 h dsp-pc [r/w] xxxxxxxx dsp-csr [r/w, r, w] 00000000 dsp-ly [r/w] xxxxxxxx xxxxxxxx 0003a4 h dsp-ot0 [r] xxxxxxxx xxxxxxxx dsp-ot1 [r] xxxxxxxx xxxxxxxx 0003a8 h dsp-ot2 [r] xxxxxxxx xxxxxxxx dsp-ot3 [r] xxxxxxxx xxxxxxxx 0003ac h ?? ?? 0003b0 h dsp-ot4 [r] xxxxxxxx xxxxxxxx dsp-ot5 [r] xxxxxxxx xxxxxxxx 0003b4 h dsp-ot6 [r] xxxxxxxx xxxxxxxx dsp-ot7 [r] xxxxxxxx xxxxxxxx 0003b8 h to 0003ec h ? reserved 0003f0 h bsd0 [w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx bit search 0003f4 h bsd1 [r/w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003f8 h bsdc [w] w xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003fc h bsrr [r] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000400 h ddr0 [r/w] b 00000000 ddr1 [r/w] b 00000000 ddr2 [r/w] b 00000000 ddr3 [r/w] b 00000000 data direction register 000404 h ddr4 [r/w] b 00000000 ddr5 [r/w] b 00000000 ddr6 [r/w] b ----0000 ddr7 [r/w] b 00000000 000408 h ?? ?? 00040c h ddrc [r/w] b 00000000 ddrd [r/w] b ------00 ddre [r/w] b ------00 ? 000410 h ddrg [r/w] b --000000 ??? 000414 h to 00041c h ? reserved 000420 h pfr0 [r/w] b 00000000 pfr1 [r/w] b -0000000 pfr2 [r/w] b --00-00- ? port function register 000424 h ?? ? pfr7 [r/w] b ------00 000428 h ?? ?? 00042c h ?? ?? 000430 h pfrg [r/w] b --00--0- ???
mb91260b series 31 (continued) address register block + 0 + 1 + 2 + 3 000434 h to 00043c h ? reserved 000440 h icr00 [r/w, r] b, h, w ----1111 icr01 [r/w, r] b, h, w ----1111 icr02 [r/w, r] b, h, w ----1111 icr03 [r/w, r] b, h, w ----1111 interrupt controller 000444 h icr04 [r/w, r] b, h, w ----1111 icr05 [r/w, r] b, h, w ----1111 icr06 [r/w, r] b, h, w ----1111 icr07 [r/w, r] b, h, w ----1111 000448 h icr08 [r/w, r] b, h, w ----1111 icr09 [r/w, r] b, h, w ----1111 icr10 [r/w, r] b, h, w ----1111 icr11 [r/w, r] b, h, w ----1111 00044c h icr12 [r/w, r] b, h, w ----1111 icr13 [r/w, r] b, h, w ----1111 icr14 [r/w, r] b, h, w ----1111 icr15 [r/w, r] b, h, w ----1111 000450 h icr16 [r/w, r] b, h, w ----1111 icr17 [r/w, r] b, h, w ----1111 icr18 [r/w, r] b, h, w ----1111 icr19 [r/w, r] b, h, w ----1111 000454 h icr20 [r/w, r] b, h, w ----1111 icr21 [r/w, r] b, h, w ----1111 icr22 [r/w, r] b, h, w ----1111 icr23 [r/w, r] b, h, w ----1111 000458 h icr24 [r/w, r] b, h, w ----1111 icr25 [r/w, r] b, h, w ----1111 icr26 [r/w, r] b, h, w ----1111 icr27 [r/w, r] b, h, w ----1111 00045c h icr28 [r/w, r] b, h, w ----1111 icr29 [r/w, r] b, h, w ----1111 icr30 [r/w, r] b, h, w ----1111 icr31 [r/w, r] b, h, w ----1111 000460 h icr32 [r/w, r] b, h, w ----1111 icr33 [r/w, r] b, h, w ----1111 icr34 [r/w, r] b, h, w ----1111 icr35 [r/w, r] b, h, w ----1111 000464 h icr36 [r/w, r] b, h, w ----1111 icr37 [r/w, r] b, h, w ----1111 icr38 [r/w, r] b, h, w ----1111 icr39 [r/w, r] b, h, w ----1111 000468 h icr40 [r/w, r] b, h, w ----1111 icr41 [r/w, r] b, h, w ----1111 icr42 [r/w, r] b, h, w ----1111 icr43 [r/w, r] b, h, w ----1111 00046c h icr44 [r/w, r] b, h, w ----1111 icr45 [r/w, r] b, h, w ----1111 icr46 [r/w, r] b, h, w ----1111 icr47 [r/w, r] b, h, w ----1111 000470 h to 00047c h ? reserved 000480 h rsrr [r/w] b, h, w 10000000 stcr [r/w] b, h, w 00110011 tbcr [r/w] b, h, w 00xxxx00 ctbr [w] b, h, w xxxxxxxx clock control 000484 h clkr [r/w] b, h, w 00000000 wpr [w] b, h, w xxxxxxxx divr0 [r/w] b, h, w 00000011 divr1 [r/w] b, h, w 00000000 000488 h to 0005fc h ? reserved 000600 h pcr0 [r/w] b 00000000 pcr1 [r/w] b 00000000 pcr2 [r/w] b 00000000 pcr3 [r/w] b 00------ pull-up controller 000604 h pcr4 [r/w] b 00000000 pcr5 [r/w] b 00000000 pcr6 [r/w] b ----0000 pcr7 [r/w] b 00000000 000608 h ???? 00060c h ????
mb91260b series 32 (continued) address register block + 0 + 1 + 2 + 3 000610 h pcrg [r/w] b --000000 ?? ? pull-up controller 000614 h to 000ffc h ? reserved 001000 h dmasa0 [r/w] w 00000000 00000000 00000000 00000000 dmac 001004 h dmada0 [r/w] w 00000000 00000000 00000000 00000000 001008 h dmasa1 [r/w] w 00000000 00000000 00000000 00000000 00100c h dmada1 [r/w] w 00000000 00000000 00000000 00000000 001010 h dmasa2 [r/w] w 00000000 00000000 00000000 00000000 001014 h dmada2 [r/w] w 00000000 00000000 00000000 00000000 001018 h dmasa3 [r/w] w 00000000 00000000 00000000 00000000 00101c h dmada3 [r/w] w 00000000 00000000 00000000 00000000 001020 h dmasa4 [r/w] w 00000000 00000000 00000000 00000000 001024 h dmada4 [r/w] w 00000000 00000000 00000000 00000000 001028 h to 006ffc h ? reserved 007000 h flcr [r/w] 0110x000 ?? ? flash 007004 h flwc [r/w] 00000011* 2 ?? ? 007008 h ?? ? ? 00700c h ?? ? ? 007010 h ?? ? ? 007014 h to 00bffc h ? reserved
mb91260b series 33 (continued) *1 : the lower 16 bits (dtc15 to dct0) of dmaca0 to dmaca4 cannot be accessed in bytes. *2 : the initial value of 1flwc (7004 h ) is ?00010011 b ? on eva tool. writing ?00000011 b ? on the evaluation model has no effect on its operation. notes : ? do not execute read modify write instructions on registers having a write-only bit. ? data is undefined in reserved or (-) area. address register block + 0 + 1 + 2 + 3 00c000 h to 00c07c h x-ram (coefficient ram) [r/w] 64 16 bits mac 00c080 h to 00c0fc h y-ram (variable ram) [r/w] 64 16 bits 00c100 h to 00c2fc h i-ram (instruction ram) [r/w] 256 16 bits 00c300 h to 00fffc h ? reserved
mb91260b series 34 interrupt vector (continued) interrupt source interrupt number interrupt level offset tbr default address rn 10 16 reset 0 00 ? 3fc h 000ffffc h ? mode vector 1 01 ? 3f8 h 000ffff8 h ? system reserved 2 02 ? 3f4 h 000ffff4 h ? system reserved 3 03 ? 3f0 h 000ffff0 h ? system reserved 4 04 ? 3ec h 000fffec h ? system reserved 5 05 ? 3e8 h 000fffe8 h ? system reserved 6 06 ? 3e4 h 000fffe4 h ? coprocessor absent trap 7 07 ? 3e0 h 000fffe0 h ? coprocessor error trap 8 08 ? 3dc h 000fffdc h ? inte instruction 9 09 ? 3d8 h 000fffd8 h ? instruction break exception 10 0a ? 3d4 h 000fffd4 h ? operand break trap 11 0b ? 3d0 h 000fffd0 h ? step trace trap 12 0c ? 3cc h 000fffcc h ? nmi request (tool) 13 0d ? 3c8 h 000fffc8 h ? undefined instruction exception 14 0e ? 3c4 h 000fffc4 h ? nmi request 15 0f 15 (f h ) fixed 3c0 h 000fffc0 h ? external interrupt 0 16 10 icr00 3bc h 000fffbc h 6 external interrupt 1 17 11 icr01 3b8 h 000fffb8 h 7 external interrupt 2 18 12 icr02 3b4 h 000fffb4 h ? external interrupt 3 19 13 icr03 3b0 h 000fffb0 h ? external interrupt 4 20 14 icr04 3ac h 000fffac h ? external interrupt 5 21 15 icr05 3a8 h 000fffa8 h ? external interrupt 6 22 16 icr06 3a4 h 000fffa4 h ? external interrupt 7 23 17 icr07 3a0 h 000fffa0 h ? reload timer 0 24 18 icr08 39c h 000fff9c h 8 reload timer 1 25 19 icr09 398 h 000fff98 h 9 reload timer 2 26 1a icr10 394 h 000fff94 h 10 uart0(reception completed) 27 1b icr11 390 h 000fff90 h 0 uart0 (rx completed) 28 1c icr12 38c h 000fff8c h 3 dtti 29 1d icr13 388 h 000fff88 h ? dmac0 (end, error) 30 1e icr14 384 h 000fff84 h ? dmac1 (end, error) 31 1f icr15 380 h 000fff80 h ? dmac2/3/4 (end, error) 32 20 icr16 37c h 000fff7c h ?
mb91260b series 35 (continued) interrupt source interrupt number interrupt level offset tbr default address rn 10 16 uart1(reception completed) 33 21 icr17 378 h 000fff78 h 1 uart1 (rx completed) 34 22 icr18 374 h 000fff74 h 4 uart2 (reception completed) 35 23 icr19 370 h 000fff70 h 2 uart2 (rx completed) 36 24 icr20 36c h 000fff6c h 5 mac 37 25 icr21 368 h 000fff68 h ? ppg0 38 26 icr22 364 h 000fff64 h ? ppg1 39 27 icr23 360 h 000fff60 h ? ppg2/3 40 28 icr24 35c h 000fff5c h ? ppg4/5/6/7 41 29 icr25 358 h 000fff58 h ? ppg8/9/10/11/12/13/14/15 42 2a icr26 354 h 000fff54 h ? external interrupt 8/9 43 2b icr27 350 h 000fff50 h ? waveform0 (under flow) 44 2c icr28 34c h 000fff4c h ? waveform1 (under flow) 45 2d icr29 348 h 000fff48 h ? waveform2 (under flow) 46 2e icr30 344 h 000fff44 h ? timebase timer overflow 47 2f icr31 340 h 000fff40 h ? free-run timer (compare clear) 48 30 icr32 33c h 000fff3c h ? free-run timer (zero detection) 49 31 icr33 338 h 000fff38 h ? a/d0 50 32 icr34 334 h 000fff34 h ? a/d1 51 33 icr35 330 h 000fff30 h ? a/d2 52 34 icr36 32c h 000fff2c h ? pwc0 (measurement completed) 53 35 icr37 328 h 000fff28 h ? pwc1 (measurement completed) 54 36 icr38 324 h 000fff24 h ? pwc0 (overflow) 55 37 icr39 320 h 000fff20 h ? pwc1 (overflow) 56 38 icr40 31c h 000fff1c h ? icu0 (capture) 57 39 icr41 318 h 000fff18 h ? icu1 (capture) 58 3a icr42 314 h 000fff14 h ? icu2/3 (capture) 59 3b icr43 310 h 000fff10 h ? ocu0/1 (match) 60 3c icr44 30c h 000fff0c h ? ocu2/3 (match) 61 3d icr45 308 h 000fff08 h ? ocu4/5 (match) 62 3e icr46 304 h 000fff04 h ? delay interrupt sour ce bit 63 3f icr47 300 h 000fff00 h ? system reserved (used by realos) 64 40 ? 2fc h 000ffefc h ? system reserved (used by realos) 65 41 ? 2f8 h 000ffef8 h ?
mb91260b series 36 (continued) interrupt source interrupt number interrupt level offset tbr default address rn 10 16 system reserved 66 42 ? 2f4 h 000ffef4 h ? system reserved 67 43 ? 2f0 h 000ffef0 h ? system reserved 68 44 ? 2ec h 000ffeec h ? system reserved 69 45 ? 2e8 h 000ffee8 h ? system reserved 70 46 ? 2e4 h 000ffee4 h ? system reserved 71 47 ? 2e0 h 000ffee0 h ? system reserved 72 48 ? 2dc h 000ffedc h ? system reserved 73 49 ? 2d8 h 000ffed8 h ? system reserved 74 4a ? 2d4 h 000ffed4 h ? system reserved 75 4b ? 2d0 h 000ffed0 h ? system reserved 76 4c ? 2cc h 000ffecc h ? system reserved 77 4d ? 2c8 h 000ffec8 h ? system reserved 78 4e ? 2c4 h 000ffec4 h ? system reserved 79 4f ? 2c0 h 000ffec0 h ? used by int instruction 80 to 255 50 to ff ? 2bc h to 000 h 000ffebc h to 000ffc00 h ?
mb91260b series 37 pin status in ea ch cpu state terms used as the status of pins mean as follows. ? input enabled ? indicates that the input function can be used. ? input 0 fixed ? indicates that the input level has been internally fixed to be 0 to prevent leakage when the input is released. ? output hi-z ? means the placing of a pin in a high impedance state by preventing the transistor for driving the pin from driving. ? output is maintained. ? indicates the output in the output state existing immediately before this mode is established. ? if the device enters this mode with an internal output peripheral operating or while serving as an output port, the output is performed by the internal peripheral or the port output is maintained, respectively. ? state existing immediately before is maintained. ? when the device serves for output or input immediately before entering this mode, the device maintains the output or is ready for the input, respectively.
mb91260b series 38 ? list of pin status (single chip mode) (continued) pin no. pin name function at initializing at sleep mode at stop mode qfp lqfp init = l* 1 init = h* 2 hiz = 0 hiz = 1 199p23 sin1 output hi-z/ input disabled output hi-z/ input enabled retention of the immediately prior state retention of the immediately prior state output hi-z/ input 0 fixed 2100p24 sot1 31p25sck1 4, 5 2, 3 p26, p27 int6, int7 input enabled input enabled input enabled 64p51 port retention of the immediately prior state retention of the immediately prior state output hi-z/ input 0 fixed 7 to 9 5 to 7 p50, p52, p53 ports/ tin0 to tin2 10 8 p54 int0 input enabled input enabled input enabled 11 9 p55 int1 12 10 p56 int2 13 11 p57 int3 14 12 pg0 cki/int4 15 13 pg1 ppg0/int5 16 14 pg2 ports retention of the immediately prior state retention of the immediately prior state output hi-z/ input 0 fixed 20 18 pg3 sin2 21 19 pg4 sot2 22 20 pg5 sck2 23 to 30 21 to 28 p40 to p47 ports 31, 32 29, 30 pe1, pe0 an11, an10 38, 39 36, 37 pd1, pd0 an9, an8 41 to 48 39 to 46 pc7 to pc0 an7 to an0 51 to 56 49 to 54 p30 to p35 rto0 to rto5 57, 58 55, 56 p36, p37 ic0, ic1 59, 60 57, 58 p60, p61 ic2, ic3 61, 62 59, 60 p62, p63 int8, int9 input enabled input enabled input enabled
mb91260b series 39 (continued) p : selection of general purpose port, f : selection of specified function *1 : init = l : indicates the pin status with init remaining at the ?l? level. *2 : init = h : indicates the pin status existing immediately after init transition from ?l? to ?h? level. pin no. pin name function at initializing at sleep mode at stop mode qfp lqfp init = l* 1 init = h* 2 hiz = 0 hiz = 1 63, 64 61, 62 p70, p71 tot1, tot2 output hi-z/ input disabled output hi-z/ input enabled retention of the immediately prior state retention of the immediately prior state output hi-z/ input 0 fixed 65 63 p72 dtti 66 64 p73 pwi0 69 67 p74 pwi1 70 68 p75 adtg0 71 69 p76 adtg1 72 70 p77 adtg2 73 71 nmi nmi input enabled input enabled input enabled input enabled input enabled 78 76 p00 ppg1 output hi-z/ input disabled output hi-z/ input enabled retention of the immediately prior state retention of the immediately prior state output hi-z/ input 0 fixed 79 77 p01 ppg2 80 78 p02 ppg3 81 79 p03 ppg4 82 80 p04 ppg5 83 81 p05 ppg6 84 82 p06 ppg7 85 83 p07 ppg8 86 84 p10 ppg9 87 85 p11 ppg10 88 86 p12 ppg11 89 87 p13 ppg12 90 88 p14 ppg13 91 89 p15 ppg14 96 94 p16 ppg15 97 95 p17 ports 98 96 p20 sin0 99 97 p21 sot0 100 98 p22 sck0
mb91260b series 40 electrical characteristics 1. absolute maximum ratings *1 : this parameter is based on v ss = av ss = 0.0 v. *2 : be careful not to exceed v cc + 0.3 v, for example, when the power is turned on. be careful not to let av cc exceed v cc , for example, when the power is turned on. *3 : the maximum output current is the peak value for a single pin. *4 : the average output current is the average current for a single pin over a period of 100 ms. *5 : the total average output current is the average current for all pins over a period of 100 ms. *6 : for use at ta = + 105 c, lower the operating frequency to reduce power consumption. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol rating unit remarks min max power supply voltage* 1 v cc v ss ? 0.5 v ss + 6.0 v analog power supply voltage* 1 av cc v ss ? 0.5 v ss + 6.0 v *2 analog reference voltage* 1 avrh v ss ? 0.5 v ss + 6.0 v *2 input voltage* 1 v i v ss ? 0.3 v cc + 0.3 v analog pin input voltage* 1 v ia v ss ? 0.3 avcc + 0.3 v output voltage* 1 v o v ss ? 0.3 v cc + 0.3 v "l" level maximum output current i ol ? 10 ma *3 "l" level average output current i olav ? 8ma*4 "l" level total maximum output current i ol ? 100 ma "l" level total average output current i olav ? 50 ma *5 "h" level maximum output current i oh ? ? 10 ma *3 "h" level average output current i ohav ? ? 4ma*4 "h" level total maximum output current i oh ? ? 50 ma "h" level total average output current i ohav ? ? 20 ma *5 power consumption p d ? 600 mw flash product 600 mask product ta + 85 c 360 mask product ta + 105 c * 6 operating temperature ta ? 40 + 105 c mask product (at single chip operating) ? 40 + 85 c flash product (at single chip operating) storage temperature tstg ? 55 125 c
mb91260b series 41 2. recommended operating conditions (vss = avss = 0 v) note : upon power up, it takes approx. 100 s for stabilization of internal power supply after the v cc power supply is stabilized. keep applying ?l? to init signal during that period. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device?s electric al characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may advers ely affect reliability and coul d result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their representatives beforehand. parameter symbol value unit remarks min max power supply voltage v cc 4.0 5.5 v at normal operating analog power supply voltage av cc v ss + 4.0 v ss + 5.5 v analog reference voltage avrh0 av ss av cc v for a/d converter 0 avrh1 av ss av cc v for a/d converter 1 avrh2 av ss av cc v for a/d converter 2 operating temperature ta ? 40 + 105 c mask product (at single chip operation) ? 40 + 85 c flash product (at single chip operation)
mb91260b series 42 3. dc characteristics (v cc = 4.0 to 5.5 v, v ss = av ss = 0 v) parameter sym bol pin conditions value unit remarks min typ max "h" level input voltage v ih other than hyster- esis input pin ? 0.8 vcc ? vcc v v ihs hysteresis input pin ? vcc ? 0.4 ? vcc v input low voltage v il other than hyster- esis input pin ? vss ? 0.2 vcc v v ils hysteresis input pin ? vss ? vss + 0.4 v "h" level output voltage v oh other than p30 to p35 v cc = 5.0 v, i oh = 4.0 ma vcc ? 0.5 ?? v v oh2 p30 to p35 v cc = 5.0 v, i oh = 8.0 ma vcc ? 0.7 ?? v output low voltage v ol other than p30 to p35 v cc = 5.0 v, i ol = 4.0 ma ?? 0.4 v v ol2 p30 to p35 v cc = 5.0 v, i ol = 12 ma ?? 0.6 v input leak current i li ? v cc = 5.0 v, v ss v i v cc ? 5 ? 5 a pull-up resistance r pull init , pull-up pin ?? 50 ? k power supply current i cc v cc v cc = 5.0 v, 33 mhz ? 90 100 ma i ccs v cc v cc = 5.0 v, 33 mhz ? 60 80 ma at sleep i cch v cc v cc = 5.0 v, ta = + 25 c ? 300 ? a at stop input capacitance c in other than v cc , v ss , av cc , av ss , avrh0, 1, 2 ?? 10 ? pf
mb91260b series 43 4. flash memory write/erase characteristics * : this value comes from the technology qualification. (using arrhenius equation to translate high temperature measurements into normalized value at + 85 c) parameter conditions value unit remarks min typ max sector erase time ta = + 25 c, vcc = 5.0 v ? 115s not including time for internal writing before deletion. chip erase time ta = + 25 c, vcc = 5.0 v ? 10 ? s not including time for internal writing before deletion. byte write time ta = + 25 c, vcc = 5.0 v ? 83,600 s not including system-level overhead time. chip write time ta = + 25 c, vcc = 5.0 v ? 2.1 ? s not including system-level overhead time. erase/write cycle ? 10,000 ?? cycle flash memory data retention time average ta = + 85 c 20 ?? year *
mb91260b series 44 5. ac characteristics (1) clock timing ratings (v cc = 4.0 to 5.5 v, v ss = av ss = 0 v) *1 : the values assume a gear cycle of 1/16. *2 : when the pll is used, the lower-limit frequency of the input clock to the x0 and x1 pins determines depending on the pll multiplication. at 1 multiplication : more than 8 mhz at 2 to 8 multiplication : more than 4 mhz ? conditions for measuring the clock timing ratings parameter sym bol pin conditions value unit remarks min typ max clock frequency f c x0 x1 ? 3.6* 2 ? 12 mhz for using the pll within the self-oscillation enabled range, set the multiplier for the internal clock not to let the operating frequency exceed 33 mhz. clock cycle time t c x0 x1 83.3 ? 278* 2 ns internal operating clock frequency f cp ? when 4.125 mhz is input as the x0 clock frequency and 8 multiplication is set for the pll of the oscillator circuit. 2.06* 1 ? 33 mhz cpu f cpp 2.06* 1 ? 33 mhz peripheral internal operating clock cycle time t cp ? 30.3 ? 485* 1 ns cpu t cpp 30.3 ? 485* 1 ns peripheral 0.8 v cc 0.2 v cc t cf t cr t c p wh p wl c = 50 pf output pin
mb91260b series 45 ? operation assurance range ? internal clock setting range 0 (mhz) 5.5 4.0 f cp / f cpp 33 0.25 v cc (v) internal clock power supply 33 (mhz) 16.5 4.125 8 : 8 4 : 4 1 : 1 notes : ? oscillation stabilizat ion time of pll > 600 s ? the internal clock gear setting should be within the value shown in clock timing ratings table. oscillation input clock f c = 4 . 192 mhz cpu : divided ratio for peripherals. internal clock peripheral (clkp) : cpu (clkb) : (pll multiplied by 8)
mb91260b series 46 (2) reset input (v cc = 4.0 to 5.5 v, v ss = av ss = 0 v) * : after the power is stable, l level is kept inputting to init for the duration of approximately 100 s until the internal power is stabilized. parameter sym- bol pin condi- tions value unit remarks min max init input time (at power-on and stop mode) t intl init ? oscillation time of oscillator + t c 10 ? ns * init input time (other than the above) t c 10 ? ns init 0.2 v cc t intl
mb91260b series 47 (3) uart timing (v cc = 4.0 to 5.5 v, v ss = av ss = 0 v) notes : ? there are the ac ratings for clk synchronous mode. ? t cycp indicates the peripheral clock cycle time. parameter symbol pin conditions value unit remarks min max serial clock cycle time t scyc sck0 to sck2 internal shift clock mode 8 t cycp ? ns sck sot delay time t slov sck0 to sck2, sot0 to sot2 ? 80 80 ns valid sin sck t ivsh sck0 to sck2, sin0 to sin2 100 ? ns sck valid sin hold time t shix sck0 to sck2, sin0 to sin2 60 ? ns serial clock h pulse width t shsl sck0 to sck2 external shift clock mode 4 t cycp ? ns serial clock l pulse width t slsh sck0 to sck2 4 t cycp ? ns sck sot delay time t slov sck0 to sck2, sot0 to sot2 ? 150 ns valid sin sck t ivsh sck0 to sck2, sin0 to sin2 60 ? ns sck valid sin hold time t shix sck0 to sck2, sin0 to sin2 60 ? ns
mb91260b series 48 ? internal shift clock mode ? external shift clock mode sck0 to sck2 t scyc t slov t ivsh t shix v ol v ol v oh v oh v ol v oh v ol v oh v ol sot0 to sot2 sin0 to sin2 t slsh t slov t ivsh t shix t shsl v oh v ol v oh v ol v oh v ol v oh v ol v ol v ol sck0 to sck2 sot0 to sot2 sin0 to sin2
mb91260b series 49 (4) free-run timer clock, pwc inpu t and reload timer trigger timing (v cc = 4.0 to 5.5 v, v ss = av ss = 0 v) note : t cycp indicates the peripheral clock cycle time. parameter symbol pin conditions value unit remarks min max input pulse width t tiwh t tiwl cki pwi0, pwi1 tin0 to tin2 ? 4 t cycp ? ns t tiwh t tiwl
mb91260b series 50 (5) trigger input timing (v cc = 4.0 to 5.5 v, v ss = av ss = 0 v) note : t cycp indicates the peripheral clock cycle time. parameter symbol pin conditions value unit remarks min max input capture trigger input t inp ic0 to ic3 ? 5 t cycp ? ns a/d activation trigger input t atgx adtg0 to adtg2 ? 5 t cycp ? ns ic0 to ic3 adtg0 to adtg2 t atgx , t inp
mb91260b series 51 6. electrical characteristics for the a/d converter (v cc = avcc = 5.0 v, v ss = av ss = 0 v) *1 : measured in the cpu sleep state *2 : vcc = avcc = 5.0 v, machine clock at 33 mhz *3 : the current when the cpu is in stop mode and the a/d converter is not operating (at vcc = avcc = avrhn = 5.0 v) *4: avrhn = avrh0, avrh1, avrh2 notes : ? the above does not guarantee the inter-unit accuracy. ? set the output impedance of the external circuit 2 k . parameter sym- bol pin value unit remarks min typ max resolution ?? ? ? 10 bit total error* 1 ?? ? 4 ? 4lsb at avrhn* 4 = 5.0 v linearity error* ?? ? 3.5 ? 3.5 lsb differential linearity error* 1 ?? ? 3 ? 3lsb zero transition voltage* 1 v ot an0 to an11 avss ? 3.5 avss + 0.5 avss + 4.5 lsb full transition voltage* 1 v fst an0 to an11 avrh ? 5.5 avrh ? 1.5 avrh + 2.5 lsb conversion time ?? 1.2* 2 ?? s analog port input current i ain an0 to an11 ?? 10 a analog input voltage v ain an0 to an11 avss ? avrh v reference voltage ? avrhn avss ? avcc v analog power supply current (analog + digital) i a avcc ? 2 ? ma per 1 unit i ah * 3 ?? 100 a per 1 unit reference power supply current (between avrh and avss) i r avrhn ? 1 ? ma per 1 unit avrhn* 4 = 5.0 v, at avss = 0 v i rh * 3 ?? 100 a per 1 unit at stop analog input capacitance ?? ? 10 ? pf inter-channel disparity ? an0 to an11 ?? 4lsb
mb91260b series 52 ? about the external impedance of the analog input and its sampling time a/d converter with sample and hold circuit. if the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sampling and hold capacitor is insufficient, adversely affecting a/d conversion precision. so, to satisfy the a/d conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the resistor value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. also, if the sampling time cannot be sufficient, connect a capacitor of about 0.1 f to the analog input pin. ? about errors as |avrh ? av ss | becomes smaller, values of relative errors grow larger. c r ? analog input circuit model comparator during sampling : on analog input note : the values are reference values. rc mb91263b 2.0 k (max) 14.4 pf (max) mb91264b 2.0 k (max) 14.4 pf (max) mb91f264b 2.0 k (max) 16.0 pf (max) 0 0 246810 10 20 30 40 50 60 70 80 90 100 mb91f264b mb91263b mb91264b 0 0 123 2 4 6 8 10 12 14 16 18 20 mb91f264b mb91263b mb91264b (external impedance = 0 k to 100 k ) minimum sampling time ( s) external impedance (k ) (external impedance = 0 k to 20 k ) minimum sampling time ( s) external impedance (k ) ? the relationship between the external impedance and minimum sampling time
mb91260b series 53 definition of a/d converter terms ? resolution : analog variation that is recognized by an a/d converter. ? linearity error : zero transition point (00 0000 0000 00 0000 0001) and full-scale transition point. difference between the line connected (11 1111 1110 11 1111 1111) and actual conversion characteristics. ? differential linearity error : deviation of input voltage, that is required for changing output code by 1 lsb, from an ideal value. ? total error : this error indicates the difference between actual and ideal values, including the zero transition error/full-scale transition error/linearity error. (continued) 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h av ss avrh 0.5 lsb' {1 lsb' (n ? 1) + 0.5 lsb'} 1.5 lsb' digital output analog input total error ideal characteristics actual conversion characteristics v nt (measurement value) actual conversion characteristics 1lsb? (ideal value) = avrh ? av ss [v] total error of digital output n = v nt ? {1 lsb? (n ? 1) + 0.5 lsb?} 1024 1 lsb? v ot ? (ideal value) = av ss + 0.5 lsb? [v] v fst ? (ideal value) = avrh ? 1.5 lsb? [v] v nt : a voltage at which digital output transitions from (n + 1) to n.
mb91260b series 54 (continued) 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h av ss avrh {1 lsb (n ? 1) + v ot } n ? 1 av ss avrh n ? 2 n n + 1 digital output analog input linearity error ideal characteristics actual conversion characteristics v fst (measurement value) actual conversion characteris tics v 0t ( measurement value) digital output analog input differential linear error actual conversion characteristics ideal characteristics v fst (measurement value) v nt (measurement value) v nt (measurement value) actual conversion characteristics v ot : a voltage at which digital output transitions from 000 h to 001 h . v fst : a voltage at which digital output transitions from 3fe h to 3ff h . linearity error in digital output n = vnt ? { 1 lsb (n ? 1) + vot } [lsb] 1 lsb differential linearity erro r in digital output n = v ( n + 1 ) t ? v nt ? 1[lsb] 1 lsb 1 lsb = v fst ? v ot [v] 1022
mb91260b series 55 example characteristics (continued) 6 5 4 3 2 1 0 4.0 4.5 5.0 5.5 v cc (v) v oh (v) 400 350 300 250 200 150 100 50 0 4.0 4.5 5.0 5.5 v cc (v) v ol (mv) 80 70 60 50 40 30 20 10 0 4.0 4.5 5.0 5.5 v cc (v) r (k ) 100 90 80 70 60 50 40 30 20 10 0 4.0 4.5 5.0 5.5 v cc (v) i cc (ma) 15 20 25 30 35 100 90 80 70 60 50 40 30 20 10 0 i cc (ma) 4.0 v 4.5 v 5.0 v 5.5 v power supply voltage ?h? level output voltage vs. power supply voltage ?l? level output voltage vs. power supply voltage pull-up resistor vs. power su pply voltage power supply current vs. power supply voltage power supply current vs. internal operation frequency (mb91263b) internal operation frequency [mhz]
mb91260b series 56 (continued) 80 70 60 50 40 30 20 10 0 4.0 4.5 5.0 5.5 v cc (v) i ccs (ma) 100 90 80 70 60 50 40 30 20 10 0 4.0 4.5 5.0 v cc (v) i cch ( a) 5.5 2 1.5 1 0.5 0 4.0 4.5 5.0 v cc (v) i a (ma) 5.5 1.0 0.8 0.6 0.4 0.2 0.0 4.0 4.5 5.0 v cc (v) i r (ma) 5.5 power supply current (at stop) vs. power supply voltage a/d conversion block per 1 unit (33 mhz) analog power supply current vs. power supply voltage a/d conversion block per 1 unit (33 mhz) reference power supply current vs. power supply voltage power supply current (at sleep) vs. power supply voltage 0 0 246810 10 20 30 40 50 60 70 80 90 100 mb91f264b mb91263b mb91264b 0 0 123 2 4 6 8 10 12 14 16 18 20 mb91f264b mb91263b mb91264b (external impedance = 0 k to 100 k ) minimum sampling time ( s) external impedance (k ) (external impedance = 0 k to 20 k ) minimum sampling time ( s) external impedance (k )
mb91260b series 57 ordering information part number package remarks mb91f264bpf-g 100-pin plastic qfp (fpt-100p-m06) mb91f264bpf-ge1 lead-free package mb91f264bpfv-g 100-pin plastic lqfp (fpt-100p-m05) mb91f264bpfv-ge1 lead-free package mb91264bpf-g-xxx 100-pin plastic qfp (fpt-100p-m06) mb91264bpf-g-xxxe1 lead-free package mb91264bpfv-g-xxx 100-pin plastic lqfp (fpt-100p-m05) MB91264BPFV-G-XXXE1 lead-free package mb91263bpf-g-xxx 100-pin plastic qfp (fpt-100p-m06) mb91263bpf-g-xxxe1 lead-free package mb91263bpfv-g-xxx 100-pin plastic lqfp (fpt-100p-m05) mb91263bpfv-g-xxxe1 lead-free package
mb91260b series 58 package dimension (continued) 100 - pin plastic qfp (fpt-100p-m06) note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. dimensions in mm (inches) note: the values in parentheses are reference values. c 2002 fujitsu limited f100008s-c-5-5 1 30 31 50 51 80 81 100 20.000.20(.787.008) 23.900.40(.941.016) 14.000.20 (.551.008) 17.900.40 (.705.016) index 0.65(.026) 0.320.05 (.013.002) m 0.13(.005) "a" 0.170.06 (.007.002) 0.10(.004) details of "a" part (.035.006) 0.880.15 (.031.008) 0.800.20 0.25(.010) 3.00 +0.35 ?0.20 +.014 ?.008 .118 (mounting height) 0.250.20 (.010.008) (stand off) 0~8 ? * *
mb91260b series 59 (continued) 100-pin plastic lqfp (fpt-100p-m05) note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. dimensions in mm (inches) note: the values in parentheses are reference values. c 2003 fujitsu limited f100007s-c-4-6 14.000.10(.551.004)sq 16.000.20(.630.008)sq 125 26 51 76 50 75 100 0.50(.020) 0.200.05 (.008.002) m 0.08(.003) 0.1450.055 (.0057.0022) 0.08(.003) "a" index .059 ?.004 +.008 ?0.10 +0.20 1.50 (mounting height) 0 ? ~8 ? 0.500.20 (.020.008) 0.600.15 (.024.006) 0.25(.010) 0.100.10 (.004.004) details of "a" part (stand off) *
fujitsu microelectronics limited shinjuku dai-ichi seimei bldg. 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0722, japan tel: +81-3-5322-3347 fax: +81-3-5322-3387 http://jp.fujitsu.com/fml/en/ for further information please contact: north and south america fujitsu microelectronics america, inc. 1250 e. arques avenue, m/s 333 sunnyvale, ca 94085-5401, u.s.a. tel: +1-408-737-5600 fax: +1-408-737-5999 http://www.fma.fujitsu.com/ europe fujitsu microelectronics europe gmbh pittlerstrasse 47, 63225 langen, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ korea fujitsu microelectronics korea ltd. 206 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 http://www.fmk.fujitsu.com/ asia pacific fujitsu microelectronics asia pte ltd. 151 lorong chuan, #05-08 new tech park, singapore 556741 tel: +65-6281-0770 fax: +65-6281-0220 http://www.fujitsu.com/sg/services/micro/semiconductor/ fujitsu microelectronics shanghai co., ltd. rm.3102, bund center, no.222 yan an road(e), shanghai 200002, china tel: +86-21-6335-1560 fax: +86-21-6335-1605 http://cn.fujitsu.com/fmc/ fujitsu microelectronics pacific asia ltd. 10/f., world commerce centre, 11 canton road tsimshatsui, kowloon hong kong tel: +852-2377-0226 fax: +852-2376-3269 http://cn.fujitsu.com/fmc/tw all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with sales representative s before ordering. the information, such as descri ptions of function and applicati on circuit examples, in this docum ent are presented solely for t he purpose of reference to show examples of ope rations and uses of fujits u microelectronics device; fujitsu microelectronics does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incor porat- ing the device based on such in formation, you must assume any responsibility arising out of such use of the information. fujitsu microelectronics assumes no liab ility for any damages whatsoever arisi ng out of the use of the information. any information in this document, including descriptions of function and schematic di agrams, shall not be construed as license of the use or exercise of any intellectual property ri ght, such as patent right or copyright, or any other right of fujitsu microelectroni cs or any third party or does fujitsu microel ectronics warrant non-infringeme nt of any third-party's intellectual property right o r other right by using such information. fu jitsu microelectronics assumes no liability for any infringement of the intellectual property rights or other rights of third parties which w ould result from the use of in formation cont ained herein. the products described in this document are designed, developed and manufa ctured as contemplated fo r general use, including wit hout limitation, ordinary indus trial use, general office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for use acco mpanying fatal risks or dangers th at, unless extremely high safety is secured, could have a ser ious effect to the public, and could lead directly to death, personal injury, severe physical damage or other lo ss (i.e., nuc lear reaction control in nuclear facility, airc raft flight control, air traffic c ontrol, mass transport control, me dical life support system, missile la unch control in weapon system), or (2) for use requiring extremely high re liability (i.e ., submersible repeater and artificial satellite). please note that fujitsu microelectronics will not be liable against you and/or any th ird party for any clai ms or damages arisi ng in connection with above-men tioned uses of the products. any semiconductor devices have an inherent ch ance of failure. you must protect against injury, damage or loss from such failure s by incorporating safety desi gn measures into your facility and equipment such as redundancy, fire protection, and prevention of ov er-current levels and other abnor mal operating conditions. exportation/release of any products described in this docum ent may require necessary procedures in accordance with the regulati ons of the foreign exchange and foreign trade control law of japan and/or us export control laws. the company names and brand na mes herein are the trademarks or registered trademarks of their respective owners. edited strategic business development dept.

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