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| - 1 - rev 0.0 may 2005 128m gddr sdram k4d263238i-vc target 128mbit gddr sdram revision 0.0 may 2005 information in this document is provided in relation to samsung products, and is subject to change without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or otherwise, to any intellectual property rights in samsung products or technology. all information in this document is provided on as "as is" basis without guara ntee or warranty of any kind. 1. for updates or additional inform ation about samsung products, contact your nearest samsung office. 2. samsung products are not intended for use in life suppor t, critical care, medical, safety equipment, or similar applications where product failure could re sult in loss of life or personal or physical harm, or any military or defense application, or any governmen tal procurement to which special terms or provisions may apply. * samsung electronics reserves the right to chan ge products or specification without notice.
- 2 - rev 0.0 may 2005 128m gddr sdram k4d263238i-vc target revision history revision month year history 0.0 may 2005 - target spec - defined target specification - 3 - rev 0.0 may 2005 128m gddr sdram k4d263238i-vc target the k4d263238i is 134,217,728 bits of hyper synchronous data rate dynamic ram organized as 4 x 1,048,576 words by 32 bits, fabr i- cated with samsung s high performance cmos technology. synchronous features with data strobe allow extremely high performance up to 2.0gb/s/chip. i/o transactions are possible on both edges of the clock cycle. range of operating frequencies, programmabl e burst length and programmable latencies allow the device to be useful for a variety of high performan ce memory system applications. ? 2.5v 5% power supply for device operation ? 2.5v 5% power supply for i/o interface ? sstl_2 compatible inputs/outputs ? 4 banks operation ? mrs cycle with address key programs -. read latency 3 (clock) -. burst length (2, 4, 8) -. burst type (sequential & interleave) ? all inputs except data & dm are sampled at the positive going edge of the system clock ? differential clock input ? write interrupted by read function ? data i/o transactions on both edges of data strobe ? dll aligns dq and dqs trans itions with clock transition ? edge aligned data & data strobe output ? center aligned data & data strobe input ? dm for write masking only ? auto & self refresh ? 32ms refresh period (4k cycle) ? lead free 144pin fbga package (rohs compliant) ? maximum clock frequency up to 250mhz ? maximum data rate up to 500mbps/pin for 1m x 32bit x 4 bank ddr sdram 1m x 32bit x 4 banks double data rate synchronous dram with bi-directional data strobe and dll *k4d263238i-gc is the leaded package part number. part no. max freq. max data rate interface package k4d263238i-vc40 250mhz 500mbps/pin sstl_2 144fbga k4d263238i-vc50 200mhz 400mbps/pin 1.0 features 2.0 ordering information 3.0 general description - 4 - rev 0.0 may 2005 128m gddr sdram k4d263238i-vc target 4.0 pin configuration (top view) pin description ck,ck differential clock input ba 0 , ba 1 bank select address cke clock enable a 0 ~a 11 address input cs chip select dq 0 ~ dq 31 data input/output ras row address strobe v dd power cas column address strobe v ss ground we write enable v ddq power for dq ? s dqs data strobe v ssq ground for dq ? s dm data mask nc no connection rfu reserved for future use mcl must connect low dqs0 vss rfu 1 thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vss thermal vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vss vss vss vss vss vss vss vss vss rfu 2 a5 a6 dq4 dq6 dq7 dq17 dq19 dqs2 dq21 dq22 cas ras cs dm0 vddq dq5 vddq dq16 dq18 dm2 dq20 dq23 we nc nc nc vdd vddq vddq nc vddq vddq vdd nc ba0 ba1 a0 dq3 vddq dq31 dq1 a10 a2 a1 vdd vdd vdd dq2 vddq vdd a11 a3 a9 a4 dq0 vddq vdd dq29 dq30 dq28 vddq nc vss a7 vddq vddq nc vddq vddq vdd ck a8/ap dm3 vddq dq26 vddq dq15 dq13 dm1 dq11 dq9 nc ck cke dqs3 dq27 dq25 dq24 dq14 dq12 dqs1 dq10 dq8 nc vref 2345678910111213 b c d e f g h j k l m n note: 1. rfu1 is reserved for a12. 2. rfu2 is reserved for ba2. 3. vss thermal balls are optional. mcl - 5 - rev 0.0 may 2005 128m gddr sdram k4d263238i-vc target *1 : the timing reference point for the differential clocking is the cross point of ck and ck. for any applications using the single ended clocking, apply v ref to ck pin. symbol type function ck, ck *1 input the differential system clock input. all of the inputs are sampled on t he rising edge of the clock except dq s and dm s that are sampled on both edges of the dqs. cke input activates the ck signal when high and deactivate s the ck signal when low. by deactivating the clock, cke low indicates the po wer down mode or self refresh mode. cs input cs enables the command decoder when low and disabled the command decoder when high. when the command decoder is disabled, new comm ands are ignored but previous operations continue. ras input latches row addresses on the positive going edge of the ck with ras low. enables row access & precharge. cas input latches column addresses on the pos itive going edge of the ck with cas low. enables col- umn access. we input enables write operation and row precharge. latches data in starting from cas , we active. dqs input/output data input and output ar e synchronized with both edge of dqs. dm 0 ~ dm 3 input data in mask. data in is masked by dm lat ency=0 when dm is high in burst write. dm 0 for dq 0 ~ dq 7, dm 1 for dq 8 ~ dq 15, dm 2 for dq 16 ~ dq 23, dm 3 for dq 24 ~ dq 31. dq 0 ~ dq 31 input/output data inputs/ outputs are multiplexed on the same pins. ba 0 , ba 1 input selects which bank is to be active. a 0 ~ a 11 input row/column addresses are multiplexed on the same pins. row addresses : ra 0 ~ ra 11 , column addresses : ca 0 ~ ca 7 . column address ca 8 is used for auto precharge. v dd /v ss power supply power and ground for the input buffers and core logic. v ddq /v ssq power supply isolated power supply and ground for the output buffers to provide improved noise immunity. v ref power supply reference voltage for inputs, used for sstl interface. mcl must connect low must connect low 5.0 input/output functional description - 6 - rev 0.0 may 2005 128m gddr sdram k4d263238i-vc target 6.0 block diagram (1mbit x 32i/o x 4 bank) bank select timing register address register refresh counter row buffer row decoder col. buffer data input register serial to parallel 1mx32 1mx32 1mx32 1mx32 sense amp 2-bit prefetch output buffer i/o control column decoder latency & burst length programming register strobe gen. ck,ck addr lcke ck,ck cke cs ras cas we dmi ldmi ck,ck lcas lras lcbr lwe lwcbr lras lcbr ck, ck 64 64 32 32 lwe ldmi x32 dqi data strobe intput buffer dll - 7 - rev 0.0 may 2005 128m gddr sdram k4d263238i-vc target ddr sdrams must be powered up and initialized in a predefined manner to prevent undefined operations. 1. apply power and keep cke at low state (all other inputs may be undefined) - apply v dd before v ddq . - apply v ddq before v ref & v tt 2. start clock and maintain stable condition for minimum 200us. 3. the minimum of 200us after stable power and clock(ck,ck ), apply nop and take cke to be high . 4. issue precharge command for all banks of the device. 5. issue a emrs command to enable dll *1 6. issue a mrs command to reset dll. the additional 200 clock cycles ar e required to lock the dll. * 1,2 7. issue precharge command for all banks of the device. 8. issue at least 2 or more auto-refresh commands. 9. issue a mode register set comm and with a8 to low to initialize the mode register. *1 the additional 200cycles of clo ck input is required to lock the dll after enabling dll. *2 sequence of 6&7 is regardless of the order. 7.1 power-up sequence 7.0 functional description power up & initialization sequence command 0 1 2 3 4 5 6 7 8 9 10111213141516171819 trp 2 clock min. precharge all banks 2nd auto refresh mode register set any command t rfc 1st auto refresh t rfc emrs mrs 2 clock min. dll reset precharge all banks t rp ck ck inputs must be stable for 200us 200 clock min. 2 clock min. * when the operating frequency is changed, dll reset should be required again. after dll reset again, the minimum 200 cycles of clock input is needed to lock the dll. - 8 - rev 0.0 may 2005 128m gddr sdram k4d263238i-vc target the mode register stores the dat a for controlling the various operating modes of ddr sdram. it programs cas latency, addressing mode, burst length, test mode, dll reset and various vendor specif ic options to make ddr sdram us eful for variety of different appli- cations. the default value of the mode register is not defined, t herefore the mode regi ster must be written after emrs setting for proper operation. the mode register is written by asserting low on cs , ras , cas and we (the ddr sdram should be in active mode with cke already high prior to writ ing into the mode r egister). the state of address pins a 0 ~ a 11 and ba 0 , ba 1 in the same cycle as cs , ras , cas and we going low is written in the mode register. minimum two cl ock cycles are requested to comple te the write operation in the mode register. the mode register contents can be changed using the same command and clock cycle requirements during operation a s long as all banks are in the idle state. t he mode register is divided into various fiel ds depending on functionality. the burst length uses a 0 ~ a 2 , addressing mode uses a 3 , cas latency(read latency from column address) uses a 4 ~ a 6 . a 7 is used for test mode. a 8 is used for dll reset. a 7, a 8 , ba 0 and ba 1 must be set to low for normal mrs operation. refer to the table for specific codes for various burst length, addressing modes and cas latencies. address bus mode register cas latency a 6 a 5 a 4 latency 0 0 0 reserved 0 0 1 reserved 0 1 0 reserved 011 3 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved burst length a 2 a 1 a 0 burst type sequential interleave 0 0 0 reserve reserve 001 2 2 010 4 4 011 8 8 1 0 0 reserve reserve 1 0 1 reserve reserve 1 1 0 reserve reserve 1 1 1 reserve reserve burst type a 3 type 0 sequential 1 interleave *1 : rfu(reserved for future use) should stay "0" during mrs cycle. ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 rfu *1 0 rfu *1 dll tm cas latency bt burst length ba 0 a n ~ a 0 0mrs 1emrs dll a8 dll reset 0no 1yes test mode a 7 mode 0normal 1test 7.2 mode register set(mrs) *1 : mrs can be issued only at all banks precharge state. *2 : minimum trp is required to issue mrs command. mrs cycle command ck, ck precharge nop nop mrs nop nop 2 01 5 34 8 67 any nop all banks command t rp t mrd =2 t ck nop - 9 - rev 0.0 may 2005 128m gddr sdram k4d263238i-vc target the extended mode register stores the data for enabling or di sabling dll and selecting output dr iver strength. the default valu e of the extended mode register is not defined, theref ore the extend mode register must be wr itten after power up for enabling or disabl ing dll. the extended mode register is wr itten by asserting low on cs , ras , cas , we and high on ba0(the ddr sdram should be in all bank precharge with cke already high prior to writ ing into the extended mode register). the state of address pins a0, a2 ~ a5, a7 ~ a11 and ba1 in the same cycle as cs , ras , cas and we going low are written in the extended m ode register. a1 and a6 are used for setting driver strength to weak or matched imp edance. two clock cycles are r equired to complete the writ e operation in the extended mod e reg- ister. the mode register contents can be changed using the same co mmand and clock cycle requiremen ts during operation as long a s all banks are in the idle state. a0 is used for dll enable or disabl e. ?high? on ba0 is used for em rs. all the other address pins e xcept a0,a1,a6 and ba0 must be set to low for proper emrs operation. refer to the table for specific codes. a 0 dll enable 0 enable 1 disable ba 0 a n ~ a 0 0mrs 1emrs address bus extended *1 : rfu(reserved for future use) should stay "0" during emrs cycle. rfu *1 1 rfu *1 d.i.c rfu *1 d.i.c dll ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 mode register 7.3 extended mode register set(emrs) note : permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. parameter symbol value unit voltage on any pin relative to vss v in , v out -0.5 ~ 3.6 v voltage on v dd supply relative to vss v dd -1.0 ~ 3.6 v voltage on v dd supply relative to vss v ddq -0.5 ~ 3.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 1.8 w short circuit current i os 50 ma 8.0 absolute maximum ratings a6 a1 output driver impedence control 0 0 full 100% 0 1 weak 60% 1 0 n/a do not use 1 1 matched 30% - 10 - rev 0.0 may 2005 128m gddr sdram k4d263238i-vc target recommended operating conditions(voltage referenced to v ss =0v, t a =0 to 65 c) note : 1. under all conditions vddq must be less than or equal to vdd. 2. v ref is expected to equal 0.50*vddq of the transmitting device and to track variations in the dc level of the same. peak to peak noise on the vref may not exceed + 2% of the dc value. thus, from 0.50*vddq, vref is allowed + 25mv for dc error and an additional + 25mv for ac noise. 3. vtt of the transmitting device must track vref of the receiving device. 4. vih(max.)= vddq +1.5v for a pulse and it which can not be greater than 1/3 of the cycle rate. 5. vil(min.)= -1.5v for a pulse width and it can not be greater than 1/3 of the cycle rate. 6. for any pin under test input of 0v vin vdd is acceptable. for all other pins that are not under test vin=0v. parameter symbol min typ max unit note device supply voltage v dd 2.375 2.5 2.625 v 1 output supply voltage v ddq 2.375 2.5 2.625 v 1 reference voltage v ref 0.49*v ddq - 0.51*v ddq v2 termination voltage v tt v ref -0.04 v ref v ref +0.04 v 3 input logic high voltage v ih v ref +0.15 - v ddq +0.30 v 4 input logic low voltage v il -0.30 - v ref -0.15 v 5 output logic high voltage v oh v tt +0.76 - - v i oh =-15.2ma output logic low voltage v ol --v tt -0.76 v i ol =+15.2ma input leakage current i il -5 - 5 ua 6 output leakage current i ol -5 - 5 ua 6 9.1 power & dc operating conditions(sstl_2 in/out) 9.0 ac & dc operating conditions recommended operating conditions unless otherwise noted ( ta=0 to 65 c) note : 1. measured with output open. 2. current meassured at v dd (max). 3. refresh period is 32ms. parameter symbol test condition version unit note -40 -50 operating current (one bank active) i cc1 burst lenth=2 t rc t rc (min) i ol =0ma, t cc = t cc (min) tbd tbd ma 1, 2 precharge standby current in power-down mode i cc2 p cke v il (max), t cc = t cc (min) tbd tbd ma 1, 2 precharge standby current in non power-down mode i cc2 n cke v ih (min), cs v ih (min), t cc = t cc (min). tbd tbd ma 1, 2 active standby current power-down mode i cc3 p cke v il (max), t cc = t cc (min) tbd tbd ma 1, 2 active standby current in in non power-down mode i cc3 n cke vih(min), cs vih(min), t cc = t cc (min) . tbd tbd ma 1, 2 operating current ( burst mode) i cc4 i ol =0ma , t cc = t cc (min), page burst, all banks activated. tbd tbd ma 1, 2 refresh current i cc5 t rc t rfc (min) tbd tbd ma 1, 2,3 self refresh current i cc6 cke 0.2v tbd ma 1, 2 9.2 dc characteristics - 11 - rev 0.0 may 2005 128m gddr sdram k4d263238i-vc target recommended operating conditions(voltage referenced to v ss =0v, v dd / v ddq =2.5v+ 5% , t a =0 to 65 c) note : 1. v id is the magnitude of the difference between the input level on ck and the input level on ck . 2. the value of v ix is expected to equal 0.5*v ddq of the transmitting device and must track variations in the dc level of the same. parameter symbol min typ max unit note input high (logic 1) voltage; dq v ih v ref +0.35 - - v input low (logic 0) voltage; dq v il --v ref -0.35 v clock input differential voltage; ck and ck v id 0.7 - v ddq +0.6 v 1 clock input crossing point voltage; ck and ck v ix 0.5*v ddq -0.2 - 0.5*v ddq +0.2 v 2 9.4 ac operating test conditions 9.3 ac input operating conditions r t =50 ? output c load =30pf (fig. 1) output load circuit z0=50 ? v ref =0.5*v ddq v tt =0.5*v ddq (vdd/ vddq=2.5v+ 5% , ta= 0 to 65 c) note 1 : in case of differential clocks(ck and ck ), input reference voltage for clock is a ck and ck ?s crossing point. parameter value unit note input reference voltage for ck(for single ended) 0.50*v ddq v1 ck and ck signal maximum peak swing 1.5 v ck signal minimum slew rate 1.0 v/ns input levels(v ih /v il )v ref +0.35/v ref -0.35 v input timing measurement reference level v ref v output timing measurement reference level v tt v output load condition see fig.1 - 12 - rev 0.0 may 2005 128m gddr sdram k4d263238i-vc target decoupling capacitance guide line 9.5 capacitance recommended decoupling capacitance added to power line at board. 1. v dd and v ddq pins are separated each other. all v dd pins are connected in chip. all v ddq pins are connected in chip. 2. v ss and v ssq pins are separated each other. all v ss pins are connected in chip. all v ssq pins are connected in chip. parameter symbol value unit decoupling capacitance between v dd and v ss c dc1 0.1 + 0.01 uf decoupling capacitance between v ddq and v ssq c dc2 0.1 + 0.01 uf (vdd=2.5v, ta= 25 c, f=1mhz) parameter symbol min max unit input capacitance( ck, ck )c in1 1.0 5.0 pf input capacitance(a 0 ~a 11 , ba 0 ~ba 1 )c in2 1.0 4.0 pf input capacitance( cke, cs , ras ,cas , we )c in3 1.0 4.0 pf data & dqs input/output capacitance(dq 0 ~dq 31 )c out 1.0 6.0 pf input capacitance(dm0 ~ dm3) c in4 1.0 6.0 pf parameter symbol -40 -50 unit note min max min max ck cycle time cl=3 tck 4.0 10 5.0 10 ns ck high level width tch 0.45 0.55 0.45 0.55 tck ck low level width tcl 0.45 0.55 0.45 0.55 tck dqs out access time from ck tdqsck -0.6 0.6 -0.7 +0.7 ns output access time from ck tac -0.6 0.6 -0.7 +0.7 ns data strobe edge to dout edge tdqsq - 0.4 - +0.45 ns read preamble trpre 0.9 1.1 0.9 1.1 tck read postamble trpst 0.4 0.6 0.4 0.6 tck ck to valid dqs-in tdqss 0.85 1.15 0.8 1.2 tck dqs-in setup time twpres 0 - 0 - ns dqs-in hold time twpreh 0.35 - 0.25 - tck dqs write postamble twpst 0.4 0.6 0.4 0.6 tck dqs-in high level width tdqsh 0.4 0.6 0.4 0.6 tck dqs-in low level width tdqsl 0.4 0.6 0.4 0.6 tck address and control input setup tis 0.9 - 1.0 - ns address and control input hold tih 0.9 - 1.0 - ns dq and dm setup time to dqs tds 0.4 - 0.45 - ns dq and dm hold time to dqs tdh 0.4 - 0.45 - ns clock half period thp tclmin or tchmin - tclmin or tchmin -ns data output hold time from dqs tqh thp-0.4 - thp-0.45 - ns 9.6 ac characteristics - 13 - rev 0.0 may 2005 128m gddr sdram k4d263238i-vc target note 1 : - the jedec ddr specification currently defines the output data valid window(tdv) as the time period when the data strobe and all data associated with that data strobe are coincidentally valid. - the previously used definition of tdv(=0.35tck) artificially penalizes system timing budgets by assuming the worst case out put valid window even then the clock duty cycle applied to the device is better than 45/55% - a new ac timing term, tqh which stands for data output hold time from dqs is defined to account for clock duty cycle variat ion and replaces tdv - tqhmin = thp-x where . thp=minimum half clock period for any given cycle and is defined by clock high or clock low time(tch,tcl) . x=a frequency dependent timing allowance account for tdqsqmax 134 thp ck, ck dqs dq cs 25 01 command reada tqh da0 tdqsq(max) tdqsq(max) da1 tqh timing (cl3, bl2) - 14 - rev 0.0 may 2005 128m gddr sdram k4d263238i-vc target ac characteristics (i) note : 1. for normal write operation, even numbers of din are to be written inside dram. 2. the number of clock of trp is restricted by the number of clock of tras and trp. 3. the number of clock of twr_a is fixed. it can?t be changed by tck. 4. trcdwr is equal to trcdrd-2tck and the number of clock can not be lower than 2tck. 5. the minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then roundi ng off to the next higher integer unconditionally. parameter symbol -40 -50 unit note min max min max row cycle time trc 48 - 50 - ns 2,5 refresh row cycle time trfc 56 - 55 - ns 5 row active time tras 32 100k 35 100k ns 5 ras to cas delay for read trcdrd 16 - 15 - ns 5 ras to cas delay for write trcdwr 8 10 ns 4 row precharge time trp 16 - 15 - ns 5 row active to row active trrd 12 - 15 - ns 5 last data in to row precharge twr 18 - 20 - ns 5 last data in to row precharge @auto precharge twr_a 3 - 3 - tck 3 auto precharge write recovery + precharge tdal7-6-tck3,5 last data in to read command tcdlr 2 - 2 - tck 1 col. address to col. address tccd 1 - 1 - tck mode register set cycle time tmrd 2 - 2 - tck exit self refresh to read command txsr 200 - 200 - tck power down exit time tpdex 3tck+tis - 3tck+tis -ns refresh interval time tref 7.8 - 7.8 - us ac characteristics (ii) (unit : number of clock) * 200/166mhz are supported in k4d263238i-vc40 * 166mhz is supported in k4d263238i-vc50 k4d263238i-vc40 frequency cas latency trc trfc tras trcdrd trcdwr trp trrd tdal unit 250mhz ( 4.0ns ) 3 12 14 8 4 2 4 3 7 tck 200mhz ( 5.0ns ) 3 10 11 7 3 2 3 3 6 tck 166mhz ( 6.0ns ) 3 9 9 6 3 2 3 2 6 tck k4d263238i-vc50 frequency cas latency trc trfc tras trcdrd trcdwr trp trrd tdal unit 200mhz ( 5.0ns ) 3 10 11 7 3 2 3 3 6 tck 166mhz ( 6.0ns ) 3 9 9 6 3 2 3 2 6 tck - 15 - rev 0.0 may 2005 128m gddr sdram k4d263238i-vc target simplified timing @ bl=2, cl=3 13467 tcl tck hi-z hi-z ck, ck dqs dq cs dm 25 tis tih 8 tds tdh 01 trpst trpre db0 db1 tdqss tdqsh tch da1 da2 twpst command reada writeb tdqsq t wpres t wpreh tdqsck tac 01 23 45 67 8 baa ra ra trcd activea activeb writea writeb db0 db1 db3 13 14 15 16 17 18 19 20 21 baa bab ca cb baa ca 9101112 prech baa 22 ra da0 da1 da2 da3 normal write burst (@ bl=4) multi bank interleaving write burst (@ bl=4) baa ra ra bab rb rb db2 tras trc trp trrd command dqs dq we dm ck, ck a8/ap addr (a0~a7, ba[1:0] a9~,a11) activea writea da0 da1 da2 da3 simplified timing(2) @ bl=4, cl=3 10.0 simplified timing - 16 - rev 0.0 may 2005 128m gddr sdram k4d263238i-vc target unit : mm 12.0 12.0 0.8 0.8 0.35 0.05 1.40 max |
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