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to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation ( http://www.renesas.com ) send any inquiries to http://www.renesas.com/inquiry .
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feb 18, 2005 page 1 of 85 rej03b0122-0101 7512 group single-chip 8-bit cmos microcomputer rej03b0122-0101 rev.1.01 feb 18, 2005 description the 7512 group is the 8-bit microcomputer based on the 740 fam- ily core technology. the 7512 group is designed for battery-pack and includes serial interface functions, 8-bit timer, a/d converter, current integrator and i 2 c-bus interface. features basic machine-language instructions ...................................... 71 minimum instruction execution time .................................. 1.0 s (at 4 mhz oscillation frequency) memory size flash memory .................................................. 36 k to 52 kbytes ram ............................................................... 1.0 k to 1.5 kbytes programmable input/output ports ............................................ 36 interrupts ................................................. 19 sources, 16 vectors timers ............................................................................. 8-bit ? 4 serial interface serial i/o1 .......... 8-bit ? 1 (uart or clock-synchronized) serial i/o2 .......................... 8-bit ? 1(clock-synchronized) multi-master i 2 c-bus interface (option) ...................... 1 channel pwm ............................................................................... 8-bit ? 1 a/d converter ............................................. 10-bit ? 10 channels pin configuration (top view) fig. 1 m37512fchp pin configuration current integrator ......................................................... 1 channel over current detector ................................................... 1 channel easy thermal sensor .................................................... 1 channel watchdog timer ............................................................ 16-bit ? 1 clock generating circuit ..................................... built-in 4 circuits (high-speed rc oscillator and 32khz rc oscillator, or connect to external ceramic resonator or quartz-crystal oscillator) power source voltage ............................................ 2.45 to 2.55 v power dissipation in high-speed mode ...................................................... 3.75 mw (at 4 mhz oscillation frequency, at 2.5 v power source voltage) in low-speed mode ........................................................ 1.05 mw (at 32 khz oscillation frequency, at 2.5 v power source voltage) operating temperature range .................................... ?0 to 85? application battery-pack, etc. 23 22 13 37 38 39 40 41 42 43 44 45 46 47 48 36 1 2 3 4 5 6 7 8 9 10 11 12 24 21 20 19 18 17 16 15 14 35 34 33 32 31 30 29 28 27 26 25 packa g e t yp e : 48p6q-a p1 7 /(led 7 ) p4 2 /int 1 p4 1 /int 0 p4 0 /cntr 1 p2 7 /cntr 0 /s rdy1 p2 6 /s clk p2 5 /scl 2 /t x d p2 3 /scl 1 p2 2 /sda 1 cnv ss p1 2 /(led 2 ) p1 3 /(led 3 ) p1 4 /(led 4 ) p1 5 /(led 5 ) p1 6 /(led 6 ) v ss x out x in p3 4 /an 4 p3 5 /an 5 p0 0 /s in2 p0 1 /s out2 p0 2 /s clk2 p0 3 /s rdy2 p0 4 /an 8 p0 5 /an 9 p0 6 /cfetcnt/an 10 p1 1 /(led 1 ) p0 7 /pwm 1 /an 11 p1 0 /(led 0 ) reset p2 0 /x cout p2 1 /x cin p4 4 /int 3 /pwm 0 p2 4 /sda 2 /r x d p3 3 /an 3 p3 2 /an 2 adv ss adv red v cc av ss isens 0 isens 1 p3 1 /an 1 p3 0 /an 0 av cc dfetcnt/p4 5 p4 3 /int 2 /s cmp2 m37512fchp
feb 18, 2005 page 2 of 85 rej03b0122-0101 7512 group functional block diagram fig. 2 functional block diagram functional block reset 15 12 cnv ss cntr 0 reset input p1(8) 19 21 23 25 20 22 24 26 i/o port p 1 timer 2 (8) prescaler y (8) timer y ( 8 ) cntr 1 p2(8) 681013 7 9 11 14 i/o port p 2 x cin x cout si/o2(8) p0(8) 27 28 29 30 31 32 33 34 i/o port p 0 si/o1(8) r a m r o m c p u a x y s pc h pc l ps v ss 18 v c c 43 39 40 p3(6) i/o port p 3 35 37 36 38 i c (8) 0 2 int 0 - int 3 p4(6) 48 4 135 i/o port p 4 2 x in out x 42 41 clock generating circuit main-clock input 16 17 10bit a/d converter adv ref adv ss x cin sub-clock input pwm (8) current integrator isens0 45 avcc 44 isens1 47 46 avss over current detector timer y ( 8 ) timer 2 (8) prescaler x (8) prescaler 12 (8) main-clock output reset watchdog timer x cout sub-clock output easy thermal sensor
feb 18, 2005 page 3 of 85 rej03b0122-0101 7512 group pin description functions name pin apply voltage of 2.5v to vcc, and 0 v to vss. apply voltage of 2.5v to avcc, and 0 v to avss, advss. reference voltage input pin for a/d converters. this pin controls the operation mode of the chip. normally connected to v ss . reset input pin for active l . input and output pins for the clock generating circuit. connect a ceramic resonator or quartz-crystal oscillator between the x in and x out pins to set the oscillation frequency. when a high-speed rc oscillator is used, leave the x in pin and x out pin open. when an external clock is used, connect the clock source to the x in pin and leave the x out pin open. 8-bit cmos i/o port. i/o direction register allows each pin to be individually programmed as either input or output. cmos compatible input level. p0 0 to p0 7 are cmos 3-state output structure, and p1 0 to p1 7 are n-channel open-drain structure. p1 0 to p1 7 (8 bits) are enabled to output large current for led drive. power source table 1 pin description function except a port function analog power source analog reference voltage cnv ss input reset input clock input clock output serial i/o2 function pin i/o port p0 a/d converter input pin / pwm output pin current integrator and over current detector input pins. connect the sense resistor. normally connect the isens0 to gnd. a/d converter input pin a/d converter input pin / over current detector function pin sub-clock generating circuit i/o pins (connect a resonat or registor and capacitor) 8-bit cmos i/o port. i/o direction register allows each pin to be individually programmed as either input or output. cmos compatible input level, but p2 2 to p2 5 can be switched between cmos compatible input level or smbus input level in the i 2 c-bus interface function. p2 0 , p2 1 , p2 6 , p2 7 : cmos3-state output structure. p2 2 to p2 5 : n-channel open-drain structure. 6-bit cmos i/o port with the same function as port p0. cmos compatible input level. cmos 3-state output structure. 6-bit cmos i/o port with the same function as port p0. cmos compatible input level. p4 0 to p4 2 , p4 5 are cmos 3-state output structure, and p4 3 and p4 4 are n-channel open-drain structure. i/o port p1 i/o port p2 i/o port p3 i/o port p4 analog input pin v cc , v ss av cc av ss adv ss ad vref cnv ss reset x in x out p0 0 /s in2 p0 1 /s out2 p0 2 /s clk2 p0 3 /s rdy2 p0 4 /an 8 p0 5 /an 9 p0 6 /cfetcnt/ an 10 p0 7 /an 11 / pwm 1 p1 0 p1 7 p2 0 /x cout p2 1 /x cin p2 2 /sda 1 p2 3 /scl 1 p2 4 /sda 2 /rxd p2 5 /scl 2 /txd p2 6 /s clk p2 7 /cntr 0 / s rdy1 p3 0 /an 0 p3 5 /an 5 p4 0 /cntr 1 p4 1 /int 0 p4 2 /int 1 p4 3 /int 2 /s cmp2 p4 4 /int 3 /pwm 0 p4 5 /dfetcnt isens0 isens1 i 2 c-bus interface function pins/ serial i/o1 function pins serial i/o1 function pin serial i/o1 function pin/ timer x function pin i 2 c-bus interface function pins a/d converter input pin timer y function pin interrupt input pins interrupt input pin/s cmp2 output pin interrupt input pin/pwm output pin over current detector function pin
feb 18, 2005 page 4 of 85 rej03b0122-0101 7512 group group expansion renesas plans to expand the 7512 group as follows. memory type support for flash memory version. memory size rom size ........................................................... 36 k to 52 k bytes ram size .......................................................... 1024 to 1536 bytes packages 48p6q-a ............................................... 48-pin plastic molded qfp fig. 3 memory expansion plan memory expansion plan 48k 32k 60k rom size (bytes) 768 1024 1280 1536 3072 ram size ( b y tes ) m37512fc mass production m37512fch under development m37512f8 mass production m37512f8h under development currently planning products are listed below. ram size (bytes) remarks package table 2 support products product name rom size (bytes) m37512f8hp m37512f8-xxxhp m37512f8hhp (note 1) M37512F8H-XXXHP (note 1) m37512fchp m37512fc-xxxhp m37512fchhp (note 1) m37512fch-xxxhp (note 1) 48p6q-a 32k + 4k 1024 48k + 4k 1536 note 1. the products of which erase/write cycles onto the blocks a and b are maximum 10k are under development.
feb 18, 2005 page 5 of 85 rej03b0122-0101 7512 group functional description central processing unit (cpu) the 7512 group uses the standard 740 family instruction set. re- fer to the table of 740 family addressing modes and machine instructions or the 740 family software manual for details on the instruction set. machine-resident 740 family instructions are as follows: the fst and slw instructions cannot be used. the stp, wit, mul, and div instructions can be used. [accumulator (a)] the accumulator is an 8-bit register. data operations such as data transfer, etc. are executed mainly through the accumulator. [index register x (x)] the index register x is an 8-bit register. in the index addressing modes, the value of the operand is added to the contents of register x and specifies the real address. [index register y (y)] the index register y is an 8-bit register. in partial instruction, the value of the operand is added to the contents of register y and specifies the real address. fig.4 740 family cpu register structure [stack pointer (s)] the stack pointer is an 8-bit register used during subroutine calls and interrupts. this register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. the low-order 8 bits of the stack address are determined by the contents of the stack pointer. the high-order 8 bits of the stack ad- dress are determined by the stack page selection bit. if the stack page selection bit is 0 , the high-order 8 bits becomes 00 16 . if the stack page selection bit is 1 , the high-order 8 bits becomes 01 16 . the operations of pushing register contents onto the stack and popping them from the stack are shown in figure 5. store registers other than those described in figure 4 with pro- gram when the user needs them during interrupts or subroutine calls (see table 3). [program counter (pc)] the program counter is a 16-bit counter consisting of two 8-bit registers pc h and pc l . it is used to indicate the address of the next instruction to be executed. a accumulator b7 b7 b7 b7 b0 b7 b15 b0 b7 b0 b0 b0 b0 x index register x y index register y s stack pointer pc l program counter pc h n v t b d i z c processor status register (ps) carry flag zero flag interrupt disable flag decimal mode flag break flag index x mode flag overflow flag negative flag
feb 18, 2005 page 6 of 85 rej03b0122-0101 7512 group table 3 push and pop instructions of accumulator or processor status register accumulator processor status register push instruction to stack pha php pop instruction from stack pla plp fig. 5 register push and pop at interrupt generation and subroutine call n o t e : c o n d i t i o n f o r a c c e p t a n c e o f a n i n t e r r u p t i n t e r r u p t e n a b l e f l a g i s 1 e x e c u t e j s r o n - g o i n g r o u t i n e m ( s )( p c h ) ( s ) ( s ) 1 m ( s )( p c l ) e x e c u t e r t s ( p c l )m ( s ) ( s ) ( s ) 1 ( s ) ( s ) + 1 ( s ) ( s ) + 1 ( p c h )m ( s ) s u b r o u t i n e p o p re t u r n a d d r e s s f r o m s t a c k p u s h r e t u r n a d d r e s s o n s t a c k m ( s )( p s ) e x e c u t e r t i ( p s )m ( s ) ( s ) ( s ) 1 ( s ) ( s ) + 1 i n t e r r u p t s e r v i c e r o u t i n e p o p c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r f r o m s t a c k m ( s )( p c h ) ( s ) ( s ) 1 m ( s )( p c l ) ( s ) ( s ) 1 ( p c l )m ( s ) ( s ) ( s ) + 1 ( s ) ( s ) + 1 ( p c h )m ( s ) p o p r e t u r n a d d r e s s f r o m s t a c k i f l a g i s s e t f r o m 0 t o 1 f e t c h t h e j u m p v e c t o r p u s h r e t u r n a d d r e s s o n s t a c k p u s h c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r o n s t a c k i n t e r r u p t r e q u e s t ( n o t e ) i n t e r r u p t d i s a b l e f l a g i s 0
feb 18, 2005 page 7 of 85 rej03b0122-0101 7512 group [processor status register (ps)] the processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide mcu operation. branch opera- tions can be performed by testing the carry (c) flag , zero (z) flag, overflow (v) flag, or the negative (n) flag. in decimal mode, the z, v, n flags are not valid. bit 0: carry flag (c) the c flag contains a carry or borrow generated by the arithmetic logic unit (alu) immediately after an arithmetic operation. it can also be changed by a shift or rotate instruction. bit 1: zero flag (z) the z flag is set if the result of an immediate arithmetic operation or a data transfer is 0 , and cleared if the result is anything other than 0 . bit 2: interrupt disable flag (i) the i flag disables all interrupts except for the interrupt generated by the brk instruction. interrupts are disabled when the i flag is 1 . bit 3: decimal mode flag (d) the d flag determines whether additions and subtractions are executed in binary or decimal. binary arithmetic is executed when this flag is 0 ; decimal arithmetic is executed when it is 1 . decimal correction is automatic in decimal mode. only the adc and sbc instructions can execute decimal arithmetic. bit 4: break flag (b) the b flag is used to indicate that the current interrupt was generated by the brk instruction. the brk flag in the processor status register is always 0 . when the brk instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to 1 . bit 5: index x mode flag (t) when the t flag is 0 , arithmetic operations are performed between accumulator and memory. when the t flag is 1 , direct arithmetic operations and direct data transfers are enabled between memory locations. bit 6: overflow flag (v) the v flag is used during the addition or subtraction of one byte of signed data. it is set if the result exceeds +127 to -128. when the bit instruction is executed, bit 6 of the memory location operated on by the bit instruction is stored in the overflow flag. bit 7: negative flag (n) the n flag is set if the result of an arithmetic operation or data transfer is negative. when the bit instruction is executed, bit 7 of the memory location operated on by the bit instruction is stored in the negative flag. table 4 set and clear instructions of each bit of processor status register set instruction clear instruction c flag sec clc z flag i flag sei cli d flag sed cld b flag t flag set clt v flag clv n flag
feb 18, 2005 page 8 of 85 rej03b0122-0101 7512 group fig. 6 structure of cpu mode register cpu mode register ( cpum : address 003b 16 ) b7 b0 note : all bits in this re g ister are p rotected b y p rotect mode. processor mode bits b1 b0 0 0 : single-chip mode 01: 1 0 : not available 11: stack page selection bit 0 : 0 page 1 : 1 page clock source switch bit 0 : built-in high speed oscillating function 1:x cin x cout oscillation function port x c switch bit 0 : i/o port function (stop oscillation) 1:x cin x cout oscillation function main clock (x in x out ) stop bit 0 : oscillation 1 : stopped main clock division ratio selection bits b7 b6 00: = f(x in )/2 (high-speed mode) 01: = f(x in )/8 (middle-speed mode) 10: = f(x in )/2 (low-speed mode) 1 1 : not available [cpu mode register (cpum)] 003b 16 the cpu mode register contains the stack page selection bit, etc. the cpu mode register is allocated at address 003b 16 .
feb 18, 2005 page 9 of 85 rej03b0122-0101 7512 group memory special function register (sfr) area the special function register area in the zero page contains con- trol registers such as i/o ports and timers. ram ram is used for data storage and for stack area of subroutine calls and interrupts. flash memory the last 2 bytes of flash memory are reserved for device testing and the rest is user area for storing programs. interrupt vector area the interrupt vector area contains reset and interrupt vectors. zero page access to this area with only 2 bytes is possible in the zero page addressing mode. special page access to this area with only 2 bytes is possible in the special page addressing mode. fig. 7 memory map diagram ram size and area ram size (bytes) address xxxx 16 1536 063f 16 m37512f8hp m37512f8-xxxhp m37512f8hhp M37512F8H-XXXHP product name m37512fchp m37512fc-xxxhp m37512fchhp m37512fch-xxxhp 1024 043f 16 rom size and area (except data block) rom size (bytes) address yyyy 16 49152 4000 16 product name 32768 8000 16 m37512f8hp m37512f8-xxxhp m37512f8hhp M37512F8H-XXXHP m37512fchp m37512fc-xxxhp m37512fchhp m37512fch-xxxhp 0100 16 0000 16 0040 16 xxxx 16 ff00 16 ffdc 16 fffe 16 ffff 16 1000 16 1fff 16 ram rom 0fe0 16 0fff 16 ffd4 16 yyyy 16 sfr area not used interrupt vector area zero page special page reserved memory area sfr area flash memory id code not used rom ff00 16 ffdc 16 fffe 16 ffff 16 ffd4 16 special page reserved memory area boot rom area f000 16 user rom area
feb 18, 2005 page 10 of 85 rej03b0122-0101 7512 group fig. 8 memory map of special function register (sfr) 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 port p0 (p0) port p0 direction register (p0d) port p1 (p1) port p1 direction register (p1d) port p2 (p2) port p2 direction register (p2d) port p3 (p3) port p3 direction register (p3d) port p4 (p4) port p4 direction register (p4d) discharge counter latch low-order register (dchargel) discharge counter latch high-order register (dchargeh) charge counter latch low-order register (chargel) charge counter latch high-order register (chargeh) current integrator control register (cinfcon) short current detector control register (scdcon) over current detector control register (ocdcon) current detect time set up register 1 (ocdtime1) wake up current detector control register1 (wudcon1) current detect status register (ocdsts) wake up current detector control register2 (wudcon2) serial i/o2 control register 1 (sio2con1) serial i/o2 control register 2 (sio2con2) serial i/o2 register (sio2) transmit/receive buffer register (tb/rb) serial i/o1 status register (siosts) serial i/o1 control register (siocon) uart control register (uartcon) baud rate generator (brg) pwm control register (pwmcon) pwm prescaler (prepwm) pwm register (pwm) 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 0ff0 16 0ff1 16 0ff2 16 0ff3 16 0ff4 16 0ff5 16 prescaler 12 (pre12) timer 1 (t1) timer 2 (t2) timer xy mode register (tm) prescaler x (prex) timer x (tx) prescaler y (prey) timer y (ty) timer count source selection register (tcss) sfr protect control register (prreg) i 2 c data shift register (s0) i 2 c address register (s0d) i 2 c status register (s1) i 2 c control register (s1d) i 2 c clock control register (s2) i 2 c start/stop condition control register (s2d) i 2 c additional register (s3) 32khz rc oscillation control register0 (32koscc0) 32khz rc oscillation control register1 (32koscc1) ad control register (adcon) ad conversion low-order register (adl) ad conversion high-order register (adh) misrg2 misrg watchdog timer control register (wdtcon) interrupt edge selection register 1 (intedge1) cpu mode register (cpum) interrupt request register 1 (ireq1) interrupt request register 2 (ireq2) interrupt control register 1 (icon1) interrupt control register 2 (icon2) charge over current detector control register (cocdcon) current detect time set up register 2 (ocdtime2) high-speed rc oscillator frequency set up register (o4rcfrg) high-speed rc oscillator frequency counter (o4rcfcnt) high-speed rc oscillator control register (o4rccot) interrupt edge selection register 2 (intedg2) * reserved : do not write any data to the reserved area. 0fe0 16 0fe1 16 0fe2 16 0fe3 16 0fe4 16 0fe5 16 0fe6 16 0fe7 16 0fe8 16 0fe9 16 0fea 16 0feb 16 0fec 16 0fed 16 0fee 16 0fef 16 flash memory control register 0 (fmcr0) flash memory control register 1 (fmcr1) flash memory control register 2 (fmcr2) reserved * reserved * reserved * reserved * reserved * reserved * reserved * reserved * reserved * reserved * reserved * reserved * reserved *
feb 18, 2005 page 11 of 85 rej03b0122-0101 7512 group pin port p0 port p1 port p2 port p3 port p4 input/output, individual bits cmos compatible input level cmos 3-state output cmos compatible input level n-channel open-drain output cmos compatible input level cmos 3-state output cmos compatible input level cmos/smbus input level (when selecting i 2 c-bus interface function) n-channel open-drain output cmos compatible input level cmos 3-state output cmos compatible input level n-channel open-drain output cmos compatible input level cmos 3-state output table 5 i/o port function i/o ports the i/o ports have direction registers which determine the input/ output direction of each individual pin. each bit in a direction reg- ister corresponds to one pin, and each pin can be set to be input port or output port. when 0 is written to the bit corresponding to a pin, that pin be- comes an input pin. when 1 is written to that bit, that pin becomes an output pin. p0 0 /s in2 p0 1 /s out2 p0 2 /s clk2 __________ p0 3 /s rdy2 p0 4 /an 8 p0 5 /an 9 p0 6 /cfetcnt/an 10 p0 7 /an 11 /pwm 1 p1 0 p1 7 p2 0 /x cout p2 1 /x cin p2 2 /sda 1 p2 3 /scl 1 p2 4 /sda 2 /rxd p2 5 /scl 2 /txd p2 6 /s clk p2 7 /cntr 0 / __________ s rdy1 p3 0 /an 0 p3 5 /an 5 p4 0 /cntr 1 p4 1 /int 0 p4 2 /int 1 p4 3 /int 2 /s cmp2 p4 4 /int 3 /pwm 0 p4 5 /dfetcnt serial i/o2 control register ad control register misrg2 ad control register, misrg2 charge over current detect control register ad control register, misrg2 pwm control register cpu mode register misrg2 i 2 c control register i 2 c control register serial i/o1 control register serial i/o1 control register serial i/o1 control register timer xy mode register ad control register misrg2 timer xy mode register interrupt edge selection register 1 interrupt edge selection register 2 serial i/o2 control register interrupt edge selection register 2 pwm control register short current detect control register over current detect control register wake up current detect control register serial i/o2 function i/o a/d conversion input a/d conversion input over current detector output a/d conversion input pwm output sub-clock generating circuit i 2 c-bus interface function i/o i 2 c-bus interface function i/o serial i/o1 function i/o serial i/o1 function i/o serial i/o1 function i/o timer x function i/o a/d conversion input timer y function i/o external interrupt input external interrupt input scmp2 output external interrupt input pwm output over current detector output if data is read from a pin which is set to output, the value of the port output latch is read, not the value of the pin itself. pins set to input are floating. if a pin set to input is written to, only the port output latch is written to and the pin remains floating. name input/output i/o structure non-port function related sfrs ref.no. (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (6) (18) (19) (20) (21) (22)
feb 18, 2005 page 12 of 85 rej03b0122-0101 7512 group fig. 9 port block diagram (1) (4) port p0 3 (1) port p0 0 (2) port p0 1 (3) port p0 2 p0 2 /s clk2 p-channel output disable bit direction register data bus port latch data bus data bus serial i/o2 input p0 1 /s out2 p-channel output disable bit data bus serial i/o2 transmit completion signal serial i/o2 port selection bit serial i/o2 output s rdy2 output enable bit serial i/o2 ready output serial i/o2 synchronous clock selection bit serial i/o2 port selection bit serial i/o2 external clock input serial i/o2 clock output (6) ports p0 5, p3 0 p3 5 (5) port p0 4 data bus a/d converter input analog input pin selection bit data bus a/d converter input analog input pin selection bit (7)port p0 6 analog input pin selection bit data bus cfetcntoutput int 3 input cfetcnt-int 3 or output valid bit 1 0 a/d converter input charge over current detector enable bit charge fet control polarity switch bit (8)port p0 7 a/d converter input pwm output analog input pin selection bit data bus pwm enable bit pwm output pin selection bit direction register port latch direction register port latch direction register port latch direction register port latch direction register port latch direction register port latch direction register port latch
feb 18, 2005 page 13 of 85 rej03b0122-0101 7512 group fig. 10 port block diagram (2) (15) port p2 5 data bus serial i/o1 enable bit transmit enable bit sda/scl pin selection bit i 2 c-bus interface enable bit scl input serial i/o1 output scl output sda/scl pin selection bit (12) port p2 2 data bus sda output sda input i 2 c-bus interface enable bit data bus (16) port p2 6 serial i/o1 enable bit serial i/o1 mode selection bit serial i/o1 enable bit serial i/o1 synchronous clock selection bit serial i/o1 external clock in p ut serial i/o1 clock output (14) port p2 4 sda output sda input sda/scl pin selection bit i 2 c-bus interface enable bit data bus serial i/o1 input serial i/o1 enable bit receive enable bit (13) port p2 3 data bus sda/scl pin selection bit scl output scl input (11) port p2 1 data bus port x c switch bit sub-clock generating circuit input (10) port p2 0 data bus port x c switch bit port p2 1 port xc switch bit 32khz rc oscillation enable bit 32khz rc oscillation enable bit reference voltage (9) port p1 data bus direction register port latch direction register port latch direction register port latch direction register port latch direction register port latch direction register port latch direction register port latch direction register port latch i 2 c-bus interface enable bit +
feb 18, 2005 page 14 of 85 rej03b0122-0101 7512 group fig. 11 port block diagram (3) (22) port p4 5 data bus discharge fet control polarity switch bit dfetcnt output int 2 input dfetcnt-int 2 or output enable bit 1 0 (21) port p4 4 (20) port p4 3 data bus serial i/o2 input/output comparison signal control bit serial i/o2 input/output comparison signal output int 2 interrupt input (19) ports p4 1 , p4 2 data bus interrupt input (18) port p4 0 data bus cntr 1 interrupt input pulse output mode timer output (17) port p2 7 data bus cntr 0 interrupt input pulse output mode timer output serial i/o1 ready output pulse output mode serial i/o1 enable bit serial i/o1 mode selection bit s rdy1 output enable bit direction register port latch direction register port latch direction register port latch direction register port latch direction register port latch pwm function enable bit pwm output data bus int 3 interrupt input direction register port latch pwm output pin selection bit short current detect enable bit over current detect enable bit wake up current detect enable bit charge over current detect enable bit
feb 18, 2005 page 15 of 85 rej03b0122-0101 7512 group interrupts interrupts occur by 16 sources among 20 sources: seven external, twelve internal, and one software. interrupt control each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software in- terrupt set by the brk instruction. an interrupt occurs if the corresponding interrupt request and enable bits are 1 and the in- terrupt disable flag is 0 . interrupt enable bits can be set or cleared by software. interrupt request bits can be cleared by software, but cannot be set by software. the reset and the brk instruction cannot be disabled with any flag or bit. the i (interrupt disable) flag disables all interrupts ex- cept the reset and the brk instruction interrupt. when several interrupts occur at the same time, the interrupts are received according to priority. interrupt operation by acceptance of an interrupt, the following operations are auto- matically performed: 1. the contents of the program counter and the processor status register are automatically pushed onto the stack. 2. the interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. the interrupt jump destination address is read from the vector table into the program counter. notes when setting the followings, the interrupt request bit may be set to 1 . when switching external interrupt active edge related register: interrupt edge selection register 1 (address 003a 16 ) i 2 c start/stop condition control register (address 0030 16 ) timer xy mode register (address 0023 16 ) when switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated related register: interrupt edge selection register 1 (address 003a 16 ) when not requiring for the interrupt occurrence synchronized with these setting, take the following sequence. (1) set the corresponding interrupt enable bit to 0 (disabled). (2) set the interrupt edge select bit or the interrupt source select bit. (3) set the corresponding interrupt request bit to 0 after 1 or more instructions have been executed. (4) set the corresponding interrupt enable bit to 1 (enabled).
feb 18, 2005 page 16 of 85 rej03b0122-0101 7512 group interrupt request generating conditions remarks interrupt source low fffc 16 high fffd 16 priority 1 table 6 interrupt vector addresses and priority vector addresses (note 1) reset (note 2) int 0 scl, sda int 1 int 2 int 3 serial i/o2 at reset at detection of either rising or falling edge of int 0 input at detection of either rising or falling edge of int 1 input at detection of either rising or falling edge of int 2 input non-maskable external interrupt (active edge selectable) external interrupt (active edge selectable) at detection of either rising or falling edge of s cl or s da input external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) fffa 16 fff8 16 fff6 16 fff4 16 fff2 16 fffb 16 fff9 16 fff7 16 fff5 16 fff3 16 2 3 4 5 6 fff0 16 fff1 16 7 i 2 c timer x timer y timer 1 timer 2 serial i/o1 reception serial i/o1 transmission over current detection valid when serial i/o1 is selected valid when serial i/o1 is selected ffee 16 ffec 16 ffea 16 ffe8 16 ffe6 16 ffe4 16 ffef 16 ffed 16 ffeb 16 ffe9 16 ffe7 16 ffe5 16 8 9 10 11 12 13 at detection of either rising or falling edge of int 3 input at completion of serial i/o2 data reception / transmission valid when serial i/o2 is selected at completion of data transfer at timer x underflow at timer y underflow at timer 1 underflow at timer 2 underflow at completion of serial i/o1 data reception at completion of serial i/o1 transfer shift or when transmis- sion buffer is empty at discharge short current is de- tected, at discharge over current is detected, at wake up current is detected, or at charge over current is detected. stp release timer underflow valid when discharge short current detector or discharge current detector, or wake up current detector, or charge over current detector is selected. notes 1: vector addresses contain interrupt jump destination addresses. 2: reset function in the same way as an interrupt with the highest priority. cntr 0 ffe2 16 ffe0 16 ffde 16 ffe3 16 ffe1 16 ffdf 16 ffdc 16 ffdd 16 14 15 16 17 at detection of either rising or falling edge of cntr 0 input at detection of either rising or falling edge of cntr 1 input cntr 1 a/d converter at completion of a/d conversion external interrupt (active edge selectable) external interrupt (active edge selectable) valid when current integrator is selected non-maskable software interrupt current integration brk instruction at end of current integration period, or at end of calibration at brk instruction execution
feb 18, 2005 page 17 of 85 rej03b0122-0101 7512 group fig. 12 interrupt control fig. 13 structure of interrupt-related registers interrupt disable flag (i) interrupt request interrupt request bit interrupt enable bit brk instruction reset b7 b0 b7 b0 b7 b0 b7 b0 b7 b0 interrupt control register 1 0 : no interrupt request issued 1 : interrupt request issued (icon1 : address 003e 16 ) interrupt request register 2 timer 1 interrupt request bit timer 2 interrupt request bit serial i/o1 reception interrupt request bit serial i/o1 transmit / over current detect interrupt request bit cntr 0 interrupt request bit cntr 1 interrupt request bit ad converter /current integrate interrupt request bit not used (returns 0 when read) (ireq2 : address 003d 16 ) interrupt control register 2 timer 1 interrupt enable bit timer 2 interrupt enable bit serial i/o1 reception interrupt enable bit serial i/o1 transmit / over current detect interrupt enable bit cntr 0 interrupt enable bit cntr 1 interrupt enable bit ad converter / current integrate interrupt enable bit not used (returns 0 when read) (do not write 1 to this bit) 0 : interrupts disabled 1 : interrupts enabled (icon2 : address 003f 16 ) interrupt request register 1 int 0 interrupt request bit scl/sda interrupt request bit int 1 interrupt request bit int 2 interrupt request bit int 3 / serial i/o2 interrupt request bit i 2 c interrupt request bit timer x interrupt request bit timer y interrupt request bit (ireq1 : address 003c 16 ) 0 : no interrupt request issued 1 : interrupt request issued int 0 interrupt enable bit scl/sda interrupt enable bit int 1 interrupt enable bit int 2 interrupt enable bit int 3 / serial i/o2 interrupt enable bit i 2 c interrupt enable bit timer x interrupt enable bit timer y interrupt enable bit 0 : interrupts disabled 1 : interrupts enabled int 0 active edge selection bit 0 : falling edge active 1 : rising edge active int 1 active edge selection bit 0 : falling edge active 1 : rising edge active not used (returns 0 when read) serial i/o2 / int 3 interrupt source bit 0 : int 3 interrupt selected 1 : serial i/o2 interrupt selected current integrate/a/d converter interrupt source bit 0 : ad converter interrupt selected 1 : current integrate interrupt selected over current detect / serial i/o1 transmit interrupt source bit 0 : serial i/o1 transmit interrupt selected 1 : over current detect interrupt selected not used (returns 0 when read) interrupt edge selection register 1 (intedge1 : address 003a 16 ) int 2 falling edge active bit 0 : no operation 1 : falling edge active int 2 rising edge active bit 0 : no operation 1 : rising edge active int 3 falling edge active bit 0 : no operation 1 : falling edge active int 3 rising edge active bit 0 : no operation 1 : rising edge active not used (returns 0 when read) b7 b0 interrupt edge selection register 2 (intedge2 : address 0ff5 16 )
feb 18, 2005 page 18 of 85 rej03b0122-0101 7512 group timers the 7512 group has four timers: timer x, timer y, timer 1, and timer 2. the division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding timer or prescaler latch. all timers are count down. when the timer reaches 00 16 , an un- derflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. when a timer underflows, the interrupt request bit corresponding to that timer is set to 1 . timer 1 and timer 2 the count source of prescaler 12 is the oscillation frequency which is selected by timer 12 count source selection bit. the out- put of prescaler 12 is counted by timer 1 and timer 2, and a timer underflow sets the interrupt request bit. timer x and timer y timer x and timer y can each select in one of four operating modes by setting the timer xy mode register. (1) timer mode the timer counts the count source selected by timer count source selection bit. (2) pulse output mode the timer counts the count source selected by timer count source selection bit. whenever the contents of the timer reach 00 16 , the signal output from the cntr 0 (or cntr 1 ) pin is inverted. if the cntr 0 (or cntr 1 ) active edge selection bit is 0 , output begins at h . if it is 1 , output starts at l . when using a timer in this mode, set the corresponding port p2 7 ( or port p4 0 ) direction register to out- put mode. (3) event counter mode operation in event counter mode is the same as in timer mode, except that the timer counts signals input through the cntr 0 or cntr 1 pin. when the cntr 0 (or cntr 1 ) active edge selection bit is 0 , the rising edge of the cntr 0 (or cntr 1 ) pin is counted. when the cntr 0 (or cntr 1 ) active edge selection bit is 1 , the falling edge of the cntr 0 (or cntr 1 ) pin is counted. (4) pulse width measurement mode if the cntr 0 (or cntr 1 ) active edge selection bit is 0 , the timer counts the selected signals by the count source selection bit while the cntr 0 (or cntr 1 ) pin is at h . if the cntr 0 (or cntr 1 ) ac- tive edge selection bit is 1 , the timer counts it while the cntr 0 (or cntr 1 ) pin is at l . the count can be stopped by setting 1 to the timer x (or timer y) count stop bit in any mode. the corresponding interrupt request bit is set each time a timer underflows. fig. 14 structure of timer xy mode register note when switching the count source by the timer 12, x and y count source bit, the value of timer count is altered in inconsiderable amount owing to generating of a thin pulses in the count input signals. therefore, select the timer count source before set the value to the prescaler and the timer. fig. 15 structure of timer count source selection register timer x count stop bit 0: count start 1: count stop timer xy mode register (tm : address 0023 16 ) timer y operating mode bit 0 0: timer mode 0 1: pulse output mode 1 0: event counter mode 1 1: pulse width measurement mode cntr 1 active edge selection bit 0: interrupt at falling edge count at rising edge in event counter mode 1: interrupt at rising edge count at falling edge in event counter mode b7 cntr 0 active edge selection bit 0: interrupt at falling edge count at rising edge in event counter mode 1: interrupt at rising edge count at falling edge in event counter mode b0 timer x operating mode bit 0 0: timer mode 0 1: pulse output mode 1 0: event counter mode 1 1: pulse width measurement mode b1b0 b5b4 timer y count stop bit 0: count start 1: count stop timer count source selection register (tcss : address 0028 16 ) b7 b0 timer x count source selection bit 0 : f(x in )/16 (f(x cin )/16 at low-speed mode) 1 : f(x in )/2 (f(x cin )/2 at low-speed mode) timer y count source selection bit 0 : f(x in )/16 (f(x cin )/16 at low-speed mode) 1 : f(x in )/2 (f(x cin )/2 at low-speed mode) timer 12 count source selection bit 0 : f(x in )/16 (f(x cin )/16 at low-speed mode) 1 : f(x cin ) not used (returns 0 when read)
feb 18, 2005 page 19 of 85 rej03b0122-0101 7512 group fig. 16 block diagram of timer x, timer y, timer 1, and timer 2 q q 1 0 p2 7 /cntr 0 q q p4 0 /cntr 1 0 1 r r 1 0 0 1 t t prescaler x latch (8) prescaler x (8) timer x latch (8) timer x (8) to timer x interrupt request bit toggle flip-flop timer x count stop bit pulse width measurement mode event counter mode to cntr 0 interrupt request bit pulse output mode port p2 7 latch port p2 7 direction register cntr 0 active edge selection bit timer x latch write pulse pulse output mode timer mode pulse output mode prescaler y latch (8) prescaler y (8) timer y latch (8) timer y (8) to timer y interrupt request bit toggle flip-flop timer y count stop bit to cntr 1 interrupt request bit pulse output mode port p4 0 latch port p4 0 direction register cntr 1 active edge selection bit timer y latch write pulse pulse output mode timer mode pulse output mode data bus data bus prescaler 12 latch (8) prescaler 12 (8) timer 1 latch (8) timer 1 (8) data bus timer 2 latch (8) timer 2 (8) to timer 2 interrupt request bit to timer 1 interrupt request bit cntr 0 active edge selection bit cntr 1 active edge selection bit pulse width measure- ment mode event counter mode f(x cin ) timer 12 count source selection bit timer y count source selection bit f(x in )/2 (f(x c in )/2 at low-speed mode) timer x count source selection bit f(x in )/16 (f(x c in )/16 at low-speed mode) f(x in )/2 (f(x c in )/2 at low-speed mode) f(x in )/16 (f(x c in )/16 at low-speed mode) f(x in )/16 (f(x c in )/16 at low-speed mode)
feb 18, 2005 page 20 of 85 rej03b0122-0101 7512 group serial i/o1 serial i/o1 can be used as either clock synchronous or asynchro- nous (uart) serial i/o1. a dedicated timer is also provided for baud rate generation. (1) clock synchronous serial i/o mode clock synchronous serial i/o mode can be selected by setting the serial i/o mode selection bit of the serial i/o1 control register (bit 6 of address 001a 16 ) to 1 . for clock synchronous serial i/o, the transmitter and the receiver must use the same clock. if an internal clock is used, transfer is started by a write signal to the tb/rb. fig. 17 block diagram of clock synchronous serial i/o1 fig. 18 operation of clock synchronous serial i/o1 function 1/4 1/4 f/f p2 6 /s clk serial i/o1 status register serial i/o1 control register p2 7 /s rdy1 p2 4 /r x d p2 5 /t x d x in receive buffer register address 0018 16 receive shift register receive buffer full flag (rbf) receive interrupt request (ri) clock control circuit shift clock serial i/o1 synchronous clock selection bit frequency division ratio 1/(n+1) baud rate generator address 001c 16 brg count source selection bit clock control circuit falling-edge detector transmit buffer register data bus address 0018 16 shift clock transmit shift completion flag (tsc) transmit buffer empty flag (tbe) transmit interrupt request (ti) transmit interrupt source selection bit address 0019 16 data bus address 001a 16 transmit shift register d 7 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 6 rbf = 1 tsc = 1 tbe = 0 tbe = 1 tsc = 0 transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) serial output txd serial input rxd write pulse to receive/transmit buffer register (address 0018 16 ) overrun error (oe) detection notes 1: as the transmit interrupt (ti), either when the transmit buffer has emptied (tbe=1) or after the transmit shift operation has ended (tsc=1), by setting the transmit interrupt source selection bit (tic) of the serial i/o1 control register. 2: if data is written to the transmit buffer register when tsc=0, the transmit clock is generated continuously and serial data is output continuously from the txd pin. 3: the receive interrupt (ri) is set when the receive buffer full flag (rbf) becomes 1 . receive enable signal s rdy1
feb 18, 2005 page 21 of 85 rej03b0122-0101 7512 group (2) asynchronous serial i/o (uart) mode clock asynchronous serial i/o mode (uart) can be selected by clearing the serial i/o1 mode selection bit (b6) of the serial i/o1 control register to 0 . eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. the transmit and receive shift registers each have a buffer, but the two buffers have the same address in memory. since the shift reg- ister cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. the transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. fig. 19 block diagram of uart serial i/o1 x in 1/4 oe pe fe 1/16 1/16 data bus receive buffer register address 0018 16 receive shift register receive buffer full flag (rbf) receive interrupt request (ri) baud rate generator frequency division ratio 1/(n+1) address 001c 16 st/sp/pa generator transmit buffer register data bus transmit shift register address 0018 16 transmit shift completion flag (tsc) transmit buffer empty flag (tbe) transmit interrupt request (ti) address 0019 16 st detector sp detector uart control register address 001b 16 character length selection bit address 001a 16 brg count source selection bit transmit interrupt source selection bit serial i/o1 synchronous clock selection bit clock control circuit character length selection bit 7 bits 8 bits serial i/o1 control register p2 6 /s clk1 serial i/o1 status register p2 4 /r x d p2 5 /t x d
feb 18, 2005 page 22 of 85 rej03b0122-0101 7512 group fig. 20 operation of uart serial i/o1 function [transmit buffer register/receive buffer register (tb/rb)] 0018 16 the transmit buffer register and the receive buffer register are lo- cated at the same address. the transmit buffer is write-only and the receive buffer is read-only. if a character bit length is 7 bits, the msb of data stored in the receive buffer is 0 . [serial i/o1 status register (siosts)] 0019 16 the read-only serial i/o1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial i/o1 function and various errors. three of the flags (bits 4 to 6) are valid only in uart mode. the receive buffer full flag (bit 1) is cleared to 0 when the receive buffer register is read. if there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer reg- ister, and the receive buffer full flag is set. a write to the serial i/o1 status register clears all the error flags oe, pe, fe, and se (bit 3 to bit 6, respectively). writing 0 to the serial i/o1 enable bit sioe (bit 7 of the serial i/o1 control register) also clears all the status flags, including the error flags. bits 0 to 6 of the serial i/o1 status register are initialized to 0 at reset, but if the transmit enable bit (bit 4) of the serial i/o1 control register has been set to 1 , the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become 1 . serial i/o1 control register (siocon)] 001a 16 the serial i/o1 control register consists of eight control bits for the serial i/o1 function. [uart control register (uartcon)] 001b 16 the uart control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial i/o is selected and set the data format of an data transfer and one bit (bit 4) which is al- ways valid and sets the output structure of the p2 5 /t x d pin. [baud rate generator (brg)] 001c 16 the baud rate generator determines the baud rate for serial trans- fer. the baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate genera- tor. note when using the serial i/o1, clear the i 2 c-bus interface enable bit to 0 or the scl/sda pin selection bit to 0 . tsc=0 tbe=1 rbf=0 tbe=0 tbe=0 rbf=1 rbf=1 st d 0 d 1 sp d 0 d 1 st sp tbe=1 tsc=1 st d 0 d 1 sp d 0 d 1 st sp transmit or receive clock transmit buffer write signal generated at 2nd bit in 2-stop-bit mode 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) 1: error flag detection occurs at the same time that the rbf flag becomes 1 (at 1st stop bit, during reception). 2: as the transmit interrupt (ti), when either the tbe or tsc flag becomes 1 , can be selected to occur depending on the setting of the transmit interrupt source selection bit (tic) of the serial i/o1 control register. 3: the receive interrupt (ri) is set when the rbf flag becomes 1 . 4: after data is written to the transmit buffer when tsc=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to tsc=0. notes serial output t x d serial input r x d receive buffer read signal
feb 18, 2005 page 23 of 85 rej03b0122-0101 7512 group fig. 21 structure of serial i/o1 control registers b7 b7 transmit buffer empty flag (tbe) 0: buffer full 1: buffer empty receive buffer full flag (rbf) 0: buffer empty 1: buffer full transmit shift completion flag (tsc) 0: transmit shift in progress 1: transmit shift completed overrun error flag (oe) 0: no error 1: overrun error parity error flag (pe) 0: no error 1: parity error framing error flag (fe) 0: no error 1: framing error summing error flag (se) 0: (oe) u (pe) u (fe)=0 1: (oe) u (pe) u (fe)=1 not used (returns 1 when read) serial i/o1 status register serial i/o1 control register b0 b0 brg count source selection bit (css) 0: f(x in ) 1: f(x in )/4 serial i/o1 synchronous clock selection bit (scs) 0: brg output divided by 4 when clock synchronous serial i/o1 is selected, brg output divided by 16 when uart is selected. 1: external clock input when clock synchronous serial i/o1 is selected, external clock input divided by 16 when uart is selected. s rdy1 output enable bit (srdy) 0: p2 7 pin operates as ordinary i/o pin 1: p2 7 pin operates as s rdy1 output pin transmit interrupt source selection bit (tic) 0: interrupt when transmit buffer has emptied 1: interrupt when transmit shift operation is completed transmit enable bit (te) 0: transmit disabled 1: transmit enabled receive enable bit (re) 0: receive disabled 1: receive enabled serial i/o1 mode selection bit (siom) 0: clock asynchronous (uart) serial i/o 1: clock synchronous serial i/o serial i/o1 enable bit (sioe) 0: serial i/o1 disabled (pins p2 4 to p2 7 operate as ordinary i/o pins) 1: serial i/o1 enabled (pins p2 4 to p2 7 operate as serial i/o1 pins) b7 uart control register character length selection bit (chas) 0: 8 bits 1: 7 bits parity enable bit (pare) 0: parity checking disabled 1: parity checking enabled parity selection bit (pars) 0: even parity 1: odd parity stop bit length selection bit (stps) 0: 1 stop bit 1: 2 stop bits p2 5 /t x d p-channel output disable bit (poff) 0: cmos output (in output mode) 1: n-channel open drain output (in output mode) not used (return 1 when read) b0 (siosts : address 0019 16 ) (siocon : address 001a 16 ) (uartcon : address 001b 16 ) notes when setting the transmit enable bit to "1", the serial i/o1 transmit interrupt request bit is automatically set to "1". when not requiring the interrupt occurrence synchronized with the transmission en- abled, take the following sequence. (1) set the serial i/o1 transmit interrupt enable bit to 0 (dis- abled). (2) set the transmit enable bit to "1". (3) set the serial i/o1 transmit interrupt request bit to 0 after 1 or more instructions have been executed. (4) set the serial i/o1 transmit interrupt enable bit to 1 (en- abled).
feb 18, 2005 page 24 of 85 rej03b0122-0101 7512 group serial i/o2 the serial i/o2 can be operated only as the clock synchronous type. as a synchronous clock for serial transfer, either internal clock or external clock can be selected by the serial i/o2 synchronous clock selection bit (b6) of serial i/o2 control register 1. the internal clock incorporates a dedicated divider and permits selecting 6 types of clock by the internal synchronous clock selec- tion bits (b2, b1, b0) of serial i/o2 control register 1. regarding s out2 and s clk2 being output pins, either cmos output format or n-channel open-drain output format can be selected by the p0 1 /s out2 , p0 2 /s clk2 p-channel output disable bit (b7) of serial i/o2 control register 1. when the internal clock has been selected, a transfer starts by a write signal to the serial i/o2 register (address 0017 16 ). after comple- tion of data transfer, the level of the s out2 pin goes to high imped- ance automatically but bit 7 of the serial i/o2 control register 2 is not set to "1" automatically. when the external clock has been selected, the contents of the serial i/o2 register is continuously sifted while transfer clocks are input. accordingly, control the clock externally. note that the s out2 pin does not go to high impedance after completion of data trans- fer. to cause the s out2 pin to go to high impedance in the case where the external clock is selected, set bit 7 of the serial i/o2 control register 2 to "1" when s clk2 is "h" after completion of data transfer. after the next data transfer is started (the transfer clock falls), bit 7 of the serial i/o2 control register 2 is set to "0" and the s out2 pin is put into the active state. when the number of bits (1 to 8 bits) selected by the optional trans- fer bit is transferred regardless of the internal clock to external clock, the serial i/o2 transmission/reception completion flag (note) is set to "1" and the interrupt request bit is set to "1". the serial i/o2 transmission/reception completion flag is not automatically set to "0", even if the next transmission starts. in case of a fractional num- ber of bits less than 8 bits as the last data, the received data to be stored in the serial i/o2 register becomes a fractional number of bits close to msb if the transfer direction selection bit of serial i/o2 control register 1 is lsb first, or a fractional number of bits close to lsb if the said bit is msb first. for the remaining bits, the previ- ously received data is shifted. at transmit operation using the clock synchronous serial i/o, the s cmp2 signal can be output by comparing the state of the transmit pin s out2 with the state of the receive pin s in2 in synchronization with a rise of the transfer clock. if the output level of the s out2 pin is equal to the input level to the s in2 pin, "l" is output from the s cmp2 pin. if not, "h" is output. at this time, an int 2 interrupt request can also be generated. select a valid edge by bit 2 of the interrupt edge selection register (address 003a 16 ). note: after reset is released, the serial i/o2 transmission/reception completion flag is undefined. after the initial setting of serial i/o2 is completed, set this flag to "0". [serial i/o2 control registers 1, 2] sio2con1 / sio2con2 the serial i/o2 control registers 1 and 2 are containing various se- lection bits for serial i/o2 control as shown in figure 22. fig. 22 structure of serial i/o2 control registers 1, 2 serial i/o2 control register 1 (sio2con1 : address 0015 16 ) serial i/o2 control register 2 (sio2con2 : address 0016 16 ) b7 b7 b0 optional transfer bits b2 b1 b0 0 0 0: 1 bit 0 0 1: 2 bit 0 1 0: 3 bit 0 1 1: 4 bit 1 0 0: 5 bit 1 0 1: 6 bit 1 1 0: 7 bit 1 1 1: 8 bit not used ( returns "0" when read) serial i/o2 transmission reception completion flag 0: transmission/reception not completed 1: transmission/reception completed serial i/o2 i/o comparison signal control bit 0: p4 3 i/o 1: s cmp2 output s out2 pin control bit (p0 1 ) 0: output active 1: output high-impedance internal synchronous clock selection bits b2 b1 b0 0 0 0: f(x in )/8 (f(x cin )/8 in low-speed mode) 0 0 1: f(x in )/16 (f(x cin )/16 in low-speed mode) 0 1 0: f(x in )/32 (f(x cin )/32 in low-speed mode) 0 1 1: f(x in )/64 (f(x cin )/64 in low-speed mode) 1 1 0: f(x in )/128 f(x cin )/128 in low-speed mode) 1 1 1: f(x in )/256 (f(x cin )/256 in low-speed mode) serial i/o2 port selection bit 0: i/o port 1: s out2 ,s clk2 output pin s rdy2 output enable bit 0: p0 3 pin is norma l i/o pin 1: p0 3 pin is s rdy2 output pin transfer direction selection bit 0: lsb first 1: msb first serial i/o2 synchronous clock selection bit 0: external clock 1: internal clock p0 1 /s out2 , p0 2 /s clk2 p-channel output disable bit 0: cmos output (in output mode) 1: n-channel open-drain output (in output mode ) b0
feb 18, 2005 page 25 of 85 rej03b0122-0101 7512 group fig. 23 block diagram of serial i/o2 fig. 24 timing chart of serial i/o2 x in "1" "0" "0" "1" "0" "1" s rdy2 s clk2 "0" "1" 1/8 1/16 1/32 1/64 1/128 1/256 "1" "0" x cin "10" "00" "01" data bus serial i/o2 interrupt request serial i/o2 port selection bit serial i/o counter 2 (3) serial i/o2 register (8) synchronous circuit serial i/o2 port selection bit serial i/o2 synchronous clock selection bit s rdy2 output enable bit external clock internal synchronous clock selection bit divider optional transfer bits (3) p0 2 /s clk2 p0 1 /s out2 p0 0 /s in2 p0 2 latch p0 1 latch p0 3 latch p0 3 /s rdy2 p4 3 /s cmp2 /int 2 serial i/o2 i/o comparison signal control bit p4 3 latch q d main clock division ratio selection bits (note) note: either high-speed, middle-speed or low-speed mode is selected by bits 6 and 7 of cpu mode register. d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 transfer clock (note 1) serial i/o2 output s out2 serial i/o2 input s in2 receive enable signal s rdy2 write-in signal to serial i/o2 register (note 2) serial i/o2 interrupt request bit set . 1: when the internal clock is selected as a transfer clock, the f(x in ) clock division (f(x cin ) in low-speed mode) can be selected by setting bits 0 to 2 of serial i/o2 control register 1. 2: when the internal clock is selected as a transfer clock, the s cout2 pin has high impedance after transfer completion. notes
feb 18, 2005 page 26 of 85 rej03b0122-0101 7512 group fig. 25 s cmp2 output operation s clk2 s in2 s out2 s cmp2 judgement of i/o data comparison
feb 18, 2005 page 27 of 85 rej03b0122-0101 7512 group function in conformity with philips i 2 c-bus standard: 10-bit addressing format 7-bit addressing format high-speed clock mode standard clock mode in conformity with philips i 2 c-bus standard: master transmission master reception slave transmission slave reception 16.1 khz to 400 khz (at = 4 mhz) table 7 multi-master i 2 c-bus interface functions item format communication mode system clock = f(x in )/2 (high-speed mode) = f(x in )/8 (middle-speed mode) multi-master i 2 c-bus interface the multi-master i 2 c-bus interface is a serial communications cir- cuit, conforming to the philips i 2 c-bus data transfer format. this interface, offering both arbitration lost detection and a synchronous functions, is useful for the multi-master serial communications. figure 26 shows a block diagram of the multi-master i 2 c-bus in- terface and table 7 lists the multi-master i 2 c-bus interface functions. this multi-master i 2 c-bus interface consists of the i 2 c address register, the i 2 c data shift register, the i 2 c clock control register, the i 2 c control register, the i 2 c status register, the i 2 c start/stop condition control register and other control circuits. when using the multi-master i 2 c-bus interface, set 1 mhz or more to . note: renesas technology corporation assumes no responsibility for in- fringement of any third-party s rights or originating in the use of the connection control function between the i 2 c-bus interface and the ports scl 1 , scl 2 , sda 1 and sda 2 with the bit 6 of i 2 c control regis- ter (002e 16 ). fig. 26 block diagram of multi-master i 2 c-bus interface ? : purchase of renesas technology corporation's i 2 c components conveys a license under the philips i 2 c patent rights to use these components an i 2 c system , provided that the system conforms to the i 2 c standard specification as defined by philips. scl clock frequency i 2 c address register b7 b0 sad6 sad5 sad4 sad3 sad2 sad1 sad0 rwb noise elimination circuit address comparator b7 i 2 c data shift register b0 data control circuit system clock ( ) interrupt generating circuit interrupt request signal (iicirq) b7 trx bb pin aas ad0 lrb b0 s1 b7 b0 tiss 10bit sad als bc2 bc1 bc0 bit counter bb circuit clock control circuit noise elimination circuit b7 b0 ack ack bit fast mode ccr4 ccr3 ccr2 ccr1 ccr0 internal data bus clock division s2 s0d al circuit es0 sis i 2 c start/stop condition control register sip ssc4 ssc3 ssc2 ssc1 ssc0 i 2 c clock control register i 2 c status register s2d tsel s1d i c control register 2 serial data (sda) serial clock (scl) al mst s0 aa aa aa aa a a b7 b0 acs web tof tom s3 scf i 2 c additional register operation status selection
feb 18, 2005 page 28 of 85 rej03b0122-0101 7512 group [i 2 c data shift register (s0)] 002b 16 the i 2 c data shift register (s0 : address 002b 16 ) is an 8-bit shift register to store receive data and write transmit data. when transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the scl clock, and each time one-bit data is output, the data of this register are shifted by one bit to the left. when data is received, it is input to this register from bit 0 in synchronization with the scl clock, and each time one-bit data is input, the data of this register are shifted by one bit to the left. the minimum 2 machine cycles are required from the rising of the scl clock until input to this register. the i 2 c data shift register is in a write enable status only when the i 2 c-bus interface enable bit (es0 bit : bit 3 of address 002e 16 ) of the i 2 c control register is 1 . the bit counter is reset by a write in- struction to the i 2 c data shift register. when both the es0 bit and the mst bit of the i 2 c status register (address 002d 16 ) are 1 , the scl is output by a write instruction to the i 2 c data shift register. reading data from the i 2 c data shift register is always enabled re- gardless of the es0 bit value. [i 2 c address register (s0d)] 002c 16 the i 2 c address register (address 002c 16 ) consists of a 7-bit slave address and a read/write bit. in the addressing mode, the slave address written in this register is compared with the address data to be received immediately after the start condition is de- tected. ?it 0: read/write bit (rwb) this is not used in the 7-bit addressing mode. in the 10-bit ad- dressing mode, the first address data to be received is compared with the contents (sad6 to sad0 + rwb) of the i 2 c address reg- ister. the rwb bit is cleared to 0 automatically when the stop condi- tion is detected. ?its 1 to 7: slave address (sad0?ad6) these bits store slave addresses. regardless of the 7-bit address- ing mode or the 10-bit addressing mode, the address data transmitted from the master is compared with these bit's contents. fig. 27 structure of i 2 c address register sad6 sad5 sad4 sad3 sad2 sad1 sad0 rwb slave address i 2 c address register (s0d: address 002c 16 ) read/write bit b7 b0
feb 18, 2005 page 29 of 85 rej03b0122-0101 7512 group table 8 set values of i 2 c clock control register and scl frequency fig. 28 structure of i 2 c clock control register scl frequency (at = 4 mhz, unit : khz) setting value of ccr4 ccr0 standard clock mode setting disabled setting disabled setting disabled high-speed clock mode ccr4 0 0 0 0 0 0 0 1 1 1 ccr3 0 0 0 0 0 0 0 1 1 1 ccr2 0 0 0 0 1 1 1 1 1 1 ccr1 0 0 1 1 0 0 1 0 1 1 ccr0 0 1 0 1 0 1 0 1 0 1 setting disabled setting disabled setting disabled 34.5 33.3 32.3 100 83.3 333 250 400 (note 3) 166 (note 2) (note 2) [i 2 c clock control register (s2)] 002f 16 the i 2 c clock control register (address 002f 16 ) is used to set ack control, scl mode and scl frequency. ?its 0 to 4: scl frequency control bits (ccr0?cr4) these bits control the scl frequency. refer to table 8. ?it 5: scl mode specification bit (fast mode) this bit specifies the scl mode. when this bit is set to 0 , the standard clock mode is selected. when the bit is set to 1 , the high-speed clock mode is selected. when connecting the bus of the high-speed mode i 2 c bus stan- dard (maximum 400 kbits/s), use 8 mhz or more oscillation frequency f(x in ) and 2 division clock. ?it 6: ack bit (ack bit) this bit sets the sda status when an ack clock ? is generated. when this bit is set to 0 , the ack return mode is selected and sda goes to l at the occurrence of an ack clock. when the bit is set to 1 , the ack non-return mode is selected. the sda is held in the h status at the occurrence of an ack clock. however, when the slave address agree with the address data in the reception of address data at ack bit = 0 , the sda is auto- matically made l (ack is returned). if there is a disagreement between the slave address and the address data, the sda is auto- matically made h (ack is not returned). ? ack clock: clock for acknowledgment ?it 7: ack clock bit (ack) this bit specifies the mode of acknowledgment which is an ac- knowledgment response of data transfer. when this bit is set to 0 , the no ack clock mode is selected. in this case, no ack clock occurs after data transmission. when the bit is set to 1 , the ack clock mode is selected and the master generates an ack clock each completion of each 1-byte data transfer. the device for transmitting address data and control data releases the sda at the occurrence of an ack clock (makes sda h ) and receives the ack bit generated by the data receiving device. note: do not write data into the i 2 c clock control register during transfer. if data is written during transfer, the i 2 c clock generator is reset, so that data cannot be transferred normally. 500/ccr value (note 3) 1000/ccr value (note 3) 17.2 16.6 16.1 notes 1: duty of scl clock output is 50 %. the duty becomes 35 to 45 % only when the high-speed clock mode is selected and ccr value = 5 (400 khz, at = 4 mhz). h duration of the clock fluctuates from 4 to +2 machine cycles in the standard clock mode, and fluctuates from 2 to +2 machine cycles in the high-speed clock mode. in the case of negative fluctuation, the frequency does not increase because l duration is extended instead of h duration reduction. these are value when scl clock synchronization by the syn- chronous function is not performed. ccr value is the decimal notation value of the scl frequency control bits ccr4 to ccr0. 2: each value of scl frequency exceeds the limit at = 4 mhz or more. when using these setting value, use of 4 mhz or less. 3: the data formula of scl frequency is described below: /(8 ? ccr value) standard clock mode /(4 ? ccr value) high-speed clock mode (ccr value 5) /(2 ? ccr value) high-speed clock mode (ccr value = 5) do not set 0 to 2 as ccr value regardless of frequency. set 100 khz (max.) in the standard clock mode and 400 khz (max.) in the high-speed clock mode to the scl frequency by setting the scl frequency control bits ccr4 to ccr0. ack ack bit fast mode ccr4 ccr3 ccr2 ccr1 ccr0 i 2 c clock control register (s2 : address 002f 16 ) b7 b0 scl frequency control bits refer to table 8. scl mode specification bit 0 : standard clock mode 1 : high-speed clock mode ack bit 0 : ack is returned. 1 : ack is not returned. ack clock bit 0 : no ack clock 1 : ack clock
feb 18, 2005 page 30 of 85 rej03b0122-0101 7512 group fig. 30 structure of i 2 c control register [i 2 c control register (s1d)] 002e 16 the i 2 c control register (address 002e 16 ) controls data communi- cation format. ?its 0 to 2: bit counter (bc0?c2) these bits decide the number of bits for the next 1-byte data to be transmitted. the i 2 c interrupt request signal occurs immediately after the number of count specified with these bits (ack clock is added to the number of count when ack clock is selected by ack clock bit (bit 7 of address 002f 16 )) have been transferred, and bc0 to bc2 are returned to 000 2 . also when a start condition is received, these bits become 000 2 and the address data is always transmitted and received in 8 bits. ?it 3: i 2 c interface enable bit (es0) this bit enables to use the multi-master i 2 c-bus interface. when this bit is set to 0 , the use disable status is provided, so that the sda and the scl become high-impedance. when the bit is set to 1 , use of the interface is enabled. when es0 = 0 , the following is performed. pin = 1 , bb = 0 and al = 0 are set (which are bits of the i 2 c status register at address 002d 16 ). writing data to the i 2 c data shift register (address 002b 16 ) is dis- abled. ?it 4: data format selection bit (als) this bit decides whether or not to recognize slave addresses. when this bit is set to 0 , the addressing format is selected, so that address data is recognized. when a match is found between a slave address and address data as a result of comparison or when a general call (refer to i 2 c status register , bit 1) is re- ceived, transfer processing can be performed. when this bit is set to 1 , the free data format is selected, so that slave addresses are not recognized. ?it 5: addressing format selection bit (10bit sad) this bit selects a slave address specification format. when this bit is set to 0 , the 7-bit addressing format is selected. in this case, only the high-order 7 bits (slave address) of the i 2 c address regis- ter (address 002c 16 ) are compared with address data. when this bit is set to 1 , the 10-bit addressing format is selected, and all the bits of the i 2 c address register are compared with address data. ?it 6: sda/scl pin selection bit this bit selects the input/output pins of scl and sda of the multi- master i 2 c-bus interface. ?it 7: i 2 c-bus interface pin input level selection bit this bit selects the input level of the scl and sda pins of the multi-master i 2 c-bus interface. fig. 29 sda/scl pin selection bit b7 tiss tsel 10 bit sad als es0 bc2 bc1 bc0 b0 sda/scl pin selection bit 0 : connect to ports p2 2 , p2 3 1 : connect to ports p2 4 , p2 5 i 2 c control register (s1d : address 002e 16 ) bit counter (number of transmit/receive bits) b2 b1 b0 00 0: 8 00 1: 7 01 0: 6 01 1: 5 10 0: 4 10 1: 3 11 0: 2 11 1: 1 i 2 c-bus interface enable bit 0 : disabled 1 : enabled data format selection bit 0 : addressing format 1 : free data format addressing format selection bit 0 : 7-bit addressing format 1 : 10-bit addressing format i 2 c-bus interface pin input level selection bit 0 : cmos input 1 : smbus input scl sda multi-master i 2 c-bus interface tsel scl 1 /p2 3 scl 2 /txd/p2 5 sda 1 /p2 2 sda 2 /rxd/p2 4 tsel tsel tsel
feb 18, 2005 page 31 of 85 rej03b0122-0101 7512 group ?it 4: scl pin low hold bit (pin) this bit generates an interrupt request signal. each time 1-byte data is transmitted, the pin bit changes from 1 to 0 . at the same time, an interrupt request signal occurs to the cpu. the pin bit is set to 0 in synchronization with a falling of the last clock (in- cluding the ack clock) of an internal clock and an interrupt request signal occurs in synchronization with a falling of the pin bit. when the pin bit is 0 , the scl is kept in the 0 state and clock generation is disabled. figure 32 shows an interrupt request signal generating timing chart. the pin bit is set to 1 in one of the following conditions: executing a write instruction to the i 2 c data shift register (ad- dress 002b 16 ). (this is the only condition which the prohibition of the internal clock is released and data can be communicated ex- cept for the start condition detection.) when the es0 bit is 0 at reset when writing 1 to the pin bit by software the conditions in which the pin bit is set to 0 are shown below: immediately after completion of 1-byte data transmission (includ- ing when arbitration lost is detected) immediately after completion of 1-byte data reception in the slave reception mode, with als = 0 and immediately af- ter completion of slave address agreement or general call address reception in the slave reception mode, with als = 1 and immediately af- ter completion of address data reception ?it 5: bus busy flag (bb) this bit indicates the status of use of the bus system. when this bit is set to 0 , this bus system is not busy and a start condition can be generated. the bb flag is set/reset by the scl, sda pins input signal regardless of master/slave. this flag is set to 1 by detecting the start condition, and is set to 0 by detecting the stop condition. the condition of these detecting is set by the start/stop condition setting bits (ssc4 ssc0) of the i 2 c start/stop condition control register (address 0030 16 ). when the es0 bit of the i 2 c control register (address 002e 16 ) is 0 or reset, the bb flag is set to 0 . for the writing function to the bb flag, refer to the sections start condition generating method and stop condition gen- erating method described later. [i 2 c status register (s1)] 002d 16 the i 2 c status register (address 002d 16 ) controls the i 2 c-bus in- terface status. the low-order 4 bits are read-only bits and the high-order 4 bits can be read out and written to. set 0000 2 to the low-order 4 bits, because these bits become the reserved bits at writing. ?it 0: last receive bit (lrb) this bit stores the last bit value of received data and can also be used for ack receive confirmation. if ack is returned when an ack clock occurs, the lrb bit is set to 0 . if ack is not returned, this bit is set to 1 . except in the ack mode, the last bit value of received data is input. the state of this bit is changed from 1 to 0 by executing a write instruction to the i 2 c data shift register (address 002b 16 ). ?it 1: general call detecting flag (ad0) when the als bit is 0 , this bit is set to 1 when a general call ? whose address data is all 0 is received in the slave mode. by a general call of the master device, every slave device receives con- trol data after the general call. the ad0 bit is set to 0 by detecting the stop condition or start condition, or reset. ? general call: the master transmits the general call address 00 16 to all slaves. ?it 2: slave address comparison flag (aas) this flag indicates a comparison result of address data when the als bit is 0 . (1)in the slave receive mode, when the 7-bit addressing format is selected, this bit is set to 1 in one of the following conditions: the address data immediately after occurrence of a start condition agrees with the slave address stored in the high-or- der 7 bits of the i 2 c address register (address 002c 16 ). a general call is received. (2)in the slave receive mode, when the 10-bit addressing format is selected, this bit is set to 1 with the following condition: when the address data is compared with the i 2 c address reg- ister (8 bits consisting of slave address and rwb bit), the first bytes agree. (3)this bit is set to 0 by executing a write instruction to the i 2 c data shift register (address 002b 16 ) when es0 is set to 1 or reset. ?it 3: arbitration lost ? detecting flag (al) in the master transmission mode, when the sda is made l by any other device, arbitration is judged to have been lost, so that this bit is set to 1 . at the same time, the trx bit is set to 0 , so that immediately after transmission of the byte whose arbitration was lost is completed, the mst bit is set to 0 . the arbitration lost can be detected only in the master transmission mode. when ar- bitration is lost during slave address transmission, the trx bit is set to 0 and the reception mode is set. consequently, it becomes possible to detect the agreement of its own slave address and ad- dress data transmitted by another master device. ? arbitration lost : the status in which communication as a master is dis- abled.
feb 18, 2005 page 32 of 85 rej03b0122-0101 7512 group fig. 32 interrupt request signal generating timing fig. 31 structure of i 2 c status register ?it 6: communication mode specification bit (transfer direc- tion specification bit: trx) this bit decides a direction of transfer for data communication. when this bit is 0 , the reception mode is selected and the data of a transmitting device is received. when the bit is 1 , the transmis- sion mode is selected and address data and control data are output onto the sda in synchronization with the clock generated on the scl. this bit is set/reset by software and hardware. about set/reset by hardware is described below. this bit is set to 1 by hardware when all the following conditions are satisfied: when als is 0 in the slave reception mode or the slave transmission mode when the r/w bit reception is 1 this bit is set to 0 in one of the following conditions: when arbitration lost is detected. when a stop condition is detected. when writing 1 to this bit by software is invalid by the start condition duplication preventing function (note) . with mst = 0 and when a start condition is detected. with mst = 0 and when ack non-return is detected. at reset ?it 7: communication mode specification bit (master/slave specification bit: mst) this bit is used for master/slave specification for data communica- tion. when this bit is 0 , the slave is specified, so that a start condition and a stop condition generated by the master are re- ceived, and data communication is performed in synchronization with the clock generated by the master. when this bit is 1 , the master is specified and a start condition and a stop condition are generated. additionally, the clocks required for data communi- cation are generated on the scl. this bit is set to 0 in one of the following conditions. immediately after completion of 1-byte data transfer when arbi- tration lost is detected when a stop condition is detected. writing 1 to this bit by software is invalid by the start condi- tion duplication preventing function (note) . at reset note: start condition duplication preventing function the mst, trx, and bb bits is set to 1 at the same time after con- firming that the bb flag is 0 in the procedure of a start condition occurrence. however, when a start condition by another master device occurs and the bb flag is set to 1 immediately after the con- tents of the bb flag is confirmed, the start condition duplication preventing function makes the writing to the mst and trx bits in- valid. the duplication preventing function becomes valid from the rising of the bb flag to reception completion of slave address. scl pin iicirq b7 mst b0 i 2 c status register (s1 : address 002d 16 ) last receive bit (note) 0 : last bit = 0 1 : last bit = 1 general call detecting flag (note) 0 : no general call detected 1 : general call detected slave address comparison flag (note) 0 : address disagreement 1 : address agreement arbitration lost detecting flag (note) 0 : not detected 1 : detected scl pin low hold bit 0 : scl pin low hold 1 : scl pin low release bus busy flag 0 : bus free 1 : bus busy communication mode specification bits 00 : slave receive mode 01 : slave transmit mode 10 : master receive mode 11 : master transmit mode trx bb pin al aas ad0 lrb note: these bits and flags can be read out, but cannot be written. write 0 to these bits at writing.
feb 18, 2005 page 33 of 85 rej03b0122-0101 7512 group fig. 35 start condition detecting timing diagram start/stop condition detecting operation the start/stop condition detection operations are shown in figures 35, 36, and table 11. the start/stop condition is set by the start/stop condition set bit. the start/stop condition can be detected only when the input signal of the scl and sda pins satisfy three conditions: scl re- lease time, setup time, and hold time (see table 11). the bb flag is set to 1 by detecting the start condition and is reset to 0 by detecting the stop condition. the bb flag set/reset timing is different in the standard clock mode and the high-speed clock mode. refer to table 11, the bb flag set/ reset time. note: when a stop condition is detected in the slave mode (mst = 0), an interrupt request signal iicirq occurs to the cpu. start condition generating method when writing 1 to the mst, trx, and bb bits of the i 2 c status register (address 002d 16 ) at the same time after writing the slave address to the i 2 c data shift register (address 002b 16 ) with the condition in which the es0 bit of the i 2 c control register (address 002e 16 ) is 1 and the bb flag is 0 , a start condition occurs. after that, the bit counter becomes 000 2 and an scl for 1 byte is output. the start condition generating timing is different in the standard clock mode and the high-speed clock mode. refer to figure 33, the start condition generating timing diagram, and table 9, the start condition generating timing table. stop condition generating method when the es0 bit of the i 2 c control register (address 002e 16 ) is 1 , write 1 to the mst and trx bits, and write 0 to the bb bit of the i 2 c status register (address 002d 16 ) simultaneously. then a stop condition occurs. the stop condition generating timing is different in the standard clock mode and the high-speed clock mode. refer to figure 34, the stop condition generating timing diagram, and table 10, the stop condition generating timing table. fig. 33 start condition generating timing diagram fig. 34 stop condition generating timing diagram table 10 stop condition generating timing table item setup time hold time standard clock mode 5.0 s (20 cycles) 4.5 s (18 cycles) note: absolute time at = 4 mhz. the value in parentheses denotes the number of cycles. high-speed clock mode 3.0 s (12 cycles) 2.5 s (10 cycles) table 9 start condition generating timing table item setup time hold time standard clock mode 5.0 s (20 cycles) 5.0 s (20 cycles) note: absolute time at = 4 mhz. the value in parentheses denotes the number of cycles. high-speed clock mode 2.5 s (10 cycles) 2.5 s (10 cycles) table 11 start condition/stop condition detecting conditions note: unit : cycle number of system clock ssc value is the decimal notation value of the start/stop condi- tion set bits ssc4 to ssc0. do not set 0 or an odd number to ssc value. the value in parentheses is an example when the i 2 c start/ stop condition control register is set to 18 16 at = 4 mhz. fig. 36 stop condition detecting timing diagram scl release time standard clock mode high-speed clock mode 4 cycles (1.0 s) 2 cycles (1.0 s) 2 cycles (0.5 s) 3.5 cycles (0.875 s) ssc value + 1 2 ssc value + 1 2 ssc value 1 2 setup time hold time bb flag set/ reset time ssc value + 1 cycle (6.25 s) cycle < 4.0 s (3.125 s) cycle < 4.0 s (3.125 s) + 2 cycles (3.375 s) i 2 c status register write signal aaa hold time setup time scl sda aaa hold time setup time scl sda bb fla g aaa scl release time bb flag reset time i 2 c status register write signal aaa aaa hold time setup time scl sda aaa hold time setup time scl sda bb flag aaaa scl release time bb flag set time
feb 18, 2005 page 34 of 85 rej03b0122-0101 7512 group [i 2 c start/stop condition control register (s2d)] 0030 16 the i 2 c start/stop condition control register (address 0030 16 ) controls start/stop condition detection. bits 0 to 4: start/stop condition set bits (ssc4 ssc0) scl release time, setup time, and hold time change the detection condition by value of the main clock divide ratio selection bit and the oscillation frequency f(x in ) because these time are measured by the internal system clock. accordingly, set the proper value to the start/stop condition set bits (ssc4 to ssc0) in considered of the system clock frequency. refer to table 11. do not set 00000 2 or an odd number to the start/stop condi- tion set bit (ssc4 to ssc0). refer to table 12, the recommended set value to start/stop condition set bits (ssc4 ssc0) for each oscillation frequency. fig. 37 structure of i 2 c start/stop condition control register b7 b0 i 2 c start/stop condition control register start/stop condition set bits scl/sda interrupt pin polarity selection bit 0 : falling edge active 1 : rising edge active scl/sda interrupt pin selection bit 0 : sda valid 1 : scl valid stp/low speed mode data receiv e enable bit 0 : disable 1 : enable sis sip ssc4 ssc3 ssc2 ssc1 ssc0 (s2d : address 0030 16 ) are bit 5: scl/sda interrupt pin polarity selection bit (sip) an interrupt can occur when detecting the falling or rising edge of the scl or sda pin. this bit selects the polarity of the scl or sda pin interrupt pin. bit 6: scl/sda interrupt pin selection bit (sis) this bit selects the pin of which interrupt becomes valid between the scl pin and the sda pin. bit 7: stp/low speed mode data receive enable bit selecting this bit 1 enables i 2 c to receive the start condition ad- dress data even if the cpu is stopping or running at the low speed mode. the detecting the falling edge of the sda pin, built-in rc oscillator begins oscillation, and receive the start condition ad- dress data. after receiving the last bit of address data ( in case of ack clock bit = 1 , after receiving ack bit), scl/sda interrupt and i 2 c interrupt are requested at the same time. and then scl pin becomes low hold state as a result of becoming scl pin low hold bit 0 . during this state, it is possible to start the xin oscilla- tion. and after oscillation becomes stable, normal i 2 c operation begins. if the start condition which is not satisfied the hold time of start condition is input, scl/sda interrupt is requested. in the low-speed mode, when this bit is set to "1", scl/sda inter- rupt which occur by the rising or falling edge of scl or sda is disabled. note: when changing the setting of the scl/sda interrupt pin polarity se- lection bit, the scl/sda interrupt pin selection bit, or the i 2 c-bus interface enable bit es0, the scl/sda interrupt request bit may be set. when selecting the scl/sda interrupt source, disable the inter- rupt before the scl/sda interrupt pin polarity selection bit, the scl/ sda interrupt pin selection bit, or the i 2 c-bus interface enable bit es0 is set. reset the request bit to 0 after setting these bits, and enable the interrupt. start/stop condition control register oscillation frequency f(x in ) (mhz) note: do not set 00000 2 or an odd number to the start/stop condition set bits (ssc4 to ssc0). table 12 recommended set value to start/stop condition set bits (ssc4 ssc0) for each oscillation frequency main clock divide ratio system clock (mhz) scl release time ( s) setup time ( s) hold time ( s) 8 8 4 2 2 8 2 2 xxx11010 xxx11000 xxx00100 xxx01100 xxx01010 xxx00100 3.375 s (13.5 cycles) 3.125 s (12.5 cycles) 2.5 s (2.5 cycles) 3.25 s (6.5 cycles) 2.75 s (5.5 cycles) 2.5 s (2.5 cycles) 6.75 s (27 cycles) 6.25 s (25 cycles) 5.0 s (5 cycles) 6.5 s (13 cycles) 5.5 s (11 cycles) 5.0 s (5 cycles) 3.375 s (13.5 cycles) 3.125 s (12.5 cycles) 2.5 s (2.5 cycles) 3.25 s (6.5 cycles) 2.75 s (5.5 cycles) 2.5 s (2.5 cycles) 4 1 2 1
feb 18, 2005 page 35 of 85 rej03b0122-0101 7512 group i 2 c additional register (1) bit 0: time-out mode bit (tom) setting the time-out mode bit 1 , continuity of i 2 c-bus busy state for about 16ms (f(x in) =4mhz, high-speed mode) makes time-out flag 1 and time-out interrupt occurs. check the time- out flag to know which interrupt source of the scl/sda interrupt is occurred. when restart condition occurs in the middle of communication, the time-out timer is cleared. (2) bit 1: time-out flag (tof) time-out flag becomes 1 when the time-out state occurs. writing 1 to this bit, time-out timer is reset, and this bit is cleared 0 also. (3) i 2 c operation enable bit at wit mode (web) this bit determines multi-master i 2 c-bus interface operation at wit mode. setting this bit "0", multi-master i 2 c interface source clock is not supplied at wit mode. setting this bit "1", multi-master i 2 c interface source clock is supplied even at wit mode, and it makes possible multi-master i 2 c interface opera- tion at wit mode. do not execute stp instruction at i 2 c operation enable bit at wit mode is "1". (4) stop condition flag (scf) this flag turns to 1 , when the stop condition is generated or detected. this bit is cleared 0 at reset, or when i 2 c-bus inter- face enable bit is 0 or writing this bit 1 . this bit is available only when i 2 c-bus interface enable bit is 1 . (5) ack clock selection mode bit (acs) setting this bit "1" clears the ack bit (bit 6 of 002f 16 ) "0" and sets the ack clock bit (bit 7 of 002f 16 ) "1" automatically, when the stop condition is detected. fig. 38 i 2 c additional register b7 b0 i 2 c additional register time-out mode bit 0 : disable 1 : enable time-out flag 0 : not generated 1 : generated *writing this bit "1", this flag is cleared i 2 c operation enable bit at wit mode 0 : disable 1 : enable stop condition flag 0 : not detect stop condition 1 : detect stop condition *writing this bit "1", this flag is cleared ack clock selection mode bit 0 : disable 1 : enable not used (returns "0" when read) (s3 : address 0031 16 ) scf web acs tof tom
feb 18, 2005 page 36 of 85 rej03b0122-0101 7512 group fig. 39 address data communication format s slave address r/w a data a/a p a data 7 bits 0 1 to 8 bits 1 to 8 bits (1) a master-transmitter transnmits data to a slave-receiver s slave address r/w a data a p a data 7 bits 1 1 to 8 bits 1 to 8 bits (2) a master-receiver receives data from a slave-transmitter 7 bits 0 8 bits (3) a master-transmitter transmits data to a slave-receiver with a 10-bit address 1 to 8 bits 1 to 8 bits s r/w a slave address 1st 7 bits slave address 2nd bytes a a data data p a/a 7 bits 0 8 bits (4) a master-receiver receives data from a slave-transmitter with a 10-bit address s : start condition a : ack bit sr : restart condition p : stop condition r/w : read/write bit 7 bits 1 1 to 8 bits 1 to 8 bits s r/w a slave address 1st 7 bits slave address 2nd bytes a sr slave address 1st 7 bits r/w a data data p a aa : master to slave : slave to master aa aa a address data communication there are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. the respective address communication formats are described below. (1)7-bit addressing format to adapt the 7-bit addressing format, set the 10bit sad bit of the i 2 c control register (address 002e 16 ) to 0 . the first 7-bit address data transmitted from the master is compared with the high-order 7-bit slave address stored in the i 2 c address register (address 002c 16 ). at the time of this comparison, address com- parison of the rwb bit of the i 2 c address register (address 002c 16 ) is not performed. for the data transmission format when the 7-bit addressing format is selected, refer to figure 39, (1) and (2). (2)10-bit addressing format to adapt the 10-bit addressing format, set the 10bit sad bit of the i 2 c control register (address 002e 16 ) to 1 . an address comparison is performed between the first-byte address data transmitted from the master and the 8-bit slave address stored in the i 2 c address register (address 002c 16 ). at the time of this comparison, an address comparison between the rwb bit of the i 2 c address register (address 002c 16 ) and the r/w bit which is the last bit of the address data transmitted from the master is made. in the 10-bit addressing mode, the rwb bit which is the last bit of the address data not only specifies the direction of communication for control data, but also is pro- cessed as an address data bit. when the first-byte address data agree with the slave address, the aas bit of the i 2 c status register (address 002d 16 ) is set to 1 . after the second-byte address data is stored into the i 2 c data shift register (address 002b 16 ), perform an address com- parison between the second-byte data and the slave address by software. when the address data of the 2 bytes agree with the slave address, set the rwb bit of the i 2 c address register (address 002c 16 ) to 1 by software. this processing can make the 7-bit slave address and r/w data agree, which are re- ceived after a restart condition is detected, with the value of the i 2 c address register (address 002c 16 ). for the data trans- mission format when the 10-bit addressing format is selected, refer to figure 39, (3) and (4).
feb 18, 2005 page 37 of 85 rej03b0122-0101 7512 group example of master transmission an example of master transmission in the standard clock mode, at the scl frequency of 100 khz and in the ack return mode is shown below. (1) set a slave address in the high-order 7 bits of the i 2 c address register (address 002c 16 ) and 0 into the rwb bit. (2) set the ack return mode and scl = 100 khz by setting 85 16 in the i 2 c clock control register (address 002f 16 ). (3) set 00 16 in the i 2 c status register (address 002d 16 ) so that transmission/reception mode can become initializing condition. (4) set a communication enable status by setting 08 16 in the i 2 c control register (address 002e 16 ). (5) confirm the bus free condition by the bb flag of the i 2 c status register (address 002d 16 ). (6) set the address data of the destination of transmission in the high-order 7 bits of the i 2 c data shift register (address 002b 16 ) and set 0 in the least significant bit. (7) set f0 16 in the i 2 c status register (address 002d 16 ) to gener- ate a start condition. at this time, a scl for 1 byte and an ack clock automatically occur. (8) set transmit data in the i 2 c data shift register (address 002b 16 ). at this time, a scl and an ack clock automatically oc- cur. (9) when transmitting control data of more than 1 byte, repeat step (8). (10) set d0 16 in the i 2 c status register (address 002d 16 ) to gen- erate a stop condition if ack is not returned from slave reception side or transmission ends. example of slave reception an example of slave reception in the high-speed clock mode, at the scl frequency of 400 khz, in the ack non-return mode and using the addressing format is shown below. (1) set a slave address in the high-order 7 bits of the i 2 c address register (address 002c 16 ) and 0 in the rwb bit. (2) set the ack non-return mode and scl = 400 khz by setting 25 16 in the i 2 c clock control register (address 002f 16 ). (3) set 00 16 in the i 2 c status register (address 002d 16 ) so that transmission/reception mode can become initializing condition. (4) set a communication enable status by setting 08 16 in the i 2 c control register (address 002e 16 ). (5) when a start condition is received, an address comparison is performed. (6) when all transmitted addresses are 0 (general call): ad0 of the i 2 c status register (address 002d 16 ) is set to 1 and an interrupt request signal occurs. when the transmitted addresses agree with the address set in (1): ass of the i 2 c status register (address 002d 16 ) is set to 1 and an interrupt request signal occurs. in the cases other than the above ad0 and aas of the i 2 c status register (address 002d 16 ) are set to 0 and no inter rupt request signal occurs. (7) set dummy data in the i 2 c data shift register (address 002b 16 ). (8) when receiving control data of more than 1 byte, repeat step (7). (9) when a stop condition is detected, the communication ends.
feb 18, 2005 page 38 of 85 rej03b0122-0101 7512 group (2) start condition generating procedure using multi-master 1. procedure example (the necessary conditions of the generat- ing procedure are described as the following 2 to 5. : : lda (taking out of slave address value) sei (interrupt disabled) bbs 5, s1, busbusy (bb flag confirming and branch process) busfree: sta s0 (writing of slave address value) ldm #$f0, s1 (trigger of start condition generating) cli (interrupt enabled) : : busbusy: cli (interrupt enabled) : : 2. use branch on bit set of bbs 5, $002d, for the bb flag confirming and branch process. 3. use sta $2b, stx $2b or sty $2b of the zero page ad- dressing instruction for writing the slave address value to the i 2 c data shift register. 4. execute the branch instruction of above 2 and the store instruc- tion of above 3 continuously shown the above procedure example. 5. disable interrupts during the following three process steps: bb flag confirming writing of slave address value trigger of start condition generating when the condition of the bb flag is bus busy, enable interrupts immediately. (3) restart condition generating procedure 1. procedure example (the necessary conditions of the generat- ing procedure are described as the following 2 to 4.) execute the following procedure when the pin bit is 0 . : : ldm #$00, s1 (select slave receive mode) lda (taking out of slave address value) sei (interrupt disabled) sta s0 (writing of slave address value) ldm #$f0, s1 ( trigger of restart condition generating ) cli (interrupt enabled) : : 2. select the slave receive mode when the pin bit is 0 . do not write 1 to the pin bit. neither 0 nor 1 is specified for the writing to the bb bit. the trx bit becomes 0 and the sda pin is released. 3. the scl pin is released by writing the slave address value to the i 2 c data shift register. 4. disable interrupts during the following two process steps: writing of slave address value trigger of restart condition generating (4) writing to i 2 c status register do not execute an instruction to set the pin bit to 1 from 0 and an instruction to set the mst and trx bits to 0 from 1 simulta- neously. it is because it may enter the state that the scl pin is released and the sda pin is released after about one machine cycle. do not execute an instruction to set the mst and trx bits to 0 from 1 simultaneously when the pin bit is 1 . it is because it may become the same as above. (5) process of after stop condition generating do not write data in the i 2 c data shift register s0 and the i 2 c sta- tus register s1 until the bus busy flag bb becomes 0 after generating the stop condition in the master mode. it is because the stop condition waveform might not be normally generated. reading to the above registers do not have the problem. precautions when using multi-master i 2 c-bus interface (1) read-modify-write instruction the precautions when the read-modify-write instruction such as seb, clb etc. is executed for each register of the multi-master i 2 c-bus interface are described below. i 2 c data shift register (s0: address 002b 16 ) when executing the read-modify-write instruction for this regis- ter during transfer, data may become a value not intended. i 2 c address register (s0d: address 002c 16 ) when the read-modify-write instruction is executed for this regis- ter at detecting the stop condition, data may become a value not intended. it is because h/w changes the read/write bit (rwb) at the above timing. i 2 c status register (s1: address 002d 16 ) do not execute the read-modify-write instruction for this register because all bits of this register are changed by h/w. i 2 c control register (s1d: address 002e 16 ) when the read-modify-write instruction is executed for this regis- ter at detecting the start condition or at completing the byte transfer, data may become a value not intended. because h/w changes the bit counter (bc0-bc2) at the above timing. i 2 c clock control register (s2: address 002f 16 ) the read-modify-write instruction can be executed for this regis- ter. i 2 c start/stop condition control register (s2d: address 0030 16 ) the read-modify-write instruction can be executed for this regis- ter.
feb 18, 2005 page 39 of 85 rej03b0122-0101 7512 group pulse width modulation (pwm) the 7512 group has a pwm function with an 8-bit resolution, based on a signal that is the clock input x in or that clock input di- vided by 2. data setting the pwm output pin also functions as port p4 4 or port p0 7 . the pwm output pin can be selected to either port p4 4 /pwm 0 or port p0 7 /pwm 1 by bit 2 (pwm output pin selectoin bit) of the pwm control register. set the pwm period by the pwm prescaler, and set the h term of output pulse by the pwm register. if the value in the pwm prescaler is n and the value in the pwm register is m (where n = 0 to 255 and m = 0 to 255) : pwm period = 255 ? (n+1) / f(x in ) = 63.75 ? (n+1) s (when f(x in ) = 4 mhz) output pulse h term = pwm period ? m / 255 = 0.25 ? (n+1) ? m s (when f(x in ) = 4 mhz) fig. 40 timing of pwm period fig. 41 block diagram of pwm function pwm operation when bit 0 (pwm enable bit) of the pwm control register is set to 1 , operation starts by initializing the pwm output circuit, and pulses are output starting at an h . if the pwm register or pwm prescaler is updated during pwm output, the pulses will change in the cycle after the one in which the change was made. 63.75 ? m ? (n+1) 255 t = [63.75 ? (n+1)] pwm output m: contents of pwm register n : contents of pwm prescaler t : pwm period (when f(x in ) = 4 mhz s s pwm prescaler pre-latch pwm register pre-latch transfer control circuit pwm prescaler latch pwm prescaler pwm register 1/2 x in pwm enable bit pwm register latch data bus "1" "0" count source selection bit port p4 4 latch portp4 4 /pwm 0 portp0 7 /pwm 1 pwm output pin selection bit port p0 7 latch
feb 18, 2005 page 40 of 85 rej03b0122-0101 7512 group fig. 42 structure of pwm control register fig. 43 pwm output timing when pwm register or pwm prescaler is changed p w m c o n t r o l r e g i s t e r ( p w m c o n : a d d r e s s 0 0 1 d 1 6 ) p w m f u n c t i o n e n a b l e b i t c o u n t s o u r c e s e l e c t i o n b i t p w m o u t p u t p i n s e l e c t i o n b i t n o t u s e d ( r e t u r n 0 w h e n r e a d ) b7 b 0 0 : p w m d i s a b l e d 1 : p w m e n a b l e d 0 : f ( x i n ) 1 : f ( x i n ) / 2 0 : p 4 4 1 : p 0 7 abc b t c t2 = pwm output pwm register write signal pwm prescaler write signal (changes h term from a to b .) (changes pwm period from t to t2 .) when the contents of the pwm register or pwm prescaler have changed, the pwm output will change from the next period after the change. t t t2 note the pwm starts after the pwm enable bit is set to enable and "l" level is output from the pwm pin. the length of this "l" level output is as follows: sec (count source selection bit = 0, where n is the value set in the prescaler) sec (count source selection bit = 1, where n is the value set in the prescaler) n+1 2 f(x in ) n+1 f(x in )
feb 18, 2005 page 41 of 85 rej03b0122-0101 7512 group a/d converter [ad conversion registers (adl, adh)] 0035 16 , 0036 16 the ad conversion registers are read-only registers that store the result of an a/d conversion. do not read these registers during an a/d conversion [ad control register (adcon)] 0034 16 the ad control register controls the a/d conversion process. bits 0 to 2 select a specific analog input pin. bit 4 indicates the completion of an a/d conversion. the value of this bit remains at 0 during an a/d conversion and changes to 1 when an a/d con- version ends. writing 0 to this bit starts the a/d conversion. comparison voltage generator the comparison voltage generator divides the voltage between av ss and v ref into 1024 and outputs the divided voltages. channel selector the channel selector selects one of ports p0 4 /an 8 to p0 7 /an 11 and ports p3 0 /an 0 to p3 5 /an 5 and inputs the voltage to the com- parator. comparator and control circuit the comparator and control circuit compare an analog input volt- age with the comparison voltage, and the result is stored in the ad conversion registers. when an a/d conversion is completed, the control circuit sets the a/d conversion completion bit and the a/d interrupt request bit to 1 . note that because the comparator consists of a capacitor cou- pling, set f(x in ) to 500 khz or more during an a/d conversion. when the a/d converter is operated at low-speed mode, f(x in ) and f(x cin ) do not have the lower limit of frequency, because of the a/d converter has a built-in self-oscillation circuit. easy thermal sensor easy thermal sensor detects voltage change of p-n diordes by thermal difference using a/d converter. setting the analog input pin selection additional bit "0" and analog input pin selection bits "111" starts a/d conversion of thermal sensor. fig. 44 structure of ad control register fig. 45 structure of ad conversion registers fig. 46 block diagram of a/d converter aa aa aa aa channel selector a/d control circuit ad conversion low-order register resistor ladder v ref av ss comparator a/d interrupt request b7 b0 4 10 p3 0 /an 0 p3 1 /an 1 p3 2 /an 2 p3 3 /an 3 p3 4 /an 4 data bus ad control register (address 0034 16 ) ad conversion high-order register (address 0036 16 ) (address 0035 16 ) p3 5 /an 5 p0 4 /an 8 p0 5 /an 9 analog input pin selection additional bit p0 6 /an 10 p0 7 /an 11 thermal sensor select signal 10-bit reading (read address 0036 16 before 0035 16 ) (address 0036 16 ) (address 0035 16 ) 8-bit reading (read only address 0035 16 ) (address 0035 16 ) b8 b7 b6 b5 b4 b3 b2 b1 b0 b7 b0 b9 b7 b0 note : the high-order 6 bits of address 0036 16 become 0 at reading. b9 b8 b7 b6 b5 b4 b3 b2 b7 b0 ad control register (adcon : address 0034 16 ) analog input pin analog input pin selection additional bit* selection bits 0 0 0 0: p3 0 /an 0 0 0 0 1: p3 1 /an 1 0 0 1 0: p3 2 /an 2 0 0 1 1: p3 3 /an 3 0 1 0 0: p3 4 /an 4 0 1 0 1: p3 5 /an 5 0 1 1 1: thermal sensor 1 0 0 0: p0 4 /an 8 1 0 0 1: p0 5 /an 9 1 0 1 0: p0 6 /an 10 1 0 1 1: p0 7 /an 11 not used (returns 0 when read) a/d conversion completion bit 0: conversion in progress 1: conversion completed not used (returns 0 when read) *bit 0 of misrg2 (0037 16 ) b7 b0
feb 18, 2005 page 42 of 85 rej03b0122-0101 7512 group fig. 47 block diagram of current integrator xx0 001 011 101 xx0 001 011 101 edge detect calibration control signal 125ms over flow charge counter latch discharge counter latch charge counter discharge counter 125ms timer x cin data bus current integrate control register xx0 : current integrate mode 001 : zero calibration 011 : full calibration for discharge 101 : full calibration for charge b2 b1 b0 current integrate interrupt isens0 isens1 calibration current selection bit 1.75v integrator v-i convertor 0.05v 0.10v 0.75v 1.00v 1.50v integrator coefficient selection bit ad conversion complete signal current integrate /ad converter interrupt source bit current integrator current integrator integrates the current which flows through sense resistor connected between isens0 pin and isens1 pin. the current between sense resistor makes electrical potential dif- ference between isens0 pin and isens1 pin, and it is integrated by the built-in integrator. the output of integrator is connected to comparator, and the integrator and comparator measures about 1ma current in case of using 10 m ? sense register. and charge/ discharge counter counts how many times the integrator over- flows. setting the current integrate enable bit "1", the current integrator starts the operation. current integrate mode setting the current integrate mode bit "0", input of the v-i con- verter is connected to the isens1 pin and isens0 pin, and the current integrator measures the electrical potential difference be- tween isens1 pin and isens0 pin. the input voltage between isens1 and isens0 is converted to current by v-i converter, and input to the integrator. the output of the integrator is connected to the comparator. the integrator integrates input voltage between isens1 pin and isens0 pin. and when output of the integrator amounts to com- pared voltage, output of the comparator rises "h", and charge(discharge) counter is increased 1 count. and at the same time, electric charge of the integrator's capacitor is discharged, then the integrator starts next integration. charge(dischrage) counter is counting the number of the times "h" output of the com- parator during integration period(125msec), and at the end of the period, charge (discharge)counter is latched onto charge(discharge) counter latch. then charge(discharge) counter is cleared "0", and starts new count. at the end of the period, cur- rent integrate interrupt occurs also. the current integrator has 2 set of comparator and counter for dis- charge and charge, and only discharge counter counts up in discharge state, and only charge counter counts up in charge state. the integrator and comparator are designed to sense ap- proximate 1ma current, then 1 count of counter means approximate 1ma. therefore reading the value of counter latch means measuring the total current which flows the sense resistor during integrate period(125msec).
feb 18, 2005 page 43 of 85 rej03b0122-0101 7512 group fig. 48 current integrator timing diagram v-i converter input isens1 input 0v integrate period 125ms integrate period 125ms charge counter charge counter latch discharge counter count value of last integrate period count value of last integrate period m m 0 n 1 2 3 1 2 3 0 n n-1 n-2 n-3 n-4 n-5 n-6 1.75v 1.25v 0.75v discharge counter latch integrator output discharge comparator charge comparator v-i converter input isens1 input discharge counter integrator output discharge comparator discharge signal for the integrator 1.75v 1.25v 0.75v n-3 n-2 n-1 0v
feb 18, 2005 page 44 of 85 rej03b0122-0101 7512 group fig. 49 calibration timing 0 the result of calibration (discharge state) v-i converter input counter latch content flag current integrate mode bit and calibration selection bit integrate period 125ms vinf input set the current integrate mode bit "1" and calibration selection bit "00" integrator output discharge comparator discharge counter latch discharge counter the result of calibration (zero) integrate period 125ms full calibration for discharge zero calibration discharge counter discharge signal for integrator discharge comparator v-i converter input integrator output 12 34 xx0 001 011 xx0 set the calibration selection bit "01" set the current integrate mode bit "0" 1.75v 1.25v 0.75v n-1 n 0 3 4 0 123456 counter value of previous integrate period (zero calibration) calibration mode (calibration for discharge state) calibration mode integrate period 125ms integrate period 125ms integrate period 125ms integrate period 125ms integrate period 125ms 0v 0v calibration mode setting the current integrate mode bit 1 , the input of v-i converter is connected to internal av ss or 0.05v or 0.1v for reference volt- age. when the calibration selection bit is 00 , both of plus and minus input of v-i converter are connected to internal av ss , and zero calibration is operated. when the calibration selection bit is 01 , plus input of v-i converter is connected to internal 0.05v or 0.1v reference voltage, and minus input of v-i converter is con- nected to internal av ss , and then full calibration for discharge state is operated. when the calibration selection bit is 10 , plus input of v-i converter is connected to internal av ss , and minus input of v-i converter is connected to 0.05v or 0.1v reference voltage, and the full calibration for charge state is operated.
feb 18, 2005 page 45 of 85 rej03b0122-0101 7512 group fig. 50 current integrator registers the calibration starts current integration for 125 ms, after dis- charging electric charge which remain in integrator's capacitor. after finished calibration period, value of the discharge(charge) counter is latched to discharge(charge) counter latch. at this time the current integrate interrupt occurs. which interrupt has oc- curred current integrate interrupt for current integrate mode or for calibration mode can be judged by reading the counter latch con- tent flag. the counter latch content flag shows the contents of counter latch, value for current integrate mode or value for calibra- tion mode. note that the contents of the counter latch is updated automatically at the end of next current integration or calibration. the calibration mode is continued until setting the current inte- grate mode bit "0". note on using current integrate circuit just after setting the current integrate mode bit "1", discharge or charge counter may count up one in surplus, in the first integrate period, because of internal analog circuit still doesn't become stable in the first integrate period. this cause increase of one count on counting up counter or stopping counter in the first inte- grate period. discharge counter latch low-order register (000a 16 ) b7 b0 b7 b0 b7 b0 b7 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b15 b14 b13 b12 b11 b10 b9 b8 b15 b14 b13 b12 b11 b10 b9 b8 b7 b0 discharge counter latch high-order register (000b 16 ) charge counter latch low-order register (000c 16 ) charge counter latch high-order register (000d 16 ) current integrate control register (000e 16 ) current integrate mode bit 0 : current integrate mode 1 : calibration mode calibration selection bit 00 : zero calibration 01 : full calibration for discharge 10 : full calibration for charge 11 : not used calibration current selection bit (note) 0 : 10a calibration 1 : 5a calibration integrate coefficient selection bit 0 : 10m ? sense register 1 : 5m ? sense register not used (returns "0" when read) counter latch contents flag 0 : current integrate data 1 : calibration data current integrate enable bit 0 : disable 1 : enable note: this bit is protected.
feb 18, 2005 page 46 of 85 rej03b0122-0101 7512 group over current detector over current detector detects the over current which flows through the sense resistor connected between isens1 pin and isens0 pin, and turn off the discharge control fet to stop battery from dis- charging or charging. in the low power state, and when current integrator disables, wake up current detector which detects ap- proximate 1ma current and generates the interrupt is also built-in. discharge short current detector discharge short current detector detects the discharge short current(10a-47.5a) with 10m ? sense resistor. setting discharge short current detect enable bit of the discharge short current de- tect control register(000f 16 ) 1 , discharge short current detector starts the operation. the compare voltage is determined by setting the discharge short current detect voltage select bit of the dis- charge short current detect control register, and the detect time is determined by setting the discharge short current detect time set up bit of the current detect time set up register 1(0011 16 ). the potential difference between sense resistor exceeds the com- pare voltage and continue more than detect time, then discharge short current detect flag(bit 2 of 0013 16 ) becomes 1 , and dis- charge short current detect interrupt occurs. enabling interrupt for discharge short current detect is determined by discharge short current interrupt enable bit(bit 4 of 000f 16 ). and in case of the fet control enable bit is 1 , the fet control signal is generated from dfetcnt pin with discharge short cur- rent interrupt. the polarity of the fet control signal is determined by setting the discharge fet control polarity switch bit(bit 5 of 000f 16 ). setting the discharge short current detect restart bit(bit 6 of 0013 16 ) 1 makes the discharge short current detect state clear. discharge over current detector discharge over current detector detects the discharge over current(5a-20.5a) with 10m ? sense resistor. setting discharge over current detect enable bit of the discharge over current detect control register(0010 16 ) 1 , discharge over current detector starts the operation. the compare voltage is determined by setting the discharge over current detect voltage select bit of the discharge over current detect control register(0010 16 ), and the detect time is determined by setting the discharge over current detect time set up bit of the current detect time set up register 1(0011 16 ). the potential difference between sense resistor exceeds the com- pare voltage and continue more than detect time, then discharge over current detect flag(bit 1 of 0013 16 ) becomes 1 , and dis- charge over current detect interrupt occurs. enabling interrupt for discharge over current detect is determined by discharge over current interrupt enable bit. and in case of the discharge fet control enable bit is 1 , the fet control signal is generated from dfetcnt pin with discharge over current inter- rupt. setting the discharge overt current detect restart bit(bit5 of 0013 16 ) 1 makes the discharge over current detect state clear. wake up current detector wake up current detector detects approximate 1a current with 10m ? sense resistor. setting wake up current detect enable bit of the wake up current detect control register 1(0012 16 ) 1 , wake up current detector starts the operation. the sensing voltage is 10 times amplified and compared by the comparator. the comparator is comparing every 3.9msec, and more than 1a current is keeping for about 62msec, wake up current detect flag(bit 0 of 0013 16 ) be- comes 1 , and the wake up current detect interrupt occurs. the enabling interrupt for wake up current detect is determined by wake up current detect interrupt enable bit(bit6 of 0012 16 ). setting the wake up current detect restart bit 1 makes the wake up cur- rent detect state clear. the offset calibration of the amplifier and comparator is able to be adjusted by setting the wake up current compare voltage select bit. setting the wake up current detect calibration enable bit(bit5 of 0014 16 ) 1 , calibration mode starts. in the calibration mode, input of level shift circuit is connected to internal gnd, and it is possible to measure the comparator threshold voltage at 0v input state, with setting wake up current detect compare voltage select bit. then set the wake up current detect compare voltage select bit the value which is added comparator threshold voltage at 0v state and 0.1v(1a worth voltage). charge over current detector charge over current detector detects the charge over current (10a-25a) with 10m ? sense resister. setting charge over current detect enable bit of the charge over current detect control register (0ff0 16 ) "1", charge over current detector starts the operation. the compare voltage is determined by setting the charge over current detect voltage select bit of the charge over current detect control register (0ff0 16 ), and the detect time is determined by set- ting the charge over current detect time set up bit of the current detect time set up register 2 (0ff1 16 ). the potential difference between sense resister exceeds the com- pare voltage and continue more than detect time, then charge over current detect flag (bit 3 of 0013 16 ) becomes "1", and charge over current detect interrupt occurs. enabling interrupt for charge over current detect is determined by charge over current interrupt enable bit. and in case of the charge fet control enable bit is "1", the charge fet control signal is gen- erated from cfetcnt pin with charge over current interrupt. the polarity of the fet control signal is determined by setting the charge fet control polarity switch bit (bit 5 of 0ff0 16 ). setting the charge over current detect restart bit (bit 7 of 0013 16 ) "1" makes the charge over current detect state clear. sfr protect control register sfr protect control register(0029 16 ), bit of misrg2 (0037 16 ) and bit4,5 of misrg (0038 16 ) protect sfr from changing the contents easily cause of like microcomputer runs away. when the bit of sfr protect control register bit of misrg2, bit 4,5 of misrg is 0 , corresponded bit register is protected. writing to the protected register, write 1 to the corresponded bit of protect register, then write the protected register in succession. if other register is written, the contents of sfr protect register is cleared 00 .
feb 18, 2005 page 47 of 85 rej03b0122-0101 7512 group fig. 51 block diagram of over current detector av cc x10 s r q s r q s r q xcin/128 discharge fet isens1 wake up calibration enable bit 0 1 level shift circuit wake up current detect time counter discharge over current detect time counter discharge short current detect time counter current detect time set up resister 1 over current detect status register fet control enable bit (when short current detect enable) fet control enable bit (when over current detect enable) fet control polarity switch bit level shift circuit discharge short current detect voltage select bit discharge over current detect voltage select bit wake up current detect voltage select bit charge over current detect voltage select bit s r q current detect time set up resister 2 charge over current detect time counter over current detect interrupt discharge fet control polarity switch bit charge fet control enable bit charge fet
feb 18, 2005 page 48 of 85 rej03b0122-0101 7512 group fig. 52 over current detector registers (1) short current detect control register protect bit (000f 16 ) 0 : write disable 1 : write enable over current detect control register protect bit (0010 16 ) 0 : write disable 1 : write enable current detect time set up register protect bit (0011 16 ) 0 : write disable 1 : write enable wake up current detect control register 1 protect bit (0012 16 ) 0 : write disable 1 : write enable over current detect status register protect bit (0013 16 ) 0 : write disable 1 : write enable wake up current detect control register 2 protect bit (0014 16 ) 0 : write disable 1 : write enable misrg2 protect bit (0037 16 ) 0 : write disable 1 : write enable cpu mode register protect bit (003b 16 ) 0 : write disable 1 : write enable b7 sfr protect control register (0029 16 ) prcr b0 b7 discharge short current detect control register protect bit (000f 16 ) short current detect voltage select bit 0000 : 0.100v 1000 : 0.300v 0001 : 0.125v 1001 : 0.325v 0010 : 0.150v 1010 : 0.350v 0011 : 0.175v 1011 : 0.375v 0100 : 0.200v 1100 : 0.400v 0101 : 0.225v 1101 : 0.425v 0110 : 0.250v 1110 : 0.450v 0111 : 0.275v 1111 : 0.475v discharge short current detect interrupt enable bit 0 : disable 1 : enable discharge fetcontrol polarity switch bit 0 : active "l" output 1 : active "h" output discharge fetcontrol enable bit (when short current detect enable) 0 : fet control disable 1 : fet control enable discharge short current detect enable bit 0 : disable 1 : enable b0 note : same bits in this register are not able to protect. note : all bits are protected. b7 discharge over current detect control register (0010 16 ) discharge short current detect voltage select bit 00000 : 0.050v 10000 : 0.130v 00001 : 0.055v 10001 : 0.135v 00010 : 0.060v 10010 : 0.140v 00011 : 0.065v 10011 : 0.145v 00100 : 0.070v 10100 : 0.150v 00101 : 0.075v 10101 : 0.155v 00110 : 0.080v 10110 : 0.160v 00111 : 0.085v 10111 : 0.165v 01000 : 0.090v 11000 : 0.170v 01001 : 0.095v 11001 : 0.175v 01010 : 0.100v 11010 : 0.180v 01011 : 0.105v 11011 : 0.185v 01100 : 0.110v 11100 : 0.190v 01101 : 0.115v 11101 : 0.195v 01110 : 0.120v 11110 : 0.200v 01111 : 0.125v 11111 : 0.205v discharge over current detect interrupt enable bit 0 : disable 1 : enable discharge fet control enable bit (when over current detect enable) 0 : fet control disable 1 : fet control enable discharge over current detect enable bit 0 : disable 1 : enable b0 note : all bits are protected. discharge short current detect time set up bit 0000 : 0 s 1000 : 488 s 0001 : 61 s 1001 : 549 s 0010 : 122 s 1010 : 610 s 0011 : 183 s 1011 : 671 s 0100 : 244 s 1100 : 732 s 0101 : 305 s 1101 : 793 s 0110 : 366 s 1110 : 854 s 0111 : 427 s 1111 : 915 s discharge over current detect time set up bit 0000 : 1.0ms 1000 : 17.0ms 0001 : 3.0ms 1001 : 19.0ms 0010 : 5.0ms 1010 : 21.0ms 0011 : 7.0ms 1011 : 23.0ms 0100 : 9.0ms 1100 : 25.0ms 0101 : 11.0ms 1101 : 27.0ms 0110 : 13.0ms 1110 : 29.0ms 0111 : 15.0ms 1111 : 31.0ms b7 current detect time set up register 1 (0011 16 ) b0 note : all bits are protected.
feb 18, 2005 page 49 of 85 rej03b0122-0101 7512 group fig. 53 over current detector registers (2) b7 wake up current detect control register 2 (0014 16 ) reserved (do not write "1"to this bit) wake up calibration enable bit 0 : disable 1 : enable reserved (do not write "1"to this bit) not used (returns "0" when read) b0 note : all bits are protected. b7 wake up current detect control register 1 (0012 16 ) wake up current detect compare voltage select bit wake up current detect interrupt enable bit 0 : disable 1 : enable wake up current detect enable bit 0 : disable 1 : enable b0 b5 b4 b3 b2 b1 b0 0 0 x x x x setting disabled 01000 0 1.04 01000 1 1.05 01001 0 1.06 01001 1 1.07 0.01n+0.88 11110 0 1.48 11110 1 1.49 11111 0 1.50 11111 1 1.51 wake up current detect compare voltage select bit n compare voltage (v) note : all bits are protected. wake up current detect flag 0 : not detected 1:detected discharge over current detect flag 0 : not detected 1:detected discharge over current detect flag 0 : not detected 1:detected charge over current detect flag 0 : not detected 1:detected wake up current detect restart bit 0 : invalid 1 : restart discharge over current detect restart bit 0 : invalid 1 : restart discharge short current detect restart bit 0 : invalid 1 : restart charge over current detect restart bit 0 : invalid 1 : restart b7 over current detect status register(0013 16 ) b0 note : all bits are protected. b7 charge over current detect control register (0ff0 16 ) charge over current detect voltage select bit 0000 : 0.025v 1000 : 0.065v 0001 : 0.030v 1001 : 0.070v 0010 : 0.035v 1010 : 0.075v 0011 : 0.040v 1011 : 0.080v 0100 : 0.045v 1100 : 0.085v 0101 : 0.050v 1101 : 0.090v 0110 : 0.055v 1110 : 0.095v 0111 : 0.060v 1111 : 0.100v charge over current detect interrupt enable bit 0 : disable 1 : enable charge fet control polarity switch bit 0 : active "l" output 1 : active "h" output charge fet control enable bit 0 : fet control disable 1 : fet control enable charge over current detect enable bit 0 : disable 1 : enable b0 note : all bits are protected. the sfr protect bit control bit is in misrg register (address 0038 16 ). b7 current detect time set up register 2 (0ff1 16 ) charge over current detect time set up bit 0000 : 1.0ms 1000 : 17.0ms 0001 : 3.0ms 1001 : 19.0ms 0010 : 5.0ms 1010 : 21.0ms 0011 : 7.0ms 1011 : 23.0ms 0100 : 9.0ms 1100 : 25.0ms 0101 : 11.0ms 1101 : 27.0ms 0110 : 13.0ms 1110 : 29.0ms 0111 : 15.0ms 1111 : 31.0ms dfetcnt-int 2 or output enable bit 0 : disable 1 : enable int 2 polarity switch bit 0 : invert 1 : not invert cfetcnt-int 3 or output enable bit 0 : disable 1 : enable int 3 polarity switch bit 0 : invert 1 : not invert b0 note : all bits are protected. the sfr protect bit control bit is in misrg register ( address 0038 16 ) . not used (returns "0" when read)
feb 18, 2005 page 50 of 85 rej03b0122-0101 7512 group watchdog timer the watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, be- cause of a software run-away). the watchdog timer consists of an 8-bit watchdog timer l and an 8-bit watchdog timer h. standard operation of watchdog timer when any data is not written into the watchdog timer control reg- ister (address 0039 16 ) after resetting, the watchdog timer is in the stop state. the watchdog timer starts to count down by writing an optional value into the watchdog timer control register (address 0039 16 ) and an internal reset occurs at an underflow of the watch- dog timer h. accordingly, programming is usually performed so that writing to the watchdog timer control register (address 0039 16 ) may be started before an underflow. when the watchdog timer control reg- ister (address 0039 16 ) is read, the values of the high-order 6 bits of the watchdog timer h, stp instruction disable bit, and watch- dog timer h count source selection bit are read. initial value of watchdog timer at reset or writing to the watchdog timer control register (address 0039 16 ), each watchdog timer h and l is set to ff 16 . fig. 55 structure of watchdog timer control register watchdog timer h count source selection bit operation bit 7 of the watchdog timer control register (address 0039 16 ) per- mits selecting a watchdog timer h count source. when this bit is set to 0 , the count source becomes the underflow signal of watchdog timer l. the detection time is set to 262.144 ms at f(x in ) = 4 mhz frequency and 32.768 s at f(x cin ) = 32 khz frequency. when this bit is set to 1 , the count source becomes the signal divided by 16 for f(x in ) (or f(x cin )). the detection time in this case is set to 1024 s at f(x in ) = 4 mhz frequency and 128 ms at f(x cin ) = 32 khz frequency. this bit is cleared to 0 after reset- ting. operation of stp instruction disable bit bit 6 of the watchdog timer control register (address 0039 16 ) per- mits disabling the stp instruction when the watchdog timer is in operation. when this bit is 0 , the stp instruction is enabled. when this bit is 1 , the stp instruction is disabled, once the stp instruction is executed, an internal reset occurs. when this bit is set to 1 , it cannot be rewritten to 0 by program. this bit is cleared to 0 after resetting. fig. 54 block diagram of watchdog timer b0 stp instruction disable bit 0: stp instruction enabled 1: stp instruction disabled watchdog timer h count source selection bit 0: watchdog timer l underflow 1: f(x in )/16 or f(x cin )/16 watchdog timer h (for read-out of high-order 6 bit) watchdog timer control register (wdtcon : address 0039 16 ) b7 x in data bus x cin 10 00 01 main clock division ratio selection bits (note) 0 1 1/16 watchdog timer h count source selection bit reset circuit stp instruction disable bit watchdog timer h (8) ff 16 is set when watchdog timer control register is written to. internal reset reset watchdog timer l (8) note: an y one of hi g h-s p eed, middle-s p eed or low-s p eed mode is selected b y bits 7 and 6 of the cpu mode re g ister. stp instruction ff 16 is set when watchdog timer control register is written to.
feb 18, 2005 page 51 of 85 rej03b0122-0101 7512 group reset circuit to reset the microcomputer, reset pin must be held at an "l" level for 20 x in cycles or more. then the reset pin is returned to an "h" level (the power source voltage must be between 2.45 v and 2.55 v, and the oscillation must be stable), reset is released. after the reset is completed, the program starts from the address contained in address fffd 16 (high-order byte) and address fffc 16 (low-order byte). make sure that the reset input voltage is less than 0.49 v for v cc of 2.45 v. fig. 57 reset sequence fig. 56 reset circuit example reset internal reset data address sync x in : 10.5 to 18.5 clock cycles x in ? ? ? ? ? fffc fffd ad h , l ? ? ? ? ? ad l ad h 1: the frequency relation of f(x in ) and f( ) is f(x in )=8 f( ). 2: the question marks (?) indicate an undefined state that depends on the previous state. reset address from the vector table. notes (note) 0.2v cc 0v 0v poweron v cc reset v cc reset power source voltage detection circuit power source voltage reset input voltage note : reset release voltage ; vcc=2.45 v
feb 18, 2005 page 52 of 85 rej03b0122-0101 7512 group fig. 58 internal status at reset port p0 direction register (p0d) port p1 direction register (p1d) port p2 direction register (p2d) port p3 direction register (p3d) port p4 direction register (p4d) discharge counter latch low-order register (dchargel) discharge counter latch high-order register (dchargeh) charge counter latch low-order register (chargel) charge counter latch high-order register (chargeh) current integrator control register (cinfcon) discharge short current detector control register (dscdcon) discharge over current detector control register (docdcon) current detect time set up register 1 (ocdtime1) wake up current detector control register 1 (wddcon1) over current detect status register (ocdsts) wake up current detector control register 2 (wddcon2) serial i/o2 control register 1 (si02con1) serial i/o2 control register 2 (si02con2) serial i/o status register (siosts) serial i/o control register (siocon) uart control register (uartcon) pwm control register (pwmcon) prescaler 12 (pre12) timer 1 (t1) timer 2 (t2) timer xy mode register (tm) prescaler x (prex) timer x (tx) prescaler y (prey) timer y (ty) timer count source select register (tcss) (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) (29) (30) (31) note : x indicates not fixed . address register contents 0001 16 0003 16 0005 16 0007 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0019 16 001a 16 001b 16 001d 16 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 ff 16 01 16 00 16 00 16 ff 16 ff 16 ff 16 ff 16 00 16 sfr protect control register (prreg) i 2 c address register (s0d) i 2 c status register (s1) i 2 c control register (s1d) i 2 c clock control register (s2) i 2 c start/stop condition control register (s2d) i 2 c additional register (s3) 32khz oscillation circuit control register 0 (32koscc0) 32khz oscillation circuit control register 1 (32koscc1) ad control register (adcon) misrg2 misrg watchdog timer control register (wdtcon) interrupt edge selection register 1 (intedge1) cpu mode register (cpum) i nterrupt request register 1 (ireq1) interrupt request register 2 (ireq2) interrupt control register 1 (icon1) interrupt control register 2 (icon2) flash memory control register 0 (fmcr0) flash memory control register 1 (fmcr1) flash memory control register 2 (fmcr2) charge over current detect control register (cocdcon) current detect time set up register 2 (ocdtime2) high-speed rc oscillator frequency set up register high-speed rc oscillator control register (o4rccot) interrupt edge selection register 2 (intedge2) processor status register program counter (32) (33) (34) (35) (36) (37) (38) (39) (40) (41) (42) (43) (44) (45) (46) (47) (48) (49) (50) (51) (52) (53) (54) (55) (56) (57) (58) (59) (60) address register contents 0029 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 0fe0 16 0fe1 16 0fe2 16 0ff0 16 0ff1 16 0ff2 16 0ff4 16 0ff5 16 (ps) (pc h ) (pc l ) 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 ab 16 00 16 00x 0 0111 10000000 11100000 00111111 01100 0 0 0 0001 0 000 0001000x 000 x x x x x 1 xx xx xx x fffd 16 contents fffc 16 contents 000 0 0001 01000000 0000000x (o4rcfrg)
feb 18, 2005 page 53 of 85 rej03b0122-0101 7512 group clock generating circuit the 7512group has four built-in oscillation circuits. built-in oscil- lation circuit about 4mhz oscillation, or an oscillation circuit can be formed by connecting a resonator between x in and x out for high speed oscillation, and an oscillation circuit can be formed by con- necting capacitor and resistor, or resonator between x cin and x cout for low speed oscillation. the oscillation source (built-in os- cillation or x in -x out oscillation) can be controlled by setting clock source switch bit (cpu mode register) and high-speed rc oscilla- tion stop bit (misrg2) and x in switching inhibit bit(misreg2). immediately after power on, only the built-in oscillation circuit starts oscillation. in case of using x in -x out oscillation circuit, change the clock source bit after start the x in -x out oscillation set- ting the main clock (x in -x out ) stop bit (cpu mode register). in case of not using x in -x out oscillation circuit, x in pin and x out pin must be open. setting the x in switching inhibit bit "1" (disable switch to x in ), clock source switch bit become invalid, and x in -x out oscillation circuit becomes disabled since. when this bit is set to "1", it can- not be rewritten to "0" by program. setting the port xc switch bit (cpu mode register) "1", 32khz rc oscillation circuit or x cin -x cout oscillation circuit starts oscilla- tion. the selection of 32khz rc oscillation circuit or xc in -x cout oscillation circuit is selected by 32khz rc oscillation enable bit (misrg2). in case of using external resonator, connect resonator to x in pin and x out pin (x cin pin and x cout pin). use the circuit constants in accordance with the resonator manufacturer s recommended values. no external resistor is needed between x in and x out since a feed-back resistor exists on-chip.(an external feed-back resistor may be needed depending on conditions.) however, an external feed-back resistor is needed between x cin and x cout . after reset, x cin and x cout pins function as i/o ports. frequency control (1) middle-speed mode the internal clock is the frequency of high-speed rc oscillation clock or x in divided by 8. after reset, this mode is selected. (2) high-speed mode the internal clock is half the frequency of x in . (3) low-speed mode the internal clock is half the frequency of high-speed rc oscil- lation clock or x cin . note if you switch the mode between middle/high-speed and low- speed, stabilize both x in and x cin oscillations. the sufficient time is required for the sub-clock to stabilize, especially immediately af- ter power on and at returning from the stop mode. when switching the mode between middle/high-speed and low-speed, set the fre- quency on condition that f(x in ) > 3 f(x cin ). (4) low power dissipation mode the low power consumption operation can be realized by stopping the main clock x in in low-speed mode. to stop the main clock, set bit 5 of the cpu mode register to 1 . when the main clock x in is restarted (by setting the main clock stop bit to 0 ), set sufficient time for oscillation to stabilize. the sub-clock x cin -x cout oscillating circuit can not directly input clocks that are generated externally. accordingly, make sure to cause an external resonator to oscillate. 32khz rc oscillation circuit setting the port xc switch bit "1" after setting the 32khz rc oscil- lation enable bit "1", the built-in 32khz rc oscillation circuit starts oscillation. in case of using 32khz rc oscillation circuit, connect 91k ? resistor between xcin-xcout, and connect 100pf capaci- tor between xcin and gnd. setting appropriate value to the 32khz oscillation circuit control register0,1 it is possible to adjust the frequency error cause by evenness of resistor and capacitor value . the resistor ladder divided by 512 adjusts the frequency, and it makes possible about 50hz step adjustment. the theoretical frequency is calculated as follow. 1 f 32krc = 2rcln(1+2r 1 /r 2 ) calibration for high-speed rc oscillation circuit setting the high-speed rc oscillation circuit calibration enable bit "1", built-in counter starts count the clock which is divided the fre- quency of the high-speed rc oscillation output by 1/2 for four cycles period of 32khz rc oscillation clock, and high-speed rc oscillation frequency can be measured. the built-in counter is 9bit counter and lower 8bit count value is stored in the high-speed rc oscillation circuit frequency counter (0ff3 16 ) and higher 1bit is stored in bit 0 of high-speed rc oscil- lation circuit control register (0ff4 16) . renewing the high-speed rc oscillation frequency set up register (0ff2 16 ), oscillation frequency is altered. high-speed rc oscilla- tion circuit frequency may change cause of change of v cc or operating, temperature, but adjusting the high-speed oscillation frequency set up register by software, oscillating frequency can be kept fixed. after power on, built-in high-speed rc oscillation starts the oscil- lation at about 4mh z .
feb 18, 2005 page 54 of 85 rej03b0122-0101 7512 group fig. 59 block diagram of 32khz rc oscillation circuit 1/2 91k ? 100pf 71.68k ? 35.84 ? 70 ? ? 512 resistor ladder vcc 2 (1.25v) x cin x cout r 1 r 2 c r 32khz oscillation circuit control register 0,1 clock control circuit comparator fig. 60 32khz oscillation control register b7 b6 b5 b4 b3 b2 b1 b7 aa aa aa aa a a aa aa a a aa aa aa aa b7 b0 b0 b8 b0 32khz oscillation control register 0 (0032 16 ) 32khz oscillation control register 1 (0033 16 ) fig. 61 high-speed rc oscillation register high-speed rc oscillation control register (0ff4 16 ) (note 1,2) aa aa aa aa a a aa aa a a aa aa aa aa b7 high-speed rc oscillation frequency counter (0ff3 16 ) (note 1,2) b7 b6 b5 b4 b3 b2 b1 b7 b0 b0 b8 b0 high-speed rc oscillation frequency set up register (0ff2 16 ) b7 b6 b5 b4 b3 b2 b1 b7 b0 b0 note 1 the first reading of high-speed rc oscillation frequency counter after enable high-speed rc oscillation calibration must be read after nine clock cycle of 32kh z oscillation clock. note 2 read first 0ff3 16 and second 0ff4 16 . note 3 when high-speed rc oscillation calibration enable bit is "1", set up the clock source high-speed rc oscillation, and set up the main clock division ratio selection bits high-speed mode. bit8 of high-speed rc oscillation counter not used (returns "0" when read) high-speed rc oscillation calibration enable bit (note 3) 0 : disable 1 : enable
feb 18, 2005 page 55 of 85 rej03b0122-0101 7512 group fig. 62 ceramic resonator circuit fig. 63 external clock input circuit oscillation control (1) stop mode if the stp instruction is executed, the internal clock stops at an h level, and high-speed rc oscillation or x in and x cin oscillation stops. when the oscillation stabilizing time set after stp instruc- tion released bit is 0 , the prescaler 12 is set to ff 16 and timer 1 is set to 01 16 . when the oscillation stabilizing time set after stp instruction released bit is 1 , set the sufficient time for oscil- lation of used oscillator to stabilize since nothing is set to the prescaler 12 and timer 1. either high-speed rc oscillation, x in or x cin divided by 16 is input to the prescaler 12 as count source. oscillator restarts when an external interrupt is received, but the internal clock is not sup- plied to the cpu (remains at h ) until timer 1 underflows. the internal clock is supplied for the first time, when timer 1 underflows. this ensures time for the clock oscillation using the ceramic resonators to be stabilized. when the oscillator is re- ____________ started by reset, apply l level to the reset pin until the oscillation is stable since a wait time will not be generated. in case of using high-speed rc oscillation circuit as main clock, the oscillation stabilizing time does not almost need. (2) wait mode if the wit instruction is executed, the internal clock stops at an h level, but the oscillator does not stop. the internal clock re- starts at reset or when an interrupt is received. since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. to ensure that the interrupts will be received to release the stp or wit state, their interrupt enable bits must be set to 1 before ex- ecuting of the stp or wit instruction. when releasing the stp state, the prescaler 12 and timer 1 will start counting the clock high-speed rc oscillation, x in divided by 16. accordingly, set the timer 1 interrupt enable bit to 0 before executing the stp instruction. note when using the oscillation stabilizing time set after stp instruction released bit set to 1 , evaluate time to stabilize oscillation of the used oscillator and set the value to the timer 1 and prescaler 12. fig. 64 high-speed rc oscillation circuit and 32khz rc oscil- lation circuit x cin x cout x in x out c i n c o u t c cin c c o u t r f r d r d ( n o t e ) n o t e s : i n s e r t a d a m p i n g r e s i s t o r i f r e q u i r e d . t h e r e s i s t a n c e w i l l v a r y d e p e n d i n g o n t h e o s c i l l a t o r a n d t h e o s c i l l a t i o n d r i v e c a p a c i t y s e t t i n g . u s e t h e v a l u e r e c o m m e n d e d b y t h e m a k e r o f t h e o s c i l l a t o r . a l s o , i f t h e o s c i l l a t o r m a n u f a c t u r e r ' s d a t a s h e e t s p e c i f i e s t h a t a f e e d b a c k r e s i s t o r b e a d d e d e x t e r n a l t o t h e c h i p t h o u g h a f e e d b a c k r e s i s t o r e x i s t s o n - c h i p , i n s e r t a f e e d b a c k r e s i s t o r b e t w e e n x i n a n d x o u t f o l l o w i n g t h e i n s t r u c t i o n . x cin x cout x in x out c cin c cout rf rd open external oscillation circuit vcc vss x in x out x cin x cout 91k ? 100pf open open
feb 18, 2005 page 56 of 85 rej03b0122-0101 7512 group fig. 65 system clock generating circuit block diagram (single-chip mode) wit instruction stp instruction stp instruction s r q s r qs r q x cout x cin interrupt request reset interrupt disable flag l 1/2 1/4 1/2 port x c switch bit 1 0 x in x out high-speed or middle-speed mode main clock division ratio selection bit (note 1) note 1: any one of high-speed mode, middle-speed mode or low-speed mode is selected by bits 7 and 6 of the cpu mode register. when low-speed mode is selected, set port xc switch bit (b1) to 1 . 2: when the oscillation stabilizing time set after stp instruction release bit is 0 . 3: although a feed-back resistor exists on-chip, an external feed-back resistor may be needed depending on conditions. timing (internal clock) main clock stop bit (x in -x out ) high-speed or low-speed mode main clock division ratio selection bits (note 1) ff 16 01 16 prescaler 12 timer 1 reset or stp instruction (note 2) middle-speed mode low-speed mode high-speed rc oscillation stop bit x in changing inhibit bit port x c switch bit port x c switch bit clock source switch bit data bus 32kh z rc oscillation enable bit 1/2 high-speed rc oscillation circuit x in -x out oscillation high-speed rc oscillation 32kh z rc oscillation enable bit 32kh z oscillation circuit control register 0, 1 (note 3) x cin -x out oscillation 32kh z rc oscillation
feb 18, 2005 page 57 of 85 rej03b0122-0101 7512 group fig. 66 structure of misrg1, misrg2 misrg2(0037 16 ) analog in additional bit bit0 adcon (0034 16 ) bit2 bit1 bit0 0 xxxp3 5 /an 5 - p3 0 /an 0 1 000p0 4 /an 8 1 001p0 5 /an 9 1 010p0 6 /an 10 1 011p0 7 /an 11 1 1 x x inhibit b7 b0 32khz rc oscillation calibration enable bit (note 4) 0: oscillating 1: enable high-speed rc oscillation stop bit (note4) 0: oscillating 1: stopping x in switching inhibit bit (note3, 4) 0: enable switch to x in 1: disable switch to x in 32khz rc oscillation enable bit (note4) 0: x cin -x cout oscillation 1: 32khz rc oscillation serial i/o2 clock source selection bit (when low-speed mode) 0: x cin 1: built-in oscillator for si/o2 integrate coefficient selection bit of current integrate control register (000e 16 ) protect bit 0: write disable 1: write enable reserved (do not write "1") note 3: when this bit is set to "1", it cannot be rewritten to "0" by program. note 4: this bit is protected. misrg(0038 16 ) oscillation stabilizing time set after stp instruction released bit 0: automatically set 01 16 to timer 1, ff 16 to prescaler 12 1: automatically set nothing middle-speed mode automatic switch set bit 0: not set automatically 1: automatic switching enable (note1, 2) middle-speed mode automatic switch wait time set bit 0: 4.5 to 5.5 machine cycles 1: 6.5 to 7.5 machine cycles middle-speed mode automatic switch start bit (depending on program) 0: invalid 1: automatic switch start (note2) charge over current detect control register (0ff0 16 ) protect.bit 0:write disable 1:write enable over current detect time set up register 2 (0014 16 ) protect bit 0:write disable 1:write enable not used (returns 0 when read) aa aa aa aa b7 b0 note 1: the microcomputer can be switched to the middle-speed mode automatically by the scl/sda interrupt during operation in the low-speed mode. note 2: when switching from the low-speed mode to the middle-speed mode, the value of the cpu mode register also changes. notes on middle-speed mode switch set bit when the middle-speed mode automatic switch set bit is set to 1 during operation in the low-speed mode, x in oscillation starts au- tomatically by detecting the rising edge or the falling edge of the scl pin or the sda pin and the microcomputer switch to the middle-speed mode. select the timing which switches from the low-speed mode to the middle-speed mode by the middle-speed mode automatic switch wait time set bit. the timing is selectable from 4.5 to 5.5 cycles or 6.5 to 7.5 cycles in the low-speed mode. select according to the oscillation start characteristic of the oscil- lator of x in to be used. by writing 1 in the middle-speed mode automatic switch start bit during operation in the low-speed mode, x in oscillation starts automatically and the microcomputer changes to the middle-speed mode.
feb 18, 2005 page 58 of 85 rej03b0122-0101 7512 group fig. 67 state transitions of system clock reset clock source switch bit 0 : built-in high-speed oscillating function 1 : x in -x out oscillation function cm 4 : port xc switch bit 0 : i/o port function (stop oscillating) 1 : x cin -x cout oscillating function cm 5 : main clock(x in - x out ) stop bit 0 : oscillating 1 : stopped cm 7 ,cm 6 : main clock division ratio selection bits b7 b6 0 0 : f= f(x in )/2 (high-speed mode) 0 1 : f= f(x in )/8 (middle-speed mode) 1 0 : f= f(x cin )/2 (low-speed mode) 1 1 : not available cpu mode register (003b 16 ) b7 cpum cm 4 "1" "0" cm 4 "0" "1" cm 6 "1" "0" cm 4 "1" "0" cm 6 "1" "0" cm 7 "1" "0" cm 4 "1" "0" cm 5 "1" "0" cm 6 "1" "0" cm 6 "1" "0" cm 7 "0" "1" cm 6 "1" "0" high-speed rc oscillation stop bit 0 : oscillating 1 : stopped misrg2 (0037 16 ) b2 cm 4 "1" "0" cm 4 "0" "1" cm 6 "0" "1" cm 4 "1" "0" cm 6 "0" "1" cm 7 "1" "0" cm 4 "1" "0" misgr2 (bit2) "1" "0" cm 6 "1" "0" cm 6 "1" "0" cm 7 "1" "0" cm 6 "0" "1" cm 5 "1" "0" cm 4 "1" "0" cm 5 "1" "0" cm 4 "1" "0" cm 5 "0" "1" cm 5 "0" "1" misrg2 (bit 2) "1" "0" cm 3 "1" "0" x in oscillation high-speed mode(f( )=2mhz) cm 7 =0 cm 6 =0 cm 5 =0(4mhz oscillating) cm 4 =0(32khz stopped) cm 3 =1 misrg2(bit2)=1(high-speed rc oscillating stopped) x in oscillation middle-speed mode(f( )=500khz) cm 7 =0 cm 6 =1 cm 5 =0(4mhz oscillating) cm 4 =1(32khz oscillating) cm 3 =1 misrg2(bit2)=1(high-speed rc oscillatin stopped) x in oscillation high-speed mode(f( )=2mhz) cm 7 =0 cm 6 =0 cm 5 =0(4mhz oscillating) cm 4 =1(32khz oscillating) cm 3 =1 misrg2(bit2)=1(high-speed rc oscillating stopped) low-speed mode(f( )=16khz) cm 7 =1 cm 6 =0 cm 5 =0(4mhz oscillating) cm 4 =1(32khz oscillating) cm 3 =1 misrg2(bit2)=1(high-speed rc oscillating stopped) rc oscillation high-speed mode(f( )= approximately 2mhz) cm 7 =0 cm 6 =0 cm 5 =0(4mhz oscillating) cm 4 =1(32khz oscillating ) cm 3 =0 misrg2(bit2)=0(high-speed rc oscillating) rc oscillation high-speed mode(f( )= approximately 2mhz) cm 7 =0 cm 6 =0 cm 5 =1(4mhz oscillating stopped) cm 4 =0(32khz stopped) cm 3 =0 misrg2(bit2)=0(high-speed rc oscillating) b3 notes 1 : switch the mode by the allows shown between the mode blocks. (do not switch between the modes directly without an allow.) 2 : the all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mo de is ended. 3 : timer operates in the wait mode. 4 : when the stop mode is ended, a delay of approximately 2 ms occurs by connecting timer 1 in middle/high-speed mode. 5 : when the stop mode is ended, the following is performed. (1) after the clock is restarted, a delay of approximately 32ms occurs in low-speed mode if timer 12 count source selec tion bit is "0". (2) after the clock is restarted, a delay of approximately 250ms occurs in low-speed mode if timer 12 count source selec tion bit is "1". 6 : wait until oscillation stabilizes after oscillating the main clock x in before the switching from the low-speed mode to middle/high-speed mode. 7 : the example assumes that 4 mhz is being applied to the x in pin and 32 khz to the x cin pin. indicates the internal clock. 8 : use the 32 khz rc oscillation enable bit (bit 4 in address 0037 16 ) to select x cin -x cout oscillation or 32 khz rc oscillation. cm 4 "1" "0" cm 3 "1" "0" misrg2 (bit 2) "1" "0" cm 3 "1" "0" low-speed mode(f( )=16mhz) cm 7 =1 cm 6 =0 cm 5 =1(4mhz oscillating stopped) cm 4 =1(32khz oscillating) cm 3 =1 misrg2(bit2)=1(high-speed rc oscillating stopped) cm 3 "1" "0" misrg2 (bit 2) "1" "0" misrg2 (bit 2) "1" "0" low-speed mode(f( )=16khz) cm 7 =1 cm 6 =0 cm 5 =1(4mhz oscillating stopped) cm 4 =1(32khz oscillating) cm 3 =0 misrg2(bit2)=1(high-speed rc oscillating stopped) rc oscillating middle-speed mode(f( ) =approximately 500khz) cm 7 =0 cm 6 =1 cm 5 =1(4mhz oscillating stopped) cm 4 =1(32khz oscillating) cm 3 =0 misrg2(bit2)=0(high-speed rc oscillating) low-speed mode(f( )=16khz) cm 7 =1 cm 6 =0 cm 5 =1(4mhz oscillating stopped) cm 4 =1(32khz oscillating) cm 3 =0 misrg2(bit2)=0(high-speed rc oscillating) x in oscillation high-speed mode(f( )=2mhz) cm 7 =0 cm 6 =0 cm 5 =0(4mhz oscillating) cm 4 =0(32khz stopped) cm 3 =1 misrg2(bit2)=0(high-speed rc oscillating) x in oscillation high-speed mode(f( )=2mhz) cm 7 =0 cm 6 =0 cm 5 =0(4mhz oscillating) cm 4 =1(32khz oscillating ) cm 3 =1 misrg2(bit2)=0(high-speed rc oscillating) x in oscillation middle-speed mode(f( )=500 khz) cm 7 =0 cm 6 =1 cm 5 =0(4mhz oscillating) cm 4 =0(32khz stopped) cm 3 =1 misrg2(bit2)=1(high-speed rc oscillating stopped) x in oscillation middle-speed mode(f( )=500khz) cm 7 =0 cm 6 =1 cm 5 =0(4mhz oscillating) cm 4 =1(32khz oscillating) cm 3 =1 misrg2(bit2)=0(high-speed rc oscillating) rc oscillating middle-speed mode(f( )= approximately 500khz) cm 7 =0 cm 6 =1 cm 5 =0(4mhz oscillating) cm 4 =0(32khz stopped) cm 3 =0 misrg2(bit2)=0(high-speed rc oscillating) rc oscillating middle-speed mode(f( )= approximately 500khz) cm 7 =0 cm 6 =1 cm 5 =0(4mhz oscillating) cm 4 =1(32khz oscillating) cm 3 =0 misrg2(bit2)=0(high-speed rc oscillating) rc oscillating middle-speed mode(f( )= approximately 500khz) cm 7 =0 cm 6 =1 cm 5 =1(4mhz oscillating stopped) cm 4 =0(32khz stopped) cm 3 =0 misrg2(bit2)=0(high-speed rc oscillating) rc oscillation high-speed mode(f( )=approximately 2mhz) cm 7 =0 cm 6 =0 cm 5 =1(4mhz oscillating stopped) cm 4 =1(32khz oscillating ) cm 3 =0 misrg2(bit2)=0(high-speed rc oscillating) x in oscillation middle-speed mode(f( )=500khz) cm 7 =0 cm 6 =1 cm 5 =0(4mhz oscillating) cm 4 =0(32khz stopped) cm 3 =1 misrg2(bit2)=0(high-speed rc oscillating) rc oscillation high-speed mode(f( )= approximately 2mhz) cm 7 =0 cm 6 =0 cm 5 =0(4mhz oscillating) cm 4 =0(32khz stopped) cm 3 =0 misrg2(bit2)=0(high-speed rc oscillating)
feb 18, 2005 page 59 of 85 rej03b0122-0101 7512 group table 13 summary of the 7512 group (flash memory version) flash memory mode the 7512 group (flash memory version) has flash memory that can be rewritten with a single power source. for this flash memory, two flash memory modes are available in which to read, program, and erase: the parallel i/o mode in which the flash memory can be manipulated using a programmer and the cpu rewrite mode in which the flash memory can be manipu- lated by the central processing unit (cpu). summary table 13 lists the summary of the 7512 group (flash memory ver- sion). the flash memory of the 7512 group is divided into 4 blocks of user rom area and boot rom area as shown in figure 68. in addition to the ordinary user rom area to store the mcu op- eration control program, the flash memory has a boot rom area that is used to store a control program in a boot mode. the user can write a rewrite control program in this boot rom area that suits the user s application system. this boot rom area can be rewritten in only parallel i/o mode. item power source voltage program / erase voltage flash memory mode erase block division user rom area boot rom area program method erase method program/erase control method number of commands number of program/ block 0 to block 3 erase times block a, block b rom code protection specifications vcc = 2.5v2% vcc = 2.5v2% 2 modes (parallel i/o mode, cpu rewrite mode) refer to the figure 68 1 block (4k bytes) ( note 1 ) byte program batch erasing program/erase control by software command 5 commands 100 times 1k times available in parallel i/o mode note 1: this boot rom area can be rewritten in only parallel i/o mode.
feb 18, 2005 page 60 of 85 rej03b0122-0101 7512 group fig. 68 block diagram of built-in flash memory (m37512fchp) (1) cpu rewrite mode in cpu rewrite mode, the internal flash memory can be operated on (read, program, or erase) under control of the central process- ing unit (cpu). in cpu rewrite mode, only the user rom area shown in figure 68 can be rewritten; the boot rom area cannot be rewritten. make sure the program and block erase commands are issued for only the user rom area and each block area. the control program for cpu rewrite mode can be stored in either user rom or boot rom area. in the cpu rewrite mode, because the flash memory cannot be read from the cpu, the rewrite con- trol program must be transferred to internal ram area to be executed before it can be executed. microcomputer mode and boot mode the control program for cpu rewrite mode must be written into the user rom or boot rom area in parallel i/o mode beforehand. see figure 68 for details about the boot rom area. normal microcomputer mode is entered when the microcomputer is reset with pulling cnv ss pin low. in this case, the cpu starts operating using the control program in the user rom area. when the microcomputer is reset by pulling the p2 4 /sda 2 /r x d pin high, the cnvss pin high, the cpu starts operating using the con- trol program in the boot rom area (program start address is fffc 16 , fffd 16 fixation). this mode is called the boot mode. block address block addresses refer to the maximum address of each block. these addresses are used in the block erase command. notes 1: the boot rom area can be rewritten in only parallel input/output mode. (access to any other areas is inhibited.) 2: to specify a block, use the maximum address in the block. data block a : 2k byte block 3 : 16k byte block 2 : 16k byte block 1 : 8k byte block 0 : 8k byte ffff 16 e000 16 c000 16 8000 16 2000 16 1800 16 1000 16 user rom area data block b : 2k byte sfr area internal ram area (1.5k byte) ffff 16 1000 16 0fff 16 0fe0 16 063f 16 0040 16 0000 16 ffff 16 f000 16 boot rom area 4k byte sfr area internal flash memory area (52k byte) ram not used 4000 16 3fff 16
feb 18, 2005 page 61 of 85 rej03b0122-0101 7512 group table 14 the difference between ew0 mode and ew1 mode items processor mode program area for rewrite control program operating area for rewrite control program rewritable area restriction of software command the mode after program or erase cpu status at program and erase state how to detect the flash memory status the condition for shift to erase suspend status (note 2) ew0 mode single-chip mode user rom area rewrite program in the flash memory area must be transfered from another area than flash memory area (ex. ram area) and executed. user rom area nothing read status register mode executing _____ read the ry/by status flag, program status flag, erase status flag of the flash memory control register 0 on program. read the sr7, sr5, sr4 of the status register after execute the read status command write "1" to the erase suspend enable bit and erase suspend requirement bit of the flash memory control register on program. ew1 mode single-chip mode user rom area rewrite program can be executed in the user rom area. (note 3) user rom area except rewrite program existing block and interrupt vector area (note 1) program, block erase command command execution for block existing rewrite program is prohibited. read status register command execution is prohibited read array mode hold state (i/o port is kept the execution previous state.) _____ read the ry/by status flag, program status flag, erase status flag of the flash memory control register 0 on program. write "1" to the erase suspend enable bit of the flash memory control register 1 on pro- gram and then interrupt request which is enabled occurred. note 1 write "1" to the 8kb userblock e/w prohibit bit of the flash memory control register 1, rewrite operation on block 0, blo ck 1 is enabled. note 2 the enable time for reading flash memory after shifting to erase suspend status is max td(sr-es). note 3 do not execute rewrite program on ram area. (do not execute program on ram area whether rewrite control program or application program.) ew0 mode setting "1" to cpu rewrite mode selection bit of flash memory con- trol register 0, cpu rewrite mode starts, and software command becomes available. at this time, ew1 mode selection bit of the flash memory control register 1 becomes "0" (ew0 mode). for cpu rewrite mode select bit to be set to "1", it is necessary to write "0" and then "1" in succession. program or erase operation is controlled by software command. the state of program or erase end can be checked by reading the flash memory control register or status register. in case of changing to the erase suspend mode during the erase operation, set the erase suspend enable bit to "1", and set the erase suspend request bit "1". and wait td(sr-es). the user rom area can be accessed after checking the erase suspend flag be- comes "1". setting the erase suspend request bit "0"(erase restart), erase operation restarts. ew1 mode setting the ew1 mode selection bit "1" (write "0" and then "1" in succession) after setting the cpu rewrite mode selection bit "1" (write "0" and then "1" in succession), the ew1 mode starts. the state of the program or erase end can be checked by reading the flash memory control register 0. do not execute the software command of the read status register in the ew1 mode. changing the erase suspend function to effective state, execute the block erase command after setting erase suspend enable bit "1". and the interrupt which triggers off shifting to erase suspend state must be enabled. td(sr-es) later after interrupt request, erase sequence shift to erase suspend state, and interrupt is ac- cepted. when the interrupt request occurs, erase suspend request bit be- comes "1" automatically, and erase operation is suspended. in case of the erase operation is not completed (ry/by status flag is "0") after interrupt routine ends, setting the erase suspend request bit "0", and execute the block erase command again.
feb 18, 2005 page 62 of 85 rej03b0122-0101 7512 group outline performance (cpu rewrite mode) cpu rewrite mode is usable in the single-chip or boot mode. the only user rom area can be rewritten in cpu rewrite mode. in cpu rewrite mode, the cpu erases, programs and reads the in- ternal flash memory by executing software commands. this rewrite control program must be transferred to the ram before it can be executed. the mcu enters cpu rewrite mode by setting 1 to the cpu rewrite mode select bit (bit 1 of address 0fe0 16 ). software commands are accepted once the mode is entered. use software commands to control program and erase operations. whether a program or erase operation has terminated normally or in error can be verified by reading the status register. figure 69 shows the flash memory control register 0. bit 0 is the ry/by status flag used exclusively to read the operat- ing status of the flash memory. during programming and erase operations, it is 0 (busy). otherwise, it is 1 (ready). bit 1 is the cpu rewrite mode select bit. when this bit is set to 1 , the mcu enters cpu rewrite mode. software commands are accepted once the mode is entered. in cpu rewrite mode, the cpu becomes unable to access the internal flash memory directly. fig. 69 structure of flash memory control register flash memory control register 0 (address 0fe0 16 ) fmcr0 ry/by status flag 0: busy (being programmed or erased) 1: ready cpu rewrite mode select bit (note 1) 0: normal mode 1: cpu rewrite mode 8 kb user block e/w enable bit (ubewen) (note 1, 2) 0: e/w disable 1: e/w enable flash memory reset bit (note 3,4) 0: normal operation 1: reset not used ( 0 at write ) user rom area selection bit (note 5) 0: boot rom area accessed 1: user rom area accessed program status flag 0: passed 1: error erase status flag 0: passed 1: error b0 b7 notes 1 : for this bit to be set to 1 , the user needs to write 0 and then 1 to it in succession. to reset this bit 0 , only write 0 . 2 : this bit is valid when the cpu rewrite mode select bit is 1 . 3 : this bit is valid when the cpu rewrite mode select bit is 1 . fix this bit 0 when the cpu rewrite mode select bit is 0 . 4 : setting this bit 1 (resetting the flash memory control circuit), access to the flash memory is disabled for 10 sec. 5 : writing this bit must be executed in the ram. therefore, use the control program in the ram for write to bit 1. to set this bit to 1 , it is necessary to write 0 and then write 1 in succession. the bit can be set to 0 by only writing 0 . bit 2 is 8kb user block e/w enable bit. setting this bit and bit 4 (all user block e/w enable bit) of the flash memory control register 2 (0fe2 16 ) according to the table t-3, e/w protect is done at cpu rewrite mode for user block bit 3 is the flash memory reset bit used to reset the control circuit of internal flash memory. this bit is used when exiting cpu rewrite mode and when flash memory access has failed. when the cpu rewrite mode select bit is 1 , setting 1 for this bit resets the con- trol circuit. to release the reset, it is necessary to set this bit to 0 . bit 5 is user rom area selection bit, and this bit is only available in boot mode. setting this bit 1 , user rom area can be ac- cessed, and cpu rewrite is available. bit 6 is the program status flag, and this flag changes 1 when flash memory write operation ends at abnormal state. if program error occurs, corresponding block is not available. bit 7 is the erase status flag, and this flag changes 1 when flash memory erase operation ends at abnormal state. if erase error oc- curs, corresponding block is not available.
feb 18, 2005 page 63 of 85 rej03b0122-0101 7512 group fig. 70 structure of flash memory control register 1 figure 70 shows the flash memory control register 1. bit 0 is erase suspend enable bit, and setting this bit 1 erase suspend mode which makes erase operation interrupt briefly dur- ing erase operation. to set this bit to 1 , it is necessary to write 0 and then write 1 in succession. this bit can be set to 0 by only writing 0 . bit 1 is erase suspend request bit. writing this bit 1 when the flash memory control register 1 (0fe1 16 , initial 40 16 ) fmcr1 erase suspend enable bit (note 1) 0 : erase suspend invalid 1 : erase suspend valid erase suspend request bit (note 2) 0 : resume erase operation (no request) 1 : interrupt erase operation (requested) not used ( 0 at write) erase suspend flag 0 : executing erase operation 1 : suspending erase operation (erase suspend mode) not used ( 0 at write) b7 b0 note 1 to set this bit 1 , write 0 and then write 1 in succession. to reset this bit 0 , only write 0 . 2 this bit is valid onl y when erase sus p end enable bit is 1 . erase suspend enable bit is 1 , erase operation is interrupted. bit 6 is erase suspend flag, and becomes 0 during erase opera- tion. figure 71 shows flash memory control register 2. bit 1 is ew1 mode select bit. setting this bit 1 , ew1 mode be- comes available. bit 4 is all user block e/w enable bit. fig. 71 structure of flash memory control register 2 table. 15 specification of e/w protect all user block e/w enable bit 0 0 1 1 8kb user block e/w enable bit 0 1 0 1 8 kbx2 block addresses c000 16 to ffff 16 protect protect protect enable 16 kbx2 block addresses 4000 16 to bfff 16 protect protect enable enable data block addresses 1000 16 to 1fff 16 enable enable enable enable flash memory control register 2 (0fe2 16 , initial 45 16 ) fmcr2 reserved (returns unknown when read) ew1 mode select bit (note 1, 3) 0 : e/w0 mode 1 : e/w1 mode reserved (returns unknown when read) all user block e/w enable bit (note 1, 2) 0 : e/w prohibit 1 : e/w enable reserved ( 0 at write, returns 0 at read) not used (indefinite at read) not used (returns 0 at read) b7 b0 note 1 to set this bit 1 , it is necessary to write 0 and then write 1 in succession. this bit can be set to 0 by only writing 0 . note 2 this bit can be written only cpu rewrite mode selection bit 1 . note 3 setting this bit 1 must be done at cpu rewrite mode select bit is 1 .
feb 18, 2005 page 64 of 85 rej03b0122-0101 7512 group fig. 72 cpu rewrite mode set/release flowchart figure 72 shows a flowchart for setting/releasing cpu rewrite mode. notes 1 : set bits 6, 7 (main clock division ratio selection bits) at cpu mode register (003b 16 ). 2: before exiting the cpu rewrite mode after completing erase or program operation, always be sure to execute the read array command. end start execute read array command (note 2) single-chip mode or boot mode set cpu mode register (note 1) using software command execute erase, program, or other operation jump to control program transferred in ram (subsequent operations are executed by control program in this ram) transfer cpu rewrite mode control program to ram write 0 to cpu rewrite mode select bit set cpu rewrite mode select bit to 1 (by writing 0 and then 1 in succession) check cpu rewrite mode entry flag e/w0 mode set all user block e/w enable bit 1 (by writing 0 and then 1 in succession) set 8kb user block e/w enable bit (writing 0 in case of e/w prohibit, writing 0 and then 1 in succession, in case of e/w enable) set all user block e/w enable bit = 0 set 8kb user block e/w enable bit = 0 end start execute read array command (note 2) single-chip mode or boot mode set cpu mode register (note 1) using software command execute erase program, or other operation set cpu rewrite mode select bit to 1 (by writing 0 and then 1 in succession) write 0 to cpu rewrite mode select bit set e/w1 mode select bit = 1 (by writing 0 and then 1 in succession) check cpu rewrite mode entry flag e/w1 mode set all user block e/w enable bit = 0 set 8kb user block e/w enable bit = 0 set all user block e/w enable bit 1 (by writing 0 and then 1 in succession) set 8kb user block e/w enable bit (writing 0 in case of e/w prohibit, writing 0 and then 1 in succession, in case of e/w enable)
feb 18, 2005 page 65 of 85 rej03b0122-0101 7512 group precautions on cpu rewrite mode described below are the precautions to be observed when rewriting the flash memory in cpu rewrite mode. (1) operation speed during cpu rewrite mode, set the internal clock frequency 4.0 mhz or less using the main clock division ratio selection bits (bit 6, 7 at 003b 16 ). (2) instructions inhibited against use the instructions which refer to the internal data of the flash memory cannot be used during ew0 mode . (3) interrupts inhibited against use the interrupts cannot be used during ew0 mode because they refer to the internal data of the flash memory. in the ew1 mode, the interrupts cannot be used during program operation or erase operation which is disabled erase suspend function. (4) watchdog timer in case of the watchdog timer has been running already, the in- ternal reset generated by watchdog timer underflow does not happen, because of watchdog timer is always clearing during program or erase operation. (5) reset reset is always valid. in case of cnv ss = h when reset is re- leased, boot mode is active. so the program starts from the ad- dress contained in address fffc 16 and fffd 16 in boot rom area.
feb 18, 2005 page 66 of 85 rej03b0122-0101 7512 group software commands (cpu rewrite mode) table 16 lists the software commands. after setting the cpu rewrite mode select bit of the flash memory control register to 1 , execute a software command to specify an erase or program operation. each software command is explained below. read array command (ff 16 ) the read array mode is entered by writing the command code ff 16 in the first bus cycle. when an address to be read is input in one of the bus cycles that follow, the contents of the specified ad- dress are read out at the data bus (d 0 to d 7 ). the read array mode is retained intact until another command is written. read status register command (70 16 ) the read status register mode is entered by writing the command code 70 16 in the first bus cycle. the contents of the status regis- ter are read out at the data bus (d 0 to d 7 ) by a read in the second bus cycle. the status register is explained in the next section. in the ew1 mode, do not execute this command. clear status register command (50 16 ) this command is used to clear the bits sr4 and sr5 of the status register after they have been set. these bits indicate that opera- tion has ended in an error. to use this command, write the command code 50 16 in the first bus cycle. program command (40 16 ) program operation starts when the command code 40 16 is writ- ten in the first bus cycle. then, if the address and data to program are written in the 2nd bus cycle, program operation (data program- ming and verification will start. whether the write operation is completed can be confirmed by _____ reading the status register or the ry/by status flag. ____ the ry/by status flag is 0 (busy) during write operation and 1 (ready) when the write operation is completed as is the status reg- ister bit 7. table 16 list of software commands (cpu rewrite mode) do not execute this command for rewrite control program address in the ew1 mode. in the e/w0 mode, when the program starts, the read status reg- ister mode is entered automatically and the contents of the status register is read at the data bus (d 0 to d 7 ). the status register bit 7 (sr7) is set to 0 at the same time the write operation starts and is returned to 1 upon completion of the write operation. in this case, the read status register mode remains active until the read array command (ff 16 ) is written. fig. 73 program flowchart start write 40 16 status register read program completed no yes write address write data program error no yes ry/by status flag = 1 ? write program status flag = 0 ? command program clear status register read array read status register x x first bus cycle second bus cycle ff 16 70 16 50 16 40 16 write write write write x srd read write (note 2) wa (note 3) wd (note 3) block erase 20 16 write d0 16 write ba (note 4) mode address mode address data (d 0 to d 7 ) (d 0 to d 7 ) (note 1) notes 1: x denotes a given address in the user rom area . 2: srd = status register data 3: wa = write address, wd = write data 4: ba = block address to be erased (input the maximum address of each block.) cycle number 1 2 1 2 2 x x x data
feb 18, 2005 page 67 of 85 rej03b0122-0101 7512 group block erase command (20 16 /d0 16 ) by writing the command code 20 16 in the first bus cycle and the confirmation command code d0 16 and the block address in the second bus cycle that follows, the block erase (erase and erase verify) operation starts for the block address of the flash memory to be specified. whether the block erase operation is completed can be confirmed ____ by reading the status register or the ry/by status flag of flash memory control register. ____ the ry/by status flag is 0 during block erase operation and 1 when the block erase operation is completed as is the status reg- ister bit 7. in case of using erase suspend function in the ew0 mode, check that the erase sequence is shifted to erase suspend mode with erase suspend flag. reading the erase status flag after block erase, the result of the block erase is gotten. do not execute this command for rewrite control program address in the ew1 mode. in the ew0 mode, at the same time the block erase operation starts, the read status register mode is automatically entered, so that the contents of the status register can be read out. the status register bit 7 (sr7) is set to 0 at the same time the block erase operation starts and is returned to 1 upon completion of the block erase operation. in this case, the read status register mode remains active until the read array command (ff 16 ) is written. fig. 74 erase flowchart in no erase suspend write 20 16 d0 16 block address erase completed no yes start write erase error yes no status register read ry/by status flag = 1 ? erase status flag = 0 ?
feb 18, 2005 page 68 of 85 rej03b0122-0101 7512 group symbol table 17 definition of each bit in status register (srd) status register (srd) the status register shows the operating status of the flash memory and whether erase operations and programs ended suc- cessfully or in error. it can be read in the following ways: in the ew0 mode. (1) by reading an arbitrary address from the user rom area after writing the read status register command (70 16 ) (2) by reading an arbitrary address from the user rom area in the period from when the program starts or erase operation starts to when the read array command (ff 16 ) is input. also, the status register can be cleared by writing the clear status register command (50 16 ). after reset, the status register is set to 80 16 . table 17 shows the status register. each bit in this register is ex- plained below. sequencer status (sr7) the sequencer status indicates the operating status of the flash memory. this bit is set to 0 (busy) during write or erase operation and is set to 1 when these operations ends. after power-on, the sequencer status is set to 1 (ready). erase status (sr5) the erase status indicates the operating status of erase operation. if an erase error occurs, it is set to 1 . when the erase status is cleared, it is set to 0 . program status (sr4) the program status indicates the operating status of write opera- tion. when a write error occurs, it is set to 1 . the program status is set to 0 when it is cleared. if 1 is written for any of the sr5 and sr4 bits, the program, erase all blocks, and block erase commands are not accepted. before executing these commands, execute the clear status regis- ter command (50 16 ) and clear the status register. also, if any commands are not correct, both sr5 and sr4 are set to 1 . sr7 (bit7) sr6 (bit6) sr5 (bit5) sr4 (bit4) sr3 (bit3) sr2 (bit2) sr1 (bit1) sr0 (bit0) definition 1 0 status name sequencer status reserved erase status program status reserved reserved reserved reserved ready - terminated in error terminated in error - - - - busy - terminated normally terminated normally - - - -
feb 18, 2005 page 69 of 85 rej03b0122-0101 7512 group full status check by performing full status check, it is possible to know the execu- tion results of erase and program operations. figure 75 shows a fig. 75 full status check flowchart and remedial procedure for errors full status check flowchart and the action to be taken when each error occurs. read status register no yes erase error no yes no program error end (erase, program) should an erase error occur, the block in error cannot be used. note : when one of erase status flag and program status flag is set to 1 , none of the read array, the program, erase all blocks, and block erase commands is accepted. execute the clear status register command (50 16 ) before executing these commands. yes command sequence error execute the clear status register command (50 16 ) to clear the status register. try performing the operation one more time after confirming that the command is entered correctly. should a program error occur, the block in error cannot be used. program status flag = 1 ? erase status flag = 1 ? program status flag = 0 ? erase status flag = 0 ?
feb 18, 2005 page 70 of 85 rej03b0122-0101 7512 group functions to inhibit rewriting flash memory version to prevent the contents of internal flash memory from being read out or rewritten easily, this mcu incorporates a rom code protect function for use in parallel i/o mode. rom code protect function (in parallel i/o mode) the rom code protect function is the function to inhibit reading out or modifying the contents of internal flash memory by using the rom code protect control (address ffdb 16 ) in parallel i/o mode. figure 76 shows the rom code protect control (address ffdb 16 ). (this address exists in the user rom area.) if one or both of the pair of rom code protect bits is set to 0 , the rom code protect is turned on, so that the contents of internal flash memory are protected against readout and modification. the rom code protect is implemented in two levels. if level 2 is se- lected, the flash memory is protected even against readout by a shipment inspection lsi tester, etc. when an attempt is made to select both level 1 and level 2, level 2 is selected by default. if both of the two rom code protect reset bits are set to 00 , the rom code protect is turned off, so that the contents of internal flash memory can be read out or modified. once the rom code protect is turned on, the contents of the rom code protect reset bits cannot be modified in parallel i/o mode. use the cpu rewrite mode to rewrite the contents of the rom code protect reset bits. rewriting of only the rom code protect control address (address ffdb 16 ) cannot be performed. when rewriting the rom code pro- tect reset bit, rewrite the whole user rom area (block 0) containing the rom code protect control address. fig. 76 structure of rom code protect control rom code protect control register (address ffdb 16 ) ( note 1 ) romcp reserved bits ( 1 at read/write) rom code protect level 2 set bits (romcp2) ( notes 1, 2 ) b3b2 0 0: protect enabled 0 1: protect enabled 1 0: protect enabled 1 1: protect disabled rom code protect reset bits (romcr) ( note 3 ) b5b4 0 0: protect removed 0 1: protect set bits effective 1 0: protect set bits effective 1 1: protect set bits effective rom code protect level 1 set bits (romcp1) ( note 2 ) b7b6 0 0: protect enabled 0 1: protect enabled 1 0: protect enabled 1 1: protect disabled b0 b7 notes 1 : when rom code protect is turned on, the internal flash memory is protected against readout or modification in parallel i/o mode. 2 : when rom code protect level 2 is turned on, rom code readout by a shipment inspection lsi tester, etc. also is inhibited. 3 : the rom code protect reset bits can be used to turn off rom code protect level 1 and rom code protect level 2. however, since these bits cannot be modified in parallel i/o mode, they need to be rewritten in cpu rewrite mode. 1 1
feb 18, 2005 page 71 of 85 rej03b0122-0101 7512 group (2) parallel i/o mode parallel i/o mode is the mode which parallel output and input soft- ware command, address, and data required for the operations (read, program, erase, etc.) to a built-in flash memory. use the ex- clusive external equipment flash programmer which supports the 7512 group (flash memory version). refer to each programmer maker s handling manual for the details of the usage. user rom and boot rom areas in parallel i/o mode, the user rom and boot rom areas shown in figure 13 can be rewritten. both areas of flash memory can be oper- ated on in the same way. the boot rom area is 4k bytes in size. it is located at addresses f000 16 through ffff 16 . make sure program and block erase opera- tions are always performed within this address range. (access to any location outside this address range is prohibited.) in the boot rom area, an erase block operation is applied to only one 4k byte block.
feb 18, 2005 page 72 of 85 rej03b0122-0101 7512 group electrical characteristics for flash rom e/w cycles table 18 characteristics (note 1) for 100 e/w cycle products (v cc = 2.5v2%, ta = 0 to 60 o c, unless otherwise noted) erase/write cycle (note 3) byte write time block erase time 2kbyte block 8kbyte block 16kbyte block time delay from suspend request until erase suspend data retention time (note 5) limits parameter min. typ. (note 2) max. symbol v cc =2.5v, ta=25 c v cc =2.5v, ta=25 c condition td(sr es) 100 (note 4) 20 75 0.2 0.4 0.7 600 9 9 9 8 cycle s s s s ms year erase/write cycle (note 3, 8, 9) byte write time block erase time (2kbyte block) time delay from suspend request until erase suspend limits parameter min. typ. (note 2) max. symbol unit v cc =2.5v, ta=25 c v cc =2.5v, ta=25 c condition td(sr es) 1000 (note 4) 100 0.3 8 cycle s s ms table 19 characteristics (note 6) for 1000 e/w cycle products [block a and block b (note 7)] (v cc = 2.5v2%, ta = 20 to 85 o c, unless otherwise noted) notes 1: specified for all blocks. 2: v cc =2.5v; ta=25 c. 3: definition of e/w cycle: each block may be written to a variable number of times - up to a maximum of the total number of disti nct byte addresses - for every block erase. performing multiple writes to the same address before an erase operation is prohibited. 4: maximum number of e/w cycles for which operation is guaranteed. 5: at ta=55 c condition 6: specified for block a and block b e/w cycles > 100 7: to reduce the number of e/w cycles, a block erase should ideally be performed after writing as many different byte addresses ( only one time each) as possible. it is important to track the total number of block erases. 8: should erase error occur during block erase, attempt to execute clear status register command, then block erase command at lea st three times un- til erase error disappears. 9: customers desiring e/w failure rate information should contact their renesas technical support representative. erase suspend request bit (interrupt request) erase suspend flag t d (sr-es) fig. 77 the transition of the timing of the erase / erase suspend unit
feb 18, 2005 page 73 of 85 rej03b0122-0101 7512 group notes on programming processor status register the contents of the processor status register (ps) after a reset are undefined, except for the interrupt disable flag (i) which is 1. af- ter a reset, initialize flags which affect program execution. in particular, it is essential to initialize the index x mode (t) and the decimal mode (d) flags because of their effect on calculations. interrupts the contents of the interrupt request bits do not change immedi- ately after they have been written. after writing to an interrupt request register, execute at least one instruction before perform- ing a bbc or bbs instruction. decimal calculations to calculate in decimal notation, set the decimal mode flag (d) to 1 , then execute an adc or sbc instruction. after executing an adc or sbc instruction, execute at least one instruction be- fore executing a sec, clc, or cld instruction. in decimal mode, the values of the negative (n), overflow (v), and zero (z) flags are invalid. timers if a value n (between 0 and 255) is written to a timer latch, the fre- quency division ratio is 1/(n+1). multiplication and division instructions the index x mode (t) and the decimal mode (d) flags do not af- fect the mul and div instruction. the execution of these instructions does not change the con- tents of the processor status register. ports the contents of the port direction registers cannot be read. the following cannot be used: the data transfer instruction (lda, etc.) the operation instruction when the index x mode flag (t) is 1 the instruction with the addressing mode which uses the value of a direction register as an index the bit-test instruction (bbc or bbs, etc.) to a direction register the read-modify-write instructions (ror, clb, or seb, etc.) to a direction register. use instructions such as ldm and sta, etc., to set the port direc- tion registers. serial interface in clock synchronous serial i/o, if the receive side is using an ex- ternal clock and it is to output the s rdy signal, set the transmit enable bit, the receive enable bit, and the s rdy output enable bit to 1. serial i/o continues to output the final bit from the t x d pin after transmission is completed. s out2 pin for serial i/o2 goes to high impedance after transfer is completed. when in serial i/os 1 and 3 (clock-synchronous mode) or in serial i/o2, an external clock is used as synchronous clock, write trans- mission data to the transmit buffer register or serial i/o2 register, during transfer clock is h. a/d converter the comparator uses capacitive coupling amplifier whose charge will be lost if the clock frequency is too low. therefore, make sure that f(x in ) is at least on 500 khz during an a/d conversion. do not execute the stp instruction during an a/d conversion. instruction execution time the instruction execution time is obtained by multiplying the pe- riod of the internal clock by the number of cycles needed to execute an instruction. the number of cycles required to execute an instruction is shown in the list of machine instructions. the period of the internal clock is double of the x in period in high-speed mode. notes on usage handling of power source pins in order to avoid a latch-up occurrence, connect a capacitor suit- able for high frequencies as bypass capacitor between power source pin (v cc pin) and gnd pin (v ss pin), and between power source pin (v cc pin) and analog power source input pin (av ss pin). besides, connect the capacitor to as close as possible. for bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 f 0.1 f is recom- mended. power source voltage when the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. in a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the power source voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this un- stable operation.
feb 18, 2005 page 74 of 85 rej03b0122-0101 7512 group electrical characteristics table 20 absolute maximum ratings (executing flash memory mode, flash memory electrical characteristics is applied.) power source voltage input voltage p0 0 p0 7 , p2 0 , p2 1, p2 6 , p2 7 , p3 0 p3 5 , p4 0 p4 2 , p4 5 , adv ref , av cc, isens1 input voltage p1 0 p1 7 , p2 2 p2 5 , p4 3 , p4 4 input voltage reset, x in input voltage cnv ss output voltage p0 0 p0 7 , p2 0 , p2 1, p2 6 , p2 7 , p3 0 p3 5 , p4 0 p4 2 , p4 5 , x out output voltage p1 0 p1 7 , p2 2 p2 5 , p4 3 , p4 4 power dissipation operating temperature storage temperature v cc v i v i v i v i v o v o p d t opr t stg symbol parameter conditions ratings 0.3 to 3.2 0.3 to v cc +0.3 0.3 to 5.8 0.3 to v cc +0.3 0.3 to v cc +0.3 0.3 to v cc +0.3 0.3 to 5.8 300 20 to 85 40 to 125 v v v v v v v mw c c unit ta = 25 c all voltages are based on v ss . output transistors are cut off. table 21 recommended operating conditions (1) (v cc = 2.5v2%, ta = 20 to 85 c, unless otherwise noted) v cc v ss adv ref adv ss v ia av cc av ss isens0 isens1 v ih v ih v ih v ih v ih v il v il v il v il v il 2.55 v cc v cc 2.55 0.2 v cc 5.8 5.8 5.8 v cc 0.2v cc 0.3v cc 0.6 0.2v cc 0.16v cc power source voltage (at 4 mhz) power source voltage a/d convert reference voltage a/d convert power source voltage analog input voltage an 0 an 5 , an 8 an 11 analog power source voltage analog power source voltage analog input voltage analog input voltage h input voltage p0 0 p0 7 , p2 0 , p2 1 , p2 6 , p2 7 , p3 0 p3 5 , p4 0 p4 2 , p4 5 h input voltage p1 0 p1 7 , p2 2 p2 5 , p4 3 , p4 4 h input voltage (when i 2 c-bus input level is selected) sda 1 , sda 2 , scl 1 , scl 2 h input voltage (when smbus input level is selected) sda 1 , sda 2 , scl 1 , scl 2 h input voltage ____________ reset, x in , cnv ss l input voltage p0 0 p0 7 , p1 0 p1 7 , p2 0 p2 7 , p3 0 p3 5 , p4 0 p4 5 l input voltage (when i 2 c-bus input level is selected) sda 1 , sda 2 , scl 1 , scl 2 l input voltage (when smbus input level is selected) sda 1 , sda 2 , scl 1 , scl 2 l input voltage ____________ reset , cnv ss l input voltage x in symbol parameter limits min. v v v v v v v v v v v v v v v v v v v unit 2.45 2.0 adv ss 2.45 -0.2 0.8v cc 0.8v cc 0.7v cc 1.4 0.8v cc 0 0 0 0 0 2.5 0 0 2.5 0 0 typ. max.
feb 18, 2005 page 75 of 85 rej03b0122-0101 7512 group table 22 recommended operating conditions (2) (v cc = 2.5v2%, ta = 20 to 85 c, unless otherwise noted) h total peak output current p0 0 p0 7 , p3 0 p3 5 (note 1) h total peak output current p2 0 , p2 1 , p2 6 p2 7 , p4 0 p4 2 , p4 5 (note1) l total peak output current p0 0 p0 7 , p3 0 p3 5 (note 1) l total peak output current p1 0 p1 7 (note1) l total peak output current p2 0 p2 7 ,p4 0 p4 5 (note1) h total average output current p0 0 p0 7 , p3 0 p3 5 (note1) h total average output current p2 0 , p2 1 , p2 6 , p2 7 ,p4 0 p4 2 , p4 5 (note1) l total average output current p0 0 p0 7 , p3 0 p3 5 (note1) l total average output current p1 0 p1 7 (note 1) l total average output current p2 0 p2 7 ,p4 0 p4 5 (note1) h peak output current p0 0 p0 7 , p2 0 , p2 1 , p2 6 , p2 7 , p3 0 p3 5 , p4 0 p4 2 , p4 5 (note 2) l peak output current p0 0 p0 7 , p2 0 p2 7 , p3 0 p3 5 , p4 0 p4 5 (note 2) l peak output current p1 0 p1 7 (note 2) h average output current p0 0 p0 7 , p2 0 , p2 1 , p2 6 , p2 7 , p3 0 p3 5 , p4 0 p4 2 , p4 5 (note 3) l average output current p0 0 p0 7 , p2 0 p2 7 , p3 0 p3 5 , p4 0 p4 5 (note 3) l peak output current p1 0 p1 7 (note 3) main clock input oscillation frequency (v cc = 2.5v 2%) (note 4) sub-clock input oscillation frequency (v cc = 2.5v 2%) (note 4,5) i oh(peak) i oh(peak) i ol(peak) i ol(peak) i ol(peak) i oh(avg) i oh(avg) i ol(avg) i ol(avg) i ol(avg) i oh(peak) i ol(peak) i ol(peak) i oh(avg) i ol(avg) i ol(avg) f(x in ) f(x in ) symbol parameter limits min. unit typ. max. notes 1: the total output current is the sum of all the currents flowing through all the applicable ports. the total average current is an average value measured over 100 ms. the total peak current is the peak value of all the currents. 2: the peak output current is the peak current flowing in each port. 3: the average output current i ol (avg), i oh (avg) are average value measured over 100 ms. 4: when the oscillation frequency has a duty cycle of 50%. 5: when using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(x cin ) < f(x in )/3. ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma mh z kh z 4 32.768 80 80 80 80 80 40 40 40 40 40 10 10 20 5 5 15 5 50
feb 18, 2005 page 76 of 85 rej03b0122-0101 7512 group table 23 electrical characteristics (1) (v cc = 2.5v2%, v ss = 0 v, ta = 20 to 85 c, unless otherwise noted) h output voltage p0 0 p0 7 , p2 0 , p2 1, p2 6 , p2 7, p3 0 p3 5 , p4 0 p4 2 , p4 5 (note) l output voltage p0 0 p0 7 , p2 0 p2 7 , p3 0 p3 5 , p4 0 p4 5 l output voltage p1 0 p1 7 hysteresis cntr 0 , cntr 1 , int 0 int 3 hysteresis rxd, s clk1 , s in2 , s clk2 ____________ hysteresis reset h input current p0 0 p0 7 , p2 0 , p2 1, p2 6 , p2 7, p3 0 p3 5 , p4 0 p4 2 , p4 5 h input current isens0, isens1 ____________ h input current reset, cnv ss h input current x in l input current p0 0 p0 7 , p1 0 p1 7 , p2 0 p2 7 p3 0 p3 5 , p4 0 p4 5 l input current isens0, isens1 l input current ____________ reset , cnv ss l input current x in ram hold voltage limits v v v v v v a a a a a a a a v parameter min. typ. max. symbol unit i oh = 1.0 ma v cc =2.5v2% i ol =1.0 ma v cc =2.5v2% i ol =10 ma v cc =2.5v2% v i = v cc v i = v cc v i = v cc v i = v cc v i = v ss v i = v ss v i = v ss v i = v ss when clock stopped test conditions 0.4 0.4 0.4 4 4 0.8 0.8 5.0 1.0 5.0 5.0 1.0 5.0 2.55 v oh v ol v ol v t+ v t v t+ v t v t+ v t i ih i ih i ih i ih i il i il i il i il v ram v cc 0.8 2.0
feb 18, 2005 page 77 of 85 rej03b0122-0101 7512 group table 24 electrical characteristics (2) (v cc = 2.5v2%, v ss = 0 v, ta = 20 to 85 c, unless otherwise noted) power source current limits parameter min. typ. max. symbol unit high-speed mode f(x in ) = 4 mhz or high-speed rc oscillating (4mh z ) f(x cin ) = 32.768 khz or rc oscillating output transistors off current integrator and current detector stopped high-speed mode f(x in ) = 4 mhz or high-speed rc oscillating (4mh z ) (in wit state) f(x cin ) = 32.768 khz output transistors off current integrator and current detector stopped low-speed mode f(x in ) = stopped f(x cin ) = 32.768 khz or 32khz rc oscillating output transistors off current integrator and current detector stopped low-speed mode f(x in ) = stopped f(x cin ) = 32.768 khz (cristal) or 32khz rc oscillating (in wit state) output transistors off current integrator and current detector stopped middle-speed mode f(x in ) = 4 mhz or high-speed rc oscillating (4mh z ) f(x cin ) = stopped output transistors off current integrator and current detector stopped middle-speed mode f(x in ) = 4 mhz or high-speed rc oscillating (4mh z ) (in wit state) f(x cin ) = stopped output transistors off current integrator and current detector stopped increment when a/d conversion is executed f(x in ) = 4 mhz or high-speed rc oscillating (4mh z ) flash memory write f(x in ) = 4mh z v cc = 2.5v flash memory erase f(x in ) = 4mh z v cc = 2.5v test conditions 2.5 i cc 1.5 0.8 420 6.4 30 1.0 0.8 200 12 22 ma ma a a a ma ma a ma ma cristal rc
feb 18, 2005 page 78 of 85 rej03b0122-0101 7512 group table 25 electrical characteristics (3) (v cc = 2.5v2%, v ss = 0 v, ta = 20 to 85 c, unless otherwise noted) power source current limits parameter min. typ. max. symbol unit increment when current integrator is executed increment when short current detector over current detector over current detector is executed. charge over current detector wake up current detector two detectors used other than wake up current detector three detectors used other than wake up current detector wake up current detector and another use wake up current detector and other two used wake up current detector and other three used all oscillation stopped (in stp state) output transistors "off" test conditions i cc 800 20 20 20 25 30 40 35 45 55 a a a a a a a a a a note : when using the 32khz rc oscillation circuit or the x cin -x cout oscillation, before stp instruction execution select the modes other than the low-speed mode with the main clock division ratio selection bit (cm7, cm6) and then set ports p2 1 and p2 0 to output port ("l" output). ta = 25 c (note) ta = 85 c 0.1 1.0 10 a a
feb 18, 2005 page 79 of 85 rej03b0122-0101 7512 group 80 16 c0 16 oscillation frequency high-speed rc oscillator frequency set up register table 26 high-speed rc oscillation circuit electrical characteristics (v cc = av cc = 2.5v2%, v ss =av ss = 0v, ta = 20 to 85 c, unless otherwise noted) limits parameter min. typ. max. symbol unit test conditions oscillating frequency ajustment width (note) oscillating frequency shift by temperature f(x in )=4 to 5 mh z 0.2 3.0 0.5 % %/ c f 4mrc f 4mrcs table 27 32khz rc oscillation circuit electrical characteristics (v cc = av cc = 2.5v2%, v ss =av ss = 0v, ta = 20 to 85 c, unless otherwise noted) limits parameter min. typ. max. symbol unit test conditions external registor, and capacitor tolerance oscillating frequency adjustment resolution oscillating frequency shift by v cc voltage oscillating frequency shift by temperature oscillating frequency shift by v cc voltage and temperature total tolerance of the resistor and capacitor when external registor=91k ? when external capacitor=100pf ta=25 c v cc =av cc =2.5v, 20 to 85 c 0.5 0.5 10 0.07 2 % khz % % % fig. 78 high-speed rc oscillation circuit register value - oscillating frequency characteristics notes : the bigger setting value of the high-speed rc oscillator frequency set up register (address 0ff2 16 ) makes the oscillating frequency of the high- speed rc oscillation circuit lower. however, since the oscillating frequency is set higher when setting the values from 7f 16 to 80 16 or from bf 16 to c0 16 , be careful of frequency adjustment by software.
feb 18, 2005 page 80 of 85 rej03b0122-0101 7512 group unit bit lsb tc( ) s k ? a a a parameter resolution absolute accuracy (excluding quantization error) conversion time ladder resistor reference power source input current a/d port input current min. 40 typ. 40 35 100 0.5 max. 10 4 61 140 5.0 5.0 test conditions high-speed mode, middle-speed mode low-speed mode v ref = 2.5 v table 28 a/d converter characteristics (v cc = 2.5 2%, v ss = av ss = 0 v, ta = 20 to 85 c, f(x in ) = 4mhz, f(x cin ) = 32.768khz, unless otherwise noted) limits symbol t conv r ladder i vref i i(ad) v ref on v ref off table 29 easy thermal sensor electrical characteristics (v cc = 2.5v2%, v ss =av ss = 0v, ta = 20 to 85 c, f(x in ) = 4mhz, f(x cin ) = 32.768khz) limits parameter min. typ. max. symbol unit test conditions easy thermal sensor output voltage at room temperature the rate of the easy thermal sensor output voltage by temperature ta=27 c v cc = v ref = 2.5 v v mv/ c 1.38 3.4 table 30 current integrator electrical characteristics (v cc = av cc = 2.5v2%, v ss =av ss = 0v, ta = 20 to 85 c, f(x in ) = 4mhz, f(x cin ) = 32.768khz) limits parameter min. typ. max. symbol unit test conditions integrate period isens1 input range integrate coefficient of integrator for discharge integrate coefficient of integrator for charge reset time of integrator for discharge reset time of integrator for charge count value at 0v input internal reference voltage for discharge integrator internal reference voltage for charge integrator linearity error after reset time caribration v cc =2.5v2%, ta=0 to 60 c v cc =2.5v2%, ta= 20 to 85 c 0.2 1.35 1.35 2400 0.11 0.09 1 3 ms v v sec v sec ns ns v v % % t inf v isens1 a d a c t rd t rc b' v refd v refc 0.15 0.68 0.68 2400 0.09 0.11 125 1.00 1.00 300 300 0.1 0.1 fig. 79 current integrator timing diagram t rd , t rc t rd , t rc t rd , t rc t rd , t rc t rd , t rc t cal t inf t inf discharge signal for the integrator note : all signals are internals. 1.25v 0.75v 1.75v integrator output t inf
feb 18, 2005 page 81 of 85 rej03b0122-0101 7512 group fig. 80 v isens1 -count value characteristics of current integrator n d b = t inf v isens1 a d n d b = t inf v isens1 a d + t rd v isens1 v isens1 v refd isens1 input voltage n c = t inf ( v isens1 - c ) a c n c = t inf ( v isens1 - c ) a c + t rc ( v isens1 - c ) v refc b n refd c b = t inf b t inf - t rd b c = v refd b n refd - b char g e discharge count value table 31 over current detector electrical characteristics (v cc = av cc = 2.5v2%, v ss =av ss = 0v, ta = 20 to 85 c, f(x in ) = 4mhz, f(x cin ) = 32.768mhz) limits parameter min. typ. max. symbol unit conditions discharge short current detect voltage error discharge over current detect voltage error charge over current detect voltage error wake up detect voltage discharge short current detect time error discharge over current detect time error discharge over current detect time error wake up detect time 8 58.6 10 t.b.d. t.b.d. 15 15 15 12 30.5 62.5 mv mv mv mv s s ms
feb 18, 2005 page 82 of 85 rej03b0122-0101 7512 group reset input l pulse width external clock input cycle time external clock input h pulse width external clock input l pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input h pulse width cntr 0 , cntr 1 input l pulse width int 0 to int 3 input h pulse width int 0 to int 3 input l pulse width serial i/o1 clock input cycle time (note) serial i/o1 clock input h pulse width (note) serial i/o1 clock input l pulse width (note) serial i/o1 clock input set up time serial i/o1 clock input hold time serial i/o2 clock input cycle time serial i/o2 clock input h pulse width serial i/o2 clock input l pulse width serial i/o2 clock input set up time serial i/o2 clock input hold time t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (cntr) t wh (cntr) t wl (cntr) t wh (int) t wl (int) t c (s clk1 ) t wh (s clk1 ) t wl (s clk1 ) t su (r x d-s clk1 ) t h (s clk1 -r x d) t c (s clk2 ) t wh (s clk2 ) t wl (s clk2 ) t su (s in2 -s clk2 ) t h (s clk2 -s in2 ) limits x in cycles ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns parameter min. 20 250 100 100 500 230 230 230 230 2000 950 950 400 200 2000 950 950 400 300 typ. max. symbol unit note : when f(x in ) = 4 mhz and bit 6 of address 001a 16 is 1 (clock synchronous). divide this value by four when f(x in ) = 8 mhz and bit 6 of address 001a 16 is 0 (uart). table 33 switching characteristics (v cc = 2.5v2%, v ss = 0 v, ta = 20 to 85 c, unless otherwise noted) serial i/o1 clock output h pulse width serial i/o1 clock output l pulse width serial i/o1 output delay time (note 1) serial i/o1 output valid time (note 1) serial i/o1 clock output rising time serial i/o1 clock output falling time serial i/o2 clock output h pulse width serial i/o2 clock output l pulse width serial i/o2 output delay time (note 2) serial i/o2 output valid time (note 2) serial i/o2 clock output falling time cmos output rising time (note 3) cmos output falling time (note 3) t wh (s clk1 ) t wl (s clk1 ) t d (s clk1 -t x d) t v (s clk1 -t x d) t r (s clk1 ) t f (s clk1 ) t wh (s clk2 ) t wl (s clk2 ) t d (s clk2 -s out2 ) t v (s clk2 -s out2 ) t f (s clk2 ) t r (cmos) t f (cmos) limits ns ns ns ns ns ns ns ns ns ns ns ns ns parameter min. t c (s clk1 )/2 50 t c (s clk1 )/2 50 30 t c (s clk2 )/2 240 t c (s clk2 )/2 240 0 typ. 20 20 symbol unit notes 1: for t wh (s clk1 ), t wl (s clk1 ), when the p2 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0 . 2: when the p0 1 /s out2 and p0 2 /s clk2 p-channel output disable bit of the serial i/o2 control register (bit 7 of address 0015 16 ) is 0 . 3: the x out pin is excluded. max. 350 50 50 400 50 50 50 test conditions fig. 82 (v cc = 2.5v2%, v ss = 0 v, ta = 20 to 85 c, unless otherwise noted) timing requirements table 32 timing requirements
feb 18, 2005 page 83 of 85 rej03b0122-0101 7512 group m e a s u r e m e n t o u t p u t p i n 1 0 0 p f c m o s o u t p u t fig. 82 circuit for measuring output switching characteristics (1) symbol parameter unit multi-master i 2 c-bus bus line characteristics table 34 multi-master i 2 c-bus bus line characteristics bus free time hold time for start condition hold time for scl clock = 0 rising time of both scl and sda signals data hold time hold time for scl clock = 1 falling time of both scl and sda signals data setup time setup time for repeated start condition setup time for stop condition t buf t hd;sta t low t r t hd;dat t high t f t su;dat t su;sta t su;sto min. max. min. max. s s s ns s s ns ns s s standard clock mode high-speed clock mode note: c b = total capacitance of 1 bus line fig. 81 timing diagram of multi-master i 2 c-bus 4.7 4.0 4.7 0 4.0 250 4.7 4.0 1000 300 1.3 0.6 1.3 20+0.1c b (note) 0 0.6 20+0.1c b (note) 100 0.6 0.6 300 0.9 300 t buf t hd:sta t hd:dat t low t r t f t high t su:dat t su:sta t hd:sta t su:sto scl p s sr p sda s : start condition sr : restart condition p : stop condition fig. 83 circuit for measuring output switching characteristics (2) measurement output pin 100pf n-channel open-drain output 1k ?
feb 18, 2005 page 84 of 85 rej03b0122-0101 7512 group fig. 84 timing diagram t c(cntr) 0.2v cc t wl(int) 0.8v cc t wh(int) 0.2v cc 0.8v cc t w(reset) reset 0.2v cc t wl(cntr) 0.8v cc t wh(cntr) 0.2v cc 0.2v cc 0.8v cc 0.8v cc 0.2v cc t wl(x in ) 0.8v cc t wh(x in ) t c(x in ) x in t f t r t d(s clk1 -t x d), t d(s clk2 -s out2 ) t v(s clk1 -t x d), t v(s clk2 -s out2 ) t c(s clk1 ), t c(s clk2 ) t wl(s clk1 ), t wl(s clk2 ) t wh(s clk1 ), t wh(s clk2 ) t h(s clk1 - r x d), t h(s clk2 - s in2 ) t su(r x d - s clk1 ), t su(s in2 - s clk2 ) t x d s out2 r x d s in2 s clk1 s clk2 int 0 to int 3 cntr 0 cntr 1
feb 18, 2005 page 85 of 85 rej03b0122-0101 7512 group package outline lqfp48-p-77-0.50 e weight(g) e jedec code eiaj package code lead material cu alloy 48p6q-a plastic 48pin 7 ?
revision history rev. date description page summary (1/1) 7512 group data sheet 1.00 nov.10, 2004 first edition issued 1.01 feb.18, 2005 14 fig.11 ports p4 4 and p4 5 are partly revised.
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