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1 32, 64 meg x 72 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. sd9_18c32_64x72ag_a.p65 ? pub. 6/01 ?2001, micron technology, inc. 256mb / 512mb (x72, ecc) 168-pin sdram dimms advance pin symbol pin symbol pin symbol pin symbol 1v ss 43 v ss 85 v ss 127 v ss 2 dq0 44 n c 86 dq32 128 cke0 3 dq1 45 s2# 87 dq33 129 s3# 4 dq2 46 dqmb2 88 dq34 130 dqmb6 5 dq3 47 dqmb3 89 dq35 131 dqmb7 6v dd 48 n c 90 v dd 132 n c 7 dq4 49 v dd 91 dq36 133 v dd 8 dq5 50 n c 92 dq37 134 n c 9 dq6 51 n c 93 dq38 135 n c 10 dq7 52 cb2 94 dq39 136 cb6 11 dq8 53 cb3 95 dq40 137 cb7 12 v ss 54 v ss 96 v ss 138 v ss 13 dq9 55 dq16 97 dq41 139 dq48 14 dq10 56 dq17 98 dq42 140 dq49 15 dq11 57 dq18 99 dq43 141 dq50 16 dq12 58 dq19 100 dq44 142 dq51 17 dq13 59 v dd 101 dq45 143 v dd 18 v dd 60 dq20 102 v dd 144 dq52 19 dq14 61 n c 103 dq46 145 n c 20 dq15 62 n c 104 dq47 146 n c 21 cb0 63 cke1 105 cb4 147 nc 22 cb1 64 v ss 106 cb5 148 v ss 23 v ss 65 dq21 107 v ss 149 dq53 24 n c 66 dq22 108 n c 150 dq54 25 n c 67 dq23 109 n c 151 dq55 26 v dd 68 v ss 110 v dd 152 v ss 27 we# 69 dq24 111 cas# 153 dq56 28 dqmb0 70 dq25 112 dqmb4 154 dq57 29 dqmb1 71 dq26 113 dqmb5 155 dq58 30 s0# 72 dq27 114 s1# 156 dq59 31 n c 73 v dd 115 ras# 157 v dd 32 v ss 74 dq28 116 v ss 158 dq60 33 a0 75 dq29 117 a1 159 dq61 34 a2 76 dq30 118 a3 160 dq62 35 a4 77 dq31 119 a5 161 dq63 36 a6 78 v ss 120 a7 162 v ss 37 a8 79 ck2 121 a9 163 ck3 38 a10 80 n c 122 ba0 164 n c 39 ba1 81 wp 123 a11 165 sa0 40 v dd 82 sda 124 v dd 166 sa1 41 v dd 83 scl 125 ck1 167 sa2 42 ck0 84 v dd 126 a12 168 v dd pin assignment (front view) synchronous dram module mt9lsdt3272a - 256mb mt18lsdt6472a - 512mb for the latest data sheet, please refer to the micron web site: www.micron.com/datasheets features ? pc133- and pc100-compliant jedec-standard 168-pin, dual in-line memory module (dimm) utilizes 125 mhz and 133 mhz sdram components unbuffered ecc-optimized pinout 256mb (32 meg x 72) and 512mb (64 meg x 72) single +3.3v 0.3v power supply fully synchronous; all signals registered on positive edge of system clock internal pipelined operation; column address can be changed every clock cycle internal sdram banks for hiding row access/ precharge programmable burst lengths: 1, 2, 4, 8, or full page auto precharge and auto refresh modes self refresh mode 64ms, 8,192-cycle refresh lvttl-compatible inputs and outputs serial presence-detect (spd) options marking package 168-pin dimm (gold) g unbuffered a frequency/cas latency 133 mhz/cl = 2 -13e 133 mhz/cl = 3 -133 100 mhz/cl = 2 -10e 168-pin dimm device timing pc100 pc133 module markings cl - t rcd - t rp cl - t rcd - t rp -13e 2 - 2 - 2 2 - 2 - 2 -133 2 - 2 - 2 3 - 3 - 3 -10e 2 - 2 - 2 na address table 256mb module 512mb module refresh count 8k 8k device banks 4 (ba0, ba1) 4 (ba0, ba1) device configuration 32 meg x 8 32 meg x 8 row addressing 8k (a0?a12) 8k (a0?a12) column addressing 1k (a0?a9) 1k (a0?a9) module banks 1 (s0,s2) 2 (s0,s2; s1,s3)
2 32, 64 meg x 72 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. sd9_18c32_64x72ag_a.p65 ? pub. 6/01 ?2001, micron technology, inc. 256mb / 512mb (x72, ecc) 168-pin sdram dimms advance part numbers part number configuration system bus speed mt9lsdt3272ag-13e_ 32 meg x 72 133 mhz mt9lsdt3272ag-133_ 32 meg x 72 133 mhz mt9lsdt3272ag-10e_ 32 meg x 72 100 mhz mt18lsdt6472ag-13e_ 64 meg x 72 133 mhz mt18lsdt6472ag-133_ 64 meg x 72 133 mhz mt18lsdt6472ag-10e_ 64 meg x 72 100 mhz note : the designators for component and pcb revision are the last two characters of each part number. consult factory for current revision codes. example: mt18lsdt6472ag- 133 b1. general description the mt9lsdt3272a and mt18lsdt6472a are high-speed cmos, dynamic random-access, 256mb and 512mb memories organized in a x72 (ecc) con- figuration. these modules use internally configured quad-bank sdrams with a synchronous interface (all signals are registered on the positive edge of the clock signals ck0-ck3). read and write accesses to the sdram modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the regis- tration of an active command, which is then followed by a read or write command. the address bits regis- tered coincident with the active command are used to select the device bank and row to be accessed (ba0, ba1 select the device bank, a0-a12 select the device row). the address bits registered coincident with the read or write command are used to select the start- ing column location for the burst access. the modules provide for programmable read or write burst lengths of 1, 2, 4 or 8 locations, or the full page, with a burst terminate option. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. the modules use an internal pipelined architecture to achieve high-speed operation. this architecture is compatible with the 2 n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. precharging one device bank while accessing one of the other three device banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. the modules are designed to operate in 3.3v, low- power memory systems. an auto refresh mode is pro- vided, along with a power-saving, power-down mode. all inputs and outputs are lvttl-compatible. sdram modules offer substantial advances in dram operating performance, including the ability to syn-chronously burst data at a high data rate with au- tomatic column-address generation, the ability to in- terleave between internal device banks in order to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access. for more information regarding sdram opera- tion, refer to the 256mb sdram data sheet. serial presence-detect operation these modules incorporate serial presence-detect (spd). the spd function is implemented using a 2,048- bit eeprom. this nonvolatile storage device contains 256 bytes. the first 128 bytes can be programmed by micron to identify the module type and various sdram organizations and timing parameters. the remaining 128 bytes of storage are available for use by the cus- tomer. system read/write operations between the master (system logic) and the slave eeprom device (dimm) occur via a standard iic bus using the dimm?s scl (clock) and sda (data) signals, together with sa(2:0), which provide eight unique dimm/eeprom addresses.
3 32, 64 meg x 72 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. sd9_18c32_64x72ag_a.p65 ? pub. 6/01 ?2001, micron technology, inc. 256mb / 512mb (x72, ecc) 168-pin sdram dimms advance functional block diagram mt9lsdt3272a (256mb) note: 1. all resistor values are 10 ohms unless otherwise specified. 2. reference designators in this diagram do not necessarily match the actual module. dqm cs# u8 a0 sa0 spd sda a1 sa1 a2 sa2 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dqmb7 dqm cs# u6 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dqmb6 dqm cs# u4 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dqmb5 dqm cs# u2 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dqmb4 dqm cs# u9 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dqmb3 dqm cs# u7 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dqmb2 dqm cs# u3 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqmb1 dqm cs# u1 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqmb0 s2# s0# ras# cas# cke0 we# ras#: sdrams u1-u9 cas#: sdrams u1-u9 cke0: sdrams u1-u9 we#: sdrams u1-u9 a0-a12: sdrams u1-u9 ba0: sdrams u1-u9 ba1: sdrams u1-u9 a0-a12 ba0 ba1 dqm cs# u5 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 v dd v ss sdrams u1-u9 sdrams u1-u9 10pf ck1, ck3 u1 u2 u3 u4 u5 ck0 u6 u7 u8 u9 ck2 3.3pf scl wp 47k u1-u9= mt48lc32m8a2tg sdrams u10 2.2 f 2.2 f
4 32, 64 meg x 72 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. sd9_18c32_64x72ag_a.p65 ? pub. 6/01 ?2001, micron technology, inc. 256mb / 512mb (x72, ecc) 168-pin sdram dimms advance functional block diagram mt18lsdt3272a (512mb) note: 1. all resistor values are 10 ohms unless otherwise specified. 2. reference designators in this diagram do not necessarily match the actual module. dqm cs# u8 a0 sa0 spd sda a1 sa1 a2 sa2 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dqmb7 dqm cs# u6 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dqmb6 dqm cs# u4 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dqmb5 dqm cs# u2 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dqmb4 dqm cs# u9 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dqmb3 dqm cs# u7 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dqmb2 dqm cs# u3 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqmb1 dqm cs# u1 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqmb0 s2# s0# cke1 cke0 cas# ras# we# cke: sdrams u11-u19 cke: sdrams u1-u9 cas#: sdrams u1-u9; u11-u19 ras#: sdrams u1-u9; u11-u19 we#: sdrams u1-u9; u11-u19 a0-a12: sdrams u1-u9; u11-u19 ba0: sdrams u1-u9; u11-u19 ba1: sdrams u1-u9; u11-u19 a0-a12 ba0 ba1 dqm cs# u5 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 v dd v ss sdrams u1-u9; u11-u19 sdrams u1-u9; u11-u19 dqm cs# u12 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqm cs# u14 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqm cs# u16 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqm cs# u18 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 s1# dqm cs# u11 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqm cs# u13 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqm cs# u17 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqm cs# u19 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqm cs# u15 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 s3# v dd 10k u1 u2 u3 u4 u5 ck0 u6 u7 u8 u9 ck2 3.3pf u11 u12 u13 u14 ck3 3.3pf u15 u16 u17 u18 u19 ck1 scl wp 47k u1-u9; u11-u19 = mt48lc32m8a2tg sdrams 2.2 f 2.2 f u10
5 32, 64 meg x 72 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. sd9_18c32_64x72ag_a.p65 ? pub. 6/01 ?2001, micron technology, inc. 256mb / 512mb (x72, ecc) 168-pin sdram dimms advance pin descriptions pin numbers symbol type description 27, 111, 115 ras#, cas#, input command inputs: ras#, cas#, and we# (along with we# s0#-s3#) define the command being entered. 42, 79, 125, 163 ck0-ck3 input clock: ck0-ck3 are driven by the system clock. all sdram input signals are sampled on the positive edge of ck. ck also increments the internal burst counter and controls the output registers. 63, 128 cke1, cke0 input clock enable: cke0-cke1 activate (high) and deacti- vate (low) the ck0-ck3 signals. deactivating the clock provides precharge power-down and self refresh operation (all device banks idle), active power-down (row active in any device bank) or clock suspend operation (burst access in progress). cke0-cke1 are synchronous except after the device enters power-down and self refresh modes, where cke0-cke1 become asynchronous until after exiting the same mode. the input buffers, including ck0-ck3, are disabled during power-down and self refresh modes, providing low standby power. 30, 45, 114, 129 s0#-s3# input chip select: s0#-s3# enable (registered low) and disable (registered high) the command decoder. all commands are masked when s0#-s3# are registered high. s0#-s3# are considered part of the command code. 28-29, 46-47, dqmb0-dqmb7 input input/output mask: dqmb is an input mask signal for 112-113, 130-131 write accesses and an output enable signal for read accesses. input data is masked when dqmb is sampled high during a write cycle. the output buffers are placed in a high-z state (two-clock latency) when dqmb is sampled high during a read cycle. 39, 122 ba0, ba1 input bank address: ba0 and ba1 define to which device bank the active, read, write, or precharge command is being applied. 33, 34, 35, 36, 37, 38, a0-a12 input address inputs: a0-a12 are sampled during the active 117, 118, 119, 120, 121, command (row-address a0-a12) and read/write 123, 126 command (column-address a0-a9, with a10 defining auto precharge) to select one location out of the memory array in the respective device bank. a10 is sampled during a precharge command to determine if all device banks are to be precharged (a10 high) or device bank selected by ba0, ba1 (low). the address inputs also provide the op-code during a load mode register command. 81 wp input write protect: serial presence-detect hardware write protect. 83 scl input serial clock for presence-detect: scl is used to synchronize the presence-detect data transfer to and from the module.
6 32, 64 meg x 72 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. sd9_18c32_64x72ag_a.p65 ? pub. 6/01 ?2001, micron technology, inc. 256mb / 512mb (x72, ecc) 168-pin sdram dimms advance pin descriptions (continued) pin numbers symbol type description 165-167 sa0-sa2 input presence-detect address inputs: these pins are used to configure the presence-detect device. 2-5, 7-11, 13-17, 19-20, dq0-dq63 input/ data i/o: data bus. 55-58, 60, 65-67, 69-72, output 74-77, 86-89, 91-95, 97-101, 103-104, 139-142, 144, 149-151, 153-156, 158-161 21, 22, 52, 53, 105, 106, cb0-cb7 input/ check bits. 136, 137 output 82 sda input/ serial presence-detect data: sda is a bidirectional pin output used to transfer addresses and data into and data out of the presence-detect portion of the module. 1, 12, 23, 32, 43, 54, 64, v ss supply ground. 68, 78, 85, 96, 107, 116, 127, 138, 148, 152, 162 6, 18, 26, 40, 41, 49, 59, v dd supply power supply: +3.3v 0.3v. 73, 84, 90, 102, 110, 124, 133, 143, 157, 168 24, 25 31, 44, 48 61, 62, nc ? not connected: these pins are not connected on this 80, 108, 109, 134, 135, module. 145-147, 164
7 32, 64 meg x 72 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. sd9_18c32_64x72ag_a.p65 ? pub. 6/01 ?2001, micron technology, inc. 256mb / 512mb (x72, ecc) 168-pin sdram dimms advance sdram functional description in general, the 256mb sdrams are quad-bank drams that operate at 3.3v and include a synchro- nous interface (all signals are registered on the positive edge of the clock signal, clk). the four banks of the x8 configured devices used for these modules are config- ured as 8,192 bit-rows by 1,024 bit-columns, by 8 in- put/output bits. read and write accesses to the sdram are burst oriented; accesses start at a selected location and con- tinue for a programmed number of locations in a pro- grammed sequence. accesses begin with the registra- tion of an active command, which is then followed by a read or write command. the address bits regis- tered coincident with the active command are used to select the device bank and row to be accessed; ba0 and ba1 select the device bank, a0?a12 select the de- vice row. the address bits a0?a9 registered coincident with the read or write command are used to select the starting column location for the burst access. prior to normal operation, the sdram must be ini- tialized. the following sections provide detailed infor- mation covering device initialization, register defini- tion, command descriptions and device operation. initialization sdrams must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined opera- tion. once power is applied to v dd and v dd q (simulta- neously) and the clock is stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the sdram requires a 100s delay prior to issuing any command other than a command inhibit or nop. starting at some point during this 100s period and continuing at least through the end of this period, command inhibit or nop commands should be applied. once the 100s delay has been satisfied with at least one command inhibit or nop command hav- ing been applied, a precharge command should be applied. all device banks must then be precharged, thereby placing the device in the all banks idle state. once in the idle state, two auto refresh cycles must be performed. after the auto refresh cycles are complete, the sdram is ready for mode register programming. because the mode register will power up in an unknown state, it should be loaded prior to applying any operational command. register definition mode register the mode register is used to define the specific mode of operation of the sdram. this definition includes the selection of a burst length, a burst type, a cas latency, an operating mode and a write burst mode, as shown in the mode register definition diagram (pg. 8). the mode register is programmed via the load mode register command and will retain the stored information until it is programmed again or the device loses power. mode register bits m0?m2 specify the burst length, m3 specifies the type of burst (sequential or inter- leaved), m4?m6 specify the cas latency, m7 and m8 specify the operating mode, m9 specifies the write burst mode, and m10 and m11 are reserved for future use. address a12 (m12) is undefined but should be driven low during loading of the mode register. the mode register must be loaded when all device banks are idle, and the controller must wait the speci- fied time before initiating the subsequent operation. violating either of these requirements will result in unspecified operation. burst length read and write accesses to the sdram are burst oriented, with the burst length being programmable, as shown in the mode register definition diagram (pg. 8). the burst length determines the maximum num- ber of column locations that can be accessed for a given read or write command. burst lengths of 1, 2, 4, or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is avail- able for the sequential type. the full-page burst is used in conjunction with the burst terminate com- mand to generate arbitrary burst lengths. reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to the burst length is effectively se- lected. all accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached, as shown in the burst defini- tion table (pg. 8). the block is uniquely selected by a1?a9 when the burst length is set to two; by a2?a9 when the burst length is set to four; and by a3?a9 when the burst length is set to eight. the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. full-page bursts wrap within the page if the boundary is reached, as shown in the burst definition table (pg. 8).
8 32, 64 meg x 72 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. sd9_18c32_64x72ag_a.p65 ? pub. 6/01 ?2001, micron technology, inc. 256mb / 512mb (x72, ecc) 168-pin sdram dimms advance burst definition table burst starting column o rder of accesses within a burst length a ddress: type = sequential type = interleaved a0 2 0 0-1 0-1 1 1-0 1-0 a1 a0 0 0 0-1-2-3 0-1-2-3 4 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 8 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 full n = a0-a11/9/8 cn, cn + 1, cn + 2 page cn + 3, cn + 4... not supported (y) (location 0-y) ? cn - 1, cn ? mode register definition diagram burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit m3. the ordering of accesses within a burst is deter- mined by the burst length, the burst type and the start- ing column address, as shown in the burst definition table. m3 = 0 1 2 4 8 reserved reserved reserved full page m3 = 1 1 2 4 8 reserved reserved reserved reserved operating mode standard operation all other states reserved 0 - 0 - defined - 0 1 burst type sequential interleaved cas latency reserved reserved 2 3 reserved reserved reserved reserved burst length m0 0 1 0 1 0 1 0 1 burst length cas latency bt a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 9 7 654 3 8 2 1 0 m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 m3 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 m6-m0 m8 m7 op mode a10 a11 10 11 reserved* wb 0 1 write burst mode programmed burst length single location access m9 *should program m12, m11, m10 = ? 0, 0, 0 ? to ensure compatibility with future devices. a12 12 note: 1. for full-page accesses: y = 1,024 . 2. for a burst length of two, a1-a9 select the block- of-two burst; a0 selects the starting column within the block. 3. for a burst length of four, a2-a9 select the block- of-four burst; a0-a1 select the starting column within the block. 4. for a burst length of eight, a3-a9 select the block- of-eight burst; a0-a2 select the starting column within the block. 5. for a full-page burst, the full row is selected and a0-a9 select the starting column. 6. whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. for a burst length of one, a0-a9 select the unique column to be accessed, and mode register bit m3 is ignored.
9 32, 64 meg x 72 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. sd9_18c32_64x72ag_a.p65 ? pub. 6/01 ?2001, micron technology, inc. 256mb / 512mb (x72, ecc) 168-pin sdram dimms advance operating mode the normal operating mode is selected by setting m7 and m8 to zero; the other combinations of values for m7 and m8 are reserved for future use and/or test modes. the programmed burst length applies to both read and write bursts. test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. write burst mode when m9 = 0, the burst length programmed via m0-m2 applies to both read and write bursts; when m9 = 1, the programmed burst length applies to read bursts, but write accesses are single-location (nonburst) accesses. cas latency the cas latency is the delay, in clock cycles, be- tween the registration of a read command and the availability of the first piece of output data. the la- tency can be set to two or three clocks. if a read command is registered at clock edge n , and the latency is m clocks, the data will be available by clock edge n + m . the dqs will start driving as a result of the clock edge one cycle earlier ( n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m . for example, assuming that the clock cycle time is such that all relevant access times are met, if a read command is registered at t0 and the latency is programmed to two clocks, the dqs will start driving after t1 and the data will be valid by t2, as shown in the cas latency diagram. the cas latency table indicates the operating frequencies at which each cas latency setting can be used. reserved states should not be used as unknown operation or incompatibility with future versions may result. cas latency diagram clk dq t2 t1 t3 t0 cas latency = 3 lz d out t oh t command nop read t ac nop t4 nop don ? t care undefined clk dq t2 t1 t3 t0 cas latency = 2 lz d out t oh t command nop read t ac nop cas latency table allowable operating frequency (mhz) cas cas speed latency = 2 latency = 3 -13e 133 143 -133 100 133 -10e 100 125
10 32, 64 meg x 72 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. sd9_18c32_64x72ag_a.p65 ? pub. 6/01 ?2001, micron technology, inc. 256mb / 512mb (x72, ecc) 168-pin sdram dimms advance commands the truth table provides a quick reference of avail- able commands. this is followed by written descrip- tion of each command. for a more detailed description truth table ? sdram commands and dqmb operation (note: 1, notes appear below table) name (function) cs# ras# cas# we# dqmb addr dqs notes command inhibit (nop) h x x x x x x no operation (nop) l h h h x x x active (select bank and activate row) l l h h x bank/row x 3 read (select bank and column, and start read burst) l h l h l/h 8 bank/col x 4 write (select bank and column, and start write burst) l h l l l/h 8 bank/col valid 4 burst terminate l h h l x x active precharge (deactivate row in bank or banks) l l h l x code x 5 auto refresh or l l l h x x x 6, 7 self refresh (enter self refresh mode) load mode register l l l l x op-code x 2 write enable/output enable ? ??? l ? active 8 write inhibit/output high-z ? ??? h ? high-z 8 note: 1. cke is high for all commands shown except self refresh. 2. a0-a11 define the op-code written to the mode register,.and a12 should be driven low 3. a0-a12 provide row address, and ba0, ba1 determine which device bank is made active. 4. a0-a9 provide column address; a10 high enables the auto precharge feature (nonpersistent), while a10 low disables the auto precharge feature; ba0, ba1 determine which device bank is being read from or written to. 5. a10 low: ba0, ba1 determine which device bank is being precharged. a10 high: all device banks are precharged and ba0, ba1 are ? don ? t care. ? 6. this command is auto refresh if cke is high, self refresh if cke is low. 7. internal refresh counter controls row addressing; all inputs and i/os are ? don ? t care ? except for cke. 8. activates or deactivates the dqs during writes (zero-clock delay) and reads (two-clock delay). of commands and operations, refer to the 256mb sdram component data sheet.
11 32, 64 meg x 72 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. sd9_18c32_64x72ag_a.p65 ? pub. 6/01 ?2001, micron technology, inc. 256mb / 512mb (x72, ecc) 168-pin sdram dimms advance absolute maximum ratings* voltage on v dd , v dd q supply relative to v ss ....................................... -1v to +4.6v voltage on inputs, nc or i/o pins relative to v ss ....................................... -1v to +4.6v operating temperature, t a .................................................................................. 0c to +70c storage temperature (plastic) ............ -55c to +150c power dissipation, 256mb ......................................... 9w power dissipation, 512mb ....................................... 18w *stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. dc electrical characteristics and operating conditions - 256mb module (notes: 1, 5, 6; notes appear following parameter tables); (v dd , v dd q = +3.3v 0.3v) parameter/condition symbol min max units notes supply voltage v dd , v dd q 3 3.6 v input high voltage: logic 1; all inputs v ih 2v dd + 0.3 v 22 input low voltage: logic 0; all inputs v il -0.3 0.8 v 22 input leakage current: any input 0v v in v dd i i -45 45 a (all other pins not under test = 0v) output leakage current: dqs are disabled; i oz -5 5 a 0v v out v dd q output levels: v oh 2.4 ? v output high voltage (i out = -4ma) output low voltage (i out = 4ma) v ol ? 0.4 v dc electrical characteristics and operating conditions - 512mb module (notes: 1, 5, 6; notes appear following parameter tables); (v dd , v dd q = +3.3v 0.3v) parameter/condition symbol min max units notes supply voltage v dd , v dd q 3 3.6 v input high voltage: logic 1; all inputs v ih 2v dd + 0.3 v 22 input low voltage: logic 0; all inputs v il -0.3 0.8 v 22 input leakage current: any input 0v v in v dd i i -90 90 a (all other pins not under test = 0v) output leakage current: dqs are disabled; i oz -10 10 a 0v v out v dd q output levels: v oh 2.4 ? v output high voltage (i out = -4ma) output low voltage (i out = 4ma) v ol ? 0.4 v
12 32, 64 meg x 72 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. sd9_18c32_64x72ag_a.p65 ? pub. 6/01 ?2001, micron technology, inc. 256mb / 512mb (x72, ecc) 168-pin sdram dimms advance max *dram components only. i dd specifications and conditions*: 512mb module (notes: 1, 6, 11, 13; notes appear following parameter tables) (v dd , v dd q = +3.3v 0.3v) parameter/condition symbol -13e -133 -10e units notes operating current: active mode; i dd 1 ? 1,188 1,143 1,143 ma 3, 18, burst = 2; read or write; t rc = t rc (min) 19, 30 standby current: power-down mode; i dd 2 ? 36 36 36 ma 30 all banks idle; cke = low standby current: active mode; i dd 3 ? 423 423 423 ma 3, 12, cke = high; cs# = high; all banks active after t rcd met; 19, 30 no accesses in progress operating current: burst mode; continuous burst; i dd 4 ? 1,233 1,233 1,233 ma 3, 18, read or write; all banks active 19, 30 auto refresh current t rfc = t rfc (min) i dd 5 ? 5,130 4,860 4,860 ma 3, 12, cs# = high; cke = high t rfc = 7.81 s i dd 6 ? 72 72 72 ma 18, 19, 30, 31 self refresh current: cke 0.2v standard i dd 7 ? 45 45 45 ma 4 max *dram components only. ?value calculated as one module bank in this operating condition, and all other module banks in power-down mode. ?value calculated reflects all module banks in this operating condition. i dd specifications and conditions*: 256mb module (notes: 1, 5, 6, 11, 13; notes appear following the parameter tables); (v dd , v dd q = +3.3v 0.3v) parameter/condition symbol -13e -133 -10e units notes operating current: active mode; i dd 1 1,188 1,143 1,143 ma 3, 18, burst = 2; read or write; t rc = t rc (min) 19, 30 standby current: power-down mode; i dd 2 18 18 18 ma 30 all banks idle; cke = low standby current: active mode; i dd 3 423 423 423 ma 3, 12, cke = high; cs# = high; all banks active after t rcd met; 19, 30 no accesses in progress operating current: burst mode; continuous burst; i dd 4 1,233 1,233 1,233 ma 3, 18, read or write; all banks active 19, 30 auto refresh current t rfc = t rfc (min) i dd 5 2,565 2,430 2,430 ma 3, 12, cke = high; cs# = high t rfc = 7.81s i dd 6 36 36 36 ma 18, 19, 30, 31 self refresh current: cke 0.2v standard i dd 7 23 23 23 ma 4
13 32, 64 meg x 72 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. sd9_18c32_64x72ag_a.p65 ? pub. 6/01 ?2001, micron technology, inc. 256mb / 512mb (x72, ecc) 168-pin sdram dimms advance 256mb 512mb capacitance (note 2; notes appear following parameter tables) parameter symbol min max min max units input capacitance: a0-a12, ba0, ba1, ras#, c i 1 22.5 34.2 45 68.4 p f cas#, we# input capacitance: ck0-ck1 c i 2 a 12.5 17.5 12.5 17.5 p f input capacitance: ck2-ck3 c i 2 b 13.3 17.3 13.3 17.3 p f input capacitance: s0#-s1# c i 3 a 12.5 19 12.5 19 p f input capacitance: s2#-s3# c i 3 b 10 15.2 10 15.2 p f input capacitance: cke0, cke1 c i 4 22.5 34.2 22.5 34.2 p f input capacitance: dqmb0, 2-4, 6, 7 c i 5 a 2.5 3.8 5 7.6 p f input capacitance: dqmb1, dqmb5 c i 5 b 5 7.6 7.5 11.4 p f input/output capacitance: scl, sa0-sa2, sda c i 6 ? 10 ? 10 p f input/output capacitance: dq0-dq63, cb0-cb7 c io 4 6 8 12 pf
14 32, 64 meg x 72 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. sd9_18c32_64x72ag_a.p65 ? pub. 6/01 ?2001, micron technology, inc. 256mb / 512mb (x72, ecc) 168-pin sdram dimms advance *module ac timing parameters comply with pc133 design specs, based on component parameters. electrical characteristics and recommended ac operating conditions (notes: 5, 6, 8, 9, 11; notes appear following parameter tables) ac characteristics -13e -133 -10e parameter symbol min max min max min max units notes access time from cl = 3 t ac(3) 5.4 5.4 6 ns 27 clk (pos. edge) cl = 2 t ac(2) 5.4 6 6 ns address hold time t ah 0.8 0.8 1 ns address setup time t as 1.5 1.5 2 ns clk high-level width t ch 2.5 2.5 3 ns clk low-level width t cl 2.5 2.5 3 ns clock cycle time cl = 3 t ck(3) 7 7.5 8 ns 23 cl = 2 t ck(2) 7.5 10 10 ns 23 cke hold time t ckh 0.8 0.8 1 ns cke setup time t cks 1.5 1.5 2 ns cs#, ras#, cas#, we#, dqm hold time t cmh 0.8 0.8 1 ns cs#, ras#, cas#, we#, dqm setup time t cms 1.5 1.5 2 ns data-in hold time t dh 0.8 0.8 1 ns data-in setup time t ds 1.5 1.5 2 ns data-out high-impedance cl = 3 t hz(3) 5.4 5.4 6 ns 10 time cl = 2 t hz(2) 5.4 6 6 ns 10 data-out low-impedance time t lz 1 1 1 ns data-out hold time (load) t oh 3 3 3 ns data-out hold time (no load) t oh n 1.8 1.8 1.8 ns 28 active to precharge command t ras 37 120,000 44 120,000 50 120,000 ns 29 active to active command period t rc 60 66 70 ns active to read or write delay t rcd 15 20 20 ns refresh period (8,192 rows) t ref 64 64 64 ms auto refresh period t rfc 66 66 70 ns precharge command period t rp 15 20 20 ns active bank a to active bank b command t rrd 14 15 20 ns transition time t t 0.3 1.2 0.3 1.2 0.3 1.2 ns 7 write recovery time t wr 1 clk + 1 clk + 1 clk + ns 24 7ns 7.5ns 7ns 14 15 15 ns 25 exit self refresh to active command t xsr 67 75 80 ns 20
15 32, 64 meg x 72 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. sd9_18c32_64x72ag_a.p65 ? pub. 6/01 ?2001, micron technology, inc. 256mb / 512mb (x72, ecc) 168-pin sdram dimms advance ac functional characteristics (notes: 5, 6, 7, 8, 9, 11; notes appear following parameter tables) parameter symbol -13e -133 -10e units notes read/write command to read/write command t ccd 1 1 1 t ck 17 cke to clock disable or power-down entry mode t cked 1 1 1 t ck 14 cke to clock enable or power-down exit setup mode t ped 1 1 1 t ck 14 dqm to input data delay t dqd 0 0 0 t ck 17 dqm to data mask during writes t dqm 0 0 0 t ck 17 dqm to data high-impedance during reads t dqz 2 2 2 t ck 17 write command to input data delay t dwd 0 0 0 t ck 17 data-in to active command t dal 4 5 4 t ck 15, 21 data-in to precharge command t dpl 2 2 2 t ck 16, 21 last data-in to burst stop command t bdl 1 1 1 t ck 17 last data-in to new read/write command t cdl 1 1 1 t ck 17 last data-in to precharge command t rdl 2 2 2 t ck 16, 21 load mode register command to active or refresh command t mrd 2 2 2 t ck 26 data-out to high-impedance from precharge command cl = 3 t roh(3) 3 3 3 t ck 17 cl = 2 t roh(2) 2 2 2 t ck 17
16 32, 64 meg x 72 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. sd9_18c32_64x72ag_a.p65 ? pub. 6/01 ?2001, micron technology, inc. 256mb / 512mb (x72, ecc) 168-pin sdram dimms advance 14. timing actually specified by t cks; clock(s) speci- fied as a reference only at minimum cycle rate. 15. timing actually specified by t wr plus t rp; clock(s) specified as a reference only at minimum cycle rate. 16. timing actually specified by t wr. 17. required clocks are specified by jedec function- ality and are not dependent on any timing param- eter. 18. the i dd current will increase or decrease propor- tionally according to the amount of frequency al- teration for the test condition. 19. address transitions average one transition every two clocks. 20. clk must be toggled a minimum of two times dur- ing this period. 21. based on t ck = 10ns for -10e, and t ck = 7.5ns for - 133 and -13e. 22. v ih overshoot: v ih (max) = v dd q + 2v for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. v il undershoot: v il (min) = -2v for a pulse width 3ns. 23. the clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during ac- cess or precharge states (read, write, including t wr, and precharge commands). cke may be used to reduce the data rate. 24. auto precharge mode only. the precharge timing budget ( t rp) begins 7ns for -13e; 7.5ns for -133 and 7ns for -10e after the first clock delay, after the last write is executed. may not exceed limit set for precharge mode. 25. precharge mode only. 26. jedec and pc100 specify three clocks. 27. t ac for -133/-13e at cl = 3 with no load is 4.6ns and is guaranteed by design. 28. parameter guaranteed by design. 29. the value of t ras. use in -13e speed grade module spds is calculated from t rc - t rp = 45ns. 30. for -10e, cl= 2 and t ck = 10ns; for -133, cl = 3 and t ck = 7.5ns; for -13e, cl = 2 and t ck = 7.5ns. 31. cke is high during refresh command period t rfc (min) else cke is low. the i dd 6 limit is actu- ally a nominal value and does not result in a fail value. notes 1. all voltages referenced to v ss . 2. this parameter is sampled. v dd , v dd q = +3.3v; f = 1 mhz, t a = 25c; pin under test biased at 1.4v. 3. i dd is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time and the outputs open. 4. enables on-chip refresh and address counters. 5. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured (0c t a +70c). 6. an initial pause of 100s is required after power- up, followed by two auto refresh commands, before proper device operation is ensured. (v dd and v dd q must be powered up simultaneously. v ss and v ss q must be at same potential.) the two auto refresh command wake-ups should be repeated any time the t ref refresh requirement is exceeded. 7. ac characteristics assume t t = 1ns. 8. in addition to meeting the transition rate specifi- cation, the clock and cke must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 9. outputs measured at 1.5v with equivalent load: q 50pf 10. t hz defines the time at which the output achieves the open circuit condition; it is not a reference to v oh or v ol . the last valid data element will meet t oh before going high-z. 11. ac timing and i dd tests have v il = 0v and v ih = 3v, with timing referenced to 1.5v crossover point. if the input transition time is longer than 1 ns, then the timing is referenced at v il (max) and v ih (min) and no longer at the 1.5v crossover point. 12. other input signals are allowed to transition no more than once every two clocks and are otherwise at valid v ih or v il levels. 13. i dd specifications are tested after the device is prop- erly initialized.
17 32, 64 meg x 72 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. sd9_18c32_64x72ag_a.p65 ? pub. 6/01 ?2001, micron technology, inc. 256mb / 512mb (x72, ecc) 168-pin sdram dimms advance scl sda data stable data stable data change figure 1 data validity scl sda start bit stop bit figure 2 definition of start and stop scl from master data output from transmitter data output from receiver 9 8 acknowledge figure 3 acknowledge response from receiver spd clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions (fig- ures 1 and 2). spd start condition all commands are preceded by the start condition, which is a high-to-low transition of sda when scl is high. the spd device continuously monitors the sda and scl lines for the start condition and will not re- spond to any command until this condition has been met. spd stop condition all communications are terminated by a stop condi- tion, which is a low-to-high transition of sda when scl is high. the stop condition is also used to place the spd device into standby power mode. spd acknowledge acknowledge is a software convention used to indi- cate successful data transfers. the transmitting de- vice, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle, the receiver will pull the sda line low to acknowledge that it received the eight bits of data (figure 3). the spd device will always respond with an ac- knowledge after recognition of a start condition and its slave address. if both the device and a write opera- tion have been selected, the spd device will respond with an acknowledge after the receipt of each subse- quent eight-bit word. in the read mode the spd device will transmit eight bits of data, release the sda line and monitor the line for an acknowledge. if an acknowl- edge is detected and no stop condition is generated by the master, the slave will continue to transmit data. if an acknowledge is not detected, the slave will termi- nate further data transmissions and await the stop con- dition to return to standby power mode.
18 32, 64 meg x 72 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. sd9_18c32_64x72ag_a.p65 ? pub. 6/01 ?2001, micron technology, inc. 256mb / 512mb (x72, ecc) 168-pin sdram dimms advance scl sda in sda out t low t su:sta t hd:sta t f t high t r t buf t dh t aa t su:sto t su:dat t hd:dat undefined spd eeprom timing diagram symbol min max units t aa 0.3 3.5 s t buf 4.7 s t dh 300 ns t f 300 ns t hd:dat 0 s t hd:sta 4 s symbol min max units t high 4 s t low 4.7 s t r1s t su:dat 250 ns t su:sta 4.7 s t su:sto 4.7 s serial presence-detect eeprom timing parameters eeprom device select code (the most significant bit (b7) is sent first) device type identifier chip enable rw b7 b6 b5 b4 b3 b2 b1 b0 memory area select code (two arrays) 1 0 1 0 e2 e1 e0 rw protection register select code 0 1 1 0 e2 e1 e0 rw eeprom operating modes (x = v ih or v il ) mode rw bit wc 1 bytes initial sequence current address read 1 x 1 start, device select, rw = 1 random address read 0 x 1 start, device select, rw = 0, address 1 x restart, device select, rw = 1 sequential read 1 x 1 similar to current or random address read byte write 0 v il 1 start, device select, rw = 0 page write 0 v il 16 start, device select, rw = 0
19 32, 64 meg x 72 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. sd9_18c32_64x72ag_a.p65 ? pub. 6/01 ?2001, micron technology, inc. 256mb / 512mb (x72, ecc) 168-pin sdram dimms advance serial presence-detect eeprom ac operating conditions (note: 1) (v dd = +3.3v 0.3v) parameter/condition symbol min max units notes scl low to sda data-out valid t aa 0.3 3.5 s time the bus must be free before a new transition can start t buf 4.7 s data-out hold time t dh 300 ns sda and scl fall time t f 300 ns data-in hold time t hd:dat 0 s start condition hold time t hd:sta 4 s clock high period t high 4 s noise suppression time constant at scl, sda inputs t i 100 ns clock low period t low 4.7 s sda and scl rise time t r1s scl clock frequency t scl 100 khz data-in setup time t su:dat 250 ns start condition setup time t su:sta 4.7 s stop condition setup time t su:sto 4.7 s write cycle time t wrc 10 ms 2 serial presence-detect eeprom dc operating conditions (note: 1) (v dd = +3.3v 0.3v) parameter/condition symbol min max units supply voltage v dd 3 3.6 v input high voltage: logic 1; all inputs v ih v dd x 0.7 v dd + 0.5 v input low voltage: logic 0; all inputs v il -1 v dd x 0.3 v output low voltage: i out = 3ma v ol ? 0.4 v input leakage current: v in = gnd to v dd i li ? 10 a output leakage current: v out = gnd to v dd i lo ? 10 a standby current: i sb ? 30 a scl = sda = v dd - 0.3v; all other inputs = gnd or 3.3v +10% power supply current: i cc ? 2ma scl clock frequency = 100 khz note: 1. all voltages referenced to v ss . 2. the spd eeprom write cycle time ( t wrc) is the time from a valid stop condition of a write sequence to the end of the eeprom internal erase/program cycle. during the write cycle, the eeprom bus interface circuit is disabled, sda remains high due to pull-up resistor, and the eeprom does not respond to its slave address.
20 32, 64 meg x 72 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. sd9_18c32_64x72ag_a.p65 ? pub. 6/01 ?2001, micron technology, inc. 256mb / 512mb (x72, ecc) 168-pin sdram dimms advance serial presence-detect matrix byte description entry (v ersion) m t9lsdt3272ag mt18lsdt6472a 0 number of bytes used by micron 128 80 80 1 total number of spd memory bytes 256 08 08 2 memory type sdram 04 04 3 number of row addresses 13 0d 0d 4 number of column addresses 10 0a 0a 5 number of banks 1 or 2 01 02 6 module data width 72 48 48 7 module data width (continued) 0 00 00 8 module voltage interface levels lvttl 01 01 9 sdram cycle time, t ck 7.5 (-13e) 70 75 (cas latency = 3) 7.5 (-133) 75 75 8 (-10e) 80 80 10 sdram access from clk , t ac 5.4 (-13e/-133) 54 54 (cas latency = 3) 6 (-10e) 60 60 11 module configuration type ecc 02 02 12 refresh rate/type 7.81s/self 82 82 13 sdram width (primary sdram) 8 08 08 14 error-checking sdram data width 8 08 08 15 minimum clock delay from back-to-back 1 01 01 random column addresses, t ccd 16 burst lengths supported 1, 2, 4, 8, page 8f 8f 17 number of banks on sdram device 4 04 04 18 cas latencies supported 2, 3 06 06 19 cs latency 0 01 01 20 we latency 0 01 01 21 sdram module attributes unbuffered 00 00 22 sdram device attributes: general 0e 0e 0e 23 sdram cycle time, t ck 7.5 (-13e) 75 75 (cas latency = 2) 10 (-133/-10e) a0 a0 24 sdram access from clk, t ac 5.4 (-13e) 54 54 (cas latency = 2) 6 (-133/-10e) 60 60 25 sdram cycle time, t ck ? 00 00 (cas latency = 1) 26 sdram access from clk, t ac ? 00 00 (cas latency = 1) 27 minimum row precharge time, t rp 15 (-13e) 0f of 20 (-133/-10e) 14 14 28 minimum row active to row active, t rrd 14 (-13e) 0e 0e 15 (-133) 0f 0f 20 (-10e) 14 14 29 minimum ras# to cas# delay, t rcd 15 (-13e) 0f 0f 20 (-133/-10e) 14 14 30 minimum ras# pulse width, t ras 45 (-13e) 2d 2d ( t ras module = t rc - t rp) 44 (-133) 2c 2c note 2 50 (-10e) 32 32 31 module bank density 256mb 40 40 32 command and address setup time, t as, t cms 1.5 (-13e/-133) 15 15 2 (-10e) 20 20 note: 1. ? 1 ? / ? 0 ? : serial data, ? driven to high ? / ? driven to low. ? 2. the value of t ras used for -13e modules is calculated from t rc - t rp. actual device spec. value is 37ns.
21 32, 64 meg x 72 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. sd9_18c32_64x72ag_a.p65 ? pub. 6/01 ?2001, micron technology, inc. 256mb / 512mb (x72, ecc) 168-pin sdram dimms advance serial presence-detect matrix (continued) byte description entry (v ersion) m t9lsdt3272ag mt18lsdt6472a 33 command and address hold time, t ah, t cmh 0.8 (-13e) 08 08 0.8 (-133) 08 08 1 (10e) 10 10 34 data signal input setup time, t ds 1.5 (-13e) 15 15 1.5 (-133) 15 15 2 (-10e) 20 20 35 data signal input hold time, t dh 0.8 (-13e) 08 08 0.8 (-133) 08 08 1 (-10e) 10 10 36-61 reserved 00 00 62 spd revision rev. 1.2 12 12 63 checksum for bytes 0-62 (-13e) 9d 9e (-133) e3 e4 (-10e) 2b 2c 64 manufacturer ? s jedec id code mi cron 2c 2c 65-71 manufacturer ? s jedec id code (cont.) ff ff 72 manufacturing location 01 01 02 02 03 03 04 04 05 05 06 06 07 07 08 08 73-90 module part number (ascii) xx xx 91 pcb identification code 1 01 01 202 02 303 03 404 04 505 05 606 06 707 07 808 08 909 09 92 identification code (cont.) 0 00 00 93 year of manufacture in bcd xx xx 94 week of manufacture in bcd xx xx 95-98 module serial number xx xx 99-125 manufacturer-specific data (rsvd) ?? 126 system frequency 100 mhz (- 13e/-133/-10e) 64 64 127 sdram component & clock detail af ff note: 1. ? 1 ? / ? 0 ? : serial data, ? driven to high ? / ? driven to low. ? 2. x = variable data.
22 32, 64 meg x 72 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. sd9_18c32_64x72ag_a.p65 ? pub. 6/01 ?2001, micron technology, inc. 256mb / 512mb (x72, ecc) 168-pin sdram dimms advance note: 1. all dimensions in inches (millimeters) max or typical where noted. min 256mb module .125 (3.18) max .054 (1.37) .046 (1.17) pin 1 (pin 85 on backside) .700 (17.78) typ .118 (3.00) (2x) .118 (3.00) typ 4.550 (115.57) .050 (1.27) typ .118 (3.00) typ .039 (1.00) typ .079 (2.00) r (2x) .039 (1.00)r (2x) front view .128 (3.25) .118 (3.00) pin 84 (pin 168 on backside) (2x) .250 (6.35) typ 1.661 (42.18) 2.625 (66.68) 1.131 (28.73) 1.119 (28.42) 5.256 (133.50) 5.244 (133.20)
23 32, 64 meg x 72 sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. sd9_18c32_64x72ag_a.p65 ? pub. 6/01 ?2001, micron technology, inc. 256mb / 512mb (x72, ecc) 168-pin sdram dimms advance 512mb module note: 1. all dimensions in inches (millimeters) max or typical where noted. min 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www.micron.com, customer comment line: 800-932-4992 micron is a registered trademark and the micron logo and m logo are trademarks of micron technology, inc. .157 (4.00) max .054 (1.37) .046 (1.17) pin 1 (pin 85 on back side) .700 (17.78) typ .118 (3.00) (2x) .118 (3.00) typ 4.550 (115.57) .050 (1.27) typ .118 (3.00) typ .039 (1.00) typ .079 (2.00) r (2x) .039 (1.00)r (2x) front view .128 (3.25) .118 (3.00) pin 84 (pin 168 on back side) (2x) .250 (6.35) typ 1.661 (42.18) 2.625 (66.68) 1.131 (28.73) 1.119 (28.42) 5.256 (133.50) 5.244 (133.20) back view pin 168 (pin 84 on front side) pin 85 (pin 1 on front side)

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