? products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by micron without notice. products are only warranted by micron to meet micron?s production data sheet specifications. 09005aef80b2cb48 128mbx16ddr_ptpadd.fm - rev. a 4/04 en 1 ?2004 micron technology, inc. all rights reserved. 128mb: x16 graphical ddr sdram addendum preliminary ? double data rate (ddr) sdram mt46v8m16 ? 2 megx16x4 banks for the latest data sheet revisions, please refer to the micron website: www.micron.com/dramds features ? 200 mhz clock, 400 mb/s/p data rate bidirectional data strobe (dqs) transmitted/ received with data, i.e., source-synchronous data capture internal, pipelined do uble-data-rate (ddr) architecture; two data accesses per clock cycle differential clock inputs (ck and ck#) commands entered on each positive ck edge dqs edge-aligned with data for reads; center- aligned with data for writes dll to align dq and dqs transitions with ck four internal banks for concurrent operation data mask (dm) for masking write data programmable burst lengths: 2, 4, or 8 concurrent auto precharge option supported auto refresh and self refresh modes t ras lockout ( t rap = t rcd) single cas latency cl=3 general description the ddr sdram is a high-speed cmos, dynamic random-access memory that operates at a frequency of 200 mhz ( t ck=5ns) with a peak data transfer rate of 400mb/s/p ddr400 continues to use the 2 n -prefetch architecture. the standard ddr266 data sheet provides a com- plete description of ddr sdram functionality and operating modes. it provides full specifications and functionality unless specified herein. this addendum data sheet concentrates on the critical parameters and key differences required to support the enhanced ddr point to point speeds. options marking configuration 8 meg x 16 (4 meg x 16 x 4 banks) 8m816 plastic package 66-pin tsop (400 mil with 0.65mm pin pitch) tg 66-pin tsop (400 mil with 0.65mm pin pitch) lead free p timing - cycle time 5ns @ cl = 3 -5g 6ns @ cl = 3 -6g self refresh standard none table 1: configuration architecture 16 meg x 8 configuration 4 meg x 8 x 4 banks refresh count 4k row addressing 4k (a0-a11) bank addressing 4 (ba0, ba1) column addressing 1k (a0-a9) table 2: key timing parameters speed grade clock rate cl = 3 1 note: 1. cl = cas (read) latency data-out window 2 2. with a 50/50 clock duty cycle access window dqs-dq skew -5g 200 mhz 1.5ns 0750ps +500ps -6g 166 mhz 1.9ns 0750ps +500ps
128mb: x16 graphical ddr sdram addendum preliminary 09005aef80b2cb48 micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16ddr_ptpadd.fm - rev. a 4/04 en 2 ?2004 micron technology, inc. all rights reserved. figure 1: 66-pin tsop package dimension figure 2: 66-pin tsop package pin assignment note: 1. all dimensions in millimeters. 2. package width and length do not in clude mold protrusion; allowable mold protrusion is 0.25mm per side. see detail a 0.10 0.65 typ 0.71 10.16 0.08 0.15 0.50 0.10 pin #1 id detail a 22.22 0.08 0.32 .075 typ +0.03 -0.02 +0.10 -0.05 1.20 max 0.10 0.25 11.76 0.10 0.80 typ 0.10 (2x) gage plane 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 v ss dq15 v ss q dq14 dq13 v dd q dq12 dq11 v ss q dq10 dq9 v dd q dq8 nc v ss q udqs dnu v ref v ss dm ck# ck cke nc nc a11 a9 a8 a7 a6 a5 a4 v ss x16 v dd dq0 v dd q dq1 dq2 vssq dq3 dq4 v dd q dq5 dq6 vssq dq7 nc v dd q ldqs nc v dd dnu ldm we# cas# ras# cs# nc ba0 ba1 a10/ap a0 a1 a2 a3 v dd x16 v ss dq7 v ss q nc dq6 v dd q nc dq5 v ss q nc dq4 v dd q nc nc v ss q dqs dnu v ref v ss dm ck# ck cke nc nc a11 a9 a8 a7 a6 a5 a4 v ss x8 v dd dq0 v dd q nc dq1 v ss q nc dq2 v dd q nc dq3 v ss q nc nc v dd q nc nc v dd dnu nc we# cas# ras# cs# nc ba0 ba1 a10/ap a0 a1 a2 a3 v dd x8
128mb: x16 graphical ddr sdram addendum preliminary 09005aef80b2cb48 micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16ddr_ptpadd.fm - rev. a 4/04 en 3 ?2004 micron technology, inc. all rights reserved. table 3: pin descriptions pin numbers symbol type description 45, 46 ck, ck# input clock: ck and ck# are di fferential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ck#. output da ta (dqs and dqs) is referenced to the crossings of ck and ck#. 44 cke input clock enable: cke high activate s and cke low deactivates the internal clock, input buffers and output driv ers. taking cke low provides precharge power-down and self refresh operations (all banks idle), or active power-down (row active in any bank). cke is synchronous for power-down entry and exit, and for self refresh entry. cke is asynchronous for self refresh exit and for disabling the outputs. cke must be ma intained high throughout read and write accesses. input buffers (excluding ck, ck#, and cke) are disabled during power-down. input buffers (excluding cke) are disabled during self refresh. cke is an sstl_2 input but will detect an lvcmos low level after v dd is applied and until cke is first brought high. after cke is brought high it becomes an sstl_2 input only. 24 cs# input chip select: cs# enables (registere d low) and disables (registered high) the command decoder. all co mmands are masked when cs# is registered high. cs# provides for ex ternal bank selection on systems with multiple banks. cs# is considered part of the command code. 23, 22, 21 ras#,cas#, we# input command inputs: ras#, cas#, and we # (along with cs#) define the commandbeingentered. 20, 47 dm input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high along with that input data during a write access. dm is sampled on both edges of dqs. although dm pins are input-only, the dm loading is designed to match that of dq and dqs pins. 26, 27 ba0, ba1 input bank address inputs: ba0 and ba1 define to which bank an active, read, write, or precharge command is being applied. 29-31 32, 35, 36 37, 38, 39 40, 28, 41 a0, a1, a2 a3, a4, a5 a6, a7, a8 a9, a10, a11 input address inputs: provide the row ad dress for active commands, and the column address and auto precharge bit (a10) for read/write commands, to select one location out of the memory array in the respective bank. a10 sampled during a precharge command determines whether the precharge ap plies to one bank (a10 low, bank selected by ba0, ba1) or all banks (a10 high). the address inputs also provide the op-code during a mode register set command. ba0 and ba1 define which mode register (mode register or extended mode register) is loaded during the load mode register command. 2, 4, 5, 7, 8, 10, 11, 13, 54, 56, 57, 59, 60, 62, 63, 65 dq0-15 i/o data input/output. 16, 51 ldqs/udqs i/o data strobe: output with read da ta, input with write data. dqs is edge-aligned with read data, centered in write data. it is used to capture data. 14, 17, 25, 43, 53 nc - no connect: these pins should be left unconnected. 19, 50 dnu - do not use: must float to minimize noise on vref 3, 9, 15, 55, 61 v dd q supply dq power supply: isolated on the die for improved noise immunity. 6, 12, 52, 58, 64 v ss q supply dq ground. isolated on the die for improved noise immunity. 1, 18, 33 v dd supply power supply. 34, 48, 66 v ss supply ground. 49 v ref supply sstl_2 reference voltage.
128mb: x16 graphical ddr sdram addendum preliminary 09005aef80b2cb48 micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16ddr_ptpadd.fm - rev. a 4/04 en 4 ?2004 micron technology, inc. all rights reserved. read latency the read latency is the delay, in clock cycles, between the registration of a read command and the availability of the first bit of output data. the latency should be set to 3 clocks, as shown in the cas latency diagram and mode register definition diagram. if a read command is registered at clock edge n , and the latency is m clocks, the data will be available nominally coincident with clock edge n + m . reserved states should not be used as unknown operation or incompatibility with future versions may result. figure 3: mode register definition diagram figure 4: example cas latency diagram with cl=3 table 4: cas latency (cl) speed allowable operating clock frequency (mhz) cl = 3 cl = 2.5 cl = 2 -5g 133 mhz f 200mhz ? ? -6g 133 mhz f 166mhz ? ? m3 = 0 reserved 2 4 8 reserved reserved reserved reserved m3 = 1 reserved 2 4 8 reserved reserved reserved reserved operating mode normal operation normal operation/reset dll all other states reserved 0 1 - 0 0 - 0 0 - 0 0 - 0 0 - valid valid - 0 1 burst type sequential interleaved burst length m0 0 1 0 1 0 1 0 1 burst length cas latency bt 0* a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 976543 8210 m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 m3 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 m6-m0 m8 m7 operating mode a10 a11 ba0 10 11 13 * m14 and m13 (ba0 and ba1) must be ?0, 0? to select the base mode register (vs. the extended mode register). m9 m10 m11 cas latency reserved reserved reserved 3 reserved reserved reserved reserved 0* ba1 14 ck ck# c ommand dq dqs cl = 3 read nop nop nop burst length = 4 in the cases shown shown with nominal t ac and nominal t dsdq t0 t1 t2 t2n t3 t3n don?t care transitioning data
128mb: x16 graphical ddr sdram addendum preliminary 09005aef80b2cb48 micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16ddr_ptpadd.fm - rev. a 4/04 en 5 ?2004 micron technology, inc. all rights reserved. absolute maximum ratings stresses greater than those listed may cause perma- nent damage to the device. th is is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. v dd supply voltage relative to vss ...............................................-1v to +3.6v v dd q supply voltage relative to v ss ..............................................-1v to +3.6v v ref and inputs voltage relative to v ss ..............................................-1v to +3.6v i/o pins voltage relative to v ss ................................ -0.5v to v dd q +0.5v operating temperature, t a (ambient)....... 0c to +70c storage temperature (plastic) ...............-55c to +150c power dissipation........................................................ 1w short circuit output current .................................50ma note 53. this is the dc voltage supplied at the dram and is inclusive of all noise up to 20mhz. any noise above 20mhz at the dram generated from any source other than the dram itself may not exc eed the dc voltage range. table 5: dc electrical charac teristics and operating conditions 0c t a +70c; notes: 1?5, 16, refer to ddr266 da ta sheet, for all notes except 53 below. parameter/condition symbol min max units notes supply voltage -5g v dd 2.6 2.83 v 36, 41, 53 i/o supply voltage -5g v dd q 2.6 2.83 v 36, 41, 44,53 supply voltage -6g v dd 2.5 2.7 v 36, 41, 53 i/o supply voltage -6g v dd q 2.5 2.7 v 36, 41, 44,53 i/o reference voltage v ref 0.49 x v dd q 0.51 x v dd qv 6, 44 i/o termination voltage (system) v tt v ref - 0.04 v ref + 0.04 v7, 44 input high (logic 1) voltage v ih (dc) v ref + 0.15 v dd + 0.3 v28 input low (logic 0) voltage v il (dc) -0.3 v ref - 0.15 v28 input leakage current any input 0v v in v dd , v ref pin 0v vin 1.35v (all other pins not under test = 0v) i i -2 2 a output leakage current (dqs are disabled; 0v vout v dd q ) i oz -5 5 a output levels: full drive option - high current (v out = v dd q - 0.373v, minimum v ref , minimum v tt ) i oh -16.8 - ma 37, 39 i ol -16.8 - ma output levels: reduced drive option high current (v out = v dd q - 0.763v, minimum v ref , minimum v tt ) i ohr -9 - ma 38, 39 low current (v out = 0.763v, maximum v ref , maximum v tt ) i olr 9-ma
128mb: x16 graphical ddr sdram addendum preliminary 09005aef80b2cb48 micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16ddr_ptpadd.fm - rev. a 4/04 en 6 ?2004 micron technology, inc. all rights reserved. table 6: ac input operating conditions 0c t a +70c; notes: 1?5, 16, refer to ddr266 data sheet for all notes. parameter/condition symbol min max units notes input high (logic 1) voltage v ih ( ac )v ref + 0.310 - v 14, 28, 40 input low (logic 0) voltage v il ( ac ) - v ref - 0.310 v 14, 28, 40 i/o reference voltage v ref ( ac ) 0.49 x v dd q 0.51 x v dd q v6 table 7: capacitance (x16 tsop) note: 13; refer to ddr266 data sheet for all notes. parameter symbol min max units notes delta input/output capacitance: dq0-dq7 (x8) dc io ?0.50pf 24 delta input capacitance: command and address dc i 1 ?0.50pf 29 delta input capacitance: ck, ck# dc i 2 ?0.25pf 29 input/output capacitance: dqs, dqs, dm c io 4.0 5.0 pf input capacitance: command and address c i 1 2.0 3.0 pf input capacitance: ck, ck# c i 2 2.0 3.0 pf input capacitance: cke c i 3 2.0 3.0 pf
128mb: x16 graphical ddr sdram addendum preliminary 09005aef80b2cb48 micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16ddr_ptpadd.fm - rev. a 4/04 en 7 ?2004 micron technology, inc. all rights reserved. table 8: electrical characteristics an d recommended ac operating conditions 0c t a +70c; notes: 1-5, 14?17, 33, 46; re fer to ddr266 data sheet for all notes. ac characteristics -5g -6g parameter symbol min max min max units notes access window of dqs from ck/ck# t ac -0.75 +0.75 -0.75 +0.75 ns ck high-level width t ch 0.45 0.55 0.45 0.55 t ck 30 ck low-level width t cl 0.45 0.55 0.45 0.55 t ck 30 clock cycle time cl=3 t ck 5 13 6 13 ns 45, 52 dq and dm input hold time relative to dqs t dh 0.6 0.6 ns 26, 31 dq and dm input setup time relative to dqs t ds 0.6 0.6 ns 26, 31 dq and dm input pulse width (for each input) t dipw 1.75 2 ns 31 access window of dqs from ck/ck# t dqsck -0.75 +0.75 -0.75 +0.75 ns dqs input high pulse width t dqsh 0.4 0.4 t ck dqs input low pulse width t dqsl 0.4 0.4 t ck dqs-dq skew, dqs to last dq valid, per group, per access t dqsq 0.5 0.5 ns 25, 26 write command to first dqs latching transition t dqss 0.75 1.25 0.75 1.25 t ck dqs falling edge to ck rising - setup time t dss 0.25 0.25 t ck dqs falling edge from ck rising - hold time t dsh 0.25 0.25 t ck half clock period t hp t ch, t cl t ch, t cl ns 34 data-out high-impedance window from ck/ck# t hz +0.50 +0.6 ns 18, 42 data-out low-impedance window from ck/ck# t lz -0.50 -0.6 ns 18, 43 address and control input hold time (slew rate = 1v/ns) t ih f 0.9 1.1 ns address and control input setu p time (slew rate = 1v/ns) t is f 0.9 1.1 ns address and control input pulse width (for each input) t ipw 2.2 2.2 ns 14 load mode register command cycle time t mrd 3 3 t ck dq-dqs hold, dqs to first dq to go non-valid, per access t qh t hp - t qhs t hp - t qhs ns 25, 26 data hold skew factor t qhs 0.55 0.6 ns active to read with auto precharge command t rap 20 20 ns active to pr echarge command t ras 40 70,000 40 70,000 ns 35 active to active/auto refresh command period t rc 60 60 ns auto refresh command period t rfc 66 66 ns 50 active to read or write delay t rcd 20 20 ns precharge command period t rp 20 20 ns dqs read preamble t rpre 0.9 1.1 0.9 1.1 t ck 42 dqs read postamble t rpst 0.4 0.6 0.4 0.6 t ck active bank a to active bank b command t rrd 10 12 ns dqs write preamble t wpre 0.25 0.25 t ck dqs write preamble setup time t wpres 0 0 ns 20, 21 dqs write postamble t wpst 0.4 0.6 0.4 0.6 t ck 19 write recovery time t wr 15 15 ns internal write to read command delay t wtr 1 1 t ck data valid output window (dvw) n/a t qh - t dqsq ns 25 refresh to refresh command interval t refc 140.6 140.6 s 23 average periodic refresh interval t refi 15.6 15.6 s 23 terminating voltage delay to v dd t vtd 0 0 ns exit self refresh to non-read command t xsnr 75 75 ns exit self refresh to read command t xsrd 200 200 t ck
128mb: x16 graphical ddr sdram addendum preliminary 09005aef80b2cb48 micron technology, inc., reserves the right to change products or specifications without notice. 128mbx16ddr_ptpadd.fm - rev. a 4/04 en 8 ?2004 micron technology, inc. all rights reserved. ? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www .micron.com, customer comment line: 800-932-4992 micron, the m logo, and the micron logo are trademarks and/or service marks of micron technology, inc. all other trademarks are the property of their respective owners. data sheet designation preliminary: this data sheet contains initial charac- terization limits that are subject to change upon full characterization of production devices. ta b l e 9: i dd specifications and conditions (x16; -5g) 0c t a +70c; notes: 1-5, 14?17, 33, 46; re fer to ddr266 data sheet for all notes. max max parameter/condition symbol -5g -6g units notes operating current: one bank; active-precharge; t rc = t rc (min); t ck = t ck (min); dq, dm and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles i dd 0 130 ma 22, 48 operating current: one bank; active-read-precharge; burst = 4; t rc = t rc (min); t ck = t ck (min); i out = 0ma; address and control inputs changing once per clock cycle i dd 1 145 ma 22, 48 precharge power-down standby current: all banks idle; power-down mode; t ck = t ck (min); cke = (low) i dd 2p 4 ma 23, 32, 50 idle standby current: cs# = high; all banks are idle; t ck = t ck (min); cke = high; address and other control inputs changing once per clock cycle. v in = v ref for dq, dqs, and dm i dd 2f 60 ma 51 active power-down standby current: one bank active; power-down mode; t ck = t ck (min); cke = low i dd 3p 45 ma 23, 32, 50 active standby current: cs# = high; cke = high; one bank active ; t rc = t ras (max); t ck = t ck (min); dq, dm and dqs inputs changing twice per clock cycl e; address and other control inputs changing once per clock cycle i dd 3n 70 ma 22 operating current: burst = 2; reads; continuous burst; one bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); i out = 0ma i dd 4r 165 ma 22, 48 operating current: burst = 2; writes; continuous burst; one bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle i dd 4w 200 ma 22 auto refresh burst current: t rc = t rfc(min) i dd 5 270 ma 50 t rfc = 7.8us, i dd 5a 6ma27, 50 self refresh current: cke 0.2v standard i dd 6 4ma11 operating current: four bank interleaving reads (burst = 4) with auto precharge, t rc = minimum trc allowed; t ck = t ck (min); address and control inpu ts change only during active read, or write commands i dd 7 355 ma 22, 49
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