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products and specifications discussed herein ar e subject to change by micron without notice. 256mb, 512mb, 1gb (x64, dr) 200-pin ddr2 sodimm features pdf: 09005aef80ebed66/source: 09005aef80ebbc49 micron technology, inc., reserves the right to change products or specifications without notice. htf8c32_64_128x64hd.fm - rev. b 3/07 en 1 ?2006 micron technology, inc. all rights reserved. ddr2 sdram small-outline dimm mt8htf3264hd ? 256mb mt8htf6464hd ? 512mb mt8htf12864hd ? 1gb for component data sheets, refer to micron?s web site: www.micron.com features ? 200-pin, small-outline, dual in-line memory module (sodimm) ? fast data transfer rates: pc2-3200, pc2-4200, pc2-5300, or pc2-6400 ? 256mb (32 meg x 64), 512mb (64 meg x 64), 1gb (128 meg x 64) ?v dd = +1.8v ?v ddspd = +1.7v to +3.6v ? jedec-standard 1.8v i/ o (sstl_18-compatible) ? differential data strobe (dqs, dqs#) option ?4 n -bit prefetch architecture ?dual rank ? multiple internal device banks for concurrent operation ? programmable cas# latency (cl) ? posted cas# additive latency (al) ? write latency = read latency - 1 t ck ? programmable burst lengths: 4 or 8 ? adjustable data-output drive strength ? 64ms, 8,192-cycle refresh ? on-die termination (odt) ? serial presence-det ect (spd) with eeprom ? gold edge contacts figure 1: 200-pin sodimm (mo-224 r/c a) notes: 1. contact micron for industrial temperature module offerings. options marking ? operating temperature 1 ? commercial (0c t a +70c) d ? industrial (?40c t a +85c) t ?package ? 200-pin dimm (pb-free) y ? frequency/cas latency ? 2.5ns @ cl = 5 (ddr2-800) -80e ? 2.5ns @ cl = 6 (ddr2-800) -800 ? 3.0ns @ cl = 5 (ddr2-667) -667 ? 3.75ns @ cl = 4 (ddr2-533) -53e ? 5.0ns @ cl = 3 (ddr2-400) -40e ?pcb height ? 30mm (1.18in) module height 30mm (1.18in) table 1: key timing parameters speed grade industry nomenclature data rate (mt/s) t rcd (ns) t rp (ns) t rc (ns) cl = 6 cl = 5 cl = 4 cl = 3 -80e pc2-6400 ? 800 533 ? 12.5 12.5 55 -800 pc2-6400 800 667 533 ? 15 15 55 -667 pc2-5300 ? 667 533 400 15 15 55 -53e pc2-4200 ? ? 533 400 15 15 55 -40e pc2-3200 ? ? 400 400 15 15 55
pdf: 09005aef80ebed66/source: 09005aef80ebbc49 micron technology, inc., reserves the right to change products or specifications without notice. htf8c32_64_128x64hd.fm - rev. b 3/07 en 2 ?2006 micron technology, inc. all rights reserved. 256mb, 512mb, 1gb (x64, dr) 200-pin ddr2 sodimm features notes: 1. data sheets for the base device s can be found on micron?s web site. 2. all part numbers end with a two-place code (not shown), designating component and pcb revisions. consult factory fo r current revision codes. example: MT8HTF6464HDY-40ED3 . table 2: addressing 256mb 512mb 1gb refresh count 8k 8k 8k row address 8k (a0?a12) 8k (a0?a12) 8k (a0?a12) device bank address 4 (ba0, ba1) 4 (ba0, ba1) 8 (ba0, ba1, ba2) device page size per bank 1kb 1kb 1kb device configuration 256mb (16 meg x 16) 512mb (32 meg x 16) 1gb (64 meg x 16) column address 512 (a0?a8) 1k (a0?a9) 1k (a0?a9) module rank address 2 (s0#, s1#) 2 (s0#, s1#) 2 (s0#, s1#) table 3: part numbers and timing parameters ? 256mb modules base device: mt47h16m16, 1 256mb ddr2 sdram part number 2 module density configuration module bandwidth memory clock/ data rate latency (cl- t rcd- t rp) mt8htf3264hd-667__ 256mb 32 meg x 64 5.3 gb/s 3.0ns/667 mt/s 5-5-5 mt8htf3264hd-53e__ 256mb 32 meg x 64 4.3 gb/s 3.75ns/533 mt/s 4-4-4 mt8htf3264hd-40e__ 256mb 32 meg x 64 3.2 gb/s 5.0ns/400 mt/s 3-3-3 table 4: part numbers and timing parameters ? 512mb modules base device: mt47h32m16, 1 512mb ddr2 sdram part number 2 module density configuration module bandwidth memory clock/ data rate latency (cl- t rcd- t rp) mt8htf6464hd-80e__ 512mb 64 meg x 64 6.4 gb/s 2.5ns/800 mt/s 5-5-5 mt8htf6464hd-800__ 512mb 64 meg x 64 6.4 gb/s 2.5ns/800 mt/s 6-6-6 mt8htf6464hd-667__ 512mb 64 meg x 64 5.3 gb/s 3.0ns/667 mt/s 5-5-5 mt8htf6464hd-53e__ 512mb 64 meg x 64 4.3 gb/s 3.75ns/533 mt/s 4-4-4 mt8htf6464hd-40e__ 512mb 64 meg x 64 3.2 gb/s 5.0ns/400 mt/s 3-3-3 table 5: part numbers and timing parameters ? 1gb modules base device: mt47h64m16, 1 1gb ddr2 sdram part number 2 module density configuration module bandwidth memory clock/ data rate latency (cl- t rcd- t rp) mt8htf12864hd-80e__ 1gb 128 meg x 64 6.4 gb/s 2.5ns/800 mt/s 5-5-5 mt8htf12864hd-800__ 1gb 128 meg x 64 6.4 gb/s 2.5ns/800 mt/s 6-6-6 mt8htf12864hd-667__ 1gb 128 meg x 64 5.3 gb/s 3.0ns/667 mt/s 5-5-5 mt8htf12864hd-53e__ 1gb 128 meg x 64 4.3 gb/s 3.75ns/533 mt/s 4-4-4 mt8htf12864hd-40e__ 1gb 128 meg x 64 3.2 gb/s 5.0ns/400 mt/s 3-3-3
pdf: 09005aef80ebed66/source: 09005aef80ebbc49 micron technology, inc., reserves the right to change products or specifications without notice. htf8c32_64_128x64hd.fm - rev. b 3/07 en 3 ?2006 micron technology, inc. all rights reserved. 256mb, 512mb, 1gb (x64, dr) 200-pin ddr2 sodimm pin assignments and descriptions pin assignments and descriptions notes: 1. pin 85 is nc for 256mb and 512mb, ba2 for 1gb. table 6: pin assignments 200-pin sodimm front 200-pin sodimm back pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol 1v ref 51 dqs2 101 a1 151 dq42 2 v ss 52 dm2 102 a0 152 dq46 3v ss 53 v ss 103 v dd 153 dq43 4 dq4 54 v ss 104 v dd 154 dq47 5 dq0 55 dq18 105 a10 155 v ss 6 dq5 56 dq22 106 ba1 156 v ss 7 dq1 57 dq19 107 ba0 157 dq48 8 v ss 58 dq23 108 ras# 158 dq52 9v ss 59 v ss 109 we# 159 dq49 10 dm0 60 v ss 110 s0# 160 dq53 11 dqs0# 61 dq24 111 v dd 161 v ss 12 v ss 62 dq28 112 v dd 162 v ss 13 dqs0 63 dq25 113 cas# 163 nc 14 dq6 64 dq29 114 odt0 164 ck1 15 v ss 65 v ss 115 s1# 165 v ss 16 dq7 66 v ss 116 nc 166 ck1# 17 dq2 67 dm3 117 v dd 167 dqs6# 18 v ss 68 dqs3# 118 v dd 168 v ss 19 dq3 69 nc 119 odt1 169 dqs6 20 dq12 70 dqs3 120 nc 170 dm6 21 v ss 71 v ss 121 v ss 171 v ss 22 dq13 72 v ss 122 v ss 172 v ss 23 dq8 73 dq26 123 dq32 173 dq50 24 v ss 74 dq30 124 dq36 174 dq54 25 dq9 75 dq27 125 dq33 175 dq51 26 dm1 76 dq31 126 dq37 176 dq55 27 v ss 77 v ss 127 v ss 177 v ss 28 v ss 78 v ss 128 v ss 178 v ss 29 dqs1# 79 cke0 129 dqs4# 179 dq56 30 ck0 80 cke1 130 dm4 180 dq60 31 dqs1 81 v dd 131dqs4181dq57 32ck0#82 v dd 132 v ss 182 dq61 33 v ss 83 nc 133 v ss 183 v ss 34 v ss 84 nc 134 dq38 184 v ss 35 dq10 85 1 nc/ba2 135 dq34 185 dm7 36 dq14 86 nc 136 dq39 186 dqs7# 37 dq11 87 v dd 137 dq35 187 v ss 38 dq15 88 v dd 138 v ss 188 dqs7 39 v ss 89 a12 139 v ss 189 dq58 40 v ss 90 a11 140 dq44 190 v ss 41 v ss 91 a9 141 dq40 191 dq59 42 v ss 92 a7 142 dq45 192 dq62 43 dq16 93 a8 143 dq41 193 v ss 44 dq20 94 a6 144 v ss 194 dq63 45 dq17 95 v dd 145 v ss 195 sda 46 dq21 96 v dd 146 dqs5# 196 v ss 47 v ss 97 a5 147 dm5 197 scl 48 v ss 98 a4 148dqs5198 sa0 49 dqs2# 99 a3 149 v ss 199 v ddspd 50 nc 100 a2 150 v ss 200 sa1
pdf: 09005aef80ebed66/source: 09005aef80ebbc49 micron technology, inc., reserves the right to change products or specifications without notice. htf8c32_64_128x64hd.fm - rev. b 3/07 en 4 ?2006 micron technology, inc. all rights reserved. 256mb, 512mb, 1gb (x64, dr) 200-pin ddr2 sodimm pin assignments and descriptions table 7: pin descriptions symbol type description odt0, odt1 input (sstl_18) on-die termination: odt (registered high) enables te rmination resistance internal to the ddr2 sdram. when enabled, odt is only applied to each of the following pins: dq, dqs, dqs#, and dm. the odt input will be ignored if disabled via the load mode command. ck0, ck0#, ck1, ck1# input (sstl_18) clock: ck and ck# are differential clock inpu ts. all address and co ntrol input signals are sampled on the crossing of the positive edge of ck and negative edge of ck#. output data (dqs and dqs/dqs#) is refe renced to the crossi ngs of ck and ck#. cke0, cke1 input (sstl_18) clock enable: cke (registered high) activates an d cke (registered low) deactivates clocking circuitry on the ddr2 sdram. s0#, s1# input (sstl_18) chip select: s# enables (registered low) an d disables (registered high) the command decoder. all commands are masked wh en s# is registered high. s# provides for external rank selection on systems with multiple ranks. s# is considered part of the command code. ras#, cas#, we# input (sstl_18) command inputs: ras#, cas#, and we# (along with s#) define the command being entered. ba0, ba1, ba2 (1gb) input (sstl_18) bank address inputs: ba0?ba1/ba2 define to which device bank an active, read, write, or precharge command is being applied. ba0?ba1/ba2 define which mode register, including mr, emr, emr(2), and emr(3), is loaded during the load mode command. a0?a12 input (sstl_18) address inputs: provide the row address for ac tive commands, an d the column address and auto pr echarge bit (a10) for read/wri te commands, to select one location out of the memory array in the respective bank. a10 sampled during a precharge command determines whether the precharge applies to one device bank (a10 low, device bank selected by ba0?ba1/ba2) or all device banks (a10 high). the address inputs also provide th e op-code during a load mode command. dm0?dm7 input (sstl_18) input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high along with that input data during a write access. dm is sampled on both edges of dqs. although dm pins are input-only, the dm loading is designed to match that of dq and dqs pins. scl input (sstl_18) serial clock for presence-detect: scl is used to synchr onize the presence-detect data transfer to and from the module. sa0?sa1 input (sstl_18) presence-detect address inputs: these pins are used to configure the presence- detect device. dq0?dq63 i/o (sstl_18) data input/output: bidirectional data bus. dqs0?dqs7, dqs0#?dqs7# i/o (sstl_18) data strobe: output with read data, input with write data for source synchronous operation. edge-aligned with r ead data, center-aligned with write data. dqs# is only used when differential data strobe mo de is enabled via the load mode command. sda i/o (sstl_18) serial presence-detect data: sda is a bidirectional pin used to transfer addresses and data into and out of the pres ence-detect portion of the module. v dd supply (sstl_18) power supply: +1.8v 0.1v. v ref supply (sstl_18) sstl_18 reference voltage. v ss supply (sstl_18) ground. v ddspd supply (sstl_18) serial eeprom positive power supply: +1.7v to +3.6v. nc ? no connect: these pins should be left unconnected.
pdf: 09005aef80ebed66/source: 09005aef80ebbc49 micron technology, inc., reserves the right to change products or specifications without notice. htf8c32_64_128x64hd.fm - rev. b 3/07 en 5 ?2006 micron technology, inc. all rights reserved. 256mb, 512mb, 1gb (x64, dr) 200-pin ddr2 sodimm functional block diagram functional block diagram figure 2: functional block diagram ba0?ba1/ba2 a0?a12 ras# cas# we# cke0 cke1 odt0 odt1 ba0?ba1/ba2: ddr2 sdram a0?a12/a13: ddr2 sdram ras#: ddr2 sdram cas#: ddr2 sdram we#: ddr2 sdram cke0: ddr2 sdram cke1: ddr2 sdram odt0: ddr2 sdram odt1: ddr2 sdram u1, u2, u8, u9 ck0 ck0# u3, u4, u5, u6 ck1 ck1# a0 spd eeprom a1 a2 sa0 sa1 sda scl wp u7 v ddspd v dd v ref v ss spd eeprom ddr2 sdram ddr2 sdram ddr2 sdram, eeprom udqs udqs# udm dq dq dq dq dq dq dq dq ldqs ldqs# ldm dq dq dq dq dq dq dq dq dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqs0 dqs0# dm0 dqs1 dqs1# dm1 cs# u1 udqs udqs# udm dq dq dq dq dq dq dq dq ldqs ldqs# ldm dq dq dq dq dq dq dq dq cs# u9 udqs udqs# udm dq dq dq dq dq dq dq dq ldqs ldqs# ldm dq dq dq dq dq dq dq dq dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dqs2 dqs2# dm2 dqs3 dqs3# dm3 cs# u2 udqs udqs# udm dq dq dq dq dq dq dq dq ldqs ldqs# ldm dq dq dq dq dq dq dq dq cs# u8 ldqs ldqs# ldm dq dq dq dq dq dq dq dq udqs udqs# udm dq dq dq dq dq dq dq dq dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dqs4 dqs4# dm4 dqs5 dqs5# dm5 cs# u3 ldqs ldqs# ldm dq dq dq dq dq dq dq dq udqs udqs# udm dq dq dq dq dq dq dq dq cs# u6 ldqs ldqs# ldm dq dq dq dq dq dq dq dq udqs udqs# udm dq dq dq dq dq dq dq dq dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dqs6 dqs6# dm6 dqs7 dqs7# dm7 cs# u4 ldqs ldqs# ldm dq dq dq dq dq dq dq dq udqs udqs# udm dq dq dq dq dq dq dq dq cs# u5 s1# s0# v ss v ss
pdf: 09005aef80ebed66/source: 09005aef80ebbc49 micron technology, inc., reserves the right to change products or specifications without notice. htf8c32_64_128x64hd.fm - rev. b 3/07 en 6 ?2006 micron technology, inc. all rights reserved. 256mb, 512mb, 1gb (x64, dr) 200-pin ddr2 sodimm general description general description the mt8htf3264hd, mt8htf6464hd, and mt8htf12864hd ddr2 sdram modules are high-speed, cmos, dynamic random-a ccess 256mb, 512mb, and 1gb memory modules organized in a x64 configuration. ddr2 sdram modules use internally config- ured 4-bank (256mb, 512mb) or 8-bank (1gb) ddr2 sdram devices. ddr2 sdram modules use double data rate architecture to achieve high-speed opera- tion. the double data rate architecture is essentially a 4 n -prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the ddr2 sdram module effectively consists of a single 4 n -bit-wide, one-clock-cycle data transfer at the internal dram core and four corre- sponding n -bit-wide, one-half-clock-cycle da ta transfers at the i/o pins. a bidirectional data strobe (dqs, dqs#) is transmitted externally, along with data, for use in data capture at the receiver. dqs is a strobe transmitted by the ddr2 sdram device during reads and by the memory controller during writes. dqs is edge- aligned with data for reads and center-aligned with data for writes. ddr2 sdram modules operate fr om a differential clock (ck and ck#); the crossing of ck going high and ck# going low will be referred to as the positive edge of ck. commands are registered at every positive edge of ck. input data is registered on both edges of dqs, and output data is referenced to both edges of dqs, as well as to both edges of ck. serial presence-detect operation ddr2 sdram modules incorporate serial presence-detect (spd). the spd function is implemented using a 2,048-bit eeprom. this nonvolatile stor age device contains 256 bytes. the first 128 bytes can be programmed by micron to identify the module type and various sdram organizations and timing parameters. the remaining 128 bytes of storage are available for use by the customer. system read/write operations between the master (system logic) and the slave eeprom device occur via a standard i 2 c bus using the dimm?s scl (clock) and sda (data) signals, together with sa (1:0), which provide four unique dimm/eeprom addresses. write protect (wp) is pulled from v ss on the module, permanently disabling hardware write protect.
pdf: 09005aef80ebed66/source: 09005aef80ebbc49 micron technology, inc., reserves the right to change products or specifications without notice. htf8c32_64_128x64hd.fm - rev. b 3/07 en 7 ?2006 micron technology, inc. all rights reserved. 256mb, 512mb, 1gb (x64, dr) 200-pin ddr2 sodimm electrical specifications electrical specifications stresses greater than those listed in ta ble 8, may cause permanent damage to the module. this is a stress rating only, and func tional operation of the module at these or any other conditions above those indicated in each device?s data sheet is not implied. exposure to absolute maximum rating condit ions for extended periods may affect reli- ability. notes: 1. refresh rate is required to double when 85c < tc 95c. 2. for further information, refer to technical note tn-00-08: thermal applications, available on micron?s web site. input capacitance micron encourages designers to simulate the performance of the module to achieve optimum values. simulations are significantly more accurate and realistic than a gross estimation of module capacitance when inductance and delay parameters associated with trace lengths are used in simulations. jedec modules are currently designed using simulations to close timing budgets. component ac timing an d operating conditions recommended ac operating conditions are given in the ddr2 component data sheets. component specifications are available on micron?s web site. module speed grades correlate with component speed grades, as shown in table 9. table 8: absolute maximum ratings symbol parameter min max units v dd v dd supply voltage relative to v ss ?0.5 2.3 v v in , v out voltage on any pin relative to v ss ?0.5 2.3 v i i input leakage curren t; any input 0v v in v dd ; v ref input 0v v in 0.95v (all other pins not under test = 0v) command/address ras#, cas#, we#, s#, cke, odt, ba ?40 40 a ck, ck# ?20 20 dm ?10 10 ioz output leakage current; 0v v out v dd ; dqs and odt are disabled dq, dqs, dqs# ?10 10 a i vref v ref leakage current; v ref = v alid v ref level ?16 16 a t a module ambient operating temperature commercial 0+70c industrial ?40 +85 c t c 1 ddr2 sdram component case operating temperature 2 commercial 0+85c industrial ?40 +95 c table 9: module and component speed grades module speed grade component speed grade -80e -25e -800 -25 -667 -3e -53e -37e -40e -5e
pdf: 09005aef80ebed66/source: 09005aef80ebbc49 micron technology, inc., reserves the right to change products or specifications without notice. htf8c32_64_128x64hd.fm - rev. b 3/07 en 8 ?2006 micron technology, inc. all rights reserved. 256mb, 512mb, 1gb (x64, dr) 200-pin ddr2 sodimm electrical specifications table 10: ddr2 i dd specifications and conditions ? 256mb values shown for mt47h16m16 ddr2 sdram only an d are computed from values specified in the 256mb (16 meg x 16) component data sheet parameter/condition symbol -667 -53e -40e units operating one bank active-precharge current: t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching i dd 0 1 380 340 320 ma operating one bank active-read-precharge current: i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, s# is high betw een valid commands; address bus inputs are switching; data pattern is same as i dd 4w i dd 1 1 420 380 360 ma precharge power-down current: all device banks idle; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stable; data bus inputs are floating i dd 2p 2 40 40 40 ma precharge quiet standby current: all device banks idle; t ck = t ck (i dd ); cke is high, s# is high; other control and address bus inputs are stable; data bus inputs are floating i dd 2q 2 400 280 200 ma precharge standby current: all device banks idle; t ck = t ck (i dd ); cke is high, s# is high; other control and address bus in puts are switching; data bus inputs are switching i dd 2n 2 320 280 240 ma active power-down current: all device banks open; t ck = t ck (i dd ); cke is low; other con trol and address bus inputs are stable; data bus inputs are floating fast pdn exit mr[12] = 0 i dd 3p 2 240 200 160 ma slow pdn exit mr[12] = 1 48 48 48 ma active standby current: all device banks open; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; other cont rol and address bus inputs ar e switching; da ta bus inputs are switching i dd 3n 2 400 320 240 ma operating burst write current: all device banks open; continuous burst writes; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between va lid commands; address bus inputs are switching; data bus inputs are switching i dd 4w 1 880 740 580 ma operating burst read current: all device banks open; continuous burst reads; i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching i dd 4r 1 780 660 500 ma burst refresh current: t ck = t ck (i dd ); refresh command at every t rfc (i dd ) interval; cke is high, s# is high between valid commands; other control and address bus inputs are switching; data bus inpu ts are switching i dd 5 2 1,440 1,360 1,320 ma self refresh current: ck and ck# at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating i dd 6 2 40 40 40 ma operating bank interleave read current: all device banks interleaving reads; i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd ) - 1 t ck (i dd ); t ck = t ck (i dd ), t rc = t rc (i dd ), t rrd = t rrd (i dd ), t rcd = t rcd (i dd ); cke is high, s# is high between valid commands; address bus inputs are stable during de selects; data bus inputs are switching i dd 7 1 1,020 980 940 ma notes: 1. value calculated as one module rank in th is operating condition; al l other module ranks in i dd 2p (cke low) mode. 2. value calculated reflects all module ranks in this operating condition.
pdf: 09005aef80ebed66/source: 09005aef80ebbc49 micron technology, inc., reserves the right to change products or specifications without notice. htf8c32_64_128x64hd.fm - rev. b 3/07 en 9 ?2006 micron technology, inc. all rights reserved. 256mb, 512mb, 1gb (x64, dr) 200-pin ddr2 sodimm electrical specifications table 11: ddr2 i dd specifications and conditions ? 512mb values shown for mt47h32m16 ddr2 sdram only an d are computed from values specified in the 512mb (32 meg x 16) component data sheet parameter/condition symbol -80e/ -800 -667 -53e -40e units operating one bank active-precharge current: t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching i dd 0 1 560 500 460 440 ma operating one bank active-read-precharge current: i out =0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, s# is high between valid commands; address bus inputs are sw itching; data pattern is same as i dd 4w i dd 1 1 680 620 560 520 ma precharge power-down current: all device banks idle; t ck = t ck (i dd ); cke is low; other control and addr ess bus inputs are stable; data bus inputs are floating i dd 2p 2 56 56 56 56 ma precharge quiet standby current: all device banks idle; t ck = t ck (i dd ); cke is high, s# is high; other cont rol and address bus inputs are stable; data bus inputs are floating i dd 2q 2 520 440 360 320 ma precharge standby current: all device banks idle; t ck = t ck (i dd ); cke is high, s# is high; other control and ad dress bus inputs are switching; data bus inputs are switching i dd 2n 2 560 480 400 360 ma active power-down current: all device banks open; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stable; data bus inputs are floating fast pdn exit mr[12] = 0 i dd 3p 2 320 280 240 200 ma slow pdn exit mr[12] = 1 96 96 96 96 ma active standby current: all device banks open; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; other control and addr ess bus inputs are switching; data bus inputs are switching i dd 3n 2 600 560 480 400 ma operating burst write current: all device banks open; continuous burst writes; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching i dd 4w 1 1,200 1,020 840 640 ma operating burst read current: all device banks open; continuous burst reads; i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching i dd 4r 1 1,120 960 800 620 ma burst refresh current: t ck = t ck (i dd ); refresh command at every t rfc (i dd ) interval; cke is high, s# is high between valid commands; other control and address bus inputs are swit ching; data bus in puts are switching i dd 5 2 1,840 1,480 1,400 1,360 ma self refresh current: ck and ck# at 0v; cke 0.2v; other control and address bus inputs are floating ; data bus inputs are floating i dd 6 2 56 56 56 56 ma operating bank interleave read current: all device banks interleaving reads; i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd ) - 1 t ck (i dd ); t ck = t ck (i dd ), t rc = t rc (i dd ), t rrd t rrd (i dd ), t rcd = t rcd (i dd ); cke is high, s# is high between valid commands; address bus inputs are stable during deselects; da ta bus inputs are switching i dd 7 1 1,500 1,420 1,380 1,360 ma notes: 1. value calculated as one module rank in this operating condition; all other module ranks in i dd 2p (cke low) mode. 2. value calculated reflects all module ranks in this operating condition.
pdf: 09005aef80ebed66/source: 09005aef80ebbc49 micron technology, inc., reserves the right to change products or specifications without notice. htf8c32_64_128x64hd.fm - rev. b 3/07 en 10 ?2006 micron technology, inc. all rights reserved. 256mb, 512mb, 1gb (x64, dr) 200-pin ddr2 sodimm electrical specifications table 12: ddr2 i dd specifications and conditions (die revision a) ? 1gb values shown for mt47h64m16 ddr2 sdram only an d are computed from values specified in the 1gb (64 meg x 16) component data sheet parameter/condition symbol -667 -53e -40e units operating one bank active-precharge current: t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching i dd 0 1 560 460 440 ma operating one bank active-read-precharge current: i out = 0ma; bl = 4, cl=cl(i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, s# is high betw een valid commands; address bus inputs are switching; data pattern is same as i dd 4w i dd 1 1 540 500 460 ma precharge power-down current: all device banks idle; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stable; data bus inputs are floating i dd 2p 2 56 56 56 ma precharge quiet standby current: all device banks idle; t ck = t ck (i dd ); cke is high, s# is high; other cont rol and address bus inputs are stable; data bus inputs are floating i dd 2q 2 520 360 320 ma precharge standby current: all device banks idle; t ck = t ck (i dd ); cke is high, s# is high; other control and address bus in puts are switching; data bus inputs are switching i dd 2n 2 560 400 320 ma active power-down current: all device banks open; t ck = t ck (i dd ); cke is low; other con trol and address bus inputs are stable; data bus inputs are floating fast pdn exit mr[12] = 0 i dd 3p 2 320 280 280 ma slow pdn exit mr[12] = 1 112 112 112 ma active standby current: all device banks open; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; other control and address bus in puts are switching; data bus inputs are switching i dd 3n 2 600 480 440 ma operating burst write current: all device banks open; continuous burst writes; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid comm ands; address bus inputs are switching; data bus inputs are switching i dd 4w 1 820 740 640 ma operating burst read current: all device banks open; continuous burst reads; i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching i dd 4r 1 900 740 640 ma burst refresh current: t ck = t ck (i dd ); refresh command at every t rfc (i dd ) interval; cke is high, s# is high between valid commands; other control and address bus inputs are switching; data bus inpu ts are switching i dd 5 2 2,160 2,000 1,920 ma self refresh current: ck and ck# at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating i dd 6 2 24 24 24 ma operating bank interleave read current: all device banks interleaving reads; i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd ) - 1 t ck (i dd ); t ck = t ck (i dd ), t rc = t rc (i dd ), t rrd = t rrd (i dd ), t rcd = t rcd (i dd ); cke is high, s# is high between valid commands; address bus inputs are stable during deselects; data bus inputs are switching i dd 7 1 1,420 1,380 1,320 ma notes: 1. value calculated as one module rank in th is operating condition; all other module ranks in i dd 2p (cke low) mode. 2. value calculated reflects all module ranks in this operating condition.
pdf: 09005aef80ebed66/source: 09005aef80ebbc49 micron technology, inc., reserves the right to change products or specifications without notice. htf8c32_64_128x64hd.fm - rev. b 3/07 en 11 ?2006 micron technology, inc. all rights reserved. 256mb, 512mb, 1gb (x64, dr) 200-pin ddr2 sodimm electrical specifications table 13: ddr2 i dd specifications and conditions (die revision e) ? 1gb values shown for mt47h64m16 ddr2 sdram only an d are computed from values specified in the 1gb (64 meg x 16) component data sheet parameter/condition symbol -80e/ -800 -667 -53e -40e units operating one bank active-precharge current: t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ); cke is high, s# is high between valid commands; address bus inputs are switch ing; data bus inpu ts are switching i dd 0 1 628 568 468 468 ma operating one bank active-read-precharge current: i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, s# is high be tween valid commands; address bus inputs are switching; da ta pattern is same as i dd 4w i dd 1 1 728 548 508 488 ma precharge power-down current: all device banks idle; t ck = t ck (i dd ); cke is low; other control and address bu s inputs are stable; data bus inputs are floating i dd 2p 2 56 56 56 56 ma precharge quiet standby current: all device banks idle; t ck = t ck (i dd ); cke is high, s# is high; other control and address bus inputs are stable; data bus inputs are floating i dd 2q 2 600 520 360 320 ma precharge standby current: all device banks idle; t ck = t ck (i dd ); cke is high, s# is high; other co ntrol and address bus inpu ts are switching; data bus inputs are switching i dd 2n 2 640 560 400 320 ma active power-down current: all device banks open; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stable; data bus inputs are floating fast pdn exit mr[12] = 0 i dd 3p 2 320 240 240 240 ma slow pdn exit mr[12] = 1 80 80 80 80 ma active standby current: all device banks open; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; other control an d address bus inputs ar e switching; data bus inputs are switching i dd 3n 2 680 600 480 440 ma operating burst write current: all device banks open; continuous burst writes; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching i dd 4w 1 1,288 828 748 668 ma operating burst read current: all device banks open; continuous burst reads; i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; address bus inputs are switch ing; data bus inpu ts are switching i dd 4r 1 1,308 908 748 668 ma burst refresh current: t ck = t ck (i dd ); refresh command at every t rfc (i dd ) interval; cke is high, s# is high between valid commands; other control and address bus inputs ar e switching; data bus inputs are switching i dd 5 2 2,240 2,160 2,000 1,920 ma self refresh current: ck and ck# at 0v; cke 0.2v; other control and address bus inputs are floating ; data bus inputs are floating i dd 6 2 56 56 56 56 ma operating bank interleave read current: all device banks interleaving reads; i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd ) - 1 t ck (i dd ); t ck = t ck (i dd ), t rc = t rc (i dd ), t rrd = t rrd (i dd ), t rcd = t rcd (i dd ); cke is high, s# is high between valid command s; address bus inputs are stable during deselects; data bus inputs are switching i dd 7 1 1,788 1,428 1,348 1,228 ma notes: 1. value calculated as one module rank in this operating condition; all other module ranks in i dd 2p (cke low) mode. 2. value calculated reflects all module ranks in this operating condition.
pdf: 09005aef80ebed66/source: 09005aef80ebbc49 micron technology, inc., reserves the right to change products or specifications without notice. htf8c32_64_128x64hd.fm - rev. b 3/07 en 12 ?2006 micron technology, inc. all rights reserved. 256mb, 512mb, 1gb (x64, dr) 200-pin ddr2 sodimm serial presence-detect serial presence-detect notes: 1. to avoid spurious start and stop conditions, a minimum delay is placed between scl = 1 and the falling or rising edge of sda. 2. this parameter is sampled. 3. for a restart condition, or following a write cycle. 4. the spd eeprom write cycle time ( t wrc) is the time from a vali d stop condition of a write sequence to the end of the eeprom intern al erase/program cycl e. during the write cycle, the eeprom bus interface circuit is disabled, sda rema ins high due to pull-up resis- tance, and the eeprom does not respond to its slave address. table 14: serial presence-detec t eeprom dc operating conditions all voltages referenced to v ss ; v ddspd = +1.7v to +3.6v parameter/condition symbol min max units supply voltage v ddspd 1.7 3.6 v input high voltage: logic 1; all inputs v ih v ddspd x 0.7 v ddspd + 0.5 v input low voltage: logic 0; all inputs v il ?0.6 v ddspd x 0.3 v output low voltage: i out = 3ma v ol ?0.4v input leakage current: v in = gnd to v dd i li 0.10 3 a output leakage current: v out = gnd to v dd i lo 0.05 3 a standby current i sb 1.6 4 a power supply curren t, read: scl clock frequency = 100 khz i cc r 0.4 1 ma power supply current, write: scl clock frequency = 100 khz i cc w 23ma table 15: serial presence-detec t eeprom ac operating conditions all voltages referenced to v ss ; v ddspd = +1.7v to +3.6v parameter/condition symbol min max units notes scl low to sda data-out valid t aa 0.2 0.9 s 1 time the bus must be free before a new transition can start t buf 1.3 ? s data-out hold time t dh 200 ? ns sda and scl fall time t f ? 300 ns 2 data-in hold time t hd:dat 0 ? s start condition hold time t hd:sta 0.6 ? s clock high period t high 0.6 ? s noise suppression time con stant at scl, sda inputs t i?50ns clock low period t low 1.3 ? s sda and scl rise time t r?0.3s2 scl clock frequency f scl ? 400 khz data-in setup time t su:dat 100 ? ns start condition setup time t su:sta 0.6 ? s 3 stop condition setup time t su:sto 0.6 ? s write cycle time t wrc ? 10 ms 4
pdf: 09005aef80ebed66/source: 09005aef80ebbc49 micron technology, inc., reserves the right to change products or specifications without notice. htf8c32_64_128x64hd.fm - rev. b 3/07 en 13 ?2006 micron technology, inc. all rights reserved. 256mb, 512mb, 1gb (x64, dr) 200-pin ddr2 sodimm serial presence-detect table 16: serial presence-detect matrix byte description entry (version) 256mb 1 512mb 1gb 0 number of spd bytes used by micron 128 80 80 80 1 total number of bytes in spd device 256 08 08 08 2 fundamental memory type ddr2 sdram 08 08 08 3 number of row addresses on assembly 13 0d 0d 0d 4 number of column addresses on assembly 9, 10 09 0a 0a 5 dimm height and module ranks 30mm, dual rank 61 61 61 6 module data width 64 40 40 40 7 reserved 00000 00 8 module voltage interface levels sstl 1.8v 05 05 05 9 sdram cycle time, t ck (cl = max value, see byte 18) -80e/800 -667 -53e -40e ? 30 3d 50 25 30 3d 50 25 30 3d 50 10 sdram access from clock, t ac (cl = max value, see byte 18) -80e/800 -667 -53e -40e ? 45 50 60 40 45 50 60 40 45 50 60 11 module configuration type non-ecc 00 00 00 12 refresh rate/type 7.81s/self 82 82 82 13 sdram device widt h (primary sdram) 16 10 10 10 14 error-checking sdram data width n/a 00 00 00 15 reserved 00000 00 16 burst lengths supported 4, 8 0c 0c 0c 17 number of banks on sdram device 4 or 8 04 04 08 18 cas latencies supported -80e -800 -667 (5, 4, 3) -53e/-40e (4, 3) ? ? 38 18 30 70 38 18 30 70 38 18 19 module thickness 01 01 01 20 ddr2 dimm type sodimm 04 04 04 21 sdram module attributes unbuffered 00 00 00 22 sdram device attributes: weak driver (01) and 50 odt (03) -80e/-800/-667 -53e/-40e ?/?/03 01 03 01 03 01 23 sdram cycle time, t ck, max cl - 1 -80e -800 -667 -53e/-40e ? ? 3d 50 3d 30 3d 50 3d 30 3d 50 24 sdram access from ck, t ac, max cl - 1 -80e/-800 -667 -53e -40e ? 45 50 60 40 45 50 60 40 45 50 60 25 sdram cycle time, t ck, max cl - 2 -80e -800 -667 -53e/-40e ? ? 50 00 00 3d 50 00 00 3d 50 00 26 sdram access from ck, t ac, max cl - 2 -80e -800 -667 -53e/-40e ? ? 45 00 00 40 45 00 00 40 45 00
pdf: 09005aef80ebed66/source: 09005aef80ebbc49 micron technology, inc., reserves the right to change products or specifications without notice. htf8c32_64_128x64hd.fm - rev. b 3/07 en 14 ?2006 micron technology, inc. all rights reserved. 256mb, 512mb, 1gb (x64, dr) 200-pin ddr2 sodimm serial presence-detect 27 min row precharge time, t rp 3c 3c 3c 28 min row active-to-row active, t rrd 28 28 28 29 min ras#-to-cas# delay, t rcd 3c 3c 3c 30 min active-to-precharge time, t ras -80e/-800 -667/-53e -40e ? 2d 28 2d 2d 28 2d 2d 28 31 module rank density 256mb, 512mb, 1gb 20 40 80 32 address and command setup time, t is b -80e/-800 -667 -53e -40e ? 20 25 35 17 20 25 35 17 20 25 35 33 address and command hold time, t ih b -80e/-800 -667 -53e -40e ? 27 37 47 25 27 37 47 25 27 37 47 34 data/data mask input setup time, t ds b -80e/-800 -667/-53e -40e ? 10 15 05 10 15 05 10 15 35 data/data mask input hold time, t dh b -80e/-800 -667 -53e -40e ? 17 22 27 12 17 22 27 12 17 22 27 36 write recovery time, t wr 3c 3c 3c 37 write-to-read command delay, t wtr -80e/-667/-53e -800/-40e ?/1e/1e ?/28 1e 28 1e 28 38 read-to-precharge command delay, t rtp -80e/-800 -667/-53e/-40e ? 1e 1e 1e 1e 1e 39 memory analysis probe 00 00 00 40 extension for bytes 41 and 42 -80e -800 -667/-53e/-40e ? ? 00 30 00 00 36 06 06 41 min active-to-active/refresh time, t rc 2 -80e -800/-667/-53e -40e ? ?/3c 37 39 3c 37 39 3c 37 42 min auto refresh-to-active/ auto refresh command period, t rfc 4b 69 7f 43 sdram device max cycle time, t ck (max) 80 80 80 44 sdram device max dqs-dq skew time, t dqsq -80e/-800 -667 -53e -40e ? 18 1e 23 14 18 1e 23 14 18 1e 23 45 sdram device max read data hold skew factor, t qhs -80e/-800 -667 -53e -40e ? 22 28 2d 1e 22 28 2d 1e 22 28 2d 46 pll relock time 00 00 00 47?61 optional features, not supported 00 00 00 62 spd revision release 1.2 12 12 12 table 16: serial presence-detect matrix (continued) byte description entry (version) 256mb 1 512mb 1gb
pdf: 09005aef80ebed66/source: 09005aef80ebbc49 micron technology, inc., reserves the right to change products or specifications without notice. htf8c32_64_128x64hd.fm - rev. b 3/07 en 15 ?2006 micron technology, inc. all rights reserved. 256mb, 512mb, 1gb (x64, dr) 200-pin ddr2 sodimm serial presence-detect notes: 1. the 256mb module is not availa ble in -80e and -800 speed grades. 2. the t rc spd values shown are jede c ddr2 device specification values. the actual micron ddr2 device specification is t rc = 55ns for all speed grades. 63 checksum for bytes 0?62 -80e -800 -667 -53e -40e ? ? e0 8b f2 63 04 1f ca 31 c3 64 7f 2a 91 64 manufacturer?s jedec id code micron 2c 2c 2c 65?71 manufacturer?s jedec id code (continued) ff ff ff 72 manufacturing location 1?12 01?0c 01?0c 01?0c 73?90 module part number (ascii) ? variable data variable data variable data 91 pcb identification code 1?9 01?09 01?09 01?09 92 identification code (continued) 00000 00 93 year of manufacture in bcd ? variable data variable data variable data 94 week of manufacture in bcd ? variable data variable data variable data 95?98 module serial number ? variable data variable data variable data 99?127 reserved for manufacturer-specific data 00 00 00 128?255 reserved for custo mer-specific data ff ff ff table 16: serial presence-detect matrix (continued) byte description entry (version) 256mb 1 512mb 1gb
? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 prodmktg@micron.com www.micron.com customer comment line: 800-932-4992 micron, the m logo, and the micron logo ar e trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified ov er the complete power supply and temperature range for production devices. althou gh considered final, these specifications are subject to change, as further product development and data characte rization sometimes occur. 256mb, 512mb, 1gb (x64, dr) 200-pin ddr2 sodimm module dimensions pdf: 09005aef80ebed66/source: 09005aef80ebbc49 micron technology, inc., reserves the right to change products or specifications without notice. htf8c32_64_128x64hd.fm - rev. b 3/07 en 16 ?2006 micron technology, inc. all rights reserved. module dimensions figure 3: 200-pin ddr2 sodimm notes: 1. all dimensions are in millimeters (i nches); max/min or typical (typ) where noted. 2. the dimensional diagram is for reference on ly. refer to the jedec mo document for com- plete design dimensions. 0.150 (3.80) max pin 1 2.667 (67.75) 2.656 (67.45) 0.787 (20.00) typ 0.071 (1.80) (2x) 0.024 (0.60) typ 0.018 (0.45) typ 0.079 (2.00) r (2x) pin 199 pin 200 pin 2 front view 0.079 (2.00) 0.236 (6.00) 2.504 (63.60) typ 0.100 (2.55) 0.039 (0.99) typ 1.187 (31.15) 1.175 (29.85) back view 0.043 (1.10) 0.035 (0.90) u1 u2 u3 u4 u5 u6 u7 u8 u9 1.87 (47.4) typ 0.45 (11.4) typ 0.165 (4.2) typ

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