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144-pin sdram sodimms preliminary data sheet 64mb, 128mb, 256mb, 512mb enhanced memory systems inc., 1850 ramtron dr., colo spgs, co 80921 2001 enhanced memory systems. all rights reserved. phone: (800) 545-dram; fax: (719) 488-9095; http://www.edram.com the information contained herein is subject to change without notice. revision 1.0 page 1 of 15 features jedec standard 144-pin pc133 sdram sodimm fast 5.4 ns clock access time supports cas latency = 2, 3 on-board serial presence detect (spd) unbuffered 144-pin sodimm 4k refresh / 64ms (8k refresh for 512mb dimm) single 3.3v 0.3v power supply description the enhanced memory systems 64mb, 128mb, 256mb, and 512mb small outline dimms (1.05-inch height) are the fastest sodimms available for notebook and embedded system applications. this pc133 product provides the lowest cost for both pc133 and pc100 sockets. the fast 5.4 ns clock access time allows unbuffered operation at 133 mhz for lower memory latency, and lower costs than registered dimms. the 64mb module is organized as 8mx64, the 128mb module is organized as 16mx64, the 256mb module is organized as 32mx64, and the 512mb module is organized as 64mx64. each module has a serial presence eeprom, which contains information on the module type, module organization, component speed, and other attributes relevant to the system controller. pin symbol pin symbol pin symbol pin symbol 1 vss 37 dq8 73 rsvd 109 vss 2 vss 38 dq40 74 ck1 110 a9 3 dq0 39 dq9 75 vss 111 a10/ap 4 dq32 40 dq41 76 vss 112 nc 5 dq1 41 dq10 77 rsvd 113 vdd 6 dq33 42 dq42 78 rsvd 114 vdd 7 dq2 43 dq11 79 rsvd 115 dqmb2 8 dq34 44 dq43 80 rsvd 116 dqmb6 9 dq3 45 vdd 81 vdd 117 dqmb3 10 dq35 46 vdd 82 vdd 118 dqmb7 11 vdd 47 dq12 83 dq16 119 vss 12 vdd 48 dq44 84 dq48 120 vss 13 dq4 49 dq13 85 dq17 121 dq24 14 dq36 50 dq45 86 dq49 122 dq56 15 dq5 51 dq14 87 dq18 123 dq25 16 dq37 52 dq46 88 dq50 124 dq57 17 dq6 53 dq15 89 dq19 125 dq26 18 dq38 54 dq47 90 dq51 126 dq58 19 dq7 55 vss 91 vss 127 dq27 20 dq39 56 vss 92 vss 128 dq59 21 vss 57 nc 93 dq20 129 vdd 22 vss 58 rsvd 94 dq52 130 vdd 23 dqmb0 59 nc 95 dq21 131 dq28 24 dqmb4 60 rsvd 96 dq53 132 dq60 25 dqmb1 61 ck0 97 dq22 133 dq29 26 dqmb5 62 cke0 98 dq54 134 dq61 27 vdd 63 vdd 99 dq23 135 dq30 28 vdd 64 vdd 100 dq55 136 dq62 29 a0 65 ras# 101 vdd 137 dq31 30 a3 66 cas# 102 vdd 138 dq63 31 a1 67 we# 103 a6 139 vss 32 a4 68 cke1 104 a7 140 vss 33 a2 69 s0# 105 a8 141 sda 34 a5 70 a12 106 ba0 142 scl 35 vss 71 s1# 107 vss 143 vdd 36 vss 72 nc 108 vss 144 vdd
144-pin sdram sodimms 64mb, 128mb, 256mb, 512mb preliminary data sheet enhanced memory systems inc., 1850 ramtron dr., colo spgs, co 80921 2001 enhanced memory systems. all rights reserved. phone: (800) 545-dram; fax: (719) 488-9095; http://www.edram.com the information contained herein is subject to change without notice. page 2 of 15 revision 1.0 pin descriptions symbol type function ck(0:1) input clo cks: all sdram i nput signals are sampled on the positive edge of ck. cke(0:1) input clock enables: cke activate (high) or deactivate (low) the ck signals. deactivating the clock initiates the power-down and self-refresh operations (all banks idle), or clock suspend operation. cke is synchronous until the device enters power-down and self-refresh modes where it is asynchronous until the mode is exited. s(0:1)# input chip select: s# enables (low) or disables (high) the command decoder. when the command decoder is disabled, new commands are ignored but previous operations continue. ras#, cas#, we# input command inputs: sampled on the rising edge of ck, these inputs define the command to be executed. ba(0:1) input bank addresses: these inputs define to which of the 4 banks a given command is being applied. a(0:12) input address inputs: a0-a12 define the row address during the bank activate command. a0-a9 define the column address during read and write commands. a10/ap invokes the auto-precharge operation. during manual precharge commands, a10/ap low specifies a single bank precharge while a10/ap high precharges all banks. the address inputs are also used to program the mode register. dq(0:63) input/ output data i/o: data bus inputs and outputs. for write cycles, input data is applied to these pins and must be set-up and held relative to the rising edge of clock. for read cycles, the device drives output data on these pins after the cas latency is satisfied. dqmb(0-7) input data i/o mask inputs: dqmb0-7 inputs mask write data (zero latency) and acts as a synchronous output enable (2-cycle latency) for read data. v dd supply power supply: +3.3 v v ss supply ground sda input/ output serial presence-detect data: sda is a bi-directional pin used to transfer addresses and data into and data out of the presence-detect portion of the module. scl input serial clock for presence-detect: scl is used to synchronize the presence detect data transfer to and from the module rfu - reserved for future use: these pins should be left unconnected. dnu - do not use. nc - no connect - open pin.
144-pin sdram sodimms preliminary data sheet 64mb, 128mb, 256mb, 512mb enhanced memory systems inc., 1850 ramtron dr., colo spgs, co 80921 2001 enhanced memory systems. all rights reserved. phone: (800) 545-dram; fax: (719) 488-9095; http://www.edram.com the information contained herein is subject to change without notice. revision 1.0 page 3 of 15 64mb dimm functional block diagram C sm6408sdt u0 u1 dq(7:0) dqmb0 s0# dq(15:8) dqmb1 u2 u3 dq(23:16) dqmb2 dq(31:24) dqmb3 u4 u5 dq(39:32) dqmb4 dq(47:40) dqmb5 u6 u7 dq(55:48) dqmb6 dq(63:56) dqmb7 clock wiring 4 sdram 4 sdram ck0 ck1 10 ck0, ck1 2 sdrams serial pd scl a0 a1 a2 sda ba1 sdram u0-7 ba1 ba0 sdram u0-7 ba0 ras# sdram u0-7 ras# a0-a11 sdram u0-7 a0-a11 vdd sdram u0-7 vdd vss sdram u0-7 vss cas# sdram u0-7 cas# we# sdram u0-7 we# cke sdram u0-7 cke0 note: all dq resistor values are 10 ohms. all ck resistor values are 10 ohms. u0-u7 are 8mx8 pc133 sdram devices. 10 2 sdrams
144-pin sdram sodimms 64mb, 128mb, 256mb, 512mb preliminary data sheet enhanced memory systems inc., 1850 ramtron dr., colo spgs, co 80921 2001 enhanced memory systems. all rights reserved. phone: (800) 545-dram; fax: (719) 488-9095; http://www.edram.com the information contained herein is subject to change without notice. page 4 of 15 revision 1.0 128mb dimm functional block diagram C sm12808asdt u0 u1 dq(7:0) dqmb0 s0# dq(15:8) dqmb1 u2 u3 dq(23:16) dqmb2 dq(31:24) dqmb3 u4 u5 dq(39:32) dqmb4 dq(47:40) dqmb5 u6 u7 dq(55:48) dqmb6 dq(63:56) dqmb7 clock wiring 4 sdram 4 sdram ck0 ck1 10 ck0, ck1 2 sdrams serial pd scl a0 a1 a2 sda ba1 sdram u0-7 ba1 ba0 sdram u0-7 ba0 ras# sdram u0-7 ras# a0-a11 sdram u0-7 a0-a11 vdd sdram u0-7 vdd vss sdram u0-7 vss cas# sdram u0-7 cas# we# sdram u0-7 we# cke sdram u0-7 cke0 note: all dq resistor values are 10 ohms. all ck resistor values are 10 ohms. u0-u7 are 16mx8 pc133 sdram devices. 10 2 sdrams
144-pin sdram sodimms preliminary data sheet 64mb, 128mb, 256mb, 512mb enhanced memory systems inc., 1850 ramtron dr., colo spgs, co 80921 2001 enhanced memory systems. all rights reserved. phone: (800) 545-dram; fax: (719) 488-9095; http://www.edram.com the information contained herein is subject to change without notice. revision 1.0 page 5 of 15 256mb dimm functional block diagram C sm25608asdt dq(7:0) dqmb0 s0# dq(15:8) dqmb1 dq(23:16) dqmb2 dq(31:24) dqmb3 dq(39:32) dqmb4 dq(47:40) dqmb5 dq(55:48) dqmb6 dq(63:56) dqmb7 u0l u1l u0u u1u u4l u4u u5l u5u u2l u2u u6l u3l u3u u6u u7l u7u s1# ba1 sdram u0-7 ba1 ba0 sdram u0-7 ba0 ras# sdram u0-7 ras# a0-a11 sdram u0-7 a0-a11 vdd sdram u0-7 vdd vss sdram u0-7 vss cas# sdram u0-7 cas# we# sdram u0-7 we# cke0 sdram u0-3 cke0 note: all dq resistor values are 10 ohms. all ck resistor values are 10 ohms. u0-u7 are stacked 16mx8 pc133 sdram devices. clock wiring pll terminated ck0 ck1 10 ck0 4 sdrams serial pd scl a0 a1 a2 sda 4 sdrams 10 ck1 4 sdrams 4 sdrams cke0 sdram u4-7 cke1 12pf 12pf pll
144-pin sdram sodimms 64mb, 128mb, 256mb, 512mb preliminary data sheet enhanced memory systems inc., 1850 ramtron dr., colo spgs, co 80921 2001 enhanced memory systems. all rights reserved. phone: (800) 545-dram; fax: (719) 488-9095; http://www.edram.com the information contained herein is subject to change without notice. page 6 of 15 revision 1.0 512mb dimm functional block diagram C sm51208bsdt dq(7:0) dqmb0 s0# dq(15:8) dqmb1 dq(23:16) dqmb2 dq(31:24) dqmb3 dq(39:32) dqmb4 dq(47:40) dqmb5 dq(55:48) dqmb6 dq(63:56) dqmb7 u0l u1l u0u u1u u4l u4u u5l u5u u2l u2u u6l u3l u3u u6u u7l u7u s1# ba1 sdram u0-7 ba1 ba0 sdram u0-7 ba0 ras# sdram u0-7 ras# a0-a12 sdram u0-7 a0-a12 vdd sdram u0-7 vdd vss sdram u0-7 vss cas# sdram u0-7 cas# we# sdram u0-7 we# cke0 sdram u0-3 cke0 note: all dq resistor values are 10 ohms. all ck resistor values are 10 ohms. u0-u7 are stacked 32mx8 pc133 sdram devices. clock wiring pll terminated ck0 ck1 10 ck0 4 sdrams serial pd scl a0 a1 a2 sda 4 sdrams 10 ck1 4 sdrams 4 sdrams cke0 sdram u4-7 cke1 12pf 12pf pll
144-pin sdram sodimms preliminary data sheet 64mb, 128mb, 256mb, 512mb enhanced memory systems inc., 1850 ramtron dr., colo spgs, co 80921 2001 enhanced memory systems. all rights reserved. phone: (800) 545-dram; fax: (719) 488-9095; http://www.edram.com the information contained herein is subject to change without notice. revision 1.0 page 7 of 15 electrical characteristics absolute maximum ratings description symbol value power supply voltage v dd -1v to +4.6v voltage on any pin with respect to ground v in , v out -0.5v to +4.6v operating temperature (ambient) t a 0 c to +70 c storage temperature t stg -55 c to +125 c power dissipation p d tbd dc output current (i/o pins) i out 50ma stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress ra ting only, and the functional operation of the device at these, or any other conditions above those listed in the operational sectio n of the specification, is not implied. exposure to conditions at absolute maximum ratings for extended periods may affect device reliab ility. dc operating conditions (t a = 0 c to 70 c) symbol parameter min typical max units notes v dd supply voltage 3.0 3.3 3.6 v v ih input high voltage 2.0 3.3 v dd + 0.3 v v il input low voltage -0.3 0.0 0.8 v i i(l) input leakage current - - 1 m a i o(l) output leakage current - - 1 m a v oh output high voltage (i out = -4ma) 2.4 - v dd v v ol output low voltage (i out = +4ma) 0.0 - 0.4 v capacitance (t a = 25 c, f = 1mhz, vdd = 3.3v 0.3v, not 100% tested) symbol parameter 64mb 128mb 256mb 512mb units c in1 input capacitance (ba1, ba0, a0-12, ras, cas,we) 36 36 55 55 pf c in2 input capacitance (s0, s1) 20 20 32 32 pf c in3 input capacitance (ck0, ck1) 20 20 6 6 pf c in4 input capacitance (cke0, cke1) 32 32 32 32 pf c in5 input capacitance (dqmb0-7) 7 7 10 10 pf c in6 input capacitance (scl) 10 10 10 10 pf c i/o1 i/o capacitance (sda) 10 10 10 10 pf c i/o2 i/o capacitance (dq0 - dq63) 10 10 14 14 pf
144-pin sdram sodimms 64mb, 128mb, 256mb, 512mb preliminary data sheet enhanced memory systems inc., 1850 ramtron dr., colo spgs, co 80921 2001 enhanced memory systems. all rights reserved. phone: (800) 545-dram; fax: (719) 488-9095; http://www.edram.com the information contained herein is subject to change without notice. page 8 of 15 revision 1.0 ac characteristics (t a = 0 c to 70 c) 1. an initial pause of 200 m s is required after power-up, then a precharge all banks command must be given followed by a minimum of eight auto (cbr) refresh cycles before the mode register set operation can begin. 2. ac timing tests have v il = 0.8v and v ih = 2.0v with the timing referenced to the v tt = 1.4v crossover point. t setup t hold clock input output t lz t ac t oh t t vih vtt vil v tt output z 0 = 50 ohm c load = 50pf ac output load circuit v tt r t = 50 ohm 3. the transition time is measured between v ih and v il (or between v ih and v il ). 4. ac measurements assume t t = 1ns. 5. in addition to meeting the transition rate specification, the clock and cke must transition v ih and v il (or between v ih and v il ) in a monotonic manner.
144-pin sdram sodimms preliminary data sheet 64mb, 128mb, 256mb, 512mb enhanced memory systems inc., 1850 ramtron dr., colo spgs, co 80921 2001 enhanced memory systems. all rights reserved. phone: (800) 545-dram; fax: (719) 488-9095; http://www.edram.com the information contained herein is subject to change without notice. revision 1.0 page 9 of 15 ac operating conditions (t a = 0 c to 70 c) clock and clock enable parameters -7.5 symbol parameter min max units notes t ck2 clock cycle time, cl = 2 10 - ns t ck3 clock cycle time, cl = 3 7.5 - ns t ckh2 , t ckl2 clock high & low times, cl=2 2.5 - ns 1 t ckh3 , t ckl3 clock high & low times, cl=1 2.5 - ns 1 t ckes clock enable set-up time 1.5 - ns t ckeh clock enable hold time 0.8 - ns t cksp cke set-up time (power down mode) 1.5 - ns t t transition time (rise and fall) 0.3 1.2 ns notes: 1. assumes clock rise and fall times are equal to 1ns. if rise or fall time exceeds 1ns, other ac timing parameters must be co mpensated by an additional [(t rise +t fall )/2-1] ns. common parameters -7.5 symbol parameter min max units notes t cs command and address set-up time 1.5 - ns t ch command and address hold time 0.8 - ns t rcd ras to cas delay time 20 - ns t rc bank cycle time 67 - ns t ras bank active time 45 100k ns t rp precharge time 20 - ns t rrd bank to bank delay time (alt. bank) 15 - ns t ccd cas to cas delay time (same bank) 7.5 - ns t mrd mode register set to active delay 2 - clk
144-pin sdram sodimms 64mb, 128mb, 256mb, 512mb preliminary data sheet enhanced memory systems inc., 1850 ramtron dr., colo spgs, co 80921 2001 enhanced memory systems. all rights reserved. phone: (800) 545-dram; fax: (719) 488-9095; http://www.edram.com the information contained herein is subject to change without notice. page 10 of 15 revision 1.0 read and write parameters -7.5 symbol parameter min max units notes t ac3 clock access time, cl = 3 - 5.4 ns 1,2 t ac2 clock access time, cl = 2 - 6.0 ns 1,2 t oh3 data output hold time (cl=3) 3.0 - ns t oh2 data output hold time (cl=2) 3.0 - ns t lz data output to low-z time 1 - ns t hz2 data output to high-z time (cl=2, 3) 3 7 ns 3 t dqz dqm data output disable time 2 - clk t ds data input set-up time 1.5 - ns t dh data input hold time 0.8 - ns t dpl data input to precharge 15 - ns t dal data input to actv/refresh 35 - ns 4 t dqw data write mask latency 0 - clk notes: 1. access time is measured at 1.4v (lvttl) at max clock rate for the cas latency specified. see ac test load. 2. access time is based on a clock rise time of 1ns. if clock rise time is longer than 1ns, then (trise/2-0.5) ns must be added to the access time. 3. referenced to the time at which the output achieves an open circuit condition. 4. tdal is equal to tdpl + trp. refresh parameters -6 -7.5 symbol parameter min max min max units notes t ref refresh period - 64 - 64 ms 1,2 t srex self refresh exit time 2clk+t rc 2clk+t rc - ns 3 notes: 1. 4096 cycles (64, 128, and 256mb dimms), 8192 cycles (512mb dimms). 2. any time that the refresh period has been exceeded, a minimum of two auto-refresh (cbr) commands must be g iven to wake up the device. 3. self-refresh exit is a synchronous operation and begins on the 2nd positive clock edge after cke returns high. self-refresh exi t is not completed until trc is satisfied once the self-refresh exit command is registered.
144-pin sdram sodimms preliminary data sheet 64mb, 128mb, 256mb, 512mb enhanced memory systems inc., 1850 ramtron dr., colo spgs, co 80921 2001 enhanced memory systems. all rights reserved. phone: (800) 545-dram; fax: (719) 488-9095; http://www.edram.com the information contained herein is subject to change without notice. revision 1.0 page 11 of 15 serial presence detect (spd) for sdram sodimms 64mb 128mb 64mb 128mb byte description ** hex code ** 0 number of bytes written into eeprom 128 128 80 80 1 total number of spd bytes 256 256 08 08 2 memory type sdram sdram 04 04 3 number of row addresses 12 12 0c 0c 4 number of column addresses 9 10 09 0a 5 number of module banks 1 1 01 01 6 module data width x64 x64 40 40 7 module data width (cont'd) 0 0 00 00 8 voltage interface levels lvttl lvttl 01 01 9 cycle time at max cas latency 7.5 ns 7.5 ns 75 75 10 sdram clock access time 5.4 ns 5.4 ns 54 54 11 dimm config (non-parity, parity, ecc) --- non-parity --- 00 00 12 refresh rate and type --- 15.625us / self --- 80 80 13 primary sdram width x8 x8 08 08 14 error checking data width n/a n/a 00 00 15 min. cas-to-cas delay (tccd) 1 clk 1 clk 01 01 16 burst lengths supported --- 1,2,4,8,full pg --- 8f 8f 17 number of banks on sdram device 4 4 04 04 18 cas latencies supported 2,3 2,3 06 06 19 cs latency 0 0 01 01 20 write latency 0 0 01 01 21 sdram module attributes --- unbuffered --- 00 00 22 sdram device attributes +/-10% vdd, precharge all 07 07 23 min. clock cycle time at cl=2 10 ns 10 ns a0 a0 24 clock access time at cl=2 (tac2) 6.0 ns 6.0 ns 60 60 25 min. clock cycle time at cl=1 n/a n/a 00 00 26 clock access time at cl=1 (tac1) n/a n/a 00 00 27 min. row precharge time (trp) 20 ns 20 ns 14 14 28 min. row-to-row delay (trrd) 20 ns 20 ns 14 14 29 min. ras-to-cas delay (trcd) 20 ns 20 ns 14 14 30 min. ras pulse width (tras) 45 ns 45 ns 2d 2d 31 density of each bank on module 64mb 128mb 10 20 32 cmd/addr input set-up time 1.5 ns 15 15 33 cmd/addr input hold time 0.8 ns 08 08 34 data input set-up time 1.5 ns 15 15 35 data input hold time 0.8 ns 08 08 36-61 superset information - - 00 00 62 spd rev. 1.2 12 12 63 checksum for bytes 0-62 - - 9c ad 64-71 jedec id code enhanced memory systems 7f32ffffffffffff 72 manufacturing location - - xxxx xxxx 73-90 manufacturer's part # sm6408sdt sm12808asdt xxxx xxxx 91,92 pcb rev. code - rrrr rrrr 93,94 manufacturing date yyww code yyww yyww 95-98 assembly serial # serial number ssss ssss 99-125 manufacturer's specific data open 00 00 126 intel specification frequency 100mhz 64 64 127 intel specification cl and clock support - - af ff 128-255 open for customer use - - 00 00
144-pin sdram sodimms 64mb, 128mb, 256mb, 512mb preliminary data sheet enhanced memory systems inc., 1850 ramtron dr., colo spgs, co 80921 2001 enhanced memory systems. all rights reserved. phone: (800) 545-dram; fax: (719) 488-9095; http://www.edram.com the information contained herein is subject to change without notice. page 12 of 15 revision 1.0 serial presence detect (spd) for sdram sodimms 256mb 512mb 256mb 512mb byte description ** hex code ** 0 number of bytes written into eeprom 128 128 80 80 1 total number of spd bytes 256 256 08 08 2 memory type sdram sdram 04 04 3 number of row addresses 12 13 0c 0d 4 number of column addresses 10 10 0a 0a 5 number of module banks 2 2 02 02 6 module data width x64 x64 40 40 7 module data width (cont'd) 0 0 00 00 8 voltage interface levels lvttl lvttl 01 01 9 cycle time at max cas latency 7.5 ns 7.5 ns 75 75 10 sdram clock access time 5.4 ns 5.4 ns 54 54 11 dimm config (non-parity, parity, ecc) --- non-parity --- 00 00 12 refresh rate and type --- 15.625us / self --- 7.8 us 80 82 13 primary sdram width x8 x8 08 08 14 error checking data width n/a n/a 00 00 15 min. cas-to-cas delay (tccd) 1 clk 1 clk 01 01 16 burst lengths supported --- 1,2,4,8,full pg --- 8f 8f 17 number of banks on sdram device 4 4 04 04 18 cas latencies supported 2,3 2,3 06 06 19 cs latency 0 0 01 01 20 write latency 0 0 01 01 21 sdram module attributes --- unbuffered --- 00 00 22 sdram device attributes +/-10% vdd, precharge all 07 07 23 min. clock cycle time at cl=2 10 ns 10 ns a0 a0 24 clock access time at cl=2 (tac2) 6.0 ns 6.0 ns 60 60 25 min. clock cycle time at cl=1 n/a n/a 00 00 26 clock access time at cl=1 (tac1) n/a n/a 00 00 27 min. row precharge time (trp) 20 ns 20 ns 14 14 28 min. row-to-row delay (trrd) 20 ns 20 ns 14 14 29 min. ras-to-cas delay (trcd) 20 ns 20 ns 14 14 30 min. ras pulse width (tras) 45 ns 45 ns 2d 2d 31 density of each bank on module 128mb 256mb 20 40 32 cmd/addr input set-up time 1.5 ns 15 15 33 cmd/addr input hold time 0.8 ns 08 08 34 data input set-up time 1.5 ns 15 15 35 data input hold time 0.8 ns 08 08 36-61 superset information - - 00 00 62 spd rev. 1.2 12 12 63 checksum for bytes 0-62 - - ae d1 64-71 jedec id code enhanced memory systems 7f32ffffffffffff 72 manufacturing location - - xxxx xxxx 73-90 manufacturer's part # sm25608asdt sm51208bsdt xxxx xxxx 91,92 pcb rev. code - rrrr rrrr 93,94 manufacturing date yyww code yyww yyww 95-98 assembly serial # serial number ssss ssss 99-125 manufacturer's specific data open 00 00 126 intel specification frequency 100mhz 64 64 127 intel specification cl and clock support - - af ff 128-255 open for customer use - - 00 00
144-pin sdram sodimms preliminary data sheet 64mb, 128mb, 256mb, 512mb enhanced memory systems inc., 1850 ramtron dr., colo spgs, co 80921 2001 enhanced memory systems. all rights reserved. phone: (800) 545-dram; fax: (719) 488-9095; http://www.edram.com the information contained herein is subject to change without notice. revision 1.0 page 13 of 15 mechanical drawing front view 2.667 (67.75) 2.656 (67.45) pin 143 (pin 144 on backside) 0.236 (6.00) typ pin 1 (pin 2 on backside) 0.059 (1.50) typ 2.386 (60.60) dimensions: inches (mm) 144 - pin so dimm .024 (0.60) typ pad width 0.079 (2.00) typ 0.157 (4.00) 0.071 (1.800) (2x) 0.150 (3.80) typ 0.043 (1.10) 0.035 (0.90) 1.056 (26.82) 1.044 (26.52) 0.787 (20.00) typ .0315 (0.80) typ pitch .079 (2.00) r (2x) 0.240 (6.10) typ 0.043 (1.10) 0.035 (0.90) 256mb & 512mb sodimms 64mb & 128mb sodimms
144-pin sdram sodimms 64mb, 128mb, 256mb, 512mb preliminary data sheet enhanced memory systems inc., 1850 ramtron dr., colo spgs, co 80921 2001 enhanced memory systems. all rights reserved. phone: (800) 545-dram; fax: (719) 488-9095; http://www.edram.com the information contained herein is subject to change without notice. page 14 of 15 revision 1.0 revision log revision date summary of changes 1.0 3/29/01 first draft
144-pin sdram sodimms preliminary data sheet 64mb, 128mb, 256mb, 512mb enhanced memory systems inc., 1850 ramtron dr., colo spgs, co 80921 2001 enhanced memory systems. all rights reserved. phone: (800) 545-dram; fax: (719) 488-9095; http://www.edram.com the information contained herein is subject to change without notice. revision 1.0 page 15 of 15 ordering information part number capacity i/o width i/o type package power supply maximum operating frequency (mhz) sm6408sdt-7.5 64 mb x64 lvttl 144-pin sodimm 3.3v 133 sm12808asdt-7.5 128 mb x64 lvttl 144-pin sodimm 3.3v 133 sm25608asdt-7.5 256 mb x64 lvttl 144-pin sodimm 3.3v 133 sm51208bsdt-7.5 512 mb x64 lvttl 144-pin sodimm 3.3v 133

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