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d a t a sh eet preliminary speci?cation supersedes data of 1997 may 20 file under integrated circuits, ic01 1997 jul 09 integrated circuits UDA1340 low-voltage low-power stereo audio codec with dsp features
1997 jul 09 2 philips semiconductors preliminary speci?cation low-voltage low-power stereo audio codec with dsp features UDA1340 features general low power consumption 3.0 v power supply 256, 384 and 512f s system clock small package size (ssop28) adc plus integrated high pass filter to cancel dc offset overload detector for easy record level control separate power control for adc and dac integrated digital filter plus dac no analog post filter required for dac easy application functions controllable by microcontroller interface. multiple format input interface i 2 s-bus, msb-justified and lsb-justified format compatible 1f s input and output format data rate. dac digital sound processing digital volume control digital tone control, bass boost and treble db-linear volume and tone control (low microcontroller load) digital de-emphasis for 32, 44.1 and 48 khz f s soft mute. advanced audio con?guration stereo single-ended input configuration stereo line output (under microcontroller volume control) power-down click prevention circuitry high linearity, dynamic range, low distortion. general description the UDA1340 is a single-chip stereo analog-to-digital converter (adc) and digital-to-analog converter (dac) with signal processing features employing bitstream conversion techniques. the low power consumption and low voltage requirements make the device eminently suitable for use in low-voltage low-power portable digital audio equipment which incorporates recording and playback functions. the UDA1340 supports the i 2 s-bus data format with word lengths of up to 20 bits, the msb-justified data format with word lengths of up to 20 bits and the lsb justified serial data format with word lengths of 16, 18 and 20 bits. the UDA1340 has special sound processing features in playback mode, de-emphasis, volume, bass boost, treble, and soft mute, which can be controlled via the microcontroller interface. ordering information type number package name description version UDA1340m ssop28 plastic shrink small outline package; 28 leads; body width 5.3 mm sot341-1
1997 jul 09 3 philips semiconductors preliminary speci?cation low-voltage low-power stereo audio codec with dsp features UDA1340 quick reference data symbol parameter conditions min. typ. max. unit supply v dda(adc) adc analog supply voltage 2.7 3.0 3.6 v v dda(dac) dac analog supply voltage 2.7 3.0 3.6 v v ddo operational ampli?ers supply voltage 2.7 3.0 3.6 v v ddd digital supply voltage 2.7 3.0 3.6 v i dda(adc) adc supply current - 4.5 - ma i dda(dac) dac supply current - 3.5 - ma i ddo operational ampli?er supply current - 4 - ma i ddd digital supply current - 6 - ma i pd(adc) digital adc power-down supply current - 3 - ma i pd(dac) digital dac power-down supply current - 3 - ma t amb operating ambient temperature - 20 - +85 c analog-to-digital converter v i(rms) input voltage (rms value) - 0.8 - v (thd + n)/s total harmonic distortion plus noise-to-signal ratio at 0 db -- 85 - 80 db at - 60 db; a-weighted -- 35 - 30 dba s/n signal-to-noise ratio v i = 0 v; a-weighted - 95 - dba a cs channel separation - 100 - db digital-to-analog converter v o(rms) output voltage (rms value) - 0.8 - v (thd + n)/s total harmonic distortion plus noise-to-signal ratio at 0 db -- 85 - 80 db at - 60 db; a-weighted -- 35 - dba s/n signal-to-noise ratio code = 0; a weighted - 100 - dba a cs channel separation - 100 - db power performance p adda power consumption in record and playback mode - 54 - mw p da power consumption in playback only mode - 33 - mw p ad power consumption in record only mode - 27 - mw p pd power consumption in power-down mode - 6 - mw
1997 jul 09 4 philips semiconductors preliminary speci?cation low-voltage low-power stereo audio codec with dsp features UDA1340 block diagram fig.1 block diagram. handbook, full pagewidth mgg839 adc 3 5 10 11 18 16 17 19 25 27 23 22 12 15 14 13 20 21 8 vinl v ddd v ssd datao bck ws datai overfl voutl 28 24 9 26 voutr sysclk l3data l3clock l3mode test3 test2 test1 vinr 21 76 4 decimation filter dc-cancellation filter digital interface l3-bus interface adc dac v ref(d) v ddo v sso dac interpolation filter noise shaper dsp features v dda(adc) v ssa(adc) v adcp v adcn v ref(a) UDA1340 v dda(dac) v ssa(dac)
1997 jul 09 5 philips semiconductors preliminary speci?cation low-voltage low-power stereo audio codec with dsp features UDA1340 pinning symbol pin description v ssa(adc) 1 adc analog ground v dda(adc) 2 adc analog supply voltage vinl 3 adc input left v ref(a) 4 adc reference voltage vinr 5 adc input right v adcn 6 adc negative reference voltage v adcp 7 adc positive reference voltage test1 8 test control 1 (pull-down) overfl 9 overload ?ag output v ddd 10 digital supply voltage v ssd 11 digital ground sysclk 12 system clock 256, 384 or 512f s l3mode 13 l3-bus mode input l3clock 14 l3-bus clock input l3data 15 l3-bus data input bck 16 bit clock input ws 17 word selection input datao 18 data output datai 19 data input test3 20 test output test2 21 test control 2 (pull-down) v ssa(dac) 22 dac analog ground v dda(dac) 23 dac analog supply voltage voutr 24 dac output right v ddo 25 operational ampli?er supply voltage voutl 26 dac output left v sso 27 operational ampli?er ground v ref(d) 28 dac reference voltage fig.2 pin configuration. handbook, halfpage v ssa(adc) v dda(adc) vinl v ref(a) vinr v adcn v adcp test1 overfl v ddd v ssd sysclk l3mode l3clock v ref(d) v sso voutl v ddo v dda(dac) v ssa(dac) voutr test2 test3 datai datao ws bck l3data 1 2 3 4 5 6 7 8 9 10 11 12 13 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 UDA1340 mgg838
1997 jul 09 6 philips semiconductors preliminary speci?cation low-voltage low-power stereo audio codec with dsp features UDA1340 functional description system clock the UDA1340 accommodates slave mode only, this means that in all applications the system devices must provide the system clock. the system frequency is selectable. the options are 256f s , 384f s and 512f s . the system clock must be locked in frequency to the digital interface input signals. multiple format input/output interface the UDA1340 supports the following data input/output formats: i 2 s-bus with data word length of up to 20 bits msb justified serial format with data word length of up to 20 bits lsb justified serial format with data word lengths of 16, 18 or 20 bits. the formats are illustrated in fig.3. left and right data-channel words are time multiplexed. analog-to-digital converter (adc) the stereo adc of the UDA1340 consists of two third-order sigma-delta modulators. they have a modified ritchie-coder architecture in a differential switched capacitor implementation. the over-sampling ratio is 128. decimation ?lter (adc) the decimation from 128f s is performed in two stages. the first stage realizes 3rd-order characteristic. this filter decreases the sample rate by 16. the second stage, an fir filter, consists of 3 half-band filters, each decimating by a factor of 2. table 1 decimation ?lter characteristics item condition value (db) passband ripple 0 - 0.45f s 0.05 stop band >0.55f s - 60 dynamic range 0 - 0.45f s 108 gain overall - 1.16 sin x x ----------- - dc cancellation ?lter (adc) an optional iir high-pass filter is provided to remove unwanted dc components. the operation is selected by the microcontroller via the l3-bus. the filter characteristics are given in table 2. table 2 dc cancellation ?lter characteristics mute (adc) on recovery from power-down or switching on of the system clock, the serial data output datao is held low until valid data is available from the decimation filter. this time depends on whether the dc cancellation filter is selected: dc cancel off: time = , t = 23.2 ms when f s = 44.1 khz dc cancel on: time = , t = 279 ms when f s = 44.1 khz overload detection (adc) in practice the output is used to indicate whenever the output data, in either the left or right channel, is greater than - 1 db (actual figure is - 1.16 db) of the maximum possible digital swing. when this condition is detected the overfl output is forced high for at least 512f s cycles (11.6 ms at f s = 44.1 khz). this time-out is reset for each infringement. item condition value (db) passband ripple none passband gain 0 droop at 0.00045f s 0.031 attenuation at dc at 0.00000036f s >40 dynamic range 0 - 0.45f s >110 1024 f s ------------ - 12288 f s ----------------
1997 jul 09 7 philips semiconductors preliminary speci?cation low-voltage low-power stereo audio codec with dsp features UDA1340 interpolation ?lter (dac) the digital filter interpolates from 1f s to 128f s by means of a cascade of a recursive filter and an fir filter. table 3 interpolation ?lter characteristics noise shaper (dac) the 3rd-order noise shaper operates at 128f s . it shifts in-band quantization noise to frequencies well above the audio band. this noise shaping technique enables high signal-to-noise ratios to be achieved. the noise shaper output is converted into an analog signal using a filter stream digital-to-analog converter. item condition value (db) passband ripple 0 - 0.45f s 0.03 stop band >0.55f s - 50 dynamic range 0 - 0.45f s 108 gain dc - 3.5 the filter stream dac (fsdac) the fsdac is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. the filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. in this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. a post-filter is not needed due to the inherent filter function of the dac. on-board amplifiers convert the fsdac output current to an output voltage signal capable of driving a line output.
1997 jul 09 8 philips semiconductors preliminary speci?cation low-voltage low-power stereo audio codec with dsp features UDA1340 d book, full pagewidth lsb-justified format 16 bits lsb-justified format 18 bits lsb-justified format 20 bits msb-justified format ws left left left left right right right right 3 2 2 2 15 16 17 18 1 15 16 1 1 3 2 1 msb b2 msb lsb lsb msb b2 b2 msb lsb b2 msb b2 b3 b4 b15 lsb b17 2 15 16 17 18 1 msb b2 b3 b4 lsb b17 2 15 16 17 18 19 20 1 msb b2 b3 b4 b5 b6 lsb b19 2 15 16 17 18 19 20 1 msb b2 b3 b4 b5 b6 lsb b19 2 15 16 1 msb lsb b2 b15 > =8 > =8 bck data ws left right 3 2 1 3 2 1 msb b2 msb lsb lsb msb b2 > =8 > =8 bck data ws bck data ws bck data ws bck data input format i 2 s-bus mgg841 fig.3 serial interface formats.
1997 jul 09 9 philips semiconductors preliminary speci?cation low-voltage low-power stereo audio codec with dsp features UDA1340 l3-interface the UDA1340 has a microcontroller input mode. in the microcontroller mode, all the digital sound processing features and the system controlling features can be controlled by the microcontroller. the controllable features are: system clock frequency data input format power control dc-filtering de-emphasis volume flat/min/max switch bass boost treble mute. the exchange of data and control information between the microcontroller and the UDA1340 is accomplished through a serial hardware interface comprising the following pins: l3data: microcontroller interface data line l3mode: microcontroller interface mode line l3clock: microcontroller interface clock line. information transfer via the microcontroller bus is organized in accordance with the so called l3 format, in which two different modes of operation can be distinguished; address mode and data transfer mode (see figs 4 and 5). the address mode is required to select a device communicating via the l3-bus and to define the destination registers for the data transfer mode. data transfer for the UDA1340 can only be in one direction, input to the UDA1340 to program its sound processing and other functional features. address mode the address mode is used to select a device for subsequent data transfer and to define the destination registers. the address mode is characterized by l3mode being low and a burst of 8 pulses on l3clock, accompanied by 8 data bits. the fundamental timing is shown in fig.4. data bits 0 to 1 indicate the type of subsequent data transfer as given in table 4. table 4 selection of data transfer data bits 7 to 2 represent a 6-bit device address, with bit 7 being the msb and bit 2 the lsb. the address of the UDA1340 is 000101 (bit 7 to bit 2). in the event that the UDA1340 receives a different address, it will deselect its microcontroller interface logic. data transfer mode the selection preformed in the address mode remains active during subsequent data transfers, until the UDA1340 receives a new address command. the fundamental timing of data transfers is essentially the same as in the address mode, shown in fig.4. the maximum input clock and data rate is 64f s . all transfers are byte wise, i.e. they are based on groups of 8 bits. data will be stored in the UDA1340 after the eighth bit of a byte has been received. a multibyte transfer is illustrated in fig.6. p rogramming the sound processing and other features the sound processing and other feature values are stored in independent registers. the first selection of the registers is achieved by the choice of data type that is transferred. this is performed in the address mode, bit 1 and bit 0 (see table 4). the second selection is performed by the 2 msbs of the data byte (bit 7 and bit 6). the other bits in the data byte (bit 5 to bit 0) is the value that is placed in the selected registers. when the data transfer of type data is selected, the features volume, bass boost, treble, de-emphasis, mute, mode and power control can be controlled. when the data transfer of type status is selected, the features system clock frequency, data input format and dc-filter can be controlled. bit 1 bit 0 transfer 0 0 data (volume, bass boost, treble, de-emphasis, mute, mode and power control) 0 1 not used 1 0 status (system clock frequency, data input format and dc-?lter) 1 1 not used
1997 jul 09 10 philips semiconductors preliminary speci?cation low-voltage low-power stereo audio codec with dsp features UDA1340 fig.4 timing address mode. handbook, full pagewidth t h;ma t s;ma t h;dat t s;dat t cy bit 0 l3mode l3clock l3data bit 7 mgd016 t lc t hc t s;ma t h;ma fig.5 timing for data transfer mode. handbook, full pagewidth t halt t s;mt t h;dat t s;dat t h;dat t halt t h;mt mgd017 t cy bit 0 l3mode l3clock l3data write bit 7 t lc t hc
1997 jul 09 11 philips semiconductors preliminary speci?cation low-voltage low-power stereo audio codec with dsp features UDA1340 table 5 data transfer of type status; note 1 note 1. x = dont care. table 6 data transfer of type data; note 1 note 1. x = dont care. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register selected 0 x sc1 sc0 if2 if1 if0 dc system clock frequency (1 : 0) data input format (2 : 0) dc-?lter 1xxxxxxx not used bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register selected 0 0 vc5 vc4 vc3 vc2 vc1 vc0 volume control (5 : 0) 0 1 bb3 bb2 bb1 bb0 tr1 tr0 bass boost (3 : 0) treble (1 : 0) 1 0 x de1 de0 mt m1 m0 de-emphasis (1 : 0) mute mode (1 : 0) 1 1xxxxpc1pc0 power control (1 : 0) fig.6 multibyte transfer. h andbook, full pagewidth t halt address l3data l3clock l3mode address data byte #1 data byte #2 mgd018
1997 jul 09 12 philips semiconductors preliminary speci?cation low-voltage low-power stereo audio codec with dsp features UDA1340 s ystem clock frequency a 2-bit value (sc1 and sc0) to select the used external clock frequency (see table 7). table 7 system clock frequency settings d ata input format a 3-bit value (if2 to if0) to select the used data format (see table 8). table 8 data input format settings sc1 sc0 function 0 0 512f s 0 1 384f s 1 0 256f s 1 1 not used if2 if1 if0 function 000 i 2 s-bus 0 0 1 lsb justi?ed, 16 bits 0 1 0 lsb justi?ed, 18 bits 0 1 1 lsb justi?ed, 20 bits 1 0 0 msb justi?ed 1 0 1 not used 1 1 0 not used 1 1 1 not used dc- filter a 1-bit value to enable the digital dc-filter (see table 9). table 9 dc-?ltering v olume control a 6-bit value to program the left and right channel volume attenuation (vc5 to vc0). the range is 0 db to - db in steps of 1 db (see table 10). table 10 volume settings dc function 0 no dc-?ltering 1 dc-?ltering vc5 vc4 vc3 vc2 vc1 vc0 volume (db) 000000 0 000001 0 000010 - 1 000011 - 2 :::::: : 111011 - 58 111100 - 59 111101 - 60 111110 - 111111 -
1997 jul 09 13 philips semiconductors preliminary speci?cation low-voltage low-power stereo audio codec with dsp features UDA1340 b ass boost a 4-bit value to program the bass boost setting. the used set depends on the mode bits. table 11 bass boost settings t reble a 2-bit value to program the treble setting. the used set depends on the mode bits. table 12 treble settings bb3 bb2 bb1 bb0 bass boost flat set (db) min. set (db) max. set (db) 0000 0 0 0 0001 0 2 2 0010 0 4 4 0011 0 6 6 0100 0 8 8 0101 0 10 10 0110 0 12 12 0111 0 14 14 1000 0 16 16 1001 0 18 18 1010 0 18 20 1011 0 18 22 1100 0 18 24 1101 0 18 24 1110 0 18 24 1111 0 18 24 tr1 tr0 treble flat set (db) min. set (db) max. set (db) 00000 01022 10044 11066
1997 jul 09 14 philips semiconductors preliminary speci?cation low-voltage low-power stereo audio codec with dsp features UDA1340 d e - emphasis a 2-bit value to enable the digital de-emphasis filter. table 13 de-emphasis settings m ute a 1-bit value to enable the digital mute. table 14 mute m ode a 2-bit value to program the mode of the sound processing filters of bass boost and treble. there are three modes: flat, min. and max. de1 de0 function 0 0 no de-emphasis 0 1 de-emphasis, 32 khz 1 0 de-emphasis, 44.1 khz 1 1 de-emphasis, 48 khz mt function 0 no muting 1 muting table 15 the ?at/min./max. switch p ower c ontrol a 2-bit value to disable the adc and/or dac to reduce power consumption. table 16 power control settings m1 m0 function 0 0 ?at 0 1 min. 1 0 min. 1 1 max. pc1 pc0 function adc dac 00offoff 0 1 off on 1 0 on off 1 1 on on limiting values in accordance with the absolute maximum rating system (iec 134). all voltage referenced to ground, v ddd =v dda =v ddo = 3 v; t amb =25 c; unless otherwise specified. notes 1. all v dd and v ss connections must be made to the same power supply. 2. equivalent to discharging a 100 pf capacitor via a 1.5 k w series resistor, except pins 24, 26 and 28 which can withstand esd pulses of - 1500 v to +1500 v. 3. equivalent to discharging a 200 pf capacitor via a 2.5 m h series inductor. thermal characteristics symbol parameter conditions min. max. unit v ddd supply voltage note 1 - 5.0 v t xtal(max) maximum crystal temperature - 150 c t stg storage temperature - 65 +125 c t amb operating ambient temperature - 20 +85 c v es electrostatic handling note 2 - 3000 +3000 v note 3 - 300 +300 v symbol parameter value unit r th j-a thermal resistance from junction to ambient in free air 90 k/w
1997 jul 09 15 philips semiconductors preliminary speci?cation low-voltage low-power stereo audio codec with dsp features UDA1340 dc characteristics v ddd =v dda =v ddo =3v; t amb =25 c; r l =5k w ; note 1; all voltages referenced to ground (pins 1, 11, 22 and 27); unless otherwise speci?ed. notes 1. all power supply pins (v dd and v ss ) must be connected to the same external power supply unit. 2. when higher capacitive loads must be driven then a 100 w resistor must be connected in series with the dac output in order to prevent oscillations in the output operational amplifier. symbol parameter conditions min. typ. max. unit supply v dda(adc) adc analog supply voltage 2.7 3.0 3.6 v v dda(dac) dac analog supply voltage 2.7 3.0 3.6 v v ddo operational ampli?ers supply voltage 2.7 3.0 3.6 v v ddd digital supply voltage 2.7 3.0 3.6 v i dda(adc) adc supply current operation mode - 4.5 - ma adc power-down - 200 -m a i dda(dac) dac supply current operation mode - 3.5 - ma dac power-down - 15 -m a i ddo operational ampli?er supply current operation mode - 4 - ma dac power-down - 15 -m a i ddd digital supply current operation mode - 6 - ma dac power-down - 3 - ma adc power-down - 3 - ma digital input pins v ih high level input voltage 0.8v ddd - v ddd + 0.5 v v il low level input voltage - 0.5 - +0.2v ddd v ? i li ? input leakage current -- 10 m a c i input capacitance -- 10 pf digital output pins v oh high level output voltage i oh = - 2 ma 0.85v ddd -- v v ol low level output voltage i ol =2ma -- 0.4 v analog-to-digital converter v ref reference voltage with respect to v ssa 0.45v dda 0.5v dda 0.55v dda v r o(ref) v refa reference output resistance pin 4 - 24 - k w r i input resistance 1 khz - 9.8 - k w c i input capacitance - 20 - pf digital-to-analog converter v ref reference voltage with respect to v ssa 0.45v dda 0.5v dda 0.55v dda v r o(ref) v refd reference output resistance pin 28 - 28 - k w r o dac output resistance - 0.13 3.0 w i o(max) maximum output current (thd + n)/s < 0.1% r l =5k w - 0.22 - ma r l load resistance 3 -- k w c l load capacitance note 2 -- 200 pf
1997 jul 09 16 philips semiconductors preliminary speci?cation low-voltage low-power stereo audio codec with dsp features UDA1340 ac characteristics (analog) v ddd =v dda =v ddo =3v; f i = 1 khz; t amb =25 c; r l =5k w all voltages referenced to ground (pins 1, 11, 22 and 27); unless otherwise speci?ed . symbol parameter conditions min. typ. max. unit analog-to-digital converter v i(rms) input voltage (rms value) - 0.8 - v d v i unbalance between channels - 0.1 - db (thd + n)/s total harmonic distortion plus noise-to-signal ratio at 0 db -- 85 - 80 db at - 60 db; a-weighted -- 35 - 30 dba s/n signal-to-noise ratio v i = 0 v; a-weighted - 95 - dba a cs channel separation - 100 - db psrr power supply rejection ratio f ripple = 1 khz; v ripple(p-p) =30mv - 30 - db digital-to-analog converter v o(rms) output voltage (rms value) - 0.8 - v d v o unbalance between channels - 0.1 - db (thd + n)/s total harmonic distortion plus noise-to-signal ratio at 0 db -- 85 - 80 db at - 60 db; a-weighted -- 35 - dba s/n signal-to-noise ratio code = 0; a-weighted - 100 - dba a cs channel separation - 80 - db psrr power supply rejection ratio f ripple = 1 khz; v ripple(p-p) = 100 mv - 50 - db
1997 jul 09 17 philips semiconductors preliminary speci?cation low-voltage low-power stereo audio codec with dsp features UDA1340 ac characteristics (digital) v ddd =v dda =v ddo = 2.7 to 3.6 v; t amb = - 20 to +85 c; r l =5k w ; all voltages referenced to ground (pins 1, 11, 22 and 27); unless otherwise specified. symbol parameter conditions min. typ. max. unit t cy clock cycle f sys = 256f s 78 88 131 ns f sys = 384f s 52 59 87 ns f sys = 512f s 39 44 66 ns t cwl f sys low level pulse width f sys < 19.2 mhz 30 - 70 %t sys f sys 3 19.2 mhz 40 - 60 %t sys t cwh f sys high level pulse width f sys < 19.2 mhz 30 - 70 %t sys f sys 3 19.2 mhz 40 - 60 %t sys serial input/output data timing; see fig.7 t bck bit clock period 1 64 f s -- ns t bck(h) bit clock high time 100 -- ns t bck(l) bit clock low time 100 -- ns t r rise time -- 20 ns t f fall time -- 20 ns t s;dati data input set-up time 20 -- ns t h;dati data input hold time 0 -- ns t d(dato)(bck) data output delay time (from bck falling edge) -- 80 ns t d(dato)(ws) data output delay time (from ws edge) msb-justi?ed format -- 80 ns t h;dato data output hold time 0 -- ns t s;ws word selection set-up time 20 -- ns t h;ws word selection hold time 10 -- ns address and data transfer mode timing; see figs 4 and 5 t cy l3clk cycle time 500 -- ns t hc l3clk high period 250 -- ns t lc l3clk low period 250 -- ns t s;ma l3mode set-up time address mode 190 -- ns t h;ma l3mode hold time address mode 190 -- ns t s;mt l3mode set-up time data transfer mode 190 -- ns t h;mt l3mode hold time data transfer mode 190 -- ns t s;dat l3data set-up time data transfer mode and address mode 190 -- ns t h;dat l3data hold time data transfer mode and address mode 30 -- ns t halt l3mode halt time 190 -- ns
1997 jul 09 18 philips semiconductors preliminary speci?cation low-voltage low-power stereo audio codec with dsp features UDA1340 fig.7 serial interface timing. handbook, full pagewidth mgg840 ws bck datao datai t f t r t h;ws t s;ws t bck(h) t bck(l) t cy t h;dato t s;dati t h;dati t d(dato)(bck) t d(dato)(ws)
1997 jul 09 19 philips semiconductors preliminary speci?cation low-voltage low-power stereo audio codec with dsp features UDA1340 application information fig.8 application diagram. handbook, full pagewidth mgk582 47 w r30 c11 100 m f (16 v) c12 100 m f (16 v) v dda v ddd l1 8lm32a07 8lm32a07 l2 3 v ground 1 v ssa(adc) UDA1340 12 4 sysclk v ref(a) 10 26711 v ddd v dda(adc) v adcn v adcp v ssd system clock 18 datao 16 bck 17 ws overload flag 9 overfl r32 1 m w c1 c31 1 nf (63 v) 47 m f (16 v) 3 vinl 26 voutl r23 100 w r22 10 k w 24 voutr r26 100 w r27 10 k w r33 680 k w c6 c32 1 nf (63 v) 47 m f (16 v) 5 vinr 19 datai 13 l3mode 14 l3clock 15 l3data 100 nf (63 v) r21 1 w r24 c2 100 m f (16 v) c25 100 nf (63 v) c21 v dda c3 47 m f (16 v) c8 47 m f (16 v) c5 47 m f (16 v) c22 100 nf (63 v) 28 v ref(d) c4 47 m f (16 v) c23 100 nf (63 v) 100 nf (63 v) r28 1 w c9 100 m f (16 v) c29 v ddd v sso 27 v ddo 25 r25 1 w c7 100 m f (16 v) c26 100 nf (63 v) v ddo v dda(dac) v ssa(dac) 23 22 r29 1 w c10 100 m f (16 v) c27 100 nf (63 v) v dda left output right output left input right input x5 x4 x2 x3
1997 jul 09 20 philips semiconductors preliminary speci?cation low-voltage low-power stereo audio codec with dsp features UDA1340 package outline unit a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 0.21 0.05 1.80 1.65 0.38 0.25 0.20 0.09 10.4 10.0 5.4 5.2 0.65 1.25 7.9 7.6 0.9 0.7 1.1 0.7 8 0 o o 0.13 0.1 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.20 mm maximum per side are not included. 1.03 0.63 sot341-1 mo-150ah 93-09-08 95-02-04 x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 114 28 15 0.25 y pin 1 index 0 2.5 5 mm scale ssop28: plastic shrink small outline package; 28 leads; body width 5.3 mm sot341-1 a max. 2.0
1997 jul 09 21 philips semiconductors preliminary speci?cation low-voltage low-power stereo audio codec with dsp features UDA1340 soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). re?ow soldering reflow soldering techniques are suitable for all ssop packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. wave soldering wave soldering is not recommended for ssop packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. even with these conditions, only consider wave soldering ssop packages that have a body width of 4.4 mm, that is ssop16 (sot369-1) or ssop20 (sot266-1) . during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1997 jul 09 22 philips semiconductors preliminary speci?cation low-voltage low-power stereo audio codec with dsp features UDA1340 definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
1997 jul 09 23 philips semiconductors preliminary speci?cation low-voltage low-power stereo audio codec with dsp features UDA1340 notes
internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1997 sca55 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reli able and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 1231, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: rua do rocio 220, 5th floor, suite 51, 04552-903 s?o paulo, s?o paulo - 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