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ltc2430/ltc2431 1 24301f the ltc ? 2430/ltc2431 are 2.7v to 5.5v micropower 20-bit differential ds analog-to-digital converters with an integrated oscillator, 3ppm inl and 0.56ppm rms noise. they use delta-sigma technology and provide single cycle settling time for multiplexed applications. through a single pin, the ltc2430/ltc2431 can be configured for better than 110db differential mode rejection at 50hz or 60hz 2%, or they can be driven by an external oscillator for a user-defined rejection frequency. the internal oscil- lator requires no external frequency setting components. the converters accept any external differential reference voltage from 0.1v to v cc for flexible ratiometric and remote sensing measurement configurations. the full- scale differential input range is from C 0.5v ref to 0.5v ref . the reference common mode voltage, v refcm , and the input common mode voltage, v incm , may be indepen- dently set anywhere within gnd to v cc . the dc common mode input rejection is better than 120db. the ltc 2430/ltc2431 communicate through a flexible 3-wire digital interface that is compatible with spi and microwire tm protocols. n direct sensor digitizer n weight scales n direct temperature measurement n gas analyzers n strain gauge transducers n instrumentation n data acquisition n industrial process control n dvms and meters , ltc and lt are registered trademarks of linear technology corporation. n low supply current (200 m a in conversion mode and 4 m a in autosleep mode) n differential input and differential reference with gnd to v cc common mode range n 3ppm inl, no missing codes n 10ppm full-scale error and 1ppm offset n 0.56ppm noise, 20.8 enobs n no latency: digital filter settles in a single cycle. each conversion is accurate, even after an input step n single supply 2.7v to 5.5v operation n internal oscillatorno external components required n 110db min, 50hz/60hz notch filter n pin compatible with 24-bit ltc2410/ltc2411 20-bit no latency ds tm adcs with differential input and differential reference no latency ds is a trademark of linear technology corporation. microwire is a trademark of national semiconductor corporation. v cc f o 64 12 ref + ref sck in + in sdo gnd cs analog input range 0.5v ref to 0.5v ref 3-wire spi interface 0.1 f 0.1 f ltc2431 24301 ta01 4.7 f = internal osc/50hz rejection = external clock source = internal osc/60hz rejection v cc lt1790 (v out + 0.25v) to 20v v out 3v to 5v descriptio u features applicatio s u typical applicatio s u input voltage (v) ?.5 tue (ppm of v ref ) 1 3 5 1.5 24301 g01 ? ? 0 2 4 ? ? ? ?.5 ? ?.5 ? 0.5 1 2 0 2.5 v cc = 5v v ref = 5v v incm = v incm = 2.5v f o = gnd 85 c 25 c ?5 c total unadjusted error (v cc = 5v, v ref = 5v)
ltc2430/ltc2431 2 24301f 2430 2430i (notes 1, 2) order part number supply voltage (v cc ) to gnd .......................C 0.3v to 7v analog input pins voltage to gnd ......................................... C 0.3v to (v cc + 0.3v) reference input pins voltage to gnd ......................................... C 0.3v to (v cc + 0.3v) digital input voltage to gnd ........ C 0.3v to (v cc + 0.3v) t jmax = 125 c, q ja = 120 c/w ltc2430cgn ltc2430ign gn part marking absolute axi u rati gs w ww u package/order i for atio uu w 1 2 3 4 5 v cc ref + ref in + in 10 9 8 7 6 f o sck sdo cs gnd top view ms package 10-lead plastic msop consult ltc marketing for parts specified with wider operating temperature ranges. digital output voltage to gnd ..... C 0.3v to (v cc + 0.3v) operating temperature range ltc2430c/ltc2431c .............................. 0 c to 70 c ltc2430i/ltc2431i ........................... C 40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c ltxd ltxe order part number ltc2431cms ltc2431ims ms part marking gn package 16-lead plastic ssop 1 2 3 4 5 6 7 8 top view 16 15 14 13 12 11 10 9 gnd v cc ref + ref in + in gnd gnd gnd gnd f o sck sdo cs gnd gnd parameter conditions min typ max units resolution (no missing codes) 0.1v v ref v cc , C 0.5 ? v ref v in 0.5 ? v ref (note 5) l 20 bits integral nonlinearity 4.5v v cc 5.5v, ref + = 2.5v, ref C = gnd, v incm = 1.25v (note 6) 2 ppm of v ref 5v v cc 5.5v, ref + = 5v, ref C = gnd, v incm = 2.5v (note 6) l 3 20 ppm of v ref ref + = 2.5v, ref C = gnd, v incm = 1.25v (note 6) 10 ppm of v ref offset error 2.5v ref + v cc , ref C = gnd, l 520 m v gnd in + = in C v cc (note 14) offset error drift 2.5v ref + v cc , ref C = gnd, 50 nv/ c gnd in + = in C v cc positive full-scale error 2.5v ref + v cc , ref C = gnd, l 10 20 ppm of v ref in + = 0.75ref + , in C = 0.25 ? ref + positive full-scale error drift 2.5v ref + v cc , ref C = gnd, 0.1 ppm of v ref / c in + = 0.75ref + , in C = 0.25 ? ref + negative full-scale error 2.5v ref + v cc , ref C = gnd, l 10 20 ppm of v ref in + = 0.25 ? ref + , in C = 0.75 ? ref + negative full-scale error drift 2.5v ref + v cc , ref C = gnd, 0.1 ppm of v ref / c in + = 0.25 ? ref + , in C = 0.75 ? ref + total unadjusted error 4.5v v cc 5.5v, ref + = 2.5v, ref C = gnd, v incm = 1.25v 3 ppm of v ref 5v v cc 5.5v, ref + = 5v, ref C = gnd, v incm = 2.5v 6 ppm of v ref ref + = 2.5v, ref C = gnd, v incm = 1.25v 15 ppm of v ref output noise 5v v cc 5.5v, ref + = 5v, v ref C = gnd, 2.8 m v rms gnd in C = in + 5v, (note 13) the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (notes 3, 4) electrical characteristics t jmax = 125 c, q ja = 110 c/w ltc2430/ltc2431 3 24301f symbol parameter conditions min typ max units in + absolute/common mode in + voltage l gnd C 0.3v v cc + 0.3v v in C absolute/common mode in C voltage l gnd C 0.3v v cc + 0.3v v v in input differential voltage range l Cv ref /2 v ref /2 v (in + C in C ) ref + absolute/common mode ref + voltage l 0.1 v cc v ref C absolute/common mode ref C voltage l gnd v cc C 0.1v v v ref reference differential voltage range l 0.1 v cc v (ref + C ref C ) c s (in + )in + sampling capacitance 1.5 pf c s (in C )in C sampling capacitance 1.5 pf c s (ref + )ref + sampling capacitance 1.5 pf c s (ref C )ref C sampling capacitance 1.5 pf i dc_leak (in + )in + dc leakage current cs = v cc , in + = gnd l C10 1 10 na i dc_leak (in C )in C dc leakage current cs = v cc , in C = v cc l C10 1 10 na i dc_leak (ref + )ref + dc leakage current cs = v cc , ref + = v cc l C10 1 10 na i dc_leak (ref C )ref C dc leakage current cs = v cc , ref C = gnd l C10 1 10 na the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) parameter conditions min typ max units input common mode rejection dc 2.5v ref + v cc , ref C = gnd, l 110 120 db gnd in C = in + 5v (note 5) input common mode rejection 2.5v ref + v cc , ref C = gnd, l 140 db 60hz 2% gnd in C = in + 5v, (notes 5, 7) input common mode rejection 2.5v ref + v cc , ref C = gnd, l 140 db 50hz 2% gnd in C = in + 5v, (notes 5, 8) input normal mode rejection (notes 5, 7) l 110 140 db 60hz 2% input normal mode rejection (notes 5, 8) l 110 140 db 50hz 2% reference common mode 2.5v ref + v cc , gnd ref C 2.5v, l 130 140 db rejection dc v ref = 2.5v, in C = in + = gnd (note 5) power supply rejection, dc ref + = 2.5v, ref C = gnd, in C = in + = gnd 110 db power supply rejection, 60hz 2% ref + = 2.5v, ref C = gnd, in C = in + = gnd, (note 7) 120 db power supply rejection, 50hz 2% ref + = 2.5v, ref C = gnd, in C = in + = gnd, (note 8) 120 db the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (notes 3, 4) co verter characteristics u a alog i put a d refere ce u u u u ltc2430/ltc2431 4 24301f symbol parameter conditions min typ max units v cc supply voltage l 2.7 5.5 v i cc supply current conversion mode cs = 0v (note 12) l 200 300 m a sleep mode cs = v cc (note 12) l 410 m a sleep mode cs = v cc , 2.7v v cc 3.3v 2 m a (note 12) the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) symbol parameter conditions min typ max units v ih high level input voltage 2.7v v cc 5.5v l 2.5 v cs, f o 2.7v v cc 3.3v 2.0 v v il low level input voltage 4.5v v cc 5.5v l 0.8 v cs, f o 2.7v v cc 5.5v 0.6 v v ih high level input voltage 2.7v v cc 5.5v (note 9) l 2.5 v sck 2.7v v cc 3.3v (note 9) 2.0 v v il low level input voltage 4.5v v cc 5.5v (note 9) l 0.8 v sck 2.7v v cc 5.5v (note 9) 0.6 v i in digital input current 0v v in v cc l C10 10 m a cs, f o i in digital input current 0v v in v cc (note 9) l C10 10 m a sck c in digital input capacitance 10 pf cs, f o c in digital input capacitance (note 9) 10 pf sck v oh high level output voltage i o = C 800 m a l v cc C 0.5v v sdo v ol low level output voltage i o = 1.6ma l 0.4 v sdo v oh high level output voltage i o = C 800 m a (note 10) l v cc C 0.5v v sck v ol low level output voltage i o = 1.6ma (note 10) l 0.4 v sck i oz hi-z output leakage l C10 10 m a sdo digital i puts a d digital outputs u u power require e ts w u ltc2430/ltc2431 5 24301f note 1: absolute maximum ratings are those values beyond which the life of the device may be impaired. note 2: all voltage values are with respect to gnd. note 3: v cc = 2.7v to 5.5v unless otherwise specified. v ref = ref + C ref C , v refcm = (ref + + ref C )/2; v in = in + C in C , v incm = (in + + in C )/2. note 4: f o pin tied to gnd or to v cc or to external conversion clock source with f eosc = 153600hz unless otherwise specified. note 5: guaranteed by design, not subject to test. note 6: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is calculated as the measured code minus the expected value. note 7: f o = 0v (internal oscillator) or f eosc = 153600hz 2% (external oscillator). note 8: f o = v cc (internal oscillator) or f eosc = 128000hz 2% (external oscillator). note 9: the converter is in external sck mode of operation such that the sck pin is used as digital input. the frequency of the clock signal driving sck during the data output is f esck and is expressed in khz. note 10: the converter is in internal sck mode of operation such that the sck pin is used as digital output. in this mode of operation the sck pin has a total equivalent load capacitance c load = 20pf. note 11: the external oscillator is connected to the f o pin. the external oscillator frequency, f eosc , is expressed in khz. note 12: the converter uses the internal oscillator. f o = 0v or f o = v cc . note 13: the output noise includes the contribution of the internal calibration operations. note 14: guaranteed by design and test correlation. symbol parameter conditions min typ max units f eosc external oscillator frequency range l 5 2000 khz t heo external oscillator high period l 0.25 200 m s t leo external oscillator low period l 0.25 200 m s t conv conversion time f o = 0v l 130.86 133.53 136.20 ms f o = v cc l 157.03 160.23 163.44 ms external oscillator (note 11) l 20510/f eosc (in khz) ms f isck internal sck frequency internal oscillator (note 10) 19.2 khz external oscillator (notes 10, 11) f eosc /8 khz d isck internal sck duty cycle (note 10) l 45 55 % f esck external sck frequency range (note 9) l 2000 khz t lesck external sck low period (note 9) l 250 ns t hesck external sck high period (note 9) l 250 ns t dout_isck internal sck 24-bit data output time internal oscillator (notes 10, 12) l 1.22 1.25 1.28 ms external oscillator (notes 10, 11) l 192/f eosc (in khz) ms t dout_esck external sck 24-bit data output time (note 9) l 24/f esck (in khz) ms t 1 cs to sdo low z l 0 200 ns t 2 cs - to sdo high z l 0 200 ns t 3 cs to sck (note 10) l 0 200 ns t 4 cs to sck - (note 9) l 50 ns t kqmax sck to sdo valid l 220 ns t kqmin sdo hold after sck (note 5) l 15 ns t 5 sck set-up before cs l 50 ns t 6 sck hold after cs l 50 ns the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) ti i g characteristics u w ltc2430/ltc2431 6 24301f typical perfor a ce characteristics uw total unadjusted error (v cc = 5v, v ref = 5v) input voltage (v) ?.5 tue (ppm of v ref ) 1 3 5 1.5 24301 g01 ? ? 0 2 4 ? ? ? ?.5 ? 0.5 ? 0.5 1 2 0 2.5 v cc = 5v v ref = 5v v incm = v incm = 2.5v f o = gnd 85 c 25 c ?5 c input voltage (v) ?.25 tue (ppm of v ref ) 1 3 5 0.75 24301 g02 ? ? 0 2 4 ? ? ? 0.75 ? 0.25 0.5 0.25 0.5 1 0 1.25 v cc = 5v v ref = 2.5v v incm = v incm = 1.25v f o = gnd 85 c ?5 c 25 c input voltage (v) ?.25 tue (ppm of v ref ) 20 15 10 5 0 ? ?0 ?5 ?0 0.75 24301 g03 0.25 1.25 0.5 ? 0 1 v cc = 2.7v v ref = 2.5v v incm = v incm = 1.25v f o = gnd 85 c ?5 c 25 c 0.75 0.25 0.5 total unadjusted error (v cc = 5v, v ref = 2.5v) total unadjusted error (v cc = 2.7v, v ref = 2.5v) integral nonlinearity (v cc = 5v, v ref = 5v) input voltage (v) ?.5 inl (ppm of v ref ) 1 3 5 1.5 24301 g04 ? ? 0 2 4 ? ? ? ?.5 ? ?.5 ? 0.5 1 2 0 2.5 v cc = 5v v ref = 5v v incm = v incm = 2.5v f o = gnd 85 c 25 c ?5 c integral nonlinearity (v cc = 5v, v ref = 2.5v) input voltage (v) ?.25 inl (ppm of v ref ) 1 3 5 0.75 24301 g05 ? ? 0 2 4 ? ? ? ? 0.25 0.5 1 0 1.25 v cc = 5v v ref = 2.5v v incm = v incm = 1.25v f o = gnd 85 c ?5 c 25 c 0.75 0.25 0.5 integral nonlinearity (v cc = 2.7v, v ref = 2.5v) input voltage (v) ?.25 inl (ppm of v ref ) 20 15 10 5 0 ? ?0 ?5 ?0 0.75 24301 g06 0.25 1.25 0.5 ? 0 1 v cc = 2.7v v ref = 2.5v v incm = v incm = 1.25v f o = gnd 85 c ?5 c 25 c 0.75 0.25 0.5 noise histogram (output rate = 7.5hz, v cc = 5v, v ref = 5v) output code (ppm of v ref ) ?.5 number of readings (%) 40 35 30 25 20 15 10 5 0 1.5 24301 g07 ?.5 0.5 0.5 2.5 1 ? ? 0 2 10,000 consecutive readings v cc = 5v v ref = 5v v in = 0v v incm = 2.5v f o = gnd t a = 25 c gaussian distribution m = 0.25ppm s = 0.550ppm noise histogram (output rate = 7.5hz, v cc = 2.7v, v ref = 2.5v) output code (ppm of v ref ) ? number of readings (%) 12 16 20 4 24301 g08 8 4 10 14 18 6 2 0 ? ? 0 ? 23 5 1 6 10,000 consecutive readings v cc = 2.7v v ref = 2.5v v in = 0v v incm = 2.5v f o = gnd t a = 25 c gaussian distribution m = ?.07ppm s = 1.06ppm rms noise vs input differential voltage input differential voltage (v) ?.5 rms noise (ppm of v ref ) 0.6 0.8 1.0 1.5 24301 g10 0.4 0.2 0.5 0.7 0.9 0.3 0.1 0 ?.5 ? 0.5 ? 0.5 1 2 0 2.5 v cc = 5v v ref = 5v v incm = 2.5v f o = gnd t a = 25 c ltc2430/ltc2431 7 24301f typical perfor a ce characteristics uw rms noise vs v incm rms noise vs temperature (t a ) v incm (v) ? 0 2.4 rms noise ( v) 2.8 3.4 1 3 4 24301 g11 2.6 3.2 3.0 2 5 6 v cc = 5v ref + = 5v ref = gnd v in = 0v v incm = gnd f o = gnd t a = 25 c temperature ( c) ?0 2.4 rms noise ( v) 2.6 2.8 3.0 3.2 3.4 ?5 02550 24301 g12 75 100 v cc = 5v v ref = 5v v in = 0v v incm = gnd f o = gnd rms noise vs v cc v cc (v) 2.7 3.1 2.4 rms noise ( v) 2.8 3.4 3.5 4.3 4.7 24301 g13 2.6 3.2 3.0 3.9 5.1 5.5 ref + = 2.5v ref = gnd v in = 0v v incm = gnd f o = gnd t a = 25 c rms noise vs v ref v ref (v) 0 rms noise ( v) 3.0 3.2 3.4 4 24301 g14 2.8 2.6 2.4 1 2 3 5 v cc = 5v ref = gnd v in = 0v v incm = gnd f o = gnd t a = 25 c offset error vs v incm v incm (v) ? ?.0 offset error (ppm of v ref ) 0.8 0.4 0.2 0 1.0 0.4 1 3 4 24301 g15 0.6 0.6 0.8 0.2 0 2 5 6 v cc = 5v ref + = 5v ref = gnd v in = 0v f o = gnd t a = 25 c offset error vs temperature offset error vs v ref temperature ( c) ?5 ?.0 offset error (ppm of v ref ) 0.8 0.4 0.2 0 1.0 0.4 ?5 15 30 90 24301 g16 0.6 0.6 0.8 0.2 ?0 0 45 60 75 v cc = 5v v ref =5v v in = 0v v incm = gnd f o = gnd offset error vs v cc v cc (v) 2.7 ?.0 offset error (ppm of v ref ) 0.8 0.4 0.2 0 1.0 0.4 3.5 4.3 4.7 24301 g17 0.6 0.6 0.8 0.2 3.1 3.9 5.1 5.5 ref + = v cc ref = gnd v in = 0v v incm = gnd f o = gnd t a = 25 c v ref (v) 0 offset error (ppm of v ref ) 1 3 5 4 24301 g18 ? ? 0 2 4 ? ? ? 1 2 3 5 v cc = 5v ref = gnd v in = 0v v incm = gnd f o = gnd t a = 25 c full-scale error vs temperature temperature ( c) ?5 ?0 full-scale error (ppm of v ref ) ?0 0 10 20 ?0 ?5 0 15 24301 g19 30 45 60 75 90 +fs error fs error v cc = 5v v ref = 5v f o = gnd v incm = 2.5v ltc2430/ltc2431 8 24301f typical perfor a ce characteristics uw psrr vs frequency at v cc conversion current vs temperature full-scale error vs v ref v ref (v) 0 full-scale error (ppm of v ref ) 20 15 10 5 0 ? ?0 ?5 ?0 4 24301 g20 123 5 3.5 0.5 1.5 2.5 4.5 +fs error fs error v cc = 5v ref = gnd f o = gnd v incm = 0.5v ref t a = 25 c full-scale error vs v cc v cc (v) 2.7 ? full-scale error (ppm of v ref ) ? ? ? 0 5 2 3.5 4.3 4.7 24301 g21 ? 3 4 1 3.1 3.9 5.1 5.5 +fs error fs error v ref = 2.5v ref = gnd f o = gnd v incm = 0.5v ref t a = 25 c frequency at v cc (hz) 0 ?40 rejection (db) ?20 ?0 ?0 ?0 0 20 100 140 24301 g22 ?00 ?0 80 180 220 200 40 60 120 160 v cc = 4.1v dc 1.4v ref + = 2.5v ref = gnd in + = gnd in = gnd f o = gnd t a = 25 c psrr vs frequency at v cc psrr vs frequency at v cc frequency at v cc (hz) 15170 ?0 ?0 0 15320 24301 g24 ?0 ?00 15220 15270 15370 ?20 ?40 ?0 rejection (db) v cc = 4.1v dc 0.7v ref + = 2.5v ref = gnd in + = gnd in = gnd f o = gnd t a = 25 c temperature ( c) ?5 conversion current ( a) 200 210 220 75 24301 g25 190 180 160 ?5 15 45 ?0 90 03060 170 240 230 v cc = 5.5v v cc = 2.7v v cc = 5v v cc = 3v f o = gnd cs = gnd sck = nc sdo = nc conversion current vs output data rate output data rate (readings/sec) 0 100 supply current ( a) 200 400 500 600 60 70 80 90 1000 24301 g26 300 10 20 30 40 50 100 700 800 900 v cc = 5v v cc = 3v v ref = v cc in + = gnd in = gnd sck = nc sdo = nc sdi = gnd cs = gnd f o = ext osc t a = 25 c sleep mode current vs temperature temperature ( c) ?5 0 sleep mode current ( a) 1 3 4 5 ?5 15 30 90 24301 g27 2 ?0 0 45 60 75 6 v cc = 5.5v v cc = 2.7v v cc = 5v v cc = 3v f o = gnd cs = v cc sck = nc sdo = nc frequency at v cc (hz) 1 0 ?0 ?0 ?0 ?0 ?00 ?20 ?40 1k 100k 24301 g23 10 100 10k 1m rejection (db) v cc = 4.1v dc ref + = 2.5v ref = gnd in + = gnd in = gnd f o = gnd t a = 25 c ltc2430/ltc2431 9 24301f v cc (pin 1): positive supply voltage. bypass to gnd (pin 6) with a 10 m f tantalum capacitor in parallel with 0.1 m f ceramic capacitor as close to the part as possible. ref + (pin 2), ref C (pin 3): differential reference input. the voltage on these pins can have any value between gnd and v cc as long as the reference positive input, ref + , is maintained more positive than the reference negative input, ref C , by at least 0.1v. in + (pin 4), in C (pin 5): differential analog input. the voltage on these pins can have any value between gnd C 0.3v and v cc + 0.3v. within these limits, the converter bipolar input range (v in = in + C in C ) extends from C 0.5 ? (v ref ) to 0.5 ? (v ref ). outside this input range, the converter produces unique overrange and underrange output codes. gnd (pin 6): ground. connect this pin to a ground plane through a low impedance connection. cs (pin 7): active low digital input. a low on this pin enables the sdo digital output and wakes up the adc. following each conversion, the adc automatically enters the sleep mode and remains in this low power state as long as cs is high. a low-to-high transition on cs during the data output transfer aborts the data transfer and starts a new conversion. uu u pi fu ctio s gnd (pins 1, 7, 8, 9, 10, 15, 16): ground. multiple ground pins internally connected for optimum ground current flow and v cc decoupling. connect each one of these pins to a ground plane through a low impedance connection. all seven pins must be connected to ground for proper operation. v cc (pin 2): positive supply voltage. bypass to gnd with a 10 m f tantalum capacitor in parallel with 0.1 m f ceramic capacitor as close to the part as possible. ref + (pin 3), ref C (pin 4): differential reference input. the voltage on these pins can have any value between gnd and v cc as long as the reference positive input, ref + , is maintained more positive than the reference negative input, ref C , by at least 0.1v. in + (pin 5), in C (pin 6): differential analog input. the voltage on these pins can have any value between gnd C 0.3v and v cc + 0.3v. within these limits the converter bipolar input range (v in = in + C in C ) extends from C 0.5 ? (v ref ) to 0.5 ? (v ref ). outside this input range the converter produces unique overrange and underrange output codes. cs (pin 11): active low digital input. a low on this pin enables the sdo digital output and wakes up the adc. following each conversion the adc automatically enters the sleep mode and remains in this low power state as long as cs is high. a low-to-high transition on cs during the data output transfer aborts the data transfer and starts a new conversion. sdo (pin 12): three-state digital output. during the data output period, this pin is used as serial data output. when the chip select cs is high (cs = v cc ) the sdo pin is in a high impedance state. during the conversion and sleep periods, this pin is used as the conversion status output. the conversion status can be observed by pulling cs low. sck (pin 13): bidirectional digital clock pin. in internal serial clock operation mode, sck is used as digital output for the internal serial interface clock during the data output period. in external serial clock operation mode, sck is used as digital input for the external serial interface clock during the data output period. a weak internal pull- up is automatically activated in internal serial clock op- eration mode. the serial clock operation mode is deter- mined by the logic level applied to the sck pin at power up or during the most recent falling edge of cs. f o (pin 14): frequency control pin. digital input that controls the adcs notch frequencies and conversion time. when the f o pin is connected to v cc (f o = v cc ), the converter uses its internal oscillator and the digital filter first null is located at 50hz. when the f o pin is connected to gnd (f o = ov), the converter uses its internal oscillator and the digital filter first null is located at 60hz. when f o is driven by an external clock signal with a frequency f eosc , the converter uses this signal as its system clock and the digital filter first null is located at a frequency f eosc /2560. (ltc2430) (ltc2431) ltc2430/ltc2431 10 24301f figure 1 uu w fu ctio al block diagra autocalibration and control dac decimating fir internal oscillator serial interface adc gnd v cc in + in sdo sck ref + ref cs f o (int/ext) 2431 fd + test circuits 1.69k sdo 2431 ta03 hi-z to v oh v ol to v oh v oh to hi-z c load = 20pf 1.69k sdo 2431 ta04 hi-z to v ol v oh to v ol v ol to hi-z c load = 20pf v cc sdo (pin 8): three-state digital output. during the data output period, this pin is used as the serial data output. when the chip select cs is high (cs = v cc ), the sdo pin is in a high impedance state. during the conversion and sleep periods, this pin is used as the conversion status output. the conversion status can be observed by pulling cs low. sck (pin 9): bidirectional digital clock pin. in internal serial clock operation mode, sck is used as the digital output for the internal serial interface clock during the data output period. in external serial clock operation mode, sck is used as the digital input for the external serial interface clock during the data output period. a weak internal pull-up is automatically activated in internal serial clock operation mode. the serial clock operation mode is determined by the logic level applied to the sck pin at power up or during the most recent falling edge of cs. f o (pin 10): frequency control pin. digital input that controls the adcs notch frequencies and conversion time. when the f o pin is connected to v cc (f o = v cc ), the converter uses its internal oscillator and the digital filter first null is located at 50hz. when the f o pin is connected to gnd (f o = ov), the converter uses its internal oscillator and the digital filter first null is located at 60hz. when f o is driven by an external clock signal with a frequency f eosc , the converter uses this signal as its system clock and the digital filter first null is located at a frequency f eosc /2560. uu u pi fu ctio s (ltc2431) ltc2430/ltc2431 11 24301f converter operation converter operation cycle the ltc2430/ltc2431 are low power, delta-sigma analog- to-digital converters with an easy-to-use 3-wire serial inter- face (see figure 1). their operation is made up of three states. the converters operating cycle begins with the conversion, followed by the low power sleep state and ends with the data output (see figure 2). the 3-wire interface consists of serial data output (sdo), serial clock (sck) and chip select (cs). initially, the ltc2430/ltc2431 perform a conversion. once the conversion is complete, the device enters the sleep state. the part remains in the sleep state as long as cs is high. while in this sleep state, power consumption is reduced by nearly two orders of magnitude. the conver- sion result is held indefinitely in a static shift register while the converter is in the sleep state. once cs is pulled low, the device exits the low power mode and enters the data output state. if cs is pulled high be- fore the first rising edge of sck, the device returns to the low power sleep mode and the conversion result is still held in the internal static shift register. if cs remains low after the first rising edge of sck, the device begins outputting the conversion result. taking cs high at this point will terminate the data output state and start a new conversion. there is no latency in the conversion result. the data out- put corresponds to the conversion just performed. this result is shifted out on the serial data out pin (sdo) under the control of the serial clock (sck). data is updated on the falling edge of sck allowing the user to reliably latch data on the rising edge of sck (see figure 3). the data output state is concluded once 24 bits are read out of the adc or when cs is brought high. the device automatically initiates a new conversion and the cycle repeats. through timing control of the cs and sck pins, the ltc2430/ltc2431 offer several flexible modes of operation (internal or external sck and free-running conversion modes). these various modes do not require programming configuration registers; moreover, they do not disturb the cyclic operation described above. these modes of operation are described in detail in the serial interface timing modes section. conversion clock a major advantage the delta-sigma converter offers over conventional type converters is an on-chip digital filter (commonly implemented as a sinc or comb filter). for high resolution, low frequency applications, this filter is typically designed to reject line frequencies of 50hz or 60hz plus their harmonics. the filter rejection perfor- mance is directly related to the accuracy of the converter system clock. the ltc2430/ltc2431 incorporate a highly accurate on-chip oscillator. this eliminates the need for external frequency setting components such as crystals or oscillators. clocked by the on-chip oscillator, the ltc2430/ ltc2431 achieve a minimum of 110db rejection at the line frequency (50hz or 60hz 2%). ease of use the ltc2430/ltc2431 data output has no latency, filter settling delay or redundant data associated with the conversion cycle. there is a one-to-one correspondence between the conversion and the output data. therefore, multiplexing multiple analog inputs is easy. the ltc2430/ltc2431 perform offset and full-scale cali- brations in every conversion cycle. this calibration is trans- parent to the user and has no effect on the cyclic operation described above. the advantage of continuous calibration is extreme stability of offset and full-scale readings with respect to time, supply voltage change and temperature drift. figure 2. ltc2430/ltc2431 state transition diagram convert sleep data output 2431 f02 true false cs = low and sck applicatio s i for atio wu uu ltc2430/ltc2431 12 24301f power-up sequence the ltc2430/ltc2431 automatically enter an internal reset state when the power supply voltage v cc drops below approximately 2v. this feature guarantees the integrity of the conversion result and of the serial interface mode selection. (see the 2-wire i/o sections in the serial interface timing modes section.) when the v cc voltage rises above this critical threshold, the ltc2430 or ltc2431 creates an internal power-on- reset (por) signal with a duration of approximately 1ms. the por signal clears all internal registers. following the por signal, the converter starts a normal conversion cycle and follows the succession of states described above. the first conversion result following por is accu- rate within the specifications of the device if the power supply voltage is restored within the operating range (2.7v to 5.5v) before the end of the por time interval. reference voltage range the ltc2430/ltc2431 accept a differential external refer- ence voltage. the absolute/common mode voltage speci- fication for the ref + and ref C pins covers the entire range from gnd to v cc . for correct converter operation, the ref + pin must always be more positive than the ref C pin. the ltc2430/ltc2431 can accept a differential reference voltage from 0.1v to v cc . the converter (ltc2430 or ltc2431) output noise is determined by the thermal noise of the front-end circuits, and, as such, its value in micro- volts is nearly constant with reference voltage. a decrease in reference voltage will not significantly improve the converters effective resolution. on the other hand, a re- duced reference voltage will improve the converters over- all inl performance. a reduced reference voltage will also improve the converter performance when operated with an external conversion clock (external f o signal) at sub- stantially higher output data rates. input voltage range the analog input is truly differential with an absolute/com- mon mode range for the in + and in C input pins extending from gnd C 0.3v to v cc + 0.3v. outside these limits, the esd protection devices begin to turn on and the errors due to input leakage current increase rapidly. within these lim- its, the ltc2430 or ltc2431 converts the bipolar differen- tial input signal, v in = in + C in C , from C fs = C 0.5 ? v ref to +fs = 0.5 ? v ref where v ref = ref + C ref C . outside this range the converter indicates the overrange or the underrange condition using distinct output codes. input signals applied to in + and in C pins may extend by 300mv below ground and above v cc . in order to limit any fault current, resistors of up to 5k may be added in series with the in + and in C pins without affecting the performance of the device. in the physical layout, it is important to main- tain the parasitic capacitance of the connection between these series resistors and the corresponding pins as low as possible; therefore, the resistors should be located as close as practical to the pins. in addition, series resistors will introduce a temperature dependent offset error due to the input leakage current. a 1na input leakage current will develop a 1ppm offset error on a 5k resistor if v ref = 5v. this error has a very strong temperature dependency. output data format the ltc2430/ltc2431 serial output data stream is 24 bits long. the first 3 bits represent status information indicat- ing the sign and conversion state. the next 21 bits are the conversion result, msb first. the third and fourth bits to- gether are also used to indicate an underrange condition (the differential input voltage is below C fs) or an overrange condition (the differential input voltage is above + fs). bit 23 (first output bit) is the end of conversion (eoc) indicator. this bit is available at the sdo pin during the conversion and sleep states whenever the cs pin is low. this bit is high during the conversion and goes low when the conversion is complete. bit 22 (second output bit) is a dummy bit (dmy) and is always low. bit 21 (third output bit) is the conversion result sign indi- cator (sig). if v in is >0, this bit is high. if v in is <0, this bit is low. bit 20 (fourth output bit) is the most significant bit (msb) of the result. this bit in conjunction with bit 21 also provides the underrange or overrange indication. if both bit 21 and bit 20 are high, the differential input voltage is applicatio s i for atio wu uu ltc2430/ltc2431 13 24301f above +fs. if both bit 21 and bit 20 are low, the differential input voltage is below Cfs. the function of these bits is summarized in table 1. table 1. ltc2430/ltc2431 status bits bit 23 bit 22 bit 21 bit 20 input range eoc dmy sig msb v in 3 0.5 ? v ref 0011 0v v in < 0.5 ? v ref 0010 C0.5 ? v ref v in < 0v 0 0 0 1 v in < C 0.5 ? v ref 0000 bits 20-0 are the 21-bit conversion result msb first. bit 0 is the least significant bit (lsb). data is shifted out of the sdo pin under control of the serial clock (sck), see figure 3. whenever cs is high, sdo remains high impedance and any externally generated sck clock pulses are ignored by the internal data out shift register. in order to shift the conversion result out of the device, cs must first be driven low. eoc is seen at the sdo pin of the device once cs is pulled low. eoc changes real time from high to low at the completion of a conversion. this signal may be used as an interrupt for an external micro- controller. bit 23 (eoc) can be captured on the first rising edge of sck. bit 22 is shifted out of the device on the first falling edge of sck. the final data bit (bit 0) is shifted out on the falling edge of the 23rd sck and may be latched on the rising edge of the 24th sck pulse. on the falling edge of the 24th sck pulse, sdo goes high indicating the initiation of a new conversion cycle. this bit serves as eoc (bit 22) for the next conversion cycle. table 2 summarizes the output data format. as long as the voltage on the in + and in C pins is maintained within the C 0.3v to (v cc + 0.3v) absolute maximum operating range, a conversion result is generated for any differential input voltage v in from Cfs = C 0.5 ? v ref to +fs = 0.5 ? v ref . for differential input voltages greater than table 2. ltc2430/ltc2431 output data format differential input voltage bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 0 v in * eoc dmy sig msb lsb v in * 3 0.5 ? v ref ** 0 0110 0 00 0.5 ? v ref ** C 1lsb 0 0101 1 11 0.25 ? v ref ** 0 0101 0 00 0.25 ? v ref ** C 1lsb 0 0100 1 11 0 0 0100 0 00 C1lsb 0 0011 1 11 C 0.25 ? v ref ** 0 0011 0 00 C 0.25 ? v ref ** C 1lsb 0 0010 1 11 C 0.5 ? v ref ** 0 0010 0 00 v in * < C0.5 ? v ref ** 0 0001 1 11 *the differential input voltage v in = in + C in C . **the differential reference voltage v ref = ref + C ref C . figure 3. output data timing msb sig ? 1234524 bit 0 lsb bit 19 bit 20 bit 21 bit 22 sdo sck cs eoc bit 23 sleep data output conversion 2431 f03 hi-z applicatio s i for atio wu uu ltc2430/ltc2431 14 24301f +fs, the conversion result is clamped to the value corre- sponding to the +fs + 1lsb. for differential input voltages below Cfs, the conversion result is clamped to the value corresponding to Cfs C 1lsb. frequency rejection selection (f o ) the ltc2430/ltc2431 internal oscillator provides better than 110db normal mode rejection at the line frequency and all its harmonics for 50hz 2% or 60hz 2%. for 60hz rejection, f o should be connected to gnd while for 50hz rejection the f o pin should be connected to v cc . the selection of 50hz or 60hz rejection can also be made by driving f o to an appropriate logic level. a selection change during the sleep or data output states will not disturb the converter operation. if the selection is made during the conversion state, the result of the conversion in progress may be outside specifications but the following conversions will not be affected. when a fundamental rejection frequency different from 50hz or 60hz is required or when the converter must be synchronized with an outside source, the ltc2430 or ltc2431 can operate with an external conversion clock. the converter automatically detects the presence of an external clock signal at the f o pin and turns off the internal oscillator. the frequency f eosc of the external signal must be at least 5khz to be detected. the external clock signal duty cycle is not significant as long as the minimum and maximum specifications for the high and low periods t heo and t leo are observed. while operating with an external conversion clock of a frequency f eosc , the ltc2430 or ltc2431 provides better than 110db normal mode rejection in a frequency range f eosc /2560 4% and its harmonics. the normal mode rejection as a function of the input frequency deviation from f eosc /2560 is shown in figure 4. whenever an external clock is not present at the f o pin, the converter (ltc2430 or ltc2431) automatically activates its internal oscillator and enters the internal conversion clock mode. its operation will not be disturbed if the change of conversion clock source occurs during the sleep state or during the data output state while the con- verter uses an external serial clock. if the change occurs during the conversion state, the result of the conversion in progress may be outside specifications but the following conversions will not be affected. if the change occurs during the data output state and the converter is in the internal sck mode, the serial clock duty cycle may be affected but the serial data stream will remain valid. table 3 summarizes the duration of each state and the achievable output data rate as a function of f o . serial interface pins the ltc2430/ltc2431 transmit the conversion results and receives the start of conversion command through a synchronous 3-wire interface. during the conversion and sleep states, this interface can be used to assess the converter status and during the data output state it is used to read the conversion result. serial clock input/output (sck) the serial clock signal present on sck is used to synchro- nize the data transfer. each bit of data is shifted out the sdo pin on the falling edge of the serial clock. in the internal sck mode of operation, the sck pin is an output and the converter (ltc2430 or ltc2431) creates its own serial clock by dividing the internal conversion clock by 8. in the external sck mode of operation, the sck pin is used as input. the internal or external sck mode is selected on power-up and then reselected every time a high-to-low transition is detected at the cs pin. if sck figure 4. ltc2430/ltc2431 normal mode rejection when using an external oscillator of frequency f eosc applicatio s i for atio wu uu differential input signal frequency deviation from notch frequency f eosc /2560(%) 12 8 404812 normal mode rejection (db) 2431 f04 ?0 ?5 ?0 ?5 100 105 110 115 120 125 130 135 140 ltc2430/ltc2431 15 24301f table 3. ltc2430/ltc2431 state duration state operating mode duration convert internal oscillator f o = low 133ms, output data rate 7.5 readings/s (60hz rejection) f o = high 160ms, output data rate 6.2 readings/s (50hz rejection) external oscillator f o = external oscillator 20510/f eosc s, output data rate f eosc /20510 readings/s with frequency f eosc khz (f eosc /2560 rejection) sleep as long as cs = high data output internal serial clock f o = low/high as long as cs = low but not longer than 1.25ms (internal oscillator) (24 sck cycles) f o = external oscillator with as long as cs = low but not longer than 192/f eosc ms frequency f eosc khz (24 sck cycles) external serial clock with as long as cs = low but not longer than 24/f sck ms frequency f sck khz (24 sck cycles) is high or floating at power-up or during this transition, the converter enters the internal sck mode. if sck is low at power-up or during this transition, the converter enters the external sck mode. serial data output (sdo) the serial data output pin, sdo, provides the result of the last conversion as a serial bit stream (msb first) during the data output state. in addition, the sdo pin is used as an end of conversion indicator during the conversion and sleep states. when cs is high, the sdo driver is switched to a high impedance state. this allows sharing the serial interface with other devices. if cs is low during the convert or sleep state, sdo will output eoc. if cs is low during the conversion phase, the eoc bit appears high on the sdo pin. once the conversion is complete, eoc goes low. chip select input (cs) the active low chip select, cs, is used to test the conversion status and to enable the data output transfer as described in the previous sections. in addition, the cs signal can be used to trigger a new conversion cycle before the entire serial data transfer has been completed. the converter (ltc2430 or ltc2431) will abort any serial data transfer in progress and start a new conversion cycle anytime a low-to-high transition is detected at the cs pin after the converter has entered the data output state (i.e., after the first rising edge of sck occurs with cs = low). finally, cs can be used to control the free-running modes of operation, see serial interface timing modes section. grounding cs will force the adc to continuously convert at the maximum output rate selected by f o . serial interface timing modes the ltc2430/ltc2431s 3-wire interface is spi and microwire compatible. this interface offers several flexible modes of operation. these include internal/exter- nal serial clock, 2- or 3-wire i/o, single cycle conversion. the following sections describe each of these serial inter- face timing modes in detail. in all these cases, the converter can use the internal oscillator (f o = low or f o = high) or an external oscillator connected to the f o pin. refer to table 4 for a summary. external serial clock, single cycle operation (spi/microwire compatible) this timing mode uses an external serial clock to shift out the conversion result and a cs signal to monitor and control the state of the conversion cycle, see figure 5. applicatio s i for atio wu uu ltc2430/ltc2431 16 24301f eoc bit 23 sdo sck (external) cs test eoc lsb msb sig bit 0 bit 19 bit 18 bit 20 bit 21 bit 22 sleep sleep test eoc data output conversion 2431 f05 conversion hi-z hi-z hi-z test eoc v cc f o ref + ref sck in + in sdo gnd cs reference voltage 0.1v to v cc analog input range 0.5v ref to 0.5v ref 1 f 2.7v to 5.5v ltc2430/ ltc2431 3-wire spi interface = 50hz rejection = external oscillator = 60hz rejection v cc test eoc table 4. ltc2430/ltc2431 interface timing modes conversion data connection sck cycle output and configuration source control control waveforms external sck, single cycle conversion external cs and sck cs and sck figures 5, 6 external sck, 2-wire i/o external sck sck figure 7 internal sck, single cycle conversion internal cs cs figures 8, 9 internal sck, 2-wire i/o, continuous conversion internal continuous internal figure 10 the serial clock mode is selected on the falling edge of cs. to select the external serial clock mode, the serial clock pin (sck) must be low during each cs falling edge. the serial data output pin (sdo) is hi-z as long as cs is high. at any time during the conversion cycle, cs may be pulled low in order to monitor the state of the converter. while cs is pulled low, eoc is output to the sdo pin. eoc = 1 while a conversion is in progress and eoc = 0 if the conversion is over. with cs high, the device auto- matically enters the low power sleep state once the con- version is complete. when cs is low, the device enters the data output mode. the result is held in the internal static shift register until the first sck rising edge is seen while cs is low. data is shifted out the sdo pin on each falling edge of sck. this enables external circuitry to latch the output on the rising edge of sck. eoc can be latched on the first rising edge of sck and the last bit of the conversion result can be latched on the 24th rising edge of sck. on the 24th falling edge of sck, the device begins a new conversion. sdo goes high (eoc = 1) indicating a conversion is in progress. at the conclusion of the data cycle, cs may remain low and eoc monitored as an end-of-conversion interrupt. alternatively, cs may be driven high setting sdo to hi-z. as described above, cs may be pulled low at any time in order to monitor the conversion status. typically, cs remains low during the data output state. however, the data output state may be aborted by pulling cs high anytime between the first rising edge and the 24th falling edge of sck, see figure 6. on the rising edge of cs, applicatio s i for atio wu uu figure 5. external serial clock, single cycle operation ltc2430/ltc2431 17 24301f eoc = 0 once the conversion ends. on the falling edge of eoc, the conversion result is loaded into an internal static shift register. data is shifted out the sdo pin on each falling edge of sck enabling external circuitry to latch data on the rising edge of sck. eoc can be latched on the first rising edge of sck. on the 24th falling edge of sck, sdo goes high (eoc = 1) indicating a new conversion has begun. internal serial clock, single cycle operation this timing mode uses an internal serial clock to shift out the conversion result and a cs signal to monitor and control the state of the conversion cycle, see figure 8. in order to select the internal serial clock timing mode, the serial clock pin (sck) must be floating (hi-z) or pulled high prior to the falling edge of cs. the device will not enter the internal serial clock mode if sck is driven low on the falling edge of cs. an internal weak pull-up resistor is active on the sck pin during the falling edge of cs; therefore, the internal serial clock timing mode is auto- matically selected if sck is not externally driven. figure 6. external serial clock, reduced data output length applicatio s i for atio wu uu sdo sck (external) cs data output conversion sleep sleep sleep test eoc (optional) test eoc data output hi-z hi-z hi-z conversion 2431 f06 msb sig bit 8 bit 19 bit 9 bit 20 bit 21 bit 22 eoc bit 23 bit 0 eoc hi-z test eoc v cc f o ref + ref sck in + in sdo gnd cs reference voltage 0.1v to v cc analog input range 0.5v ref to 0.5v ref 3-wire spi interface 1 f 2.7v to 5.5v ltc2430/ ltc2431 = 50hz rejection = external oscillator = 60hz rejection v cc the device aborts the data output state and immediately initiates a new conversion. this is useful for systems not requiring all 24 bits of output data, aborting an invalid con- version cycle or synchronizing the start of a conversion. external serial clock, 2-wire i/o this timing mode utilizes a 2-wire serial i/o interface. the conversion result is shifted out of the device by an exter- nally generated serial clock (sck) signal, see figure 7. cs may be permanently tied to ground, simplifying the user interface or isolation barrier. the external serial clock mode is selected at the end of the power-on reset (por) cycle. the por cycle is concluded approximately 1ms after v cc exceeds 2v. the level applied to sck at this time determines if sck is internal or external. sck must be driven low prior to the end of por in order to enter the external serial clock timing mode. since cs is tied low, the end-of-conversion (eoc) can be continuously monitored at the sdo pin during the convert and sleep states. eoc may be used as an interrupt to an external controller indicating the conversion result is ready. eoc = 1 while the conversion is in progress and ltc2430/ltc2431 18 24301f figure 7. external serial clock, cs = 0 operation figure 8. internal serial clock, single cycle operation applicatio s i for atio wu uu eoc bit 23 sdo sck (external) cs msb sig bit 0 lsb bit 19 bit 18 bit 20 bit 21 bit 22 data output conversion 2431 f07 conversion v cc f o ref + ref sck in + in sdo gnd cs reference voltage 0.1v to v cc analog input range 0.5v ref to 0.5v ref 2-wire i/o 1 f 2.7v to 5.5v = 50hz rejection = external oscillator = 60hz rejection v cc ltc2430/ ltc2431 sdo sck (internal) cs msb sig bit 0 lsb test eoc bit 19 bit 18 bit 20 bit 21 bit 22 eoc bit 23 sleep sleep test eoc (optional) data output conversion conversion 2431 f08 |