View MACH215-15JC_3972802.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

publication# 16751 rev. e amendment /0 issue date: may 1995 mach215-12/15/20 high-density ee cmos programmable logic final com'l: -12/15/20 ind: -14/18/24 distinctive characteristics n 44 pins n 32 output macrocells n 32 input macrocells n product terms for: individual flip-flop clock individual asynchronous reset, preset individual output enable n 12 ns t pd commercial 14.5 ns t pd industrial n 67 mhz f cnt n 38 inputs with pull-up resistors n 32 outputs n 64 flip-flops n for asynchronous and synchronous applications n 4 pal22ra8 blocks with buried macrocells n pin-compatible with mach110, mach111, mach210, and mach211 general description t h e m a c h 2 1 5 i s a m e m b e r o f t h e h i g h - p e r f o r m a n c e ee cmos mach device family. this device has approximately three times the capability of the popular pal20ra10 without loss of speed. this device is designed for use in asynchronous as well as synchro- nous applications. the mach215 consists of four pal blocks intercon- nected by a programmable switch matrix. the four pal blocks are essentially pal22ra8 structures complete with product-term arrays and programmable macro- cells, individual register control product terms, and input registers. the switch matrix connects the pal blocks to each other and to all input pins, providing a high degree of connectivity between the fully-connected pal blocks. this allows designs to be placed and routed efficiently. the mach215 has two kinds of macrocell: output and input. the mach215 output macrocell provides regis- tered, latched, or combinatorial outputs with program- mable polarity. if a registered configuration is chosen, the register can be configured as d-type or t-type to help reduce the number of product terms. the register type decision can be made by the designer or by the software. each macrocell has its own dedicated clock, asynchronous reset, and asynchronous preset control. the polarity of the clock signal is programmable. all output macrocells can be connected to an i/o cell. the mach215 has dedicated input macrocells which provide input registers or latches for synchronizing input signals and reducing setup time requirements. lattice semiconductor
2 mach215-12/15/20 block diagram input macrocells output macrocells input macrocells output macrocells 44x64 and logic array and logic allocator switch matrix i/o cells output macrocells i/o 0 Ci/o 7 input macrocells 8 8 i 0 Ci 1, i 3 Ci 4 i/o 16 Ci/o 23 clk 0 /i 2 i/o 24 Ci/o 31 16751e-1 4 2 8 8 8 i/o cells i/o 8 Ci/o 15 8 8 8 88 i/o cells 8 8 888 i/o cells 8 888 22 22 output macrocells input macrocells 44x64 and logic array and logic allocator 44x64 and logic array and logic allocator 44x64 and logic array and logic allocator 22 22 clk 1 /i 5 oe oe oe clkclk clk clkoe 8
3 mach215-12/15/20 connection diagram top view plcc i/o 5 i/o 6 i/o 7 i 0 i 1 clk 0 /i 2 i/o 8 i/o 9 gnd i/o 10 i/o 11 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 gnd v cc i/o 31 i/o 30 i/o 29 i/o 28 i/o 27 i/o 26 i/o 25 i 3 i 4 i/o 24 clk 1 /i 5 gnd i/o 23 i/o 22 i/o 21 i/o 12 i/o 13 i/o 14 v cc gnd i/o 16 i/o 15 i/o 17 i/o 18 i/o 19 i/o 20 7 8 9 10 11 12 13 15 16 14 17 5 61 32 4 4443424140 29 30 31 32 33 34 35 36 37 38 39 18 282726252423222119 20 pin designations clk/i = clock or input gnd = ground i = input i/o = input/output v cc = supply voltage note: pin-compatible with mach110, mach111, mach210, and mach211. 16751e-2
4 mach215-12/15/20 (com'l) ordering information commercial products p r o g r a m m a b l e l o g i c p r o d u c t s f o r c o m m e r c i a l a p p l i c a t i o n s a r e a v a i l a b l e w i t h s e v e r a l o r d e r i n g o p t i o n s . t h e o r d e r n u m b e r (valid combination) is formed by a combination of: operating conditions c = commercial (0 c to +70 c) family type mach = macro array cmos high-speed speed -12 = 1 2 ns t pd -15 = 15 ns t pd -20 = 20 ns t pd mach215-12 mach215-15 mach215-20 mach -12 j c valid combinations the valid combinations table lists configurations planned to be supported in volume for this device. c o n s u l t your local sales office to confirm availabil- ity of specific valid combinations and to check on newly released combinations. valid combinations optional processing blank = standard processing 215 device number 215 = 3 2 asynchronous output macrocells, 44 pins package type j = 44-pin plastic leaded chip carrier (pl 044) jc
5 mach215-14/18/24 (ind) ordering information industrial products p r o g r a m m a b l e l o g i c p r o d u c t s f o r i n d u s t r i a l a p p l i c a t i o n s a r e a v a i l a b l e w i t h s e v e r a l o r d e r i n g o p t i o n s . t h e o r d e r n u m b e r ( v a l i d combination) is formed by a combination of: operating conditions i = industrial (C40 c to +85 c) family type mach = macro array cmos high-speed speed -14 = 14.5 ns t pd -18 = 1 8 ns t pd -24 = 24 ns t pd mach215-14 mach215-18 mach215-24 mach -14 j i valid combinations the valid combinations table lists configurations planned to be supported in volume for this device. c o n s u l t your local sales office to confirm availabil- ity of specific valid combinations and to check on newly released combinations. valid combinations optional processing blank = standard processing 215 device number 215 = 3 2 asynchronous output macrocells, 44 pins package type j = 44-pin plastic leaded chip carrier (pl 044) ji
6 mach215-12/15/20 functional description the mach215 consists of four asynchronous pal blocks connected by a switch matrix. there are 32 i/o pins and 4 dedicated input pins feeding the switch matrix. these signals are distributed to the four pal blocks for efficient design implementation. there are also two additional global clock pins that can be used as dedicated inputs. this device provides two kinds of macrocell: output macrocells and input macrocells. this adds greater logic density without affecting the number of pins. the pal blocks each pal block in the mach215 (figure 1) contains a 64-product-term array, a logic allocator, 8 output macrocells, 8 input macrocells, and 8 i/o cells. the switch matrix feeds each pal block with 22 inputs. this makes the pal block look effectively like an independ- ent pal22ra8 with 8 input macrocells. all flip-flops within the device can operate independently. the switch matrix the mach215 switch matrix is fed by the inputs and feedback signals from the pal blocks. each pal block provides 16 internal feedback signals and 8 i/o feedback signals. the switch matrix distributes these signals back to the pal blocks in an efficient manner that also provides for high performance. the design software automatically configures the switch matrix when fitting a design into the device. the product-term array the mach215 product-term array consists of 32 product terms for logic use and 32 product terms for generating macrocell control signals. the logic allocator the logic allocator in the mach215 (figure 2) takes the 32 logic product terms and allocates them to the 16 macrocells as needed. each macrocell can be driven by up to 12 product terms. the design software automati- cally configures the logic allocator when fitting the design into the device. table 1 illustrates which product term clusters are available to each macrocell within a pal block. refer to figure 1 for cluster and macrocell numbers. table 1. logic allocation available output macrocell clusters m 0 c 0 , c 1 m 1 c 0 , c 1 , c 2 m 2 c 1 , c 2 , c 3 m 3 c 2 , c 3 , c 4 m 4 c 3 , c 4 , c 5 m 5 c 4 , c 5 , c 6 m 6 c 5 , c 6 , c 7 m 7 c 6 , c 7 the macrocell there are two types of macrocell in the mach215: output macrocells and input macrocells. the output macrocell takes the logic of the device and provides it to i/o pins and/or provides feedback for additional logic generation. the input macrocell allows i/o pins to be configured as registered or latched inputs. the output macrocell (figure 3) can generate regis- tered or combinatorial outputs. in addition, a transpar- ent-low latched configuration is provided. if used, the register can be configured as a t-type or a d-type flip-flop. register and latch functionality is defined in table 2. programmable polarity and the t-type flip-flop both give the software a way to minimize the number of product terms needed. these choices can be made automatically by the software when it fits the design into the device. configuration d/t clk/le* q+ d-register x 0 , 1, ( - )q 0 - ( )0 1 - ( )1 t-register x 0 , 1, ( - )q 0 - ( )q 1 - ( ) q latch x 1 (0) q 0 0 (1) 0 1 0 (1) 1 table 2. register/latch operation *polarity of clk/le can be programmed.
7 mach215-12/15/20 the output macrocell sends its output back to the switch matrix, via internal feedback, and to the i/o cell. the feedback is always available regardless of the configu- ration of the i/o cell. this allows for buried combinatorial or registered functions, freeing up the i/o pins for use as inputs if not needed as outputs. the basic output macrocell configurations are shown in figure 4. the clock/latch-enable for each individual output mac- rocell can be driven by one of four signals. two of the signals are provided by the global clock pin clk 0 / le 0 ; either polarity may be chosen. the other two signals come from a product term provided for each output macrocell. either polarity of the logic generated by the product term can be chosen. the global clock pin is also available as an input, although care must be taken when a signal acts as both clock and input to the same device. each individual output macrocell also has a product term for asynchronous reset and a product term for asynchronous preset. this means that any register or latch may be reset or preset without affecting any other register or latch in the device. the functionality of the flip-flops with respect to initialization is illustrated in table 3. ar ap clk/le q+ 0 0 x see table 12 0 1 x 1 1 0 x 0 1 1 x 0 table 3. asynchronous reset/preset operation the input macrocell (figure 5) consists of a flip-flop that can be used to provide registered or latched inputs. the flip-flop can be clocked by either polarity of one of the two global clock/latch-enable pins. reset or preset are not provided for these flip-flops. if combinatorial inputs are desired, this macrocell is not used, and the feedback from the i/o pin is used directly. both the i/o pin feedback and the output of the input register or latch are always available to the switch matrix. possible input macrocell configurations are shown in figure 6. the i/o cell the i/o cell (figure 7) provides a three-state output buffer. the three-state control is provided by an individual product term for each i/o cell. depending on the logic programmed onto this product term, the i/o pin can be configured as an output, an input, or a bidirectional pin. the feedback from the i/o pin is always available to the switch matrix, regardless of the state of the output buffer or the output macrocell.
8 mach215-12/15/20 0 4 8 12 16 20 24 28 4032 43 36 0 4 8 12 16 20 24 28 4032 43 36 8 i/o cell i/o i/o i/o i/o i/o i/o i/o i/o switch matrix clk0 clk1 2 2 2 2 16 0 i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell output macro cell 2 2 2 2 output macro cell output macro cell output macro cell output macro cell output macro cell output macro cell output macro cell input macro cell 2 i/o cell 64 c 2 c 3 c 4 input macro cell 2 input macro cell 2 input macro cell 2 input macro cell 2 input macro cell 2 input macro cell 2 input macro cell 2 m 4 m 3 m 2 m 1 c 6 c 5 c 1 c 0 m 0 m 6 m 5 m 7 logic allocator c 7 63 16751e-3 figure 1. mach215 pal block
9 mach215-12/15/20 figure 2. product term clusters and the logic allocator product term cluster logic allocator from n+1 from nC1 to nC1 n to n+1 n to macrocell n 16751e-4 clk 0 1 0 1 0 ar ap qd/t/l to switch matrix sum of products from logic allocator individual asynchronous preset to i/o cell individual asynchronous reset figure 3. output macrocell individual clock 16751e-5
10 mach215-12/15/20 16751e-6 n from logic allocator to switch matrix to i/o cell a. combinatorial, active high n from logic allocator to switch matrix to i/o cell b. combinatorial, active low n from logic allocator to switch matrix to i/o cell c. d-type register, active high ap ar dq d. d-type register, active low e. t-type register, active high f. t-type register, active low g. latch, active high h. latch, active low clk 0 individual preset individual preset individual clock ap ar dq n from logic allocator to switch matrix to i/o cell clk 0 individual preset individual preset individual clock ap ar tq n from logic allocator to switch matrix to i/o cell clk 0 individual preset individual preset individual clock ap ar tq n from logic allocator to switch matrix to i/o cell clk 0 individual preset individual preset individual clock ap ar lq ap ar q n from logic allocator to switch matrix to i/o cell clk 0 individual preset individual preset individual clock n from logic allocator to switch matrix to i/o cell clk 0 individual preset individual preset individual clock g l g figure 4. output macrocell configurations
11 mach215-12/15/20 qd/l to switch matrix 16751e-7 from i/o pin clk 0 clk 1 figure 5. input macrocell ap a. input register dq to switch matrix from i/o cell b. input latch lq to switch matrix from i/o cell 16751e-8 g clk 0 clk 1 clk 0 clk 1 figure 6. input macrocell configurations 16751e-9 individual output enable product term from output macrocell to switch matrix to input macrocell figure 7. i/o cell
12 mach215-12/15/20 (com'l) absolute maximum ratings storage temperature C65 c to +150 c . . . . . . . . . . . ambient temperature with power applied C55 c to +125 c . . . . . . . . . . . . . supply voltage with respect to ground C0.5 v to +7.0 v . . . . . . . . . . . . . dc input voltage C0.5 v to v cc + 0.5 v . . . . . . . . . . . . dc output or i/o pin voltage C0.5 v to v cc + 0.5 v. . . . . . . . . . . . . . . static discharge voltage 2001 v . . . . . . . . . . . . . . . . . latchup current (t a = 0 c to +70 c) 200 ma . . . . . . . . . . . . . . . . . . . . stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. programming conditions may differ. operating ranges commercial (c) devices temperature (t a ) operating in free air 0 c to +70 c . . . . . . . . . . . . . . . . . . . . . . . supply voltage (v cc ) with respect to ground +4.75 v to +5.25 v . . . . . . . . . . . . operating ranges define those limits between which the func- tionality of the device is guaranteed. dc characteristics over commercial operating ranges unless otherwise specified parameter symbol parameter description test conditions min typ max unit v oh output high voltage i oh = C3.2 ma, v cc = min 2.4 v v in = v ih or v il v ol output low voltage i ol = 24 ma, v cc = min 0.5 v v in = v ih or v il (note 1) v ih input high voltage guaranteed input logical high 2.0 v voltage for all inputs (note 2) v il input low voltage guaranteed input logical low 0.8 v voltage for all inputs (note 2) i ih input high current v in = 5.25 v, v cc = max (note 3) 10 m a i il input low current v in = 0 v, v cc = max (note 3) C100 m a i ozh off-state output leakage v out = 5.25 v, v cc = max 10 m a current high v in = v ih or v il (note 3) i ozl off-state output leakage v out = 0 v, v cc = max C100 m a current low v in = v ih or v il (note 3) i sc output short-circuit current v out = 0.5 v, v cc = max (note 4) C30 C160 ma i cc supply current (typical) v cc = 5 v, t a = 25 c, f = 25 mhz 95 ma (note 5) notes: 1. total i ol for one pal block should not exceed 128 ma. 2. these are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 3. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 4. not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. v out = 0.5 v has been chosen to avoid test problems caused by tester ground degradation. 5. measured with a 16-bit up/down counter pattern. this pattern is programmed in each pal block and is capable of being loaded, enabled, and reset.
13 mach215-12/15/20 (com'l) capacitance (note 1) parameter symbol parameter description test conditions typ unit c in input capacitance v in = 2.0 v v cc = 5.0 v, t a = 25 c, 6 p f c out output capacitance v out = 2.0 v f = 1 mhz 8 p f switching characteristics over commercial operating ranges (note 2) parameter symbol parameter description min max min max min max unit t pd input, i/o, or feedback to combinatorial output (note 3) 3 1 2 3 15 3 2 0 n s d-type 5 6 8 n s t-type 6 7 9 n s t ha register data hold time using product term clock 5 6 8 n s t coa product term clock to output (note 3) 4 1 4 4 18 4 2 2 n s t wla low 8 9 12 ns t wha high 8 9 12 ns d-type 52.6 41.7 33.3 mhz t-type 50 40 32.2 mhz d-type 58.8 45.5 35.7 mhz t-type 55.6 43.5 34.5 mhz 62.5 55.6 41.7 mhz d-type 7 1 0 1 3 n s t-type 8 1 1 1 4 n s t hs register data hold time using global clock 0 0 0 n s t cos global clock to output (note 3) 2 8 2 10 2 1 2 n s t wls low 6 6 8 n s t whs high 6 6 8 n s d-type 66.7 50 40 mhz t-type 62.5 47.6 38.5 mhz f maxs d-type 83.3 66.6 50 mhz t-type 76.9 62.5 47.6 mhz 83.3 83.3 62.5 mhz t sla 568ns t hla latch data hold time using product term clock 5 6 8 n s t goa product term gate to output (note 3) 16 19 22 ns t gwa product term gate width low (for low transparent) 8 9 12 ns or high (for high transparent) t sls setup time from input, i/o, or feedback to global gate 7 1 0 1 3 n s t hls latch data hold time using global gate 0 0 0 n s t gos gate to output (note 3) 10 11 12 ns t gws global gate width low (for low transparent) 6 6 8 n s or high (for high transparent) maximum frequency using product term clock (note 1) external feedback 1/(t sa + t coa ) internal feedback (f cnta ) no feedback 1/(t wla + t wha ) global clock width -12 maximum frequency using global clock (note 1) setup time from input, i/o, or feedback to product term clock external feedback 1/(t ss + t cos ) internal feedback (f cnts ) no feedback 1/(t wls + t whs ) -15 -20 t ss t sa setup time from input, i/o, or feedback to global clock setup time from input, i/o, or feedback to product term gate f maxa product term, clock width
14 mach215-12/15/20 (com'l) switching characteristics over commercial operating ranges (note 2) (continued) parameter symbol parameter description min max min max min max unit t pdl input, i/o, or feedback to output through transparent input or output latch 14 17 22 ns t sir input register setup time 2 2 2 n s t hir input register hold time 2 2.5 3 n s t ico input register clock to combinatorial output 15 18 23 ns t ics input register clock to output register setup d-type 12 15 20 ns t-type 13 16 21 ns t wicl low 6 6 8 n s t wich high 6 6 8 n s f maxir maximum input register frequency 1/(t wicl + t wich ) 83.3 83.3 62.5 mhz t sil input latch setup time 2 2 2 n s t hil input latch hold time 2 2.5 3 n s t igo input latch gate to combinatorial output 17 20 25 ns t igol input latch gate to output through transparent output latch 19 22 27 ns setup time from input, i/o, or feedback through t slla transparent input latch to product term output 7 8 10 ns latch gate t igsa input latch gate to output latch setup using 7 8 10 ns product term output latch gate t slls setup time from input, i/o, or feedback through transparent input latch to global output latch gate 9 1 2 1 5 n s t igss input latch gate to output latch setup using global 13 16 21 ns output latch gate t wigl input latch gate width low 6 6 8 n s t pdll input, i/o, or feedback to output through transparent input and output latches 16 19 24 ns t ar asynchronous reset to registered or latched output 16 20 25 ns t arw asynchronous reset width (note 1) 12 15 20 ns t arr asynchronous reset recovery time (note 1) 8 1 0 1 5 n s t ap asynchronous preset to registered or latched output 16 20 25 ns t apw asynchronous preset width (note 1) 12 15 20 ns t apr asynchronous preset recovery time (note 1) 8 1 0 1 5 n s t ea input, i/o, or feedback to output enable (note 3) 2 1 2 2 15 2 2 0 n s t er input, i/o, or feedback to output disable (note 3) 2 1 2 2 15 2 2 0 n s notes: 1. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 2. see switching test circuit for test conditions. switching waveforms illustrate true clocks only. switching waveforms can be used to illustrate both synchronous and asynchronous clock timing. for example, t ss is the t s parameter for synchronous clocks and t sa is the t s parameter for asynchronous clocks. 3. parameters measured with 16 outputs switching. -12 -15 -20 input register clock width
15 mach215-14/18/24 (ind) absolute maximum ratings storage temperature C65 c to +150 c . . . . . . . . . . . ambient temperature with power applied C55 c to +125 c . . . . . . . . . . . . . supply voltage with respect to ground C0.5 v to +7.0 v . . . . . . . . . . . . . dc input voltage C0.5 v to v cc + 0.5 v. . . . . . . . . . . . dc output or i/o pin voltage C0.5 v to v cc + 0.5 v. . . . . . . . . . . . . static discharge voltage 2001 v . . . . . . . . . . . . . . . . . latchup current (t a = C40 c to +85 c) 200 ma . . . . . . . . . . . . . . . . . . stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. programming conditions may differ. industrial operating ranges ambient temperature (t a ) operating in free air C40 c to +85 c . . . . . . . . . . . . supply voltage (v cc ) with respect to ground +4.5 v to +5.5 v. . . . . . . . . . . . . . operating ranges define those limits between which the func- tionality of the device is guaranteed. dc characteristics over industrial operating ranges unless otherwise specified parameter symbol parameter description test conditions min typ max unit v oh output high voltage i oh = C3.2 ma, v cc = min 2.4 v v in = v ih or v il v ol output low voltage i ol = 24 ma, v cc = min 0.5 v v in = v ih or v il (note 1) v ih input high voltage guaranteed input logical high 2.0 v voltage for all inputs (note 2) v il input low voltage guaranteed input logical low 0.8 v voltage for all inputs (note 2) i ih input high leakage current v in = 5.25 v, v cc = max (note 3) 10 m a i il input low leakage current v in = 0 v, v cc = max (note 3) C100 m a i ozh off-state output leakage v out = 5.25 v, v cc = max 10 m a current high v in = v ih or v il (note 3) i ozl off-state output leakage v out = 0 v, v cc = max C100 m a current low v in = v ih or v il (note 2) i sc output short-circuit current v out = 0.5 v, v cc = max (note 4) C30 C160 ma i cc supply current (typical) v cc = 5 v, t a = 25 c, f = 25 mhz (note 5) 95 ma notes: 1. total i ol for one pal block should not exceed 128 ma. 2. these are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 3. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 4. not more than one output should be shorted at a time. duration of the short-circuit should not exceed one second. v out = 0.5 v has been chosen to avoid test problems caused by tester ground degradation. 5. measured with a 16-bit up/down counter pattern. this pattern is programmed in each pal block and is capable of being loaded, enabled, and reset.
16 mach215-14/18/24 (ind) capacitance (note 1) parameter symbol parameter description test conditions typ unit c in input capacitance v in = 2.0 v v cc = 5.0 v, t a = 25 c, 6 p f c out output capacitance v out = 2.0 v f = 1 mhz 8 p f switching characteristics over industrial operating ranges (note 2) parameter symbol parameter description min max min max min max unit t pd input, i/o, or feedback to combinatorial output 14.5 18 24 ns (note 3) d-type 6 7.5 10 ns t-type 7.5 8.5 11 ns t ha register data hold time using product term clock 6 7.5 10 ns t coa product term clock to output (note 3) 17 22 26.5 ns t wla low 10 11 15 ns t wha high 10 11 15 ns d-type 42 33 26.5 mhz t-type 40 32 25.5 mhz d-type 47 36 28.5 mhz t-type 44 34.5 27.5 mhz 50 44.5 33 mhz d-type 8.5 12 16 ns t-type 10 13.5 17 ns t hs register data hold time using global clock 0 0 0 n s t cos global clock to output (note 3) 10 12 14.5 ns t wls low 7.5 7.5 10 ns t whs high 7.5 7.5 10 ns d-type 53 40 32 mhz t-type 50 38 30.5 mhz f maxs d-type 66.5 53 40 mhz t-type 61.5 50 38 mhz 66.5 66.5 50 mhz t sla 6 7.5 10 ns t hla latch data hold time using product term clock 6 7.5 10 ns t goa product term gate to output (note 3) 19.5 23 26.5 ns t gwa product term gate width low (for low transparent) 10 11 14.5 ns or high (for high transparent) t sls setup time from input, i/o, or feedback to global gate 8.5 12 16 ns t hls latch data hold time using global gate 0 0 0 n s t gos gate to output (note 3) 12 13.5 14.5 ns t gws global gate width low (for low transparent) 7.5 7.5 10 ns or high (for high transparent) maximum frequency using product term clock (note 1) external feedback 1/(t sa + t coa ) internal feedback (f cnta ) no feedback 1/(t wla + t wha ) global clock width -14 maximum frequency using global clock (note 1) setup time from input, i/o, or feedback to product term clock external feedback 1/(t ss + tcos ) internal feedback (f cnts ) no feedback 1/(t wls + t whs ) -18 -24 t ss t sa setup time from input, i/o, or feedback to global clock setup time from input, i/o, or feedback to product term gate f maxs product term, clock width
17 mach215-14/18/24 (ind) switching characteristics over industrial operating ranges (note 2) (continued) parameter symbol parameter description min max min max min max unit t pdl input, i/o, or feedback to output through 17 20.5 26.5 ns transparent input or output latch t sir input register setup time 2.4 2.4 2.4 ns t hir input register hold time 3 3.5 4 n s t ico input register clock to combinatorial output 18 22 28 ns t ics input register clock to output register setup d-type 14.5 18 24 ns t-type 16 19.5 25.5 ns t wicl low 7.5 7.5 10 ns t wich high 7.5 7.5 10 ns f maxir maximum input register frequency 1/(t wicl + t wich ) 66.5 66.5 50 mhz t sil input latch setup time 2.5 2.5 2.5 ns t hil input latch hold time 3 3.5 4 n s t igo input latch gate to combinatorial output 20.5 24 30 ns t igol input latch gate to output through transparent 23 26.5 32.5 ns output latch setup time from input, i/o, or feedback through t slla transparent input latch to product term output 8.5 10 12 ns latch gate t igsa input latch gate to output latch setup using 8.5 10 12 ns product term output latch gate t slls setup time from input, i/o, or feedback through 11 14.5 18 ns transparent input latch to global output latch gate t igss input latch gate to output latch setup using global 16 19.5 25.5 ns output latch gate t wigl input latch gate width low 7.5 7.5 10 ns t pdll input, i/o, or feedback to output through transparent 19.5 23 29 ns input and output latches t ar asynchronous reset to registered or latched output 19.5 24 30 ns t arw asynchronous reset width (note 1) 14.5 18 24 ns t arr asynchronous reset recovery time (note 1) 10 12 18 ns t ap asynchronous preset to registered or latched output 19.5 24 30 ns t apw asynchronous preset width (note 1) 14.5 18 24 ns t apr asynchronous preset recovery time (note 1) 10 12 18 ns t ea input, i/o, or feedback to output enable (note 3) 14.5 18 24 ns t er input, i/o, or feedback to output disable (note 3) 14.5 18 24 ns notes: 1. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 2. see switching test circuit for test conditions. switching waveforms illustrate true clocks only. switching waveforms can be used to illustrate both synchronous and asynchronous clock timing. for example, t ss is the t s parameter for synchronous clocks and t sa is the t s parameter for asynchronous clocks. 3. parameters measured with 16 outputs switching. -14 -18 -24 input register clock width
18 mach215-12/15/20 typical current vs. voltage (i-v) characteristics v cc = 5.0 v, t a = 25 c input 20 C40 C60 C80 C2 C1 123 output, high i i (ma) v i (v) C20 i oh (ma) v oh (v) 25 C50 C75 C100 C3 C2 C1 123 C25 C125 C150 45 45 C100 C0.8 C0.6 C0.4 .2 C0.2C1.0 16751e-10 output, low .4 .6 1.0 .8 60 40 20 C20 C40 80 C60 C80 i ol (ma) v ol (v) 16751e-11 16751e-12
19 mach215-12/15/20 typical i cc characteristics v cc = 5 v, t a = 25 c mach215 150 125 100 75 50 25 0 0 10203040 5060708090 i cc (ma) frequency (mhz) the selected typical pattern is a 16-bit up/down counter. this pattern is programmed in each pal block and is capable of being loaded, enabled, and reset. maximum frequency shown uses internal feedback and a d-type register. 16751e-13
20 mach215-12/15/20 typical thermal characteristics measured at 25 c ambient. these parameters are not tested. parameter symbol parameter description plcc units q jc thermal impedance, junction to case 15 c/w q ja thermal impedance, junction to ambient 40 c/w q jma thermal impedance, junction to 200 lfpm air 36 c/w 400 lfpm air 33 c/w 600 lfpm air 31 c/w 800 lfpm air 29 c/w plastic q jc considerations the data listed for plastic q jc are for reference only and are not recommended for use in calculating junction temperatures. the heat-flow paths in plastic-encapsulated devices are complex, making the q jc measurement relative to a specific location on the package surface. tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package. furthermore, q jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. therefore, the measurements can only be used in a similar environment. typ ambient with air flow
21 mach215-12/15/20 switching waveforms notes: 1. v t = 1.5 v. 2. input pulse amplitude 0 v to 3.0 v. 3. input rise and fall times 2 nsC4 ns typical. t pd input, i/o, or feedback combinatorial output v t v t combinatorial output v t input, i/o, or feed- back registered output registered output t s t co v t t h v t clock t wh clock clock width t wl v t combinatorial output registered input (mach 2 and 4) t sir t ico v t t hir v t input register clock registered input latched output (mach 2, 3, and 4) gate gate width (mach 2, 3, and 4) t gws v t v t v t v t t ics input register to output register setup (mach 2 and 4) output register clock input register clock registered input t pdl input, i/o, or feedback latched out gate v t t hl t sl t go v t v t 16751e-14 16751e-15 16751e-16 16751e-17 16751e-18 16751e-19 16751e-20
22 mach215-12/15/20 switching waveforms notes: 1. v t = 1.5 v. 2. input pulse amplitude 0 v to 3.0 v. 3. input rise and fall times 2 nsC4 ns typical. latched input (mach 2 and 4) latched input and output (mach 2, 3, and 4) latched in output latch gate latched out t sll combinatorial output gate t hil t sil t igo latched in t pdll t igol t igs input latch gate v t v t v t v t v t v t 16751e-21 16751e-22
23 mach215-12/15/20 switching waveforms t wich clock input register clock width (mach 2 and 4) v t t wicl v t v t t arw v t t ar asynchronous reset input, i/o, or feedback registered output clock t arr asynchronous preset registered output clock v t v t outputs output disable/enable t er t ea v oh - 0.5v v ol + 0.5v notes: 1. v t = 1.5 v. 2. input pulse amplitude 0 v to 3.0 v. 3. input rise and fall times 2 nsC4 ns typical. input, i/o, or feedback v t v t input, i/o, or feedback t apw v t t ap t apr input latch gate input latch gate width (mach 2 and 4) t wigl v t 16751e-23 16751e-24 16751e-25 16751e-26 16751e-27
24 mach215-12/15/20 key to switching waveforms ks000010-pal must be steady may change from h to l may change from l to h does not apply don't care, any change permitted will be steady will be changing from h to l will be changing from l to h changing, state unknown center line is high- impedance off state waveform inputs outputs switching test circuit measured specification s 1 c l r 1 r 2 output value t pd , t co closed 1.5 v t ea z ? h: open 35 pf 1.5 v z ? l: closed 300 w 390 w t er h ? z: open 5 pf h ? z: v oh C 0.5 v l ? z: closed l ? z: v ol + 0.5 v commercial 16751e-28 c l output r 1 r 2 s 1 test point 5 v *switching several outputs simultaneously should be avoided for accurate measurement.
25 mach215-12/15/20 f max parameters the parameter f max is the maximum clock rate at which the device is guaranteed to operate. because the flexi- bility inherent in programmable logic devices offers a choice of clocked flip-flop designs, f max is specified for three types of synchronous designs. the first type of design is a state machine with feedback signals sent off-chip. this external feedback could go back to the device inputs, or to a second device in a multi-chip state machine. the slowest path defining the period is the sum of the clock-to-output time and the in- put setup time for the external signals (t s + t co ). the re- ciprocal, f max , is the maximum frequency with external feedback or in conjunction with an equivalent speed de- vice. this f max is designated f max external. the second type of design is a single-chip state ma- chine with internal feedback only. in this case, flip-flop inputs are defined by the device inputs and flip-flop out- puts. under these conditions, the period is limited by the internal delay from the flip-flop outputs through the inter- nal feedback and logic to the flip-flop inputs. this f max is designated f max internal. a simple internal counter is a good example of this type of design; therefore, this pa- rameter is sometimes called f cnt. the third type of design is a simple data path applica- tion. in this case, input data is presented to the flip-flop and clocked through; no feedback is employed. under these conditions, the period is limited by the sum of the data setup time and the data hold time (t s + t h ). however, a lower limit for the period of each f max type is the mini- mum clock period (t wh + t wl ). usually, this minimum clock period determines the period for the third f max , des- ignated f max no feedback. for devices with input registers, one additional f max pa- rameter is specified: f maxir . because this involves no feedback, it is calculated the same way as f max no feed- back. the minimum period will be limited either by the sum of the setup and hold times (t sir + t hir ) or the sum of the clock widths (t wicl + t wich ). the clock widths are nor- mally the limiting parameters, so that f maxir is specified as 1/(t wicl + t wich ). note that if both input and output reg- isters are use in the same path, the overall frequency will be limited by t ics . all frequencies except f max internal are calculated from other measured ac parameters. f max internal is meas- ured directly. t hir t sir logic register tt clk (second chip) sco t s f max external; 1/(t s + t co ) logic register clk f max internal (f cnt ) logic register t clk s f max no feedback; 1/(t s + t h ) or 1/(t wh + t wl ) 16751e-29 logic register clk f maxir ; 1/(t sir + t hir ) or 1/(t wicl + t wich )
26 mach215-12/15/20 endurance characteristics t h e m a c h f a m i l i e s a r e m a n u f a c t u r e d u s i n g o u r advanced electrically erasable process. this technol- ogy uses an ee cell to replace the fuse link used in bipolar parts. as a result, the device can be erased and reprogrammed, a feature which allows 100% testing at the factory. endurance characteristics parameter symbol parameter description min units test conditions 10 years max storage temperature 20 years max operating temperature n max reprogramming cycles 100 cycles normal programming conditions t dr min pattern data retention time
27 mach215-12/15/20 input/output equivalent schematics input i/o preload circuitry esd protection feedback input v cc v cc 1 k w 100 k w v cc v cc 100 k w 1 k w 16751e-30
28 mach215-12/15/20 power-up reset the mach devices have been designed with the capa- bility to reset during system power-up. following power- up, all flip-flops will be reset to low. the output state will depend on the logic polarity. this feature provides extra flexibility to the designer and is especially valuable in simplifying state machine initialization. a timing dia- gram and parameter table are shown below. due to the synchronous operation of the power-up reset and the wide range of ways v cc can rise to its steady state, two conditions are required to insure a valid power-up reset. these conditions are: 1. the v cc rise must be monotonic. 2. following reset, the clock input must not be driven from low to high until all applicable input and feedback setup times are met. parameter symbol parameter descriptions max unit t pr power-up reset time 10 m s t s input or feedback setup time t wl clock width low see switching characteristics t pr t wl t s 4 v v cc power registered output clock 16751e-31 power-up reset waveform
29 mach215-12/15/20 using preload and observability in order to be testable, a circuit must be both controllable and observable. to achieve this, the mach devices incorporate register preload and observability. in preload mode, each flip-flop in the mach device can be loaded from the i/o pins, in order to perform functional testing of complex state machines. register preload makes it possible to run a series of tests from a known starting state, or to load illegal states and test for proper recovery. this ability to control the mach device's internal state can shorten test sequences, since it is easier to reach the state of interest. the observability function makes it possible to see the internal state of the buried registers during test by overriding each register's output enable and activating the output buffer. the values stored in output and buried registers can then be observed on the i/o pins. without this feature, a thorough functional test would be impossible for any designs with buried registers. while the implementation of the testability features is fairly straightforward, care must be taken in certain instances to insure valid testing. one case involves asynchronous reset and preset. if the mach registers drive asynchronous reset or preset lines and are preloaded in such a way that reset or preset are asserted, the reset or preset may remove the preloaded data. this is illustrated in figure 8. care should be taken when planning functional tests, so that states that will cause unexpected resets and presets are not preloaded. another case to be aware of arises in testing combinato- rial logic. when an output is configured as combinato- rial, the observability feature forces the output into registered mode. when this happens, all product terms are forced to zero, which eliminates all combinatorial data. for a straight combinatorial output, the correct value will be restored after the preload or observe function, and there will be no problem. if the function implements a combinatorial latch, however, it relies on feedback to hold the correct value, as shown in figure 9. as this value may change during the preload or observe operation, you cannot count on the data being correct after the operation. to insure valid testing in these cases, outputs that are combinatorial latches should not be tested immediately following a preload or observe sequence, but should first be restored to a known state. all mach 2 devices support both preload and observability. contact individual programming vendors in order to verify programmer support. ar figure 8. preload/reset conflict q 1 on off preload mode q 2 ar preloaded high d q q 1 d q ar preloaded high q 2 16751e-32 figure 9. combinatorial latch set reset 16751e-33
34 mach215-12/15/20 physical dimensions* pl 044 44-pin plastic leaded chip carrier (measured in inches) top view seating plane .685 .695 .650 .656 pin 1 i.d. .685 .695 .650 .656 .026 .032 .050 ref .042 .056 .062 .083 .013 .021 .590 .630 .500 ref .009 .015 .165 .180 .090 .120 16-038-sq pl 044 da78 6-28-94 ae side view *for reference only. bsc is an ansi standard for basic space centering.

▲Up To Search▲

Price & Availability of MACH215-15JC

	To Download MACH215-15JC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .