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1.5 ghz ultrahigh speed op amp ad8000 features high speed 1.5 ghz, ?3 db bandwidth (g = +1) 650 mhz, full power bandwidth (g = +2, v o = 2 v p-p) slew rate: 4100 v/s 0.1% settling time: 12 ns excellent video specifications 0.1 db flatness: 170 mhz differential gain: 0.02% differential phase: 0.01 output overdrive recovery: 22 ns low noise: 1.6 nv/hz input voltage noise low distortion over wide bandwidth 75 dbc sfdr @ 20 mhz 62 dbc sfdr @ 50 mhz input offset voltage: 1 mv typ high output current: 100 ma wide supply voltage range: 4.5 v to 12 v supply current: 13.5 ma power-down mode applications professional video high speed instrumentation video switching if/rf gain stage ccd imaging general description the ad8000 is an ultrahigh speed, high performance, current feedback amplifier. using adis proprietary extra fast com- plementary bipolar (xfcb) process, the amplifier can achieve a small signal bandwidth of 1.5 ghz and a slew rate of 4100 v/s. the ad8000 has low spurious-free dynamic range (sfdr) of 75 dbc @ 20 mhz and input voltage noise of 1.6 nv/hz. the ad8000 can drive over 100 ma of load current with minimal distortion. the amplifier can operate on +5 v to 6 v. these specifications make the ad8000 ideal for a variety of applica- tions, including high speed instrumentation. with a differential gain of 0.02%, differential phase of 0.01, and 0.1 db flatness out to 170 mhz, the ad8000 has excellent video specifications, which ensure that even the most demanding video systems maintain excellent fidelity. connection diagrams 1 power down 2 feedback 3 ?in 4 +in 7output 8+v s 6nc 5?v s 0 5321-001 ad8000 notes 1. nc = no connect. 2. the exposed paddle is connected to ground. figure 1. 8-lead ad8000, 3 mm 3 mm lfcsp_vd (cp-8-2) feedback 1 ?in 2 +in 3 ?v s 4 power down 8 +v s 7 output 6 nc 5 05321-002 ad8000 notes 1. nc = no connect. 2. the exposed paddle is connected to ground. figure 2. 8-lead ad8000 soic_n_ep (rd-8-1) ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 normalized gain (db) 05321-003 frequency (mhz) 1 100 10 1000 v s = ? 5v r l = 150 ? v out = 2v p-p g = +2, r f = 432 ? figure 3. large signal frequency response the ad8000 power-down mode reduces the supply current to 1.3 ma. the amplifier is available in a tiny 8-lead lfcsp pack- age, as well as in an 8-lead soic package. the ad8000 is rated to work over the extended industrial temperature range (?40c to +125c). a triple version of the ad8000 (ad8003) is under- development. rev. a information furnished by analog devices is believed to be accurate and reliable. however, no re- sponsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2005-2010 analog devices, inc. all rights reserved.
ad8000 rev. a | page 2 of 20 table of contents table of contents .............................................................................. 2 ? specifications with 5 v supply ..................................................... 3 ? specifications with +5 v supply ..................................................... 4 ? absolute maximum ratings ............................................................ 5 ? thermal resistance ...................................................................... 5 ? esd caution .................................................................................. 5 ? typical performance characteristics ............................................. 6 ? test circuits ..................................................................................... 13 ? applications ..................................................................................... 14 ? circuit configurations ............................................................... 14 ? video line driver ....................................................................... 14 ? low distortion pinout ............................................................... 15 ? exposed paddle ........................................................................... 15 ? printed circuit board layout ................................................... 15 ? signal routing ............................................................................. 15 ? power supply bypassing ............................................................ 15 ? grounding ................................................................................... 16 ? outline dimensions ....................................................................... 17 ? ordering guide .......................................................................... 17 ? revision history 3/10rev. 0 to rev. a changes to figure 1 and figure 2 ................................................... 1 changes to table 3 ............................................................................ 5 updated outline dimensions and changes to ordering guide ............................................................................... 17 1/05rev. 0: initial version
ad8000 rev. a | page 3 of 20 specifications with 5 v supply at t a = 25c, v s = 5 v, r l = 150 , gain = +2, r f = r g = 432 , unless otherwise noted. exposed paddle should be connected to ground. table 1. parameter conditions min typ max unit dynamic performance ?3 db bandwidth g = +1, v o = 0.2 v p-p, soic/lfcsp 1580/1350 mhz g = +2, v o = 2 v p-p, soic/lfcsp 650/610 mhz bandwidth for 0.1 db flatness v o = 2 v p-p, soic/lfcsp 190/170 mhz slew rate g = +2, v o = 4 v step 4100 v/s settling time to 0.1% g = +2, v o = 2 v step 12 ns noise/harmonic performance second/third harmonic v o = 2 v p-p, f = 5 mhz, lfcsp only 86/89 dbc second/third harmonic v o = 2 v p-p, f = 20 mhz, lfcsp only 75/79 dbc input voltage noise f = 100 khz 1.6 nv/hz input current noise f = 100 khz, ?in 26 pa/hz f = 100 khz, +in 3.4 pa/hz differential gain error ntsc, g = +2 0.02 % differential phase error ntsc, g = +2 0.01 degree dc performance input offset voltage 1 10 mv input offset voltage drift 11 v/c input bias current (enabled) +i b ?5 +4 a ?i b ?3 +45 a transimpedance 570 890 1600 k input characteristics noninverting input impedance 2/3.6 m/pf input common-mode voltage range ?3.5 to +3.5 v common-mode rejection ratio v cm = 2.5 v ?52 ?54 ?56 db overdrive recovery g = +1, f = 1 mhz, triangle wave 30 ns power down pin power-down input voltage power-down < +v s C 3.1 v enabled > +v s C 1.9 v turn-off time 50% of power-down voltage to 10% of v out final, v in = 0.3 v p-p 150 ns turn-on time 50% of power-down voltage to 90% of v out final, v in = 0.3 v p-p 300 ns input bias current enabled ?1.1 +0.17 +1.4 a power-down ?300 ?235 ?160 a output characteristics output voltage swing r l = 100 3.7 3.9 v output voltage swing r l = 1 k 3.9 4.1 v linear output current v o = 2 v p-p, second hd < ?50 dbc 100 ma overdrive recovery g = + 2, f = 1 mhz, triangle wave 45 ns g = +2, v in = 2.5 v to 0 v step 22 ns power supply operating range 4.5 12 v quiescent current 12.7 13.5 14.3 ma quiescent current (power-down) 1.1 1.3 1.65 ma power supply rejection ratio ?psrr/+psrr ?56/?61 ?59/?63 db
ad8000 rev. a | page 4 of 20 specifications with +5 v supply at t a = 25c, v s = +5 v, r l = 150 , gain = +2, r f = r g = 432 , unless otherwise noted. exposed paddle should be connected to ground. table 2. parameter conditions min typ max unit dynamic performance ?3 db bandwidth g = +1, v o = 0.2 v p-p 980 mhz g = +2, v o = 2 v p-p 477 mhz g = +10, v o = 0.2 v p-p 328 mhz bandwidth for 0.1 db flatness v o = 0.2 v p-p 136 mhz v o = 2 v p-p 136 mhz slew rate g = +2, v o = 2 v step 2700 v/s settling time to 0.1% g = +2, v o = 2 v step 16 ns noise/harmonic performance second/third harmonic v o = 2 v p-p, 5 mhz, lfcsp only 71/71 dbc second/third harmonic v o = 2 v p-p, 20 mhz, lfcsp only 60/62 dbc input voltage noise f = 100 khz 1.6 nv/hz input current noise f = 100 khz, ?in 26 pa/hz f = 100 khz, +in 3.4 pa/hz differential gain error ntsc, g = +2 0.01 % differential phase error ntsc, g = +2 0.06 degree dc performance input offset voltage 1.3 10 mv input offset voltage drift 18 v/c input bias current (enabled) +i b ?5 +3 a ?i b ?1 +45 a transimpedance 440 800 1500 k input characteristics noninverting input impedance 2/3.6 m/pf input common-mode voltage range 1.5 to 3.6 v common-mode rejection ratio v cm = 2.5 v ?51 ?52 ?54 db overdrive recovery g = +1, f = 1 mhz, triangle wave 60 ns power down pin power-down input voltage power-down < +v s ? 3.1 v enable > +v s ? 1.9 v turn-off time 50% of power-down voltage to 10% of v out final, v in = 0.3 v p-p 200 ns turn-on time 50% of power-down voltage to 90% of v out final, v in = 0.3 v p-p 300 ns input current enabled ?1.1 +0.17 +1.4 a power-down ?50 ?40 ?30 a output characteristics output voltage swing r l = 100 1.1 to 3.9 1.05 to 4.1 v r l = 1 k 1 to 3.1 0.85 to 4.15 v linear output current v o = 2 v p-p, second hd < ?50 dbc 70 ma overdrive recovery g = +2, f = 100 khz, triangle wave 65 ns power supply operating range 4.5 12 v quiescent current 11 12 13 ma quiescent current (power-down) 0.7 0.95 1.25 ma power supply rejection ratio ?psrr/+psrr ?55/?60 ?57/?62 db
ad8000 rev. a | page 5 of 20 absolute maximum ratings table 3. the power dissipated in the package (p d ) is the sum of the quiescent power dissipation and the power dissipated in the die due to the ad8000 drive at the output. the quiescent power is the voltage between the supply pins (v s ) times the quiescent current (i s ). parameter rating supply voltage 12.6 v power dissipation see figure 4 common-mode input voltage ?v s ? 0.7 v to +v s + 0.7 v differential input voltage v s storage temperature ?65c to +125c operating temperature range ?40c to +125c lead temperature range (soldering, 10 sec) 300c junction temperature 150c p d = quiescent power + ( total d r ive power C load power ) () l 2 out l out s ss d r v C r v 2 v ivp ? ? ? ? ? ? ? ? += rms output voltages should be considered. if r l is referenced to ?v s , as in single-supply operation, the total drive power is v s i out . if the rms signal levels are indeterminate, consider the worst case, when v out = v s /4 for r l to midsupply. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. () ( ) l s ss d r /v ivp 2 4 += in single-supply operation with r l referenced to ?v s , worst case is v out = v s /2. thermal resistance ja is specified for the worst-case conditions, that is, ja is speci- fied for device soldered in the circuit board for surface-mount packages. table 4. thermal resistance package type ja jc unit soic-8 80 30 c/w 3 mm 3 mm lfcsp 93 35 c/w airflow increases heat dissipation, effectively reducing ja . also, more metal directly in contact with the package leads and exposed paddle from metal traces, through holes, ground, and power planes reduces ja . figure 4 shows the maximum safe power dissipation in the package vs. the ambient temperature for the exposed paddle soic (80c/w) and the lfcsp (93c/w) package on a jedec standard 4-layer board. ja values are approximations. maximum power dissipation 0 0.5 1.0 1.5 2.0 2.5 3.0 maximum power dissipation (w) 05321-063 ?30 ?20 ?10 0 10 20 40 80 30 50 60 70 10090 120110 ambient temperature ( c) soic lfcsp ?40 the maximum safe power dissipation for the ad8000 is limited by the associated rise in junction temperature (t j ) on the die. at approximately 150 c, which is the glass transition temperature, the properties of the plastic change. even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric perfor- mance of the ad8000. exceeding a junction temperature of 175 c for an extended period of time can result in changes in silicon devices, potentially causing degradation or loss of functionality. figure 4. maximum power dissipation vs. temperature for a 4-layer board esd caution esd (electrostatic discharge) sensitive device. electr ostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. althou gh this product features proprietary esd protection circuitry, permanent damage may occur on devices subjec ted to high energy elec- trostatic discharges. therefore, proper esd precaution s are recommended to avoid performance degradation and loss of functionality.
ad8000 rev. a | page 6 of 20 typical performance characteristics normalized gain (db) 05321-006 frequency (mhz) 10 1 100 1000 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 v s = 5v r l = 150 v out = 200mv p-p g = +1, r f = 432 g = +2, r f = 432 , r g = 432 g = +10, r f = 357 , r g = 40.2 figure 5. small signal frequency response vs. various gains normalized gain (db) frequency (mhz) 10 1 100 1000 05321-007 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 v s = 5v r l = 150 v out = 200mv p-p g = ?1, r f = r g = 249 g = ?2, r f = 432 , r g = 215 g = ?10, r f = 432 , r g = 43.2 figure 6. small signal frequency response vs. various gains ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 normalized gain (db) 05321-008 frequency (mhz) 1 100 10 1000 v s = 5v r l = 150 v out = 2v p-p g = +1, r f = 432 g = +2, r f = r g = 432 g = +4, r f = 357 , r g = 121 g = +10, r f = 357 , r g = 40.2 figure 7. large signal frequency response vs. various gains ?3 0 3 6 9 gain (db) frequency (mhz) 10 1 100 1000 05321-011 v s = 5v g = +2 r l = 150 v out = 200mv p-p lfcsp r f = 392 r f = 432 r f = 487 figure 8. small signal frequency response vs. r f ?3 0 3 6 9 gain (db) frequency (mhz) 10 1 100 1000 05321-012 r f = 392 r f = 432 r f = 487 v s = 5v g = +2 r l = 150 v out = 2v p-p lfcsp figure 9. large signal frequency response vs. r f transimpedance (k ) 05321-027 frequency (mhz) phase (degrees) 0.1 1 10 100 1000 0.1 1 10 100 1000 10000 tz phase 50 0 50 100 150 100 200 v s = 5v r l = 100 figure 10. transimpedance and phase vs. frequency
ad8000 rev. a | page 7 of 20 gain (db) 05321-010 frequency (mhz) ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 0.1 1 10 100 1000 r l = 1k g = +1 r f = 432 v out = 200mv p-p lfcsp v s = +5v, r s = 0 v s = 5v, r s = 50 v s = +5v, r s = 50 v s = 5v, r s = 0 figure 11. small signal frequency response vs. supply voltage ?9 ?6 ?3 0 3 6 9 gain (db) frequency (mhz) 10 1 100 1000 05321-009 r l = 150 g = +1 r f = 432 v out = 200mv p-p lfcsp v s = 5v v s = +5v figure 12. small signal frequency response vs. supply voltage 5.5 5.6 5.7 5.8 5.9 6.0 6.1 6.2 6.3 6.4 6.5 gain (db) 05321-013 frequency (mhz) 1 100 10 v s = 5v r l = 150 v out = 2v p-p g = +2 r f = 432 soic lfcsp figure 13. 0.1 db flatness ?3 0 3 6 9 gain (db) frequency (mhz) 10 1 100 1000 05321-014 v s = 5v g = +2 r l = 150 v out = 200mv p-p lfcsp ?40 c +125 c +25 c figure 14. small signal frequency response vs. temperature ?3 0 3 6 9 gain (db) frequency (mhz) 10 1 100 1000 05321-015 v s = 5v g = +2 r l = 1k v out = 200mv p-p lfcsp ?40 c +125 c +25 c figure 15. small signal frequency response vs. temperature ?3 0 3 6 9 gain (db) frequency (mhz) 10 1 100 1000 05321-016 v s = 5v g = +2 r l = 150 v out = 2v p-p lfcsp +125 c +25 c ?40 c figure 16. large signal frequency response vs. temperature
ad8000 rev. a | page 8 of 20 ?3 0 3 6 9 gain (db) frequency (mhz) 10 1 100 1000 05321-017 v s = 5v g = +2 r l = 150 lfcsp v out = 1v p-p v out = 4v p-p v out = 2v p-p figure 17. large signal frequency response vs. various outputs ?120 ?110 ?100 ?90 ?80 ?70 distortion (dbc) ?60 ?50 ?40 05321-040 frequency (mhz) 1 10 100 second hd third hd v s = 5v v out = 2v p-p g = +1 r l = 150 lfcsp figure 18. harmonic distortion vs. frequency ?120 ?110 ?100 ?90 ?80 ?70 distortion (dbc) ?60 ?50 ?40 05321-039 frequency (mhz) 1 10 100 second hd third hd v s = 5v g = +10 v out = 2v p-p r l = 1k lfcsp figure 19. harmonic distortion vs. frequency ?120 ?110 ?100 ?90 ?80 ?70 distortion (dbc) ?60 ?50 ? 40 05321-042 frequency (mhz) 1 10 100 second hd third hd v s = 5v v out = 2v p-p g = +1 r l = 1k lfcsp figure 20. harmonic distortion vs. frequency ?100 ?90 ?80 ?70 ?60 ?50 distortion (dbc) ?40 ?30 ?20 05321-041 frequency (mhz) 1 10 100 second hd third hd v s = 5v v out = 4v p-p g = +1 r l = 1k lfcsp figure 21. harmonic distortion vs. frequency ?100 ?90 ?80 ?70 distortion (dbc) ?60 ?50 ? 40 05321-043 frequency (mhz) 1 10 100 v s = 5v v out = 2v p-p g = +2 r l = 150 soic second hd lfcsp second hd lfcsp third hd soic third hd figure 22. harmonic distortion vs. frequency
ad8000 rev. a | page 9 of 20 distortion (dbc) 05321-044 frequency (mhz) ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 1 10 100 v s = 5v v out = 2v p-p g = +2 r l = 150 lfcsp second hd third hd figure 23. harmonic distortion vs. frequency ?100 ?90 ?80 ?70 ?60 ?50 distortion (dbc) ?40 ?30 ?20 05321-045 frequency (mhz) 1 10 100 v s = 5v v out = 2v p-p g = +2 r l = 1k lfcsp second hd third hd figure 24. harmonic distortion vs. frequency distortion (dbc) 05321-047 frequency (mhz) ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 1 10 100 v s = 5v v out = 2v p-p g = +2 r l = 1k lfcsp second hd third hd figure 25. harmonic distortion vs. frequency distortion (dbc) 05321-048 frequency (mhz) ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 1 10 100 second hd third hd v s = 2.5v v out = 2v p-p g = ?1 r l = 150 lfcsp figure 26. harmonic distortion vs. frequency distortion (dbc) 05321-049 frequency (mhz) ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 1 10 100 second hd third hd v s = 5v v out = 2v p-p g = ?1 r l = 1k lfcsp figure 27. harmonic distortion vs. frequency ?110 ?100 ?90 ?80 ?70 distortion (dbc) ?60 ?50 ?40 05321-050 frequency (mhz) 1 10 100 v s = 5v v out = 2v p-p g = ?1 r l = 150 lfcsp second hd third hd figure 28. harmonic distortion vs. frequency
ad8000 rev. a | page 10 of 20 ?120 ?110 ?100 ?90 ?80 ?70 distortion (dbc) ?60 ?50 ? 40 05321-051 frequency (mhz) 1 10 100 second hd third hd v s = 5v v out = 2v p-p g = ?1 r l = 1k lfcsp figure 29. harmonic distortion vs. frequency 0.01 0.1 1 10 100 1k impedance ( ) frequency (mhz) 1 0.1 10 100 1000 05321-023 v s = 5v v in = 0.2v p-p r f = 432 lfcsp g = +1 or g = +2 figure 30. output impedance vs. frequency 2.35 2.40 2.45 2.50 2.55 2.60 2.65 response (v) 0 5 10 15 20 25 30 35 40 45 50 time (ns) 05321-072 g = +2 g = +1 v s = 5v r f = 432 r s = 0 r l = 100 figure 31. small signal transient response psrr (db) frequency (mhz) 1 0.1 10 100 05321-021 ?75 ?70 ?60 ?40 ?30 ?20 ?15 ?10 ?50 ?65 ?45 ?35 ?25 ?55 v s = 5v v in = 2v p-p r l = 100 g = +1 r f = 432 ?psrr +psrr figure 32. power supply rejection ratio (psrr) vs. frequency cmrr (db) 05321-031 frequency (mhz) 1 0.1 10 100 1000 ?60 ?40 ?30 ?50 ?65 ?45 ?35 ?25 ?55 v s = 5v v in = 1v p-p r l = 100 lfcsp figure 33. common-mode rejection ratio vs. frequency ?0.150 ?0.125 ?0.075 0.025 0.075 0.125 0.150 0.175 ?0.025 ?0.100 0 0.050 0.100 ?0.050 response (v) time (ns) 05321-066 ?0.175 0 5 10 15 20 25 30 35 40 45 50 g = +1 g = +2 v s = 5v r f = 432 r s = 0 r l = 100 figure 34. small signal transient response
ad8000 rev. a | page 11 of 20 ?1.50 ?1.25 ?0.75 0.25 0.75 1.25 1.50 1.75 ?0.25 ?1.00 0 0.50 1.00 ?0.50 response (v) time (ns) 0 5 10 15 20 25 30 35 40 45 50 05321-067 ?1.75 g = +1 g = +2 v s = 5v r f = 432 r s = 0 r l = 100 figure 35. large signal transient response ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 settling time (%) 0.1 0.2 0.3 v cm (v) 05321-068 ?5 ?4 ?3 ?2 ?1 0 1 2 3 0.4 0.5 v in g = +2 5ns/div t = 0s 1v figure 36. settling time 0 1k 2k 3k 4k 5k 6k sr (v/ s) 01234567 v out (v p-p) 05321-018 g = +2 r f = 432 r l = 150 lfcsp, v s = +5v soic, v s = 5v lfcsp, v s = 5v soic, v s = +5v figure 37. slew rate vs. output level ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 output voltage (v) 0 200 400 600 800 1000 time (ns) 05321-019 g = +1 r l = 150 r f = 432 v s = 2.5v, v out v s = 2.5v, v in v s = 5v, v out v s = 5v, v in figure 38. input overdrive ?6 ?4 ?2 ?3 ?5 0 ?1 output voltage (v) 2 1 4 3 6 5 0 200 400 600 800 1000 time (ns) 05321-020 g = +2 r l = 150 r f = 432 v s = 2.5v, v out v s = 2.5v, 2 v in v s = 5v, v out v s = 5v, 2 v in figure 39. output overdrive input voltage noise (nv/ hz) 05321-058 frequency (hz) 0.1 10 1 100 100k 10k 100 1k 10 1m 10m 100m v s = 5v g = +10 r f = 432 r n = 47.5 figure 40. input voltage noise
ad8000 rev. a | page 12 of 20 input current noise (pa/ hz) 05321-055 frequency (hz) 0.1 1 10 100 1000 100k 10k 100 1k 10 1m 10m 100m 1g v s = 5v inverting current noise, r f = 1k noninverting current noise, r f = 432 figure 41. input current noise ?20 ?15 ?10 ?5 0 5 v os (mv) 10 15 20 v cm (v) 05321-024 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 v s = +5v v s = 5v figure 42. input v os vs. common-mode voltage ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 25 i b ( a) ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 v out (v) 05321-069 v s = +5v v s = 5v figure 43. input bias current vs. output voltage ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 i b ( a) 05321-070 v cm (v) v s = +5v v s = 5v figure 44. input bias current vs. common-mode voltage s22 (db) 05321-065 frequency (mhz) ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 10 100 1000 r back term = 50 v s = 5v g = +2 p out = ?10dbm soic figure 45. output voltage standing wave ratio (s22) s11 (db) 05321-064 frequency (mhz) ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 10 100 1000 input r s = 0 v s = 5v p out = ?10dbm soic g = +10 g = +1 g = +2 figure 46. input voltage standing wave ratio (s11)
ad8000 rev. a | page 13 of 20 test circuits ad8000 50 transmission line 200 r f 432 432 200 10 f 0.1 f 49.9 ?v s 0.1 f 10 f 05321-028 50 transmission line +v s 49.9 60.4 v in figure 47. cmrr 49.9 termination 50 0.1 f 10 f ?v s v p = v s + v in r f 432 r g 432 49.9 ad8000 49.9 50 transmission line 05321-029 50 transmission line termination 50 figure 48. positive psrr 49.9 termination 50 +v s v n =?v s + v in r f 432 r g 432 49.9 ad8000 49.9 10 f 0.1 f 50 transmission line 05321-030 50 transmission line t ermination 50 figure 49. negative psrr
ad8000 rev. a | page 14 of 20 applications fb ad8000 10 f 0.1 f r g +v s v o v in r l ? + v o +v ?v s ?v 10 f 0.1 f r f + + 05321-036 all current feedback amplifier operational amplifiers are affected by stray capacitance at the inverting input pin. as a practical consideration, the higher the stray capacitance on the inverting input to ground, the higher r f needs to be to minimize peaking and ringing. circuit configurations figure 50 and figure 51 show typical schematics for non- inverting and inverting configurations. for current feedback amplifiers, the value of feedback resistance determines the stability and bandwidth of the amplifier. the optimum performance values are shown in table 5 and should not be deviated from by more than 10% to ensure stable operation. figure 8 shows the influence varying r f has on bandwidth. in noninverting unity-gain configurations, it is recommended that an r s of 50 be used, as shown in figure 50 . figure 51. inverting configuration video line driver the ad8000 is designed to offer outstanding performance as a video line driver. the important specifications of differential gain (0.02%), differential phase (0.01), and 650 mhz band- width at 2 v p-p meet the most exacting video demands. figure 52 shows a typical noninverting video driver with a gain of +2. table 5 provides a quick reference for the circuit values, gain, and output voltage noise. fb ad8000 10 f 0.1 f r g r s +v s v o v in r l ? + v o +v ?v s ?v 10 f 0.1 f r f + + noninverting 05321-035 432 432 75 cable 75 75 v out +v s ?v s v in 0.1 f 4.7 f ad8000 0.1 f 4.7 f 75 cable 75 + + + 05321-071 fb figure 52. video line driver figure 50. noninver ting configuration table 5. typical values (lfcsp/soic) gain component values () ?3 db ss bandwidth (mhz) ?3 db ls bandwidth (mhz) slew rate (v/sec) output noise (nv/hz) total output noise including resistors (nv/hz) r f r g lfcsp soic lfcsp soic 1 432 --- 1380 1580 550 600 2200 10.9 11.2 2 432 432 600 650 610 650 3700 11.3 11.9 4 357 120 550 550 350 350 3800 10 12 10 357 40 350 365 370 370 3200 18.4 19.9
ad8000 rev. a | page 15 of 20 low distortion pinout the ad8000 lfcsp features adis new low distortion pinout. the new pinout lowers the second harmonic distortion and simplifies the circuit layout. the close proximity of the non- inverting input and the negative supply pin creates a source of second harmonic distortion. physical separation of the non- inverting input pin and the negative power supply pin reduces this distortion significantly, as seen in figure 22 . by providing an additional output pin, the feedback resistor can be connected directly across pin 2 and pin 3. this greatly simplifies the routing of the feedback resistor and allows a more compact circuit layout, which reduces its size and helps to mi- nimize parasitics and increase stability. the soic also features a dedicated feedback pin. the feedback pin is brought out on pin 1, which is typically a no connect on standard soic pinouts. existing applications that use the standard soic pinout can take full advantage of the performance offered by the ad8000. for drop-in replacements, ensure that pin 1 is not connected to ground or to any other potential because this pin is connected internally to the output of the amplifier. for existing designs, pin 6 can still be used for the feedback resistor. exposed paddle the ad8000 features an exposed paddle, which can lower the thermal resistance by 25% compared to a standard soic plastic package. the paddle can be soldered directly to the ground plane of the board. figure 53 shows a typical pad geometry for the lfcsp, the same type of pad geometry can be applied to the soic package. thermal vias or heat pipes can also be incorporated into the design of the mounting pad for the exposed paddle. these addi- tional vias improve the thermal transfer from the package to the pcb. using a heavier weight copper on the surface to which the amplifiers exposed paddle is soldered also reduces the over- all thermal resistance seen by the ad8000. 05321-034 figure 53. lfcsp exposed paddle layout printed circuit board layout laying out the printed circuit board (pcb) is usually the last step in the design process and often proves to be one of the most critical. a brilliant design can be rendered useless because of a poor or sloppy layout. since the ad8000 can operate into the r f frequency spectrum, high frequency board layout con- siderations must be taken into account. the pcb layout, signal routing, power supply bypassing, and grounding all must be addressed to ensure optimal performance. signal routing the ad8000 lfcsp features the new low distortion pinout with a dedicated feedback pin and allows a compact layout. the dedicated feedback pin reduces the distance from the output to the inverting input, which greatly simplifies the routing of the feedback network. to minimize parasitic inductances, ground planes should be used under high frequency signal traces. however, the ground plane should be removed from under the input and output pins to minimize the formation of parasitic capacitors, which degrades phase margin. signals that are susceptible to noise pickup should be run on the internal layers of the pcb, which can provide maximum shielding. power supply bypassing power supply bypassing is a critical aspect of the pcb design process. for best performance, the ad8000 power supply pins need to be properly bypassed. a parallel connection of capacitors from each of the power supply pins to ground works best. paralleling different values and sizes of capacitors helps to ensure that the power supply pins see a low ac impedance across a wide band of frequen- cies. this is important for minimizing the coupling of noise into the amplifier. starting directly at the power supply pins, the smallest value and sized component should be placed on the same side of the board as the amplifier, and as close as possible to the amplifier, and connected to the ground plane. this process should be repeated for the next larger value capacitor. it is recommended for the ad8000 that a 0.1 f ceramic 0508 case be used. the 0508 offers low series inductance and excellent high frequency performance. the 0.1 f case provides low impedance at high frequencies. a 10 f electrolytic capacitor should be placed in parallel with the 0.1 f. the 10 f capacitor provides low ac impedance at low frequencies. smaller values of electrolytic capacitors can be used, depending on the circuit requirements. additional smaller value capacitors help to provide a low impedance path for unwanted noise out to higher frequencies but are not always necessary.
ad8000 rev. a | page 16 of 20 placement of the capacitor returns (grounds), where the capaci- tors enter into the ground plane, is also important. returning the capacitors grounds close to the amplifier load is critical for distortion performance. keeping the capacitors distance short, but equal from the load, is optimal for performance. in some cases, bypassing between the two supplies can help to improve psrr and to maintain distortion performance in crowded or difficult layouts. this is as another option to improve performance. minimizing the trace length and widening the trace from the capacitors to the amplifier reduce the trace inductance. a series inductance with the parallel capacitance can form a tank circuit, which can introduce high frequency ringing at the output. this additional inductance can also contribute to increased distor- tion due to high frequency compression at the output. the use of vias should be minimized in the direct path to the amplifier power supply pins since vias can introduce parasitic inductance, which can lead to instability. when required, use multiple large diameter vias because this lowers the equivalent parasitic inductance. grounding the use of ground and power planes is encouraged as a method of proving low impedance returns for power supply and signal currents. ground and power planes can also help to reduce stray trace inductance and to provide a low thermal path for the amplifier. ground and power planes should not be used under any of the pins of the ad8000. the mounting pads and the ground or power planes can form a parasitic capacitance at the amplifiers input. stray capacitance on the inverting input and the feedback resistor form a pole, which degrades the phase margin, leading to instability. excessive stray capacitance on the output also forms a pole, which degrades phase margin.
ad8000 rev. a | page 17 of 20 outline dimensions compliant to jedec standards ms-012-a a controlling dimensions are in millimeter; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. 072808- a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.050) 0.40 (0.016) 0.50 (0.020) 0.25 (0.010) 45 8 0 1.75 (0.069) 1.35 (0.053) 1.65 (0.065) 1.25 (0.049) seating plane 85 4 1 5.00 (0.197) 4.90 (0.193) 4.80 (0.189) 4.00 (0.157) 3.90 (0.154) 3.80 (0.150) 1.27 (0.05) bsc 6.20 (0.244) 6.00 (0.236) 5.80 (0.228) 0.51 (0.020) 0.31 (0.012) coplanarity 0.10 top view 2.29 (0.090) bottom view (pins up) 2.29 (0.090) 0.10 (0.004) max for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 54. 8-lead standard small outline package, with exposed pad [soic_n_ep] narrow body (rd-8-1) dimensions shown in millimeters and (inches) 0 90308-b 1 exposed pa d (bottom view) 0.50 bsc pin 1 indicator 0.50 0.40 0.30 top view 12 max 0.70 max 0.65 typ 0.90 max 0.85 nom 0.05 max 0.01 nom 0.20 ref 1.89 1.74 1.59 4 1.60 1.45 1.30 3.25 3.00 sq 2.75 2.95 2.75 sq 2.55 5 8 pin 1 indicator seating plane 0.30 0.23 0.18 0.60 max 0.60 max for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 55. 8-lead lead frame chip scale package [lfcsp_vd] 3 mm 3 mm body, very thin, dual lead (cp-8-2) dimensions shown in millimeters ordering guide model 1 temperature range package description pack age option branding ordering quantity ad8000yrdz C40c to +125c 8-lead soic_n_ep rd-8-1 1 ad8000yrdz-reel C40c to +125c 8-lead soic_n_ep rd-8-1 2,500 AD8000YRDZ-REEL7 C40c to +125c 8-lead soic_n_ep rd-8-1 1,000 ad8000ycpz-r2 C40c to +125c 8-lead lfcsp_vd cp-8-2 hnb 250 ad8000ycpz-reel C40c to +125c 8-lead lfcsp_vd cp-8-2 hnb 5,000 ad8000ycpz-reel7 C40c to +125c 8-lead lfcsp_vd cp-8-2 hnb 1,500 1 z = rohs compliant part.
ad8000 rev. a | page 18 of 20 notes
ad8000 rev. a | page 19 of 20 notes
ad8000 rev. a | page 20 of 20 notes ? 2005-2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d05321C0C3/10(a)

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