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general description the MAX9450/max9451/max9452 clock generators provide high-precision clocks for timing in sonet/sdh systems or gigabit ethernet systems. the MAX9450/ max9451/max9452 can also provide clocks for the high- speed and high-resolution adcs and dacs in 3g base stations. additionally, the devices can also be used as a jitter attenuator for generating high-precision clk signals. the MAX9450/max9451/max9452 feature an integrated vcxo. this configuration eliminates the use of an exter- nal vcxo and provides a cost-effective solution for gen- erating high-precision clocks. the MAX9450/max9451/ max9452 feature two differential inputs and clock out- puts. the inputs accept lvpecl, lvds, differential sig- nals, and lvcmos. the input reference clocks range from 8khz to 500mhz. the MAX9450/max9451/max9452 offer lvpecl, hstl, and lvds outputs, respectively. the output range is up to 160mhz, depending on the selection of crystal. the input and output frequency selection is implemented through the i 2 c or spi interface. the MAX9450/ max9451/max9452 feature clock output jitter less than 0.8ps rms (in a 12khz to 20mhz band) and phase- noise attenuation greater than -130dbc/hz at 100khz. the phase-locked loop (pll) filter can be set externally, and the filter bandwidth can vary from 1hz to 20khz. the MAX9450/max9451/max9452 feature an input clock monitor with a hitless switch. when a failure is detected at the selected reference clock, the device can switch to the other reference clock. the reaction to the recovery of the failed reference clock can be revertive or nonrevertive. if both reference clocks fail, the pll retains its nominal frequency within a range of ?0ppm at +25?. the MAX9450/max9451/max9452 operate from 2.4v to 3.6v supply and are available in 32-pin tqfp packages with exposed pads. applications sonet/sdh systems 10 gigabit network routers and switches 3g cellular phone base stations general jitter attenuation features ? integrated vcxo provides a cost-effective solution for high-precision clocks ? 8khz to 500mhz input frequency range ? 15mhz to 160mhz output frequency range ? i 2 c or spi programming for the input and output frequency selection ? pll lock range > 60ppm ? two differential outputs with three types of signaling: lvpecl, lvds, or hstl ? input clock monitor with hitless switch ? internal holdover function within 20ppm of the nominal frequency ? low output clk jitter: < 0.8ps rms in the 12khz to 20mhz band ? low phase noise > -130dbc at 100khz, > -140dbc at 1mhz MAX9450/max9451/max9452 high-precision clock generators with integrated vcxo ________________________________________________________________ maxim integrated products 1 ordering information 19-0547; rev 2; 9/06 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. note: all devices are specified over the -40? to +85? temperature range. for lead-free packages, contact factory. * ep = exposed paddle. part pin-package output pkg code MAX9450 ehj 32 tqfp-ep* lvpecl h32e-6 max9451 ehj 32 tqfp-ep* hstl h32e-6 max9452 ehj 32 tqfp-ep* lvds h32e-6 MAX9450 max9451 max9452 tqfp (5mm x 5mm) top view exposed pad (gnd) 24 20 21 22 23 17 18 19 clk1+ clk1- gnd clk0+ v ddq clk0- v ddq oe 2 5 7 6 8 34 1 sel0 in0- in0+ in1+ v dd 9 10 11 12 13 14 15 ad1 16 ad0 sda scl mr int 26 27 28 29 30 31 32 rj gnda lp2 lp1 v dda x2 x1 25 v dd sel1 lock in1- gnd/cs cmon pin configuration spi is a trademark of motorola, inc.
MAX9450/max9451/max9452 high-precision clock generators with integrated vcxo 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics (v dda = v dd = v ddq = 2.4v to 3.6v, and v ddq = 1.4v to 1.6v for max9451, t a = -40? to +85?. typical values at v dda = v dd = v ddq = 3.3v, and v ddq = 1.5v for max9451, t a = +25?, unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to gnd ...........................................................-0.3v to +4.0v v dda to gnda ......................................................-0.3v to +4.0v all other pins to gnd ...................................-0.3v to v dd + 0.3v short-circuit duration (all pins) ..................................continuous continuous power dissipation (t a = +85?) 32-pin tqfp (derate 27.8mw/? above +70?)........2222mw storage temperature range .............................-65? to +165? maximum junction temperature .....................................+150? operating temperature range ...........................-40? to +85? lead temperature (soldering, 10s) .................................+300? esd protection human body model (r d = 1.5k ? , c s = 100pf) ..............?kv parameter symbol conditions min typ max units lvcmos input (sel_, cmon , oe , mr) input high level v ih1 2.0 v dd v input low level v il1 0 0.8 v input current i in1 v in = 0v to v dd -50 +50 ? lvcmos output (int, lock ) output high level v oh1 i oh1 = -4ma v dd - 0.4 v output low level v ol1 i ol1 = 4ma 0.4 v three-level input (ad0, ad1) input high level v ih2 1.8 v input low level v il2 0.8 v input open level v io2 measured at the opened inputs 1.05 1.35 v input current i il2 , i ih2 v il2 = 0v or v ih2 = v dd -15 +15 ? differential inputs (in0, in1) differential input high threshold v idh v id = v in+ - v in- 50 mv differential input low threshold v idl v id = v in+ - v in- -50 mv common-mode input-voltage range v com v id = v in+ - v in- |v id / 2| 2.4 - |v id / 2| v input current i in+ , i in- -1 +1 ? MAX9450 outputs (clk0, clk1) (lvpecl) output high voltage v oh2 50 ? load connected to v ddq - 2.0v v d d q - 1.42 v d d q - 1.00 v output low voltage v ol2 50 ? load connected to v ddq - 2.0v v d d q - 2.15 v d d q - 1.70 v max9451 outputs (clk0, clk1) (differential hstl) output high-level voltage v oh3 w i th 50 ? l oad r esi stor to g n d , fi g ur e 1 v d d q - 0.4v v d d q v output low-level voltage v ol3 wi th 50 ? to gn d and 16m a si nk cur r ent 0.4 v max9452 outputs (clk0, clk1) (lvds) differential output voltage v od with a total 100 ? load, figure 1 300 370 450 mv change in v od between complementary output states ? v od 10 35 mv
MAX9450/max9451/max9452 high-precision clock generators with integrated vcxo _______________________________________________________________________________________ 3 dc electrical characteristics (continued) (v dda = v dd = v ddq = 2.4v to 3.6v, and v ddq = 1.4v to 1.6v for max9451, t a = -40? to +85?. typical values at v dda = v dd = v ddq = 3.3v, and v ddq = 1.5v for max9451, t a = +25?, unless otherwise noted.) parameter symbol conditions min typ max units output offset voltage v os 1.05 1.2 1.35 v change in v os between complementary output states ? v os 10 35 mv output short-circuit current i os two output pins connected to gnd - 7.5 - 15 ma serial interface input, output (scl, sda, cs ) input high level v ih 0.7 x v dd v input low level v il 0.3 x v dd v input leakage current i il -1 +1 ? output low level v ol 3ma sink current 0.4 v input capacitance c i 10 pf power consumption MAX9450 55 85 max9451 70 94 v dd and v dda supply current i cc1 output clock frequency = 155mhz max9452 65 88 ma MAX9450 55 80 max9451 65 80 v ddq supply current i cc2 output clock frequency = 155mhz (MAX9450) max9452 14 25 ma ac electrical characteristics (v dda = v dd = v ddq = 2.4v to 3.6v, and v ddq = 1.4v to 1.6v for max9451, t a = -40? to +85?. |v id | = 200mv, v com = |v id / 2| to 2.4 - |v id / 2|. typical values at v dda = v dd = v ddq = 3.3v and v ddq = 1.5v for max9451, t a = +25?. c l = 10pf, clock output = 155.5mhz and clock input = 19.44mhz, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units clk outputs (clk0, clk1) reference input frequency f in measured at in0 or in1 0.008 500 mhz output frequency f out measured at clk0 or clk1 15 160 mhz vcxo pulling range c l = 8pf (note 2) ?0 ppm skew between clk0 and clk1 (MAX9450 and max9452) 50 90 output-to-output skew t sko skew between c lk0 and c lk1 (m ax9451) 55 106 ps rise time t r 20% to 80% of output swing 0.4 0.590 ns fall time t f 80% to 20% of output swing 0.4 0.590 ns duty cycle 43 56 % period jitter (rms) t j measured at the band 12khz to 20mhz 0.8 ps 1khz offset -70 10khz offset -110 100khz offset -130 phase noise 1mhz offset -140 dbc
note 1: all timing ac electrical characteristics and timing specifications are guaranteed by design and not production tested. note 2: the vcxo tracks the input clock frequency by ?0ppm. note 3: a master device must provide a hold time of at least 300ns for the sda signal to bridge the undefined regions of scl? falling edge. note 4: c b = total capacitance of one bus line in pf. tested with c b = 400pf. note 5: input filters on sda and scl suppress noise spikes less than 50ns. parameter symbol conditions min typ max units serial-clock frequency f scl 2 mhz cs fall to clk rise setup time t css 12.5 ns din setup time t ds 12.5 ns din hold time t dh 0ns clk high to cs high t csh 0ns cs pulse-high time t csw 20 ns serial spi interface timing characteristics (v dd = 2.4v to 3.6v, t a = -40? to +85?. see figure 7 for the timing parameters definition.) MAX9450/max9451/max9452 high-precision clock generators with integrated vcxo 4 _______________________________________________________________________________________ parameter symbol conditions min typ max units serial clock f scl 400 khz bus free time between stop and start conditions t buf 1.3 ? rep eated h ol d ti m e s tart c ond i ti on t hd , sta 0.6 ? rep eated s tart c ond i ti on s etup ti m et su , sta 0.6 ? stop condition setup time t su , sto 0.6 ? data hold time t hd , dat (note 3) 100 ns data setup time t su , dat 100 ns scl clock-low period t low 1.3 ? scl clock-high period t high 0.7 ? maximum receive scl/sda rise time t r 300 ns minimum receive scl/sda rise time t r (note 4) 20 + 0.1 x c b ns maximum receive scl/sda fall time t f 300 ns minimum receive scl/sda fall time t f (note 4) 20 + 0.1 x c b ns fall time of sda, transmitting t f,tx (note 4) 20 + 0.1c b 250 ns pulse width of suppressed spike t sp (note 5) 0 50 ns capacitive load for each bus line c b (note 4) 400 pf serial i 2 c-compatible interface timing characteristics (v dd = 2.4v to 3.6v, t a = -40? to +85?. see figure 4 for the timing parameters definition.)
MAX9450/max9451/max9452 high-precision clock generators with integrated vcxo _______________________________________________________________________________________ 5 v dd and v dda supply current vs. voltage (MAX9450) MAX9450 toc01 voltage (v) i dd + i dda (ma) 3.2 3.0 2.8 2.6 48 56 64 72 80 40 2.4 3.6 3.4 t a = -40 c t a = +25 c t a = +85 c v ddq supply current vs. voltage (MAX9450) MAX9450 toc02 voltage (v) i ddq (ma) 3.2 3.0 2.8 2.6 48 56 64 72 80 40 2.4 3.6 3.4 t a = -40 c t a = +25 c t a = +85 c output frequency change vs. temperature MAX9450 toc04 temperature ( c) output frequency change (ppm) 60 35 -15 10 -20 0 20 40 -40 -40 85 phase noise vs. frequency MAX9450 toc05 phase noise (dbc) 100k frequency (hz) 1m 10m 10k 1k 0 -20 -40 -60 -80 -100 -120 -140 -160 input reference = 38.88 mhz output clock = 155.52 mhz output rms jitter vs. temperature MAX9450 toc03 temperature ( c) rms jitter (ps) 60 35 10 -15 2 4 6 8 10 0 -40 85 output clock synchronized to input reference MAX9450 toc06 153.13mv/div 100mv/div 10ns/div input reference = 19.44mhz output clock = 155.52 mhz typical operating characteristics (v dd = v dda = v ddq = 3.3v. t a = +25?, unless otherwise noted.)
MAX9450/max9451/max9452 high-precision clock generators with integrated vcxo 6 _______________________________________________________________________________________ pin description pin name function 1 lock lock indicator. lock goes low when the pll locks. lock is high when the pll is not locked. 2, 3 s e l0, s e l1 ino_ and in1_ select inputs. drive sel0 high to activate in0; drive sel1 high to activate in1. driving sel0 and sel1 low disables the corresponding input. a 165k ? pullup resistor pulls sel0 and sel1 up to v dd . 4, 5 in0+, in0- differential reference input pair. in0+ and in0- accept lvpecl, lvds, and lvcmos signals. 6, 25 v dd digital power supply. connect a 2.4v to 3.6v power supply to v dd . bypass v dd to gnd with a 0.1? capacitor. 7, 8 in1+, in1- differential reference input pair. in1+ and in1- accept lvpecl, lvds, and lvcmos signals. 9 int reference input condition indicator. a high indicates a failed reference. 10 mr master reset. drive mr high to reset all i 2 c registers to their default state and int to zero. 11 gnd/ cs ground and chip-select input. connect to gnd in i 2 c mode. this is the chip-select input in spi mode. 12 scl clock input. scl is the clock input in i 2 c bus mode and spi bus mode. 13 sda data input. sda is the data input in i 2 c bus mode and spi bus mode. 14, 15 ad0, ad1 i 2 c address selection. drive ad0 and ad1 high to convert the serial interface from i 2 c to spi. gnd/ cs becomes cs . see table 3 for the unique addresses list. 16 cmon c m cmon low to enable the clock monitor. drive cmon high to disable the clock monitor. 17 oe output enable input. drive oe low to enable the clock outputs. driving oe high disables the clock outputs, and the outputs go high impedance. an internal 165k ? pullup resistor pulls oe up to v dd . 18, 24 v ddq clock-output power supply. connect a 2.4v to 3.6v power supply to v ddq for the MAX9450 and max9452. connect a 1.5v power supply to v ddq for the max9451. connect a 0.1? bypass capacitor from v ddq to gnd. 19, 20 clk0-, clk0+ differential clock output 0. the MAX9450 features lvpecl outputs. the max9451 features hstl outputs and the max9452 features lvds outputs. 21 gnd digital gnd 22, 23 clk1-, clk1+ differential clock output 1. the MAX9450 features lvpecl outputs. the max9451 features hstl outputs, and the max9452 features lvds outputs. 26, 27 x1, x2 reference crystal input. connect the reference crystal from x1 to x2. 28 v dda anal og p ow er s up p l y. c onnect a 2.4v to 3.6v p ow er sup p l y to v d d a . byp ass v d d a to gn d a w i th a 0.1f cap aci tor . 29, 30 lp1, lp2 external loop filter. connect an rc circuit between lp1 and lp2. see the external loop filter section. 31 gnda analog ground 32 rj charge-pump set current. connect an external resistor to gnd to set the charge-pump current. see table 11. ep ep exposed paddle. connect to ground.
MAX9450/max9451/max9452 high-precision clock generators with integrated vcxo _______________________________________________________________________________________ 7 gnda v dda v dd gnd vcxo crystal 5mhz to 160mhz fundamental mode and at cut lock det 1/m lut for p loop filter rj lp2 60nf 6nf 10k ? lp1 x1 x2 i 2 c port scl sda lut for n1, n2 lut for m ad0 ad1 in0+ in0- in1+ in1- sel0 0 1 clk monitor cmon int 1/n1 clk1+ clk1- oe clk0+ clk0- 1/n0 1/p pfd/cp sel1 mr spi port control registers gnd/cs mux lock 12k ? to 200k ? div0 div1 MAX9450 max9451 max9452 functional diagram detailed description the MAX9450/max9451/max9452 clock generators provide high-precision clocks for timing in sonet/sdh systems or gigabit ethernet systems. the MAX9450/ max9451/max9452 can also provide clocks for the high-speed and high-resolution adcs and dacs in 3g base stations. additionally, the MAX9450/max9451/ max9452 can be used as a jitter attenuator for generat- ing high-precision clock signals. the MAX9450/max9451/max9452 feature two differen- tial inputs and two differential clock outputs. the inputs accept lvpecl, lvds, and lvcmos signals. the input reference clock ranges from 8khz to 500mhz and the output clock ranges from 15mhz to 160mhz. the internal clock monitor observes the condition of the input reference clocks and provides a hitless switch when an input failure is detected. the MAX9450/ max9451/max9452 also provide holdover in case no input clock is supplied. control and status registers the MAX9450/max9451/max9452 contain eight 8-bit control registers named cr0 to cr7. the registers are accessible through the i 2 c/spi interface. cr0 is for the frequency-dividing factor, p. cr1 and cr2 hold the values of the divider, m. cr3 and cr4 are for dividers
MAX9450/max9451/max9452 high-precision clock generators with integrated vcxo 8 _______________________________________________________________________________________ n1 and n2, respectively. cr5 and cr6 are the control function registers for output enabling, reference clock selection, and activation of the clock monitor and the holdover function. cr7 contains the status of clock monitor, holdover, and pll locking. the addresses of the eight registers are shown in table 4. tables 5 through 10 show the register maps. output buffers three different output formats (lvpecl, hstl, and lvds) are available. each output contains its own frequency divider. all the output clocks align to their coincident rising edges. after changing the dividing ratio, the output clocks complete the current cycle and stay logic-low until the rising edges of the newly divided clock. when cr5[7] is high, the MAX9450/max9451/ max9452 set all the outputs to logic-low. setting the bits cr5[6] and cr5[5] properly enables and disables the outputs individually; see table 8. a disabled output is always in high impedance. at the receiver end, the two cables or pcb traces can be terminated as shown in figure 1. the vcxo output is divided down before driving the out- put buffers. program the dividing factor through the serial interface. the MAX9450/max9451/max9452 feature two output dividers div0 and div1 (see the functional diagram ). div0 drives out0 and either div0 or div1 can drive out1. cr6[2] sets which divider output drives out1. this function allows for programming out1 and out0 to different frequencies. reference clock inputs the MAX9450/max9451/max9452 feature two ?ny- thing?differential clock inputs. ?nything?means that the inputs take any differential signals, such as cml, lvds, lvpecl, or hstl. the inputs can also take a single-ended input. for example, with lvcmos refer- ence inputs, connect the inputs to the positive pins inn+ and connect the negative pins inn- to a reference voltage of v dd - 1.32v. see figure 2. setting cr5[4] and cr6[3] selects the input reference. failure detection and revert function apply only to in0 and in1. also, sel0 and sel1 or cr5[3:2] can disable the corresponding inputs. see table 2. frequency selection and programming the output frequency at clkn, (n = 0, 1) is determined by the reference clock and the dividing factors m, ni (i = 0, 1) , and p, shown in the following equation: ff m ni p clkn ref = lvcmos clk output v ref = v dd - 1.32v anything input figure 2. connecting lvcmos output to lvpecl input z = 50 ? lvpecl output 127 ? 127 ? 3.3v 83 ? 83 ? lvpecl input (a) lvpecl dc-coupling z = 50 ? hstl output 50 ? 50 ? hstl input (c) hstl dc-coupling (b) lvds coupling z = 50 ? lvds output 100 ? lvds input figure 1. dc lvpecl, lvds, and hstl termination
MAX9450/max9451/max9452 high-precision clock generators with integrated vcxo _______________________________________________________________________________________ 9 10 gigabit ethernet sonet input clk: 50mhz input clk: 19.44mhz crystal frequency (mhz) pmni output frequency (mhz) crystal frequency (mhz) pm ni output frequency (mhz) 50 2 2 1 50 51.84 1 8 1 51.84 125 2 5 2 62.5 77.76 1 4 1 77.76 125 2 5 1 125 155.52 1 8 1 155.52 155.52 1 4 2 77.76 table 1. output frequency selection and register content values where f clkn is the frequency at the clkn output, f ref is the frequency of the reference clock, m (1 to 32,768) is the dividing factor in the feedback loop, ni (1, 2, 3, 4, 5, 6, 8, 16) are the dividing factors of the outputs, and p (1 to 256) is the dividing factor to the input reference clock. it is possible to set various frequencies at the two differential clk_ outputs with this configuration. for example, in 10 gigabit ethernet or sonet applica- tions, set the dividing factors to generate the required frequencies, as shown in table 1. input clock monitor failure detection the MAX9450/max9451/max9452 clock-failure-detec- tion function monitors the two reference inputs simultane- ously. if a reference input clock signal (in_) does not transition for two or more vco cycles, the device reports a failure by setting int high and bit cr7[6] or cr7[5] to 1. see table 9. after a reference clock failure, the moni- tor switches to the other valid input reference. at the same time, the clock monitor loads cr7 with the status of the reference clocks and which input is selected. the mapping of cr7 is given in table 9. if one of the inputs is disabled according to the bits in cr5[3:2], then the mon- itor is disabled. revert function the response of the MAX9450/max9451/max9452 to a detected input failure depends on the setting of the revert function. if the failed input recovers from the failure, int and cr7[5:6] resets to zero if revert is acti- vated. if the recovered input is selected by cr5[4] as the default input reference, the MAX9450/max9451/ max9452 reselect this input. if the revert function is not activated, once an input failure is detected, the monitor remains in the failure state with int = 1 and cr7[5:6] = 1, until the MAX9450/max9451/max9452 are reset. activate the revert function using the bit cr5[1]. failure-detection monitor reset reset the fault by toggling cmon from low to high, toggling mr or cr6[4] from low to high, or by toggling the bit cr5[0] from low to high. in revert mode, when the monitor is reset, int and cr7[5:6] reset to zero and the default input is the one indicated by cr5[4]. holdover function the holdover function locks the output frequency to its nominal value within ?0ppm. activate this function by setting cr6[7] to 1. the MAX9450/max9451/max9452 enter holdover when the devices detect a failure from both input references. setting cr6[6] to 1 forces the device into the holdover state, while resetting cr6[6] exits holdover. use a reset holdover. if the revert function is activated once an input is recovered from the failure, the device also exits holdover and switches to the recovered input reference. if both inputs recover simultaneously, the device switches to the default input. vcxo frequency during holdover is the value of the frequency right before the failure of inputs. when cr6[5] goes from 0 to 1, the value of the vcxo frequency is acquired and stored. the vcxo can be switched to this acquired frequency by setting cr6[1] to 1. such a transition can happen in both the normal mode of operation and the holdover mode. pll lock detect the MAX9450/max9451/max9452 also feature pll lock detection. the MAX9450/max9451/max9452 compare the frequency of the phase-detector input with the output frequency of the loop frequency divider. when these two frequencies deviate more than 20ppm, the lock output goes high. at power-up, lock is high. lock goes low when the pll locks. pll lock time also depends on the loop filter bandwidth.
MAX9450/max9451/max9452 high-precision clock generators with integrated vcxo 10 ______________________________________________________________________________________ external loop filter when the device switches from one input reference to the other or reverts to an input reference from holdover, the output phase changes smoothly during the transition due to the narrowband external pll filter. the narrower the filter bandwidth is, the smoother the phase transition. however, if bandwidth is too narrow, it can cause some degradation on output jitter performance. charge-pump current setting the MAX9450/max9451/max9452 allow external setting of the charge-pump current in the pll. connect a resis- tor from rj to gnda to set the pll charge-pump current: charge-pump current (?) = 2.48 x 1000 / (r set (k ? ) + 0.375) where r set is in k ? and the value of the charge-pump current is in ?. use r set to adjust the loop response to meet individual application requirements. the charge-pump current and the external filter compo- nents change the pll bandwidth. table 11 shows the charge-pump current vs. the resistor? value. the loop response equation is defined as: unity-gain bandwidth = (i cp x r filt x 12khz) / m where i cp is the charge-pump current set by rext, r filt is the external filter resistance, and m is the feed- back divider. input disable the two inputs can be disabled separately by sel0 and sel1 or the 2 bits in cr5[3:2]. table 2 shows the state map. power-up and master reset upon power-up, default frequency divider rates and the states of the monitor, inputs, and outputs are set according to table 10. setting mr high or cr6[4] to 1 also resets the device. when the device resets, int and cr7[5:6] go low and all the registers revert to their default values. i 2 c interface the control interface of the MAX9450/max9451/max9452 is an i 2 c or spi depending on the states of ad0 and ad1. drive both ad0 and ad1 high to active spi mode. otherwise, i 2 c is activated. the device operates as a slave that sends and receives data through the clock line, scl, and data line, sda, to achieve bidirectional communication with the masters. a master (typically a microcontroller) initiates all data transfers to and from slaves, and generates the scl clock that synchronizes the data transfer. figure 4 shows the timing of scl and sda. the sda line operates as both an input and an open-drain output. sda requires a pullup resistor, typi- cally 4.7k ? . the scl line operates only as an input. a pullup resistor, typically 4.7k ? , is required on scl if there are multiple masters on the 2-wire bus, or if the master in a single-master system has an open-drain scl output. i 2 c device address every i 2 c port has a 7-bit device address. this 7-bit address is the slave (MAX9450/max9451/max9452) id for the master to write and read. in the MAX9450/ max9451/max9452, the first 4 bits (1101) of the address are hard coded into the device at the factory. see table 3. the last 3 bits of the address are input programmable by the three-level ad0 and ad1. this configuration provides eight selectable addresses for the MAX9450/max9451/max9452, allowing eight devices to be connected to one master. start and stop conditions both scl and sda remain high when the interface is not busy. the active master signals the beginning of a transmission with a start (s) condition by transitioning sda from high to low while scl is high. when the master has finished communicating with the slave, it issues a stop (p) condition by transitioning sda from low to high while scl is high. the bus is then free for another transmission (figure 3). the interval between a start and a stop is called a session. sel1 sel0 cr5[3:2] in1 in0 0000 disabled disabled 0100 disabled enabled 1000 enabled disabled 1100 enabled enabled xx01 disabled enabled xx10 enabled disabled xx11 enabled enabled table 2. input activation by sel0, sel1, or cr5[3:2] sda scl s start condition p stop condition figure 3. start and stop conditions
MAX9450/max9451/max9452 high-precision clock generators with integrated vcxo ______________________________________________________________________________________ 11 data transfer and acknowledge following the start condition, each scl clock pulse transfers 1 bit. between a start and a stop, multiple bytes can be transferred on the 2-wire bus. the first 7 bits (b0?6) are for the device address. the eighth bit (b7) indicates the writing (low) or reading (high) operation (w/r). the ninth bit (b8) is the ack for the address and operation type. a low ack bit indicates a successful transfer; otherwise, a high ack bit indicates an unsuc- cessful transfer. the next 8 bits (register address), b9?16, form the address byte for the control register to be written (figure 4). the next bit, bit 17, is the ack for the register address byte. the following byte (data1) is the content to be written into the addressed register of the slave. after this, the address counter of i 2 c is increased by 1 (rgst addr + 1) and the next byte (data2) writes into a new register. to read the contents in the MAX9450/max9451/max9452s?control registers, the master sends the register address to be read to the slave by a writing operation. then it sends the byte of device address + r to the slave. the slave (MAX9450/ max9451/max9452) responds with the content bytes from the registers, starting from the pointed register to the last register, cr8, consecutively back to the master (figures 5 and 6). smbclk a = start condition b = msb of address clocked into slave c = lsb of address clocked into slave d = r/w bit clocked into slave ab cd e fg hij smbdata t su:sta t hd:sta t low t high t su:dat t su:sto t buf lm k e = slave pulls smbdata line low f = acknowledge bit clocked into master g = msb of data clocked into slave h = lsb of data clocked into slave i = master pulls data line low j = acknowledge clocked into slave k = acknowledge clock pulse l = stop condition m = new start condition figure 5. smbus write timing diagram write byte format read byte format send byte format receive byte format slave address: equiva- lent to chip-select line of a 3-wire interface command byte: selects to which register you are writing slave address: equivalent to chip-select line command byte: selects from which register you are reading slave address: repeated due to change in data- flow direction data byte: reads from the register set by the command byte command byte: sends com- mand with no data, usually used for one-shot command data byte: reads data from the register commanded by the last read byte or write byte transmission; also used for smbus alert response return address s = start condition shaded = slave transmission p = stop condition /// = not acknowledged figure 4. i 2 c interface data structure s address rd ack data /// p 7 bits 8 bits wr s ack command ack p 8 bits address 7 bits p 1 ack data 8 bits ack command 8 bits ack s address wr ack command ack s address 7 bits 8 bits 7 bits rd ack data 8 bits /// p data byte: data goes into the register set by the command byte (to set thresholds, configuration masks, and sampling rate) wr address 7 bits s
MAX9450/max9451/max9452 high-precision clock generators with integrated vcxo 12 ______________________________________________________________________________________ smbclk ab cd e fg h i j k smbdata t su:sta t hd:sta t low t high t su:dat t hd:dat t su:sto t buf a = start condition b = msb of address clocked into slave c = lsb of address clocked into slave d = r/w bit clocked into slave e = slave pulls smbdata line low l m f = acknowledge bit clocked into master g = msb of data clocked into master h = lsb of data clocked into master i = master pulls data line low j = acknowledge clocked into slave k = acknowledge clock pulse l = stop condition m = new start condition figure 6. smbus read timing diagram t css t csh f scl t csw cs sclk din t ds t ds d0 d1 d14 d15 figure 7. spi write operation timing diagram slk sda d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 register address register data cs figure 8. spi register address and data configuration function setting tables spi interface the spi interface is activated when ad0 = ad1 = high. the spi port is a write-only interface, and it uses the three inputs: cs , scl, and sda. bit d15 is always zero, indicating the write-only mode, as shown in figure 5. d14?8 are the register address bits and d7?0 are the data bits. in table 4, the register address mapping is still valid, except the first address bit on the left is not used. d14 is the msb of the address, and d7 is the msb of the data. d15?0 are sent with msb (d15) first. the maximum scl frequency is 2mhz. to perform a write, set d15 = 0, drive cs low, toggle scl to latch sda data on the rising edge, then drive cs high after 16 scl cycles for two scl cycles to sig- nal the boundary of a 16-bit word (figure 5). scl must be low when cs falls at the start of a transmission. switching of scl and sda is ignored unless cs is low. figure 7 shows the spi write operation timing diagram and figure 8 shows spi register address and data con- figuration function setting tables.
MAX9450/max9451/max9452 high-precision clock generators with integrated vcxo ______________________________________________________________________________________ 13 ad0 ad1 address low low 1101000 low open 1101001 low high 1101010 open low 1101011 open open 1101100 open high 1101101 high low 1101110 high open 1101111 high high convert to spi table 3. i 2 c address setting by ad0 and ad1 register name register address function cr0 00000000 p divider cr1 00000001 m divider byte 1 cr2 00000010 m divider byte 2 cr3 00000011 n1 divider cr4 00000100 n2 divider cr5 00000101 control cr6 00000110 control cr7 00000111 status cr8 00001000 reserved table 4. i 2 c and spi register address* cr0 dividing rate for p 0000-0000 1 0000-0001 2 1111-1110 255 1111-1111 256 table 5. dividing rate setting for p divider cr1 cr2[7:1]* dividing value of m 0000-0000 0000-000 1 0000-0000 0000-001 2 1111-1111 0011-110 8191 1111-1111 0011-111 8192 1111-1111 1111-111 32,768 table 6. dividing rate setting for m divider * when the spi port is activated, the first address bit on the left is omitted and the remaining 7 bits are used. the lsb is the first bit on the right. * the last 5 lsbs of cr3[4:0] and cr4[4:0] are reserved. * cr2[0], the last lsb, is reserved. cr3* dividing value of n0 cr4* dividing value of n1 000xxxxx 1 000xxxxx 1 001xxxxx 2 001xxxxx 2 010xxxxx 3 010xxxxx 3 011xxxxx 4 011xxxxx 4 100xxxxx 5 100xxxxx 5 101xxxxx 6 101xxxxx 6 110xxxxx 8 110xxxxx 8 111xxxxx 16 111xxxxx 16 table 7. dividing rate setting for n0 and n1 divider
MAX9450/max9451/max9452 high-precision clock generators with integrated vcxo 14 ______________________________________________________________________________________ register action default cr0 p = 1 00000000 cr1 m = 1 00000000 cr2 m = 1 00000000 cr3 n0 = 1 00000000 cr4 n1 = 1 00000000 cr5, cr6 1. outputs enable 2. in0 is the default input 3. both inputs are enabled by sel0 and sel1 4. monitor is nonrevertive 5. holdover is disabled cr5: 01100000 cr6: 00000000 cr7 status 00000000 cr8 reserved 00000000 table 10. register default values at power-up cr5, cr6 function state cr5[7] output disable 0: outputs are enabled 1: outputs disabled to logic-low cr5[6] clk0 enabling 0: clk0 is disabled to high impedance (overrides cr5[7] = 1 setting) 1: clk0 is enabled cr5[5] clk1 enabling 0: clk1 is disabled to high impedance (overrides cr5[7] = 1 setting) 1: clk1 is enabled cr5[4] default input setting 0: in0 is the default input 1: in1 is the default input cr5[3:2] input enabling 00: the selection is controlled by sel0, sel1 (see table 2) 01: enable in0, disable in1 10: enable in1, disable in0 11: enable both in0 and in1 cr5[1] revert function 0: the function is not activated 1: the function is activated cr5[0] clk monitor reset c lk m oni tor i s r eset i n r ever t m od e: in t = 0 and c r7[ 7] = 0, and the p ll sw i tches to the d efaul t i np ut cr6[7] holdover function enabling 0: holdover function is disabled 1: holdover function is enabled cr6[6] forced holdover 0: holdover is in normal mode 1: holdover is forced to be activated as the bit goes from 0 to 1, the current vcxo frequency is taken as the nominal value cr6[5] acquiring nominal vcxo frequency as this bit is toggling from 0 to 1, the current vcxo frequency is taking as the nominal holdover value cr6[4] master reset the bit acts at the same as the input mr; cr6[4] = 1, the chip is reset cr6[3] ref this bit is always set to zero cr6[2] odiv select cr6[2] = 0: div0 output drives clk2 cr6[2] = 1: div1 output drives clk2 cr6[1] acquire select cr6[1] = 0 pll controls the xtal frequency cr6[1] = 1 xtal frequency is controlled by the acquired value (acquired at rising edge of cr6[5]) cr6[0] reserved ? table 8. control registers and control functions cr7 function state cr7[6] status of in0 cr7[5] status of in1 0: normal 1: failure detected cr7[4] input clock selection indicator 0: in0 is currently used 1: in1 is currently used cr7[3] lock indicator 1: pll not locked 0: pll locked cr7[2] holdover status 1: device is in holdover state 0: device is in normal state cr7[1:0] reserved ? table 9. mapping for the input monitor status
MAX9450/max9451/max9452 high-precision clock generators with integrated vcxo ______________________________________________________________________________________ 15 applications information crystal selection the MAX9450/max9451/max9452 internal vcxo cir- cuitry requires an external crystal. the frequency of the crystal ranges from 15mhz to 160mhz, depending on the application. it is important to use a quartz crystal that prevents reduction of the frequency pulling range, temperature stability, or excessive output phase jitter. choose an at-cut crystal that oscillates at the required frequency on its fundamental mode with a variation of 25ppm, including frequency accuracy and operating temperature range. select a crystal with a load capaci- tance of 8pf and a motional capacitance of at least 7ff to achieve the specified pulling range. crystals from manufacturers kds (www.kdsj.co.jp) and 4timing (www.4timing.com) are recommended. lvds cables and connectors the interconnect for lvds typically has a 100 ? differ- ential impedance. use cables and connectors that have matched differential impedance to minimize impedance discontinuities. twisted-pair and shielded twisted-pair cables offer superior signal quality compared to ribbon cable and tend to generate less emi due to magnetic-field-cancel- ing effects. power-supply bypassing bypass v dda , v dd , and v ddq to ground with high-fre- quency, surface-mount ceramic 0.1? and 0.01? capacitors. place the capacitors as close as possible to the device with the 0.01? capacitor closest to the device pins. board layout circuit-board trace layout is very important to maintain the signal integrity of high-speed differential signals. maintaining integrity is accomplished in part by reduc- ing signal reflections and skew and increasing com- mon-mode noise immunity. signal reflections are caused by discontinuities in the 50 ? (100 ? for lvds outputs) characteristic impedance of the traces. avoid discontinuities by maintaining the distance between differential traces, not using sharp corners or vias. ensure the two traces are parallel and close to each other to increase common-mode noise immunity and reduce emi. matching the electrical length of the differential traces further reduces signal skew. output termination terminate the MAX9450 outputs with 50 ? to v cc - 2v or use an equivalent thevenin termination. when a sin- gle-ended signal is taken from a differential output, ter- minate both outputs. the max9452 outputs are specified for a 100 ? load, but can drive 90 ? to 132 ? to accommodate various types of interconnects. the termination resistor at the driven receiver should match the differential character- istic impedance of the interconnect and be located close to the receiver input. use a ?% surface-mount termination resistor. chip information process: cmos resistor (k ? ) current (a) 12 200.5 20 121.88 50 49.41 100 24.86 150 16.61 200 12.48 table 11. resistor value vs. charge-pump current
MAX9450/max9451/max9452 high-precision clock generators with integrated vcxo 16 ______________________________________________________________________________________ package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) 32l,tqfp.eps f 1 2 21-0079 package outline, 32l tqfp, 5x5x1.0mm, ep option
MAX9450/max9451/max9452 high-precision clock generators with integrated vcxo maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 17 2006 maxim integrated products is a registered trademark of maxim integrated products, inc. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) f 2 2 21-0079 package outline, 32l tqfp, 5x5x1.0mm, ep option revision history pages changed at rev 2: 1?, 7?0, 12, 15, 16

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