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1 of 10 102902 features 2mbits organized as a 64k x 40 memory 6 years minimum data retention in the absence of external power nonvolatile circuitry transparent to and independent of host system automatic write protection circuitry safeguards against data loss battery monitor checks remaining capacity daily fast access time of 70ns operating v cc range of 3.0v to 3.6v employs popular jedec standard 72- position simm connector operating temperature: 0 o c to +70 o c pin description a0 - a15 - address inputs dq0 ? dq39 - data inputs/outputs cea\ - chip enable inputs we\ - write enable inputs oe\ - output enable inputs vcc - 3.3v power supply gnd - ground pin assignment ds38464 72-pin simm ds38464 3.3v 64k x 40 nv sram simm www.maxim-ic.com
ds38464 2 of 10 description the ds38464 is a self-contained 2,621,440-bit, nonvolatile st atic ram, which is organized as a 64k x 40 memory. built using three 64k x 16 srams, one nonvolatile control ic, and one lithium battery, this nonvolatile memory contains all the necessary control circu itry and lithium energy source to maintain data integrity in the absence of power for more than 6 years. the ds38464 employs the popular jedec standard 72-position simm connection scheme and re quires no additional circuitry. read mode the ds38464 executes a read cycle wh enever we\ is inactive (high) and ce\ and oe\ are active (low). the unique address specified by the 16 address inputs (a 0 - a 15 ) defines which byte of data is to be accessed from the selected srams. valid data will be ava ilable to the data output drivers within t acc (access time) after the last address input signal is stable, providing that ce\ and oe\ access times are also satisfied. if oe\ and ce\ access times are not sa tisfied, then data access must be measured from the later occurring signal (ce\ or oe\) and the limiting parameter is either t co for ce\ or t oe for oe\ rather than t acc . write mode the ds38464 executes a write cycle whenever both we\ and ce\ signals are in the active (low) state after address inputs are stable. th e later occurring falling edge of ce \ or we\ will determine the start of the write cycle. the write cycle is terminated by the earlier rising edge of ce\ or we\. all address inputs must be kept valid throughout the write cycle. we\ must return to the high state for a minimum recovery time (t wr ) before another cycle can be initiated. the oe\ control signal should be kept inactive (high) during write cycles to avoid bus contention. however, if the output drivers are enabled (ce\ and oe\ active) then we\ will disable the outputs in t odw from its falling edge. data retention mode the ds38464 provides full functional capability for v cc greater than 3.0 volts and write protects by 2.8 volts. data is maintained in the absence of v cc without any additional support circuitry. the nonvolatile static ram c onstantly monitors v cc . should the supply voltage decay, the nv sram automatically write protects itsel f, all inputs become ?don?t care ,? and all outputs become high impedance. as v cc falls below approximately 2.5 volts, power switching circuits connect the lithium energy sources to the rams to reta in data. during power-up, when v cc rises above a pproximately 2.5 volts, the power switching circuits connect external v cc to the rams and disconnects the lithium energy source. normal ram operation can resume after v cc exceeds 3.0 volts. battery monitoring the ds38464 automatically performs periodic battery voltage monitoring on a 24 hour time interval. such monitoring begins within t rec after v cc rises about v tp and is suspended when power failure occurs. after each 24 hour period has elapsed, the ba ttery is connected to an internal 1m test resistor for one second. during this one second, if ba ttery voltage falls below the battery voltage trip point (2.6v), the battery warning output bw\ is asserted. once asserted, bw\ remains active until the simm is replaced. the battery is still retested after each v cc power-up, even if bw\ is active. if the battery voltage is found to be higher than 2.6v during such testing, bw\ is de-asserted a nd regular 24-hour testing resumes. bw\ has an open drain output driver.
ds38464 3 of 10 pin assignment pin signal name pin signal name pin signal name 1 nc 25 a15 49 a11 2 dq0 26 a1 50 v ss 3 dq1 27 a2 51 nc 4 dq2 28 a3 52 a12 5 dq3 29 a4 53 a13 6 dq4 30 a5 54 a14 7 dq5 31 a6 55 dq24 8 dq6 32 a7 56 dq25 9 dq7 33 dq16 57 dq26 10 bw\ 34 v cc 58 dq27 11 cea\ 35 dq17 59 dq28 12 oe\ 36 dq18 60 dq29 13 we\ 37 v ss 61 dq30 14 dq8 38 dq19 62 dq31 15 dq9 39 dq20 63 dq32 16 dq10 40 dq21 64 dq33 17 dq11 41 dq22 65 dq34 18 dq12 42 dq23 66 dq35 19 dq13 43 nc 67 v cc 20 dq14 44 a8 68 dq36 21 dq15 45 a9 69 dq37 22 v cc 46 v cc 70 dq38 23 a0 47 v ss 71 dq39 24 v ss 48 a10 72 v ss
ds38464 4 of 10 block diagram ds1314s-2 v bat v cco ceo bw v cci v cc a0-a15 a0-18 a0-a15 a0-15 we oe we oe we oe we oe ce ce ce bw cei cea 64k x 16 sram 64k x 16 sram 64k x 16 sram v cc v cc v cc dqo-dq7 dq24-dq31 dq32-dq39 br1632 dq16-dq23 dq8-dq15
ds38464 5 of 10 absolute maximum ratings* voltage on any pin relative to ground -0.3 to +4.6v operating temperature 0 c to 70 c storage temperature -40 c to +85 c *this is a stress rating only and f unctional operation of the device at these or any other conditions above those indicated in the operation s ections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (t a = 0 to 70 c) parameter symbol min typ max units notes power supply voltage v cc 3.0 3.3 3.6 v logic 1 input voltage v ih 2.2 v cc v logic 0 input voltage v il 0.0 +0.4 v dc electrical characteristics (t a = 0 to 70 c; v cc = 3.3v 0.3v) parameter symbol test conditions min typ max units input leakage current i il 0v < v in < v cc -4 +4 a output leakage current i lo 0v < v out < v cc , all ce \ = v ih -1 +1 a operating current i cco duty=100% all ce\ = v il , i i/o =0, v in =v ih or v il 300 ma standby current i ccs all ce\ = v ih 1ma output high current i oh v oh = 2.4v -1.0 ma output low current i ol v ol = 0.4v 2.1 ma write protection voltage v tp 2.8 2.9 3.0 v capacitance (t a = 25 c) parameter symbol min typ max units notes input capacitance c in 24 pf output capacitance c i/o 10 pf
ds38464 6 of 10 ac electrical characteristics (t a = 0 to 70 c; v cc = 3.3v 0.3v) parameter symbol min typ max units notes read cycle time t rc 70 ns access time t acc 70 ns oe to output valid t oe 35 ns ce to output valid t co 70 ns oe or ce to output active t coe 5ns5 deselection to output high-z t od 25 ns 5 output hold after address change t oh 5ns write cycle time t wc 70 ns write pulse width t wp 55 ns 3 address setup time t aw 0ns write recovery time t wr1 t wr2 5 20 ns ns 11 12 we active to output high-z t odw 25 ns 5 we inactive to output active t oew 5ns5 data setup time t ds 30 ns 4 data hold time t dh1 t dh2 0 20 ns ns 11 12 timing diagram: read cycle see note 1 t rc address t acc ce oe d out t oh t co t oe t coe t coe t od t od data valid
ds38464 7 of 10 timing diagram: write cycle 1 (we\ controlled) see notes 2, 3, 4, 6, 7, 8 and 11 timing diagram: write cycle 2 (ce\ controlled) see notes 2, 3, 4, 6, 7 8 and 12 t wc t wr1 t aw t oew t ds data valid t oh t dh1 t odw t wp address ce\ we\ d in d out data valid t wc t wr2 t aw t ds t dh2 t coe t odw t wp address ce\ we\ d out d in
ds38464 8 of 10 timing diagram: powe r-down and power-up see note 10 power-down/power-up timing (t a = 0 to 70 c) parameter symbol min typ max units notes v cc fail detect to ce\ and we\ inactive t pd 1.5 s 10 v cc slew from v tp to 0v t f 150 s v cc slew from 0v to v tp t r 150 s v cc valid to ce\ and we\ inactive t pu 2ms v cc valid to end of write protection t rec 125 ms (t a = 25 c) parameter symbol min typ max units notes expected data retention time t dr 6 years 9 warning under no circumstances are negativ e undershoots, of any amplitude, a llowed when device is in battery backup mode. v cc v tp ~2.7v t f t r t rec t pd t pu t dr ce\, we\ backup current supplied from lithium battery
ds38464 9 of 10 notes 1. we\ is high throughout read cycle. 2. oe\ = v ih or v il . if oe\ = v ih during write cycle, the output buffers remain in a high impedance state. 3. t wp is specified as the logical and of ce\ and we\. t wp is measured from the latter of ce\ or we\ going low to the earlier of ce\ or we\ going high. 4. t ds is measured from the earlier of ce\ or we\ going high. 5. these parameters are sampled with a 5 pf load and are not 100% tested. 6. if the ce\ low transition occurs simultaneously w ith or later than the we\ low transition, the output buffers remain in a high imp edance state during this period. 7. if the ce\ high transition occurs prior to or s imultaneously with the we\ high transition, the output buffers remain in a high imp edance state during this period. 8. if we\ is low or the we\ low transition occurs prior to or simultaneously with the ce\ low transition, the output buffers remain in a high impedance state during this period. 9. each ds38464 has a built-in switch that disconnects the lithium source until v cc is first applied by the user. the expected t dr is defined as accumulative time in the absence of v cc starting from the time power is first applied by the user. 10. in a power down condition the voltage on any pin may not exceed the voltage on v cc . 11. t wr1 , t dh1 are measured from we\ going high. 12. t wr2 , t dh2 are measured from ce\ going high. 13. bw\ is an open-drain output and cannot source current. dc test conditions ac test conditions outputs open output load: 50 pf + 1 ttl gate cycle = 200 ns input pulse levels: 0 v to 2.7 v all voltages are referenced to ground timing measurement reference levels input: 1.5 v output: 1.5 v input pulse rise and fall times: 5 ns
ds38464 10 of 10 ds38464 72-pin simm module pkg inches dim min max a 4.245 4.255 b 3.979 3.989 c 0.845 0.855 d 0.395 0.405 e 0.245 0.255 f 0.050 bsc g 0.075 0.085 h 0.245 0.255 i 1.750 bsc j 0.120 0.130 k 2.120 2.130 l 2.245 2.255 m 0.057 0.067 n 0.130 o 0.047 0.054 c n o battery + nv controller side + srams d e a b h 172 j m i k l f g i
e nglish ? ???? ? ??? ? ??? what's ne w p roducts solutions de sign ap p note s sup p ort buy comp any me mbe rs ds38464 part number table notes: see the ds38464 quickview data sheet for further information on this product family or download the ds38464 full data sheet (pdf, 192kb). 1. other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales . 2. didn't find what you need? ask our applications engineers. expert assistance in finding parts, usually within one business day. 3. part number suffixes: t or t&r = tape and reel; + = rohs/lead-free; # = rohs/lead-exempt. more: see full data sheet or part naming c onventions . 4. * some packages have variations, listed on the drawing. "pkgc ode/variation" tells which variation the product uses. 5. part number notes free sample buy direct package: type pins size drawing code/var * temp rohs/lead-free? materials analysis DS38464-070 3.3v, 70ns module 0c to +70c rohs/lead-free: no didn't find what you need? c ontac t us: send us an email c opyright 2 0 0 7 by m axim i ntegrated p roduc ts , dallas semic onduc tor ? legal n otic es ? p rivac y p olic y

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