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83021ami www.icst.com/products/hiperclocks.html rev. c december 12, 2005 1 integrated circuit systems, inc. ics83021i 1- to -1 2.5v, 3.3v d ifferential - to -lvcmos/lvttl t ranslator g eneral d escription the ics83021i is a 1-to-1 d ifferential-to- lvcmos/lvttl translator and a member of the hiperclocks? family of high perfor- mance clock solutions from ics. the differ- ential input is highly flexible and can accept the following input types: lvpecl, lvds, lvhstl, sstl, and hcsl. the small 8-lead soic footprint makes this device ideal for use in applications with limited board space. f eatures ? one lvcmos / lvttl output ? differential clk, nclk input pair ? clk, nclk pair can accept the following differential input levels: lvpecl, lvds, lvhstl, hcsl, sstl ? maximum output frequency: 350mhz (typical) ? part-to-part skew: 500ps (maximum) ? additive phase jitter, rms: 0.21ps (typical), 3.3v output ? small 8 lead soic package saves board space ? full 3.3v, 2.5v operating supply ? -40c to 85c ambient operating temperature ? available in both standard and lead-free rohs-compliant packages b lock d iagram p in a ssignment ics83021i 8-lead soic 3.8mm x 4.8mm, x 1.47mm package body m package top view nc clk nclk nc 1 2 3 4 q0 clk nclk hiperclocks? ic s v dd q0 nc gnd 8 7 6 5
83021ami www.icst.com/products/hiperclocks.html rev. c december 12, 2005 2 integrated circuit systems, inc. ics83021i 1- to -1 2.5v 3.3v d ifferential - to -lvcmos/lvttl t ranslator t able 1. p in d escriptions t able 2. p in c haracteristics l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p c d p e c n a t i c a p a c n o i t a p i s s i d r e w o p ) t u p t u o r e p ( v d d v 6 . 3 =3 2f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k r t u o e c n a d e p m i t u p t u o572 1 r e b m u ne m a ne p y tn o i t p i r c s e d 6 , 4 , 1c nd e s u n u. t c e n n o c o n 2k l ct u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 3k l c nt u p n ip u l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i 5d n gr e w o p. d n u o r g y l p p u s r e w o p 70 qt u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l . t u p t u o k c o l c e l g n i s 8v d d r e w o p. n i p y l p p u s e v i t i s o p : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r
83021ami www.icst.com/products/hiperclocks.html rev. c december 12, 2005 3 integrated circuit systems, inc. ics83021i 1- to -1 2.5v, 3.3v d ifferential - to -lvcmos/lvttl t ranslator t able 3a. p ower s upply dc c haracteristics , v dd = 3.3v0.3v or 2.5v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d d e g a t l o v y l p p u s e v i t i s o p 0 . 33 . 36 . 3v 5 7 3 . 25 . 25 2 6 . 2v i d d t n e r r u c y l p p u s r e w o p 0 2a m t able 3bc. lvcmos / lvttl dc c haracteristics , v dd = 3.3v0.3v or 2.5v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h o 1 e t o n ; e g a t l o v h g i h t u p t u o v d d v 6 . 3 =6 . 2v v d d v 5 2 6 . 2 =8 . 1v v l o 1 e t o n ; e g a t l o v w o l t u p t u o 5 . 0v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n v o t d d t i u c r i c t s e t d a o l t u p t u o , n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p e e s . 2 / . s m a r g a i d t able 3c. d ifferential dc c haracteristics , v dd = 3.3v0.3v or 2.5v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i h i t n e r r u c h g i h t u p n i k l c nv n i v = d d v 5 2 6 . 2 r o v 6 . 3 =5a k l cv n i v = d d v 5 2 6 . 2 r o v 6 . 3 =0 5 1a i l i t n e r r u c w o l t u p n i k l c nv n i v , v 0 = d d v 5 2 6 . 2 r o v 6 . 3 =0 5 1 -a k l cv n i v , v 0 = d d v 5 2 6 . 2 r o v 6 . 3 =5 -a v p p e g a t l o v t u p n i k a e p - o t - k a e p 5 1 . 03 . 1v v r m c ; e g a t l o v t u p n i e d o m n o m m o c 2 , 1 e t o n 5 . 0 + d n gv d d 5 8 . 0 -v s n o i t a c i l p p a d e d n e e l g n i s r o f : 1 e t o n , v s i k l c n , k l c r o f e g a t l o v t u p n i m u m i x a m e h t d d . v 3 . 0 + s i e g a t l o v e d o m n o m m o c : 2 e t o nv s a d e n i f e d h i . a bsolute m aximum r atings supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5 v outputs, v o -0.5v to v dd + 0.5v package thermal impedance, ja 112.7c/w (0 lfpm) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions be- yond those listed in the dc characteristics or ac character- istics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability.
83021ami www.icst.com/products/hiperclocks.html rev. c december 12, 2005 4 integrated circuit systems, inc. ics83021i 1- to -1 2.5v 3.3v d ifferential - to -lvcmos/lvttl t ranslator t able 4a. ac c haracteristics , v dd = 3.3v0.3v, t a = -40c to 85c t able 4b. ac c haracteristics , v dd = 2.5v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o 0 5 3z h m t d p 1 e t o n , y a l e d n o i t a g a p o r p? z h m 0 5 37 . 10 . 23 . 2s n t ) p p ( k s3 , 2 e t o n ; w e k s t r a p - o t - t r a p 0 0 5s p t t i j ; s m r , r e t t i j e s a h p e v i t i d d a r e f f u b n o i t c e s r e t t i j e s a h p e v i t i d d a o t r e f e r e g n a r n o i t a r g e t n i , z h m 0 0 1 ) z h m 0 1 - z h k 7 3 6 ( 1 2 . 0s p t r t / f e m i t l l a f / e s i r t u p t u ov 2 o t v 8 . 00 0 10 5 20 0 4s p c d oe l c y c y t u d t u p t u o ? z h m 6 6 15 40 55 5% ? < z h m 6 6 1 z h m 0 5 30 40 50 6% f t a d e r u s a e m s r e t e m a r a p l l a x a m . e s i w r e h t o d e t o n s s e l n u v t a t u p t u o e h t o t t n i o p g n i s s o r c t u p n i l a i t n e r e f f i d e h t m o r f d e r u s a e m : 1 e t o n d d . 2 / s e g a t l o v y l p p u s e m a s e h t t a g n i t a r e p o s e c i v e d t n e r e f f i d n o s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n v t a d e r u s a e m e r a s t u p t u o e h t , e c i v e d h c a e n o s t u p n i f o e p y t e m a s e h t g n i s u . s n o i t i d n o c d a o l l a u q e h t i w d n a d d . 2 / . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 3 e t o n l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o 0 5 3z h m t d p 1 e t o n , y a l e d n o i t a g a p o r p? z h m 0 5 39 . 12 . 25 . 2s n t ) p p ( k s3 , 2 e t o n ; w e k s t r a p - o t - t r a p 0 0 5s p t t i j ; s m r , r e t t i j e s a h p e v i t i d d a r e f f u b n o i t c e s r e t t i j e s a h p e v i t i d d a o t r e f e r e g n a r n o i t a r g e t n i , z h m 0 0 1 ) z h m 0 1 - z h k 7 3 6 ( 1 2 . 0s p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 5 20 5 5s p c d oe l c y c y t u d t u p t u o ? z h m 0 5 25 40 55 5% ? < z h m 0 5 2 z h m 0 5 30 40 50 6% f t a d e r u s a e m s r e t e m a r a p l l a x a m . e s i w r e h t o d e t o n s s e l n u v t a t u p t u o e h t o t t n i o p g n i s s o r c t u p n i l a i t n e r e f f i d e h t m o r f d e r u s a e m : 1 e t o n d d . 2 / s e g a t l o v y l p p u s e m a s e h t t a g n i t a r e p o s e c i v e d t n e r e f f i d n o s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n v t a d e r u s a e m e r a s t u p t u o e h t , e c i v e d h c a e n o s t u p n i f o e p y t e m a s e h t g n i s u . s n o i t i d n o c d a o l l a u q e h t i w d n a d d . 2 / . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 3 e t o n
83021ami www.icst.com/products/hiperclocks.html rev. c december 12, 2005 5 integrated circuit systems, inc. ics83021i 1- to -1 2.5v, 3.3v d ifferential - to -lvcmos/lvttl t ranslator a dditive p hase j itter additive phase jitter @ 100mhz (12khz to 20mhz) = 0.21ps typical 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1m 10m 100m the spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundamental frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a as with most timing specifications, phase noise measure- ments have issues. the primary issue relates to the limita- tions of the equipment. often the noise floor of the equipment is higher than the noise floor of the device. this is illustrated ratio of the power in the 1hz band to the power in the funda- mental. when the required offset is specified, the phase noise is called a dbc value, which simply means dbm at a specified offset from the fundamental. by investigating jitter in the fre- quency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. above. the device meets the noise floor of what is shown, but can actually be lower. the phase noise is dependant on the input source and measurement equipment. o ffset f rom c arrier f requency (h z ) ssb p hase n oise dbc/h z
83021ami www.icst.com/products/hiperclocks.html rev. c december 12, 2005 6 integrated circuit systems, inc. ics83021i 1- to -1 2.5v 3.3v d ifferential - to -lvcmos/lvttl t ranslator p arameter m easurement i nformation 3.3v o utput r ise /f all t ime p ropagation d elay clock outputs 0.8v 2v 2v 0.8v t r t f d ifferential i nput l evel p art - to -p art s kew 3.3v o utput l oad ac t est c ircuit scope qx lvcmos v cmr cross points v pp gnd clk nclk v dd t sk(pp) v dd 2 v dd 2 qx qy part 1 part 2 nclk clk q0 t pd v dd 2 -1.65v 0.15v 1.65v 0.15v o utput d uty c ycle /p ulse w idth /p eriod t period t pw t period odc = v dd 2 x 100% t pw q0 gnd clock outputs 20% 80% 80% 20% t r t f 2.5v o utput l oad ac t est c ircuit 2.5v o utput r ise /f all t ime v dd scope qx lvcmos -1.25v 5% 1.25v 5% gnd v dd
83021ami www.icst.com/products/hiperclocks.html rev. c december 12, 2005 7 integrated circuit systems, inc. ics83021i 1- to -1 2.5v, 3.3v d ifferential - to -lvcmos/lvttl t ranslator a pplication i nformation figure 1 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v dd /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio f igure 1. s ingle e nded s ignal d riving d ifferential i nput w iring the d ifferential i nput to a ccept s ingle e nded l evels of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v dd = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. v_ref r1 1k c1 0.1u r2 1k single ended clock input clk nclk vdd
83021ami www.icst.com/products/hiperclocks.html rev. c december 12, 2005 8 integrated circuit systems, inc. ics83021i 1- to -1 2.5v 3.3v d ifferential - to -lvcmos/lvttl t ranslator f igure 2c. h i p er c lock s clk/nclk i nput d riven by 3.3v lvpecl d river f igure 2b. h i p er c lock s clk/nclk i nput d riven by 3.3v lvpecl d river f igure 2d. h i p er c lock s clk/nclk i nput d riven by 3.3v lvds d river 3.3v r1 50 r3 50 zo = 50 ohm lvpecl zo = 50 ohm hiperclocks clk nclk 3.3v input r2 50 zo = 50 ohm input hiperclocks clk nclk 3.3v r3 125 r2 84 zo = 50 ohm 3.3v r4 125 lvpecl r1 84 3.3v d ifferential c lock i nput i nterface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 2a to 2e show inter- face examples for the hiperclocks clk/nclk input driven by the most common driver types. the input interfaces suggested f igure 2a. h i p er c lock s clk/nclk i nput d riven by ics h i p er c lock s lvhstl d river here are examples only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example in figure 2a, the input termination applies for ics hiperclocks lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. 1.8v r2 50 input lvhstl driver ics hiperclocks r1 50 lvhstl 3.3v zo = 50 ohm zo = 50 ohm hiperclocks clk nclk f igure 2e. h i p er c lock s clk/ n clk i nput d riven by 3.3v lvpecl d river with ac c ouple zo = 50 ohm r3 125 hiperclocks clk nclk 3.3v r5 100 - 200 3.3v r2 84 3.3v r6 100 - 200 input r5,r6 locate near the driver pin. zo = 50 ohm r1 84 r4 125 c2 lvpecl c1 zo = 50 ohm r1 100 3.3v lvds_driv er zo = 50 ohm receiv er clk nclk 3.3v
83021ami www.icst.com/products/hiperclocks.html rev. c december 12, 2005 9 integrated circuit systems, inc. ics83021i 1- to -1 2.5v, 3.3v d ifferential - to -lvcmos/lvttl t ranslator t ransistor c ount the transistor count for ics83021i is: 416 pin-to-pin compatible with mc100ept21 t able 5. ja vs . a ir f low t able for 8 l ead soic ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 153.3c/w 128.5c/w 115.5c/w multi-layer pcb, jedec standard test boards 112.7c/w 103.3c/w 97.1c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. r eliability i nformation
83021ami www.icst.com/products/hiperclocks.html rev. c december 12, 2005 10 integrated circuit systems, inc. ics83021i 1- to -1 2.5v 3.3v d ifferential - to -lvcmos/lvttl t ranslator t able 6. p ackage d imensions reference document: jedec publication 95, ms-012 p ackage o utline - s uffix m for 8 l ead soic l o b m y s s r e t e m i l l i m m u m i n i mm u m i x a m n8 a5 3 . 15 7 . 1 1 a0 1 . 05 2 . 0 b3 3 . 01 5 . 0 c9 1 . 05 2 . 0 d0 8 . 40 0 . 5 e0 8 . 30 0 . 4 ec i s a b 7 2 . 1 h0 8 . 50 2 . 6 h5 2 . 00 5 . 0 l0 4 . 07 2 . 1 0 8
83021ami www.icst.com/products/hiperclocks.html rev. c december 12, 2005 11 integrated circuit systems, inc. ics83021i 1- to -1 2.5v, 3.3v d ifferential - to -lvcmos/lvttl t ranslator t able 7. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorpor ated (ics) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patent s, or licenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability or other extr aordinary environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without noti ce. ics does not authorize or warrant any ics product for use in life support devices or critical medical instruments. the aforementioned trademark, hiperclocks is a trademark of integrated circuit systems, inc. or its subsidiaries in the united states and/or other countries. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t i m a 1 2 0 3 8 s c ii m a 1 2 0 3 8c i o s d a e l 8e b u tc 5 8 o t c 0 4 - t i m a 1 2 0 3 8 s c ii m a 1 2 0 3 8c i o s d a e l 8l e e r & e p a t 0 0 5 2c 5 8 o t c 0 4 - f l i m a 1 2 0 3 8 s c il i a 1 2 0 3 8c i o s " e e r f - d a e l " d a e l 8e b u tc 5 8 o t c 0 4 - t f l i m a 1 2 0 3 8 s c il i a 1 2 0 3 8c i o s " e e r f - d a e l " d a e l 8l e e r & e p a t 0 0 5 2c 5 8 o t c 0 4 - . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n
83021ami www.icst.com/products/hiperclocks.html rev. c december 12, 2005 12 integrated circuit systems, inc. ics83021i 1- to -1 2.5v 3.3v d ifferential - to -lvcmos/lvttl t ranslator t e e h s y r o t s i h n o i s i v e r v e re l b a te g a pe g n a h c f o n o i t p i r c s e de t a d b 2 t b 3 t c 3 t d 3 t b 4 t 2 3 3 3 4 5 6 7 c v 5 . 2 d e d d a - e l b a t s c i t s i r e t c a r a h c n i p d p . . e l b a t y l p p u s r e w o p v 5 . 2 d e d d a v v 5 . 2 d e d d a - e l b a t s o m c v l h o . . v 5 . 2 d e d d a - e l b a t l a i t n e r e f f i d . e l b a t s c i t s i r e t c a r a h c c a v 5 . 2 d e d d a l l a f / e s i r t u p t u o v 5 . 2 d n a m a r g a i d t i u c r i c t s e t c a d a o l t u p t u o v 5 . 2 d e d d a . s m a r g a i d e m i t . 1 e r u g i f d e t a d p u . n o i t c e s e c a f r e t n i t u p n i k c o l c l a i t n e r e f f i d d e d d a 4 0 / 3 / 6 b a 4 t 2 4 c d e g n a h c - e l b a t s c i t s i r e t c a r a h c n i p n i . l a c i p y t f p 4 o t . x a m f p 4 . s n o i t i d n o c t s e t c d o d e g n a h c - e l b a t s c i t s i r e t c a r a h c c a v 3 . 3 4 0 / 0 3 / 6 b 7 t 1 0 1 . t e l l u b e e r f - d a e l d e d d a - n o i t c e s s e r u t a e f . r e b m u n t r a p e e r f - d a e l d e d d a - e l b a t n o i t a m r o f n i g n i r e d r o 5 0 / 1 2 / 3 c b 4 t , a 4 t 7 t 1 4 5 1 1 . t e l l u b r e t t i j e s a h p e v i t i d d a d e d d a - n o i t c e s s e r u t a e f . w o r r e t t i j e s a h p e v i t i d d a d e d d a - s e l b a t s c i t s i r e t c a r a h c c a . t o l p r e t t i j e s a h p e v i t i d d a d e d d a . e t o n e e r f - d a e l d e d d a 5 0 / 2 1 / 2 1

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