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d a t a sh eet preliminary speci?cation supersedes data of 2000 dec 22 file under integrated circuits, ic02 2001 may 29 integrated circuits TDA9991HL vertical line driver and dc-dc converter for full frame and frame transfer ccd image sensors www.datasheet.co.kr datasheet pdf - http://www..net/
2001 may 29 2 philips semiconductors preliminary speci?cation vertical line driver and dc-dc converter for full frame and frame transfer ccd image sensors TDA9991HL features enables compact and cost effective camera design eight two-level low-ohmic line drivers suitable for philips full frame (ff) and frame transfer (ft) ccd image sensors versatile programmable dc-dc converters and voltage regulators to create all required low-noise supply voltages for the philips ft ccd sensor family and for the on-chip drivers dc-dc converter can be operated with an on-chip free running oscillator or with an external clock wide supply range also suitable for direct use on batteries electronic shutter driver (charge reset) fast start-up dc ready signal available indicating the TDA9991HL has started up 3-wire serial bus separate digital supply voltage for optimal interfacing with dsp circuit and serial bus low current consumption in power-down mode. applications digital still camera desktop video camera security camera camcorder dsp applications. general description the TDA9991HL forms the interface between the pulse pattern generator and the ccd image sensor in camera systems and minimizes the component count significantly by integration of various functions. the device contains eight vertical line drivers, a shutter driver for charge reset, a versatile programmable dc-dc converter, a non-programmable dc-dc converter and voltage regulators which create all required low noise supply voltages for ft and ff ccd sensors. a three wire serial bus, similar to the ones used in the philips front-end ics (tda8786 and tda8783) is used for programming the device. the versatile programmable dc-dc converter generates two positive voltages (v capns and v caph ) and the non programmable dc-dc converter generates a negative voltage (v vl ) which is used internally. voltage regulators convert the dc-dc converter outputs into low-noise output voltages (v ns ,v sfd ,v hfb and v sh ). the required voltages for the image sensor and the drivers can be programmed via the serial bus with sufficient accuracy to optimize the performance of the sensors. an on-board reference voltage ensures stable output voltages over the entire temperature range. an internal dcok signal enables the vertical line drivers when the dc-dc converter output voltages and the regulator output voltages are at their required (programmable) level. when either v hfb , v capns or v ns drops below 80% of its programmed level, the dcok signal will become low. a signal on pin start (inverse of dcok signal) indicates that the device has started up and is externally available. the use of two external coils enables high efficiency of the dc-dc converters and fast starting up. the maximum current built-up in coil l2 can be set with an external resistor r lim optimizing the efficiency of the dc-dc converter and making it independent of supply voltage variations. the dc-dc converter operates from an on-chip free running oscillator or from an external clock signal. the low impedance of the drivers enables fast transfer of the image of the sensor. the drivers can switch between 0 v and v hfb (8 to 15 v). the eight vertical drivers (image gate drivers) can be put into 3-state via the serial bus. charge reset of the ccd can be performed with a separate electronic shutter driver. when the tda9991 is in power-on mode, a high level at pin pwd will put the chip in power-down mode. a low level at pin pwd will enable power-on mode again. when pin pwd is left open-circuit, a pull-down resistor will keep this input low. in the power-down mode (set via the serial bus or through pin pwd) the current consumption becomes virtually zero. the serial bus is still available. www.datasheet.co.kr datasheet pdf - http://www..net/
2001 may 29 3 philips semiconductors preliminary speci?cation vertical line driver and dc-dc converter for full frame and frame transfer ccd image sensors TDA9991HL quick reference data ordering information symbol parameter conditions min. typ. max. unit supplies v dda1 analog supply voltage 1 3.6 - 7v v dda2 analog supply voltage 2 3.6 - 7v v ddd digital supply voltage 2.6 - 3.6 v vertical line drivers r o(on) high- and low-level output on-resistance i l(h) = 200 ma; i l(l) = - 200 ma - 0.66 -w shutter driver r o(on) high- and low-level output on-resistance i l(h) = 3 ma; i l(l) = - 3ma - 16.5 -w output voltage regulators v hfb high output voltage programmable 8 - 15 v v ns nwell substrate output voltage programmable 17 - 31 v v sfd source follower drain output voltage programmable 18 - 24 v v sh shutter driver output voltage programmable 3 - 10 v temperature range t oper operating temperature - 20 - +70 c type number package name description version TDA9991HL lqfp48 plastic low pro?le quad ?at package; 48 leads; body 7 7 1.4 mm sot313-2 www.datasheet.co.kr datasheet pdf - http://www..net/
2001 may 29 4 philips semiconductors preliminary speci?cation vertical line driver and dc-dc converter for full frame and frame transfer ccd image sensors TDA9991HL block diagram mgt242 handbook, full pagewidth vertical line drivers a1 30 logic control and interface shutter driver band gap reference voltage serial interface sho 11 a2 29 a3 26 a4 25 b1 31 b2 32 b3 35 b4 36 pwd 37 va1 47 shin 10 7 agnd1 va2 46 va3 45 va4 44 vb1 42 vb2 41 vb3 40 vb4 39 voltage regulators sdata 1 oscillator dc-dc converters osc v dda2 l2 l1 l2 l1 agnd2 6 15 17 14 16 sclk 3 sen 2 start dcok 38 sfd 23 ns 22 sh 20 vbe 21 hfb cap12 12 v5v 5 vl 13 capns 18 caph 19 lim r lim r osc 9 24 28 agnd3 34 agnd4 27 hda 33 hdb 48 dgnd 43 capbg 8 v dda1 + v dda + v dda + + - 4 v ddd + v ddd v sh v sh TDA9991HL fig.1 block diagram. www.datasheet.co.kr datasheet pdf - http://www..net/
2001 may 29 5 philips semiconductors preliminary speci?cation vertical line driver and dc-dc converter for full frame and frame transfer ccd image sensors TDA9991HL pinning symbol pin description sdata 1 serial bus data input sen 2 serial bus enable input sclk 3 serial bus clock input v ddd 4 digital supply voltage v5v 5 ?lter capacitor of digital supply voltage osc 6 external oscillator resistor or clock input agnd1 7 analog ground 1 v dda1 8 analog supply voltage 1 lim 9 peak current limiting resistor shin 10 electronic shutter driver input sho 11 electronic shutter driver output cap12 12 ?lter capacitor of dc-dc converter vl 13 dc-dc converter negative low voltage l1 14 coil 1 connection v dda2 15 dc-dc converter analog supply voltage 2 agnd2 16 dc-dc converter analog ground 2 l2 17 coil 2 connection capns 18 ?lter capacitor of dc-dc converter capns voltage caph 19 ?lter capacitor of dc-dc converter caph voltage output sh 20 shutter voltage output vbe 21 base voltage output ns 22 nwell substrate voltage output sfd 23 source follower drain voltage output hfb 24 horizontal voltage feedback output a4 25 a4 driver output a3 26 a3 driver output hda 27 a drivers high voltage supply agnd3 28 a drivers analog ground 3 a2 29 a2 driver output a1 30 a1 driver output b1 31 b1 driver output b2 32 b2 driver output hdb 33 b drivers high voltage supply agnd4 34 b drivers analog ground 4 b3 35 b3 driver output b4 36 b4 driver output pwd 37 power-down input start 38 dc voltages ready output vb4 39 b4 driver digital input vb3 40 b3 driver digital input vb2 41 b2 driver digital input vb1 42 b1 driver digital input capbg 43 ?lter capacitor of band gap reference va4 44 a4 driver digital input va3 45 a3 driver digital input va2 46 a2 driver digital input va1 47 a1 driver digital input dgnd 48 digital ground symbol pin description www.datasheet.co.kr datasheet pdf - http://www..net/
2001 may 29 6 philips semiconductors preliminary speci?cation vertical line driver and dc-dc converter for full frame and frame transfer ccd image sensors TDA9991HL handbook, full pagewidth 1 2 3 4 5 6 7 8 9 10 11 36 35 34 33 32 31 30 29 28 27 26 13 14 15 16 17 18 19 20 21 22 23 48 47 46 45 44 43 42 41 40 39 38 12 24 37 25 TDA9991HL mgt243 b4 b3 agnd4 hdb b1 a1 a2 agnd3 hda a3 a4 b2 va1 va2 va3 va4 capbg vb1 vb3 vb4 start pwd dgnd vb2 sdata sen sclk v ddd v5v osc v dda1 lim sho cap12 agnd1 shin l1 v dda2 agnd2 l2 capns caph sh ns sfd hfb vl vbe fig.2 pin configuration. www.datasheet.co.kr datasheet pdf - http://www..net/
2001 may 29 7 philips semiconductors preliminary speci?cation vertical line driver and dc-dc converter for full frame and frame transfer ccd image sensors TDA9991HL functional description the TDA9991HL can be separated into three main blocks (see fig.1): dc-dc converters voltage regulators drivers. the functionality of the blocks is described below. dc-dc converters the principle of the dc-dc converter with positive output voltages v capns and v caph is shown in fig.3. the two voltages are generated by charging coil l2 (closing s1) and then discharging the charge built-up in coil l2 (by opening s1) into the capacitor at pin capns or, when s2 is closed, into the capacitor at pin caph. since v capns is always higher than v caph , closing s2 will not cause a discharge of the capacitor at pin capns into the capacitor at pin caph. the current through switch s1 is being monitored and will not exceed the maximum value set by an external resistor at pin lim. limiting the maximum current will make the charge built-up in coil l2 independent of the supply voltage therefore keeping the converter efficiency constant. the principle of the dc-dc converter with the negative output voltage v vl is shown in fig.4. the negative voltage is generated by charging coil l1 (closing s3) and then discharging the charge built-up in coil l1 (by opening s3) into the capacitor at pin vl. the capacitor at pin vl will be charged to approximately - 3 v; there is no current limiting. voltage regulators for an optimal performance of the ccd, the sensor voltages v sh ,v ns ,v sfd and v hfb are being generated by programmable voltage regulators with a very high ripple rejection. the voltage regulators for v sh ,v ns and v sfd all have the same principle shown in fig.5. peak currents are being supplied by the capacitor at the output while the voltage regulator charges the capacitor more slowly. the value of the capacitor determines the output voltage drop when a peak current is being drawn. handbook, halfpage mgt244 s1 s2 l2 v dda v caph v capns fig.3 principle of dc-dc converter with positive output voltage. handbook, halfpage mgt245 s3 l1 l1 v dda v vl fig.4 principle of dc-dc converter with negative output voltage. mgt246 amp1, amp2, amp3 v dac v sh = v ns = 1 v sfd = 1 sh, ns, sfd capns, caph fig.5 principle of voltage regulators. www.datasheet.co.kr datasheet pdf - http://www..net/
2001 may 29 8 philips semiconductors preliminary speci?cation vertical line driver and dc-dc converter for full frame and frame transfer ccd image sensors TDA9991HL the voltage regulator for the drivers supply (v hfb ) can operate in two modes, depending on the application it is used in: mode 1 at fast transport with high peak current mode 2 at slow transport with constant current. m ode 1 in applications where the transport of the image is done in a very short period large currents (up to 1.5 a) are being drawn which cannot be supplied by the voltage regulator itself. in that event an external transistor is used to supply the large peak currents (see fig.6). mode 1 is selected via the serial interface (latch 1, bit d1 = 0; see table 3). in mode 1 the external transistor can supply large peak currents which are being drawn from the capacitor used at pin caph. since v caph is chosen to be 2.6 or 5.15 v (programmable via the serial bus with bit vd2x) above v hfb the voltage at the capacitor at pin caph can drop approximately 1.8 or 4.5 v during the transport without affecting v hfb . this reduces the value (size) of the capacitor required at pin caph. during the transport the base-emitter voltage of the external transistor will increase causing a drop on v hfb . the drop depends on the static current set by r1 and the maximum peak current being drawn and can be calculated with the following formula: the static current should be approximately 500 m a. capacitor c2, connected to the emitter, filters out the spikes averaging the peak current. when the peak current stops, the increased base-emitter voltage will drop back to its normal level (see fig.7). the base voltage v vbe might have been changed slightly (tens of millivolts) but will get back to its desired level fast. after transport the capacitor at pin caph will be charged again by the dc-dc converter. m ode 2 in applications where the transport of the image is slow, a constant current is required which can be supplied by the voltage regulator and no external transistor is needed. mode 2 is selected via the serial interface (bit d1 = 1). in mode 2, pins vbe and hfb must be tied together (see fig.8). in this mode the voltage regulator can supply currents up to 30 ma. peak currents need to be filtered out by capacitor c1. v drop 25 mv ln i peak i r1 ----------- = handbook, halfpage mgt247 amp4 v dac v hfb = 8 to 15 v hfb caph vbe c1 r1 c2 fig.6 principle of voltage regulator of drivers supply in mode 1. handbook, halfpage mgt249 transport v v caph v hfb transport t fig.7 output voltage at pin caph during transport. mgt248 amp4 v dac v hfb = 8 hfb caph vbe c1 fig.8 principle of voltage regulator of drivers supply in mode 2. www.datasheet.co.kr datasheet pdf - http://www..net/
2001 may 29 9 philips semiconductors preliminary speci?cation vertical line driver and dc-dc converter for full frame and frame transfer ccd image sensors TDA9991HL s ta rt - up cycle during the start-up (pin start = high and the internal signal dcok = low) the maximum output current of amp4 (see fig.8) will be increased from 0.5 ma minimum to 30 ma maximum. this is done to decrease the time required to fully charge capacitor c1 during starting up. when pin start = low (all voltages are at their required level) or when v vbe is at its required level, the minimum output current of amp4 will automatically drop back to 0.5 ma. when mode 2 is selected the maximum output current of amp4 will remain 30 ma after starting up. an integrated start-up cycle ensures a fast and safe start-up of the TDA9991HL. the principle of the start-up cycle (hysteresis) is shown in fig.9. when starting up the signal at pin start will be high. when v capns and v caph are at 100% of their programmed level and v hfb and v ns are above 80% of their programmed level, pin start will become low. when v capns ,v hfb or v ns drops below approximately 80% of their programmed level the TDA9991HL will start again with the start-up cycle. when starting up, the capacitor at pin capns will be charged prior to the capacitor at pin caph. the capacitor at pin vl is charged by a separate dc-dc converter independent of the start-up cycle. vertical line drivers for frame transport the TDA9991HL has eight two-level low-ohmic drivers available. the principle of the driver outputs is shown in fig.10. a logic interface converts the digital input signal into the two control signals for the driver transistors. it also prevents both transistors to switch on at the same time. during start-up the drivers are kept in 3-state. table 1 a and b drivers; note 1 note 1. the internal dcok signal will keep the a and b outputs in 3-state until the output voltages of the dc-dc converter and voltage regulators are at their required level. shutter driver table 2 shutter driver output level at input pins level at output pins low high high low input level at pin shin output level at pin sho low high high low handbook, halfpage mgt250 0% 80 5% 100% regulator output voltage h l v start fig.9 hysteresis of start-up cycle. handbook, halfpage mgt251 logic interface 3-state dcok v hfb a1 to a4, b1 to b4 hda, hdb va1 to va4, vb1 to vb4 fig.10 principle of driver output. www.datasheet.co.kr datasheet pdf - http://www..net/
2001 may 29 10 philips semiconductors preliminary speci?cation vertical line driver and dc-dc converter for full frame and frame transfer ccd image sensors TDA9991HL serial interface handbook, full pagewidth vd2x, mode (latch 1) v hfb (latch 2) v ns (latch 3) v sfd (latch 4) v sh (latch 5) latch selection d0 lsb msb sdata sclk sen mode 4-bit dac mgt252 4-bit dac 5-bit dac 4-bit dac d1 d2 d3 d4 5 shift register a0 a1 a2 vd2x 2 4 5 4 4 power on/off, 3-state on/off, oscillator free/external (latch 0) outputs 3-state oscillator on/off 5 fig.11 serial interface block diagram. handbook, full pagewidth mgt253 a2 sdata sclk sen a1 a0 d4 d2 d1 d0 t h(sen) t su(sen) t h(sdata) t su(sdata) d3 pin sen must stay high for at least two clock cycles after each word. fig.12 loading sequence of input data to control dacs via the serial interface. www.datasheet.co.kr datasheet pdf - http://www..net/
2001 may 29 11 philips semiconductors preliminary speci?cation vertical line driver and dc-dc converter for full frame and frame transfer ccd image sensors TDA9991HL table 3 serial interface programming (see fig.11) notes 1. x is a dont care. 2. the power-down mode also shuts down the dc-dc converter. latch address bits data bits (1) description a2 a1 a0 d4 d3 d2 d1 d0 0 0 0 0 power-on, 3-state and clock selection 0 power-down (note 2) 1 power-on 0 outputs in normal operation 1 outputs in 3-state x dont care 0 free running oscillator 1 external clock signal 0 fixed value 1 0 0 1 voltage drop and mode selection 0 2.7 v drop (bit vd2x = 0) 1 5.4 v drop (bit vd2x = 1) 0 mode 1 1 mode 2 2 0 1 0 4 bits of v hfb x0000 output is 8 v x:::: steps of approximately 467 mv x1111 output is 15 v 3 0 1 1 5 bits of v ns 00000 output is 17 v ::::: steps of approximately 450 mv 11111 output is 31 v 4 1 0 0 4 bits of v sfd x0000 output is 18 v x:::: steps of approximately 400 mv x1111 output is 24 v 5 1 0 1 4 bits of v sh x0000 output is 3 v x:::: steps of approximately 467 mv x1111 output is 10 v www.datasheet.co.kr datasheet pdf - http://www..net/
2001 may 29 12 philips semiconductors preliminary speci?cation vertical line driver and dc-dc converter for full frame and frame transfer ccd image sensors TDA9991HL limiting values in accordance with the absolute maximum rating system (iec 60134). note 1. maximum value of v ddd + 0.3 v but not higher than 5.5 v. quality specification in accordance with snw-fq-611e . characteristics v dda =5v; v ddd = 3.3 v; t amb =25 c; inputs va1 to va4 and vb1 to vb4 are high; v shin =0v; l1=47 m h; l2 = 4.7 m h; r lim = 680 w ; v hfb = 12 v; v ns = 24 v; v sfd =20v; v sh =8v; v start = low; no load for regulator output voltages; unless otherwise speci?ed. symbol parameter conditions min. max. unit v dda1 analog supply voltage 1 - 0.3 +7 v v dda2 analog supply voltage 2 - 0.3 +7 v v ddd digital supply voltage - 0.3 +5.5 v v n voltage at pins va1 to va4, vb1 to vb4, v5v, pwd, sdata, sen, sclk, shin and osc - 0.3 v ddd + 0.3 (1) v capbg - 0.3 v v5v + 0.3 v cap12 - 0.3 +15 v vbe, sh, hfb, hda and hdb - 0.3 +20 v caph coil not connected - 0.3 +20 v capns coil not connected - 0.3 +45 v ns and sfd - 0.3 +45 v vl - 6 - v agnd1, agnd2, agnd3 and agnd4 v dgnd - 0.3 v dgnd + 0.3 v i n current at pins a1 to a4 and b1 to b4 static current - 100 +100 ma vl 0 5 ma lim - 30 ma sho - 50 +50 ma start - 3 +0.2 ma symbol parameter conditions min. typ. max. unit supplies v dda1 analog supply voltage 1 3.6 5 7 v i dda1 analog supply current 1 v va1 to v va4 =v ddd ; v vb1 to v vb4 =v ddd ; v sen =0 - 3.5 - ma i q(dda1) quiescent analog supply current 1 power-down mode; latc h 0 = 00x00; note 1 -- 300 m a v dda2 analog supply voltage 2 3.6 5 7 v www.datasheet.co.kr datasheet pdf - http://www..net/
2001 may 29 13 philips semiconductors preliminary speci?cation vertical line driver and dc-dc converter for full frame and frame transfer ccd image sensors TDA9991HL i dda2 analog supply current 2 v va1 to v va4 =v ddd ; v vb1 to v vb4 =v ddd ; v sen = 0; note 2 - 130 - ma i q(dda2) quiescent analog supply current 2 power-down mode; latc h 0 = 00x00; note 1 -- 4 m a v ddd digital supply voltage 2.6 3.3 3.6 v i ddd digital supply current v va1 to v va4 =v ddd ; v vb1 to v vb4 =v ddd ; v sen =0 - 460 -m a i q(ddd) quiescent digital supply current power-down mode; latc h 0 = 00x00; note 1 -- 100 m a vertical line drivers a and b r o(on) high- and low-level output on-resistance i l(h) = 200 ma; i l(l) = - 200 ma 0.6 0.66 0.72 w t r rise time of outputs v ns - v hfb >7v; c l = 6.8 nf 16 20 29 ns t f fall time of outputs v ns - v hfb >7v; c l = 6.8 nf 18 23 29 ns v oh high-level output voltage - v hfb - v v ol low-level output voltage - 0 - v i lo(z) output leakage current in 3-state 3-state; v o <6v; latc h 0 = 00x11 - 1 - +1 m a t pd propagation delay no load 40 ns d t pd propagation delay difference between channels -- 3ns shutter driver (pin sho) r o(on) high- and low-level output on-resistance i l(h) = 3 ma; i l(l) = - 3ma - 16.5 -w v oh high-level output voltage - v sh - v v ol low-level output voltage - 0 - v t r rise time v ns - v sh >7v; c l =2nf - 50 ns t f fall time v ns - v sh >7v; c l =2nf - 50 ns dc-dc converters v capns output voltage at pin capns - v ns +6 - v v caph output voltage at pin caph bit vd2x = 0; note 3 v hfb + 2.45 v hfb + 2.6 v hfb + 2.75 v bit vd2x = 1; note 3 v hfb + 4.9 v hfb + 5.15 v hfb + 5.4 v d i l2(max) variation of maximum current built-up in coil l2 note 4 - 15 - +15 % t start start-up time of the dc-dc converter v start = high; r lim = 680 w ; v hfb = 13.1 v; note 5 - 35 60 ms symbol parameter conditions min. typ. max. unit www.datasheet.co.kr datasheet pdf - http://www..net/
2001 may 29 14 philips semiconductors preliminary speci?cation vertical line driver and dc-dc converter for full frame and frame transfer ccd image sensors TDA9991HL output voltage regulators h igh voltage feedback output ( pin hfb) v hfb high voltage output programmable (4 bits) 8 - 15 v d v hfb output voltage variation - 5 0 +5 % d v hfb(t) output voltage variation with temperature t amb = - 20 to +70 c -- 0.5 % rr ripple rejection v start =low; f = 0 to 1 mhz; note 6 60 -- db b ase voltage output ( pin vbe) i vbe dc output current v start = low; note 7 0.5 -- ma i vbe(start) output current during start-up v start = high or in mode 2; note 7 30 -- ma n well substrate voltage output ( pin ns) v ns output voltage programmable (5 bits); note 8 17 - 31 v i ns dc output current -- 4ma d v ns output voltage variation - 5 0 +5 % d v ns(t) output voltage variation with temperature t amb = - 20 to +70 c -- 0.5 % rr ripple rejection v start =low; f = 0 to 1 mhz; note 6 50 -- db s ource follower drain voltage output ( pin sfd) v sfd output voltage programmable (4 bits); note 8 18 - 24 v i sfd dc output current -- 20 ma d v sfd output voltage variation - 5 0 +5 % d v sfd(t) output voltage variation with temperature t amb = - 20 to +70 c -- 0.5 % rr ripple rejection v start =low; f = 0 to 1 mhz; note 6 50 -- db s hutter driver voltage output ( pin sh) v sh output voltage programmable (4 bits) 3 - 10 v i sh dc output current -- 3ma d v sh output voltage variation - 5 0 +5 % d v sh(t) output voltage variation with temperature t amb = - 20 to +70 c -- 0.5 % rr ripple rejection v start =low; f = 0 to 1 mhz; note 6 60 -- db symbol parameter conditions min. typ. max. unit www.datasheet.co.kr datasheet pdf - http://www..net/
2001 may 29 15 philips semiconductors preliminary speci?cation vertical line driver and dc-dc converter for full frame and frame transfer ccd image sensors TDA9991HL oscillator f fr free running oscillator frequency latc h 0 = 00x01; r osc =47k w ; note 9 4 5.35 6.75 mhz f clk external clock input frequency latc h 0 = 01x01; note 9 4 - 6.75 mhz d duty factor external clock input frequency 40 - 60 % serial interface (see fig.12) f sclk(max) maximum clock frequency v ddd = 3.6v -- 4.0 mhz v ddd = 3.3v -- 3.3 mhz v ddd = 3.0v -- 2.5 mhz v ddd = 2.6v -- 1.8 mhz t su(sen) sen set-up time compared to sclk rising edge -- s t su(sdata) sdata set-up time compared to sclk rising edge -- s t h(sen) sen hold time compared to sclk rising edge -- s t h(sdata) sdata hold time compared to sclk rising edge -- s control inputs v il low-level input voltage at pins sen, sdata, sclk, shin, pwd, va1 to va4, vb1 to vb4 and osc note 10 - 0.2 - 0.3v ddd v v ih high-level input voltage at pins sen, sdata, sclk, shin, pwd, va1 to va4, vb1 to vb4 and osc note 11 0.7v ddd - 5.5 v digital output (pin start) v start(l) low-level output voltage i sink(max) =20 m a; note 12 -- 0.4 v v start(h) high-level output voltage i source(max) =20 m a; note 13 v ddd - 0.4 -- v temperature range t oper operating temperature - 20 - +70 c symbol parameter conditions min. typ. max. unit 0.16 f sclk(max) ------------------------ - 0.16 f sclk(max) ------------------------ - 0.08 f sclk(max) ------------------------ - 0.16 f sclk(max) ------------------------ - www.datasheet.co.kr datasheet pdf - http://www..net/
2001 may 29 16 philips semiconductors preliminary speci?cation vertical line driver and dc-dc converter for full frame and frame transfer ccd image sensors TDA9991HL notes 1. a power-on reset function puts the TDA9991HL in the power-down mode when v ddd is supplied. 2. the supply current is measured without load (ccd) using the following programmed voltages: v ns =28v;v sfd =21v;v hfb =13v;v sh = 8 v. the power consumption depends on the value of r lim , the supply voltages, programmed voltages and the efficiency of the dc-dc convertor under load condition. therefore, the value of i dda2 in this table is a rough indication. 3. during transport v caph may drop to v hfb + 0.7 v (over the entire temperature range): a) bit vdx2 = 0: voltage drop is 1.8 v b) bit vdx2 = 1: voltage drop is 4.5 v. 4. 5. the charging time of the electrolytic capacitor at pin capns is very small compared to the charging time of the electrolytic capacitor at pin caph. the start-up time depends on: a) peak current i l2(max) chosen through coil l2; the maximum allowable peak current is 2.1 a b) value of the electrolytic capacitor at pin caph (470 m f) c) oscillator frequency d) required voltage level at pin caph. 6. drivers not active. 7. during start-up (v start = high) the maximum output current at pin hfb is increased to allow fast starting up. 8. v ns >v sfd . 9. pin osc can be connected to an external clock or to an external resistor (in case the internal oscillator is used). 10. at v ddd = 2.6 v the maximum low-level voltage is 0.2v ddd . 11. at v ddd = 2.6 v the minimum high-level voltage is 0.8v ddd . 12. v start will become low when: a) all output voltages at pins hfb, ns and capns are at 100% of their required (programmable) level b) v caph =v hfb + 2.7 v (bit vd2x = 0) or v caph =v hfb + 5.4 v (bit vd2x = 1); v caph needs to have reached the programmed voltage only once for v start to go low. 13. v start will become high when either v hfb ,v ns or v capns drops below 80% (typical) of their programmed level. i l2(max) 1308 r lim ------------- = www.datasheet.co.kr datasheet pdf - http://www..net/
2001 may 29 17 philips semiconductors preliminary speci?cation vertical line driver and dc-dc converter for full frame and frame transfer ccd image sensors TDA9991HL application information handbook, full pagewidth 47 m f 22 m f 470 m f 10 m f 10 m f 1 m f 27 k w (1) 47 k w 47 k w bc868 (1) 1 2 3 4 5 6 7 8 9 10 11 36 35 34 33 32 31 30 29 28 27 26 24 23 22 21 20 19 18 17 16 15 14 13 37 38 39 40 41 42 43 44 45 46 47 48 12 25 TDA9991HL mgt254 b4 b3 philips ccd(ft) b1 a1 a2 a3 a4 b2 va1 va2 va3 va4 capbg vb1 vb3 vb4 start pwd dgnd vb2 sdata drivers control shutter control serial bus sen sclk v ddd v5v osc v dda1 v dda r lim v ddd lim sho 220 nf 220 nf 100 nf 100 nf 100 nf 330 nf cap12 agnd1 shin l1 l1 v dda2 v dda v dda agnd2 l2 capns caph sh ns sfd ns sfd hfb vl vbe 100 nf l2 b4 start b3 agnd4 hdb b1 a1 a2 agnd3 hda a3 a4 b2 (1) the (emitter) current through the external resistor should be approximately 500 m a. the value of the resistor can be adjusted depending on the emitter voltage (v hfb ). l1=47 m h. l2 = 4.7 m h. r lim = 680 w . fig.13 application diagram. www.datasheet.co.kr datasheet pdf - http://www..net/
2001 may 29 18 philips semiconductors preliminary speci?cation vertical line driver and dc-dc converter for full frame and frame transfer ccd image sensors TDA9991HL package outline unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 1.60 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 0.5 9.15 8.85 0.95 0.55 7 0 o o 0.12 0.1 0.2 1.0 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot313-2 ms-026 136e05 99-12-27 00-01-19 d (1) (1) (1) 7.1 6.9 h d 9.15 8.85 e z 0.95 0.55 d b p e e b 12 d h b p e h v m b d z d a z e e v m a 1 48 37 36 25 24 13 q a 1 a l p detail x l (a ) 3 a 2 x y c w m w m 0 2.5 5 mm scale pin 1 index lqfp48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm sot313-2 www.datasheet.co.kr datasheet pdf - http://www..net/
2001 may 29 19 philips semiconductors preliminary speci?cation vertical line driver and dc-dc converter for full frame and frame transfer ccd image sensors TDA9991HL soldering introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 220 c for thick/large packages, and below 235 c for small/thin packages. wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. www.datasheet.co.kr datasheet pdf - http://www..net/
2001 may 29 20 philips semiconductors preliminary speci?cation vertical line driver and dc-dc converter for full frame and frame transfer ccd image sensors TDA9991HL suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 2. these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 4. wave soldering is only suitable for lqfp, tqfp and qfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package soldering method wave reflow (1) bga, hbga, lfbga, sqfp, tfbga not suitable suitable hbcc, hlqfp, hsqfp, hsop, htqfp, htssop, hvqfn, sms not suitable (2) suitable plcc (3) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (3)(4) suitable ssop, tssop, vso not recommended (5) suitable www.datasheet.co.kr datasheet pdf - http://www..net/
2001 may 29 21 philips semiconductors preliminary speci?cation vertical line driver and dc-dc converter for full frame and frame transfer ccd image sensors TDA9991HL data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. data sheet status (1) product status (2) definitions objective data development this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. preliminary data quali?cation this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. product data production this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. changes will be communicated according to the customer product/process change noti?cation (cpcn) procedure snw-sq-650a. definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. www.datasheet.co.kr datasheet pdf - http://www..net/
2001 may 29 22 philips semiconductors preliminary speci?cation vertical line driver and dc-dc converter for full frame and frame transfer ccd image sensors TDA9991HL notes www.datasheet.co.kr datasheet pdf - http://www..net/
2001 may 29 23 philips semiconductors preliminary speci?cation vertical line driver and dc-dc converter for full frame and frame transfer ccd image sensors TDA9991HL notes www.datasheet.co.kr datasheet pdf - http://www..net/
? philips electronics n.v. sca all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. internet: http://www.semiconductors.philips.com 2001 72 philips semiconductors C a worldwide company for all other countries apply to: philips semiconductors, marketing communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 3 figtree drive, homebush, nsw 2140, tel. +61 2 9704 8141, fax. +61 2 9704 8139 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101 1248, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 20 0733, fax. +375 172 20 0773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 68 9211, fax. +359 2 68 9102 canada: philips semiconductors/components, tel. +1 800 234 7381, fax. +1 800 943 0087 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: sydhavnsgade 23, 1780 copenhagen v, tel. +45 33 29 3333, fax. +45 33 29 3905 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615 800, fax. +358 9 6158 0920 france: 7 - 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