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features applications description dac5686 slws147b ? april 2003 ? revised august 2004 16-bit, 500-msps, 2?16 interpolating dual-channel digital-to-analog converter on-chip 1.2-v reference 500 msps maximum update rate dac 1.8-v digital and 3.3-v analog supplies wcdma acpr 1.8-v/3.3-v cmos compatible interface ? 1 carrier: 76 db centered at 30.72-mhz if, power dissipation: 950 mw at full maximum 245.76 msps operating conditions ? 1 carrier: 73 db centered at 61.44-mhz if, package: 100-pin htqfp 245.76 msps ? 2 carrier: 72 db centered at 30.72-mhz if, 245.76 msps cellular base transceiver station transmit channel ? 4 carrier: 64 db centered at 92.16-mhz if, ? cdma: w-cdma, cdma2000, is-95 491.52 msps ? tdma: gsm, is-136, edge/uwc-136 selectable 2, 4, 8, and 16 interpolation baseband i and q transmit ? linear phase input interface: quadrature modulation for ? 0.05-db pass-band ripple interfacing with baseband complex mixing ? 80-db stop-band attenuation asics ? stop-band transition 0.4?0.6 f data single-sideband up-conversion 32-bit programmable nco diversity transmit on-chip 2?16 pll clock multiplier with cable modem termination system bypass mode differential scalable current outputs: 2 ma to 20 ma the dac5686 is a dual-channel 16-bit high-speed digital-to-analog converter (dac) with integrated 2, 4, 8, and 16 interpolation filters, a numerically controlled oscillator (nco), onboard clock multiplier, and on-chip voltage reference. the dac5686 has been specifically designed to allow for low input data rates between the dac and asic, or fpga, and high output transmit intermediate frequencies (if). target applications include high-speed digital data transmission in wired and wireless communication systems and high-frequency direct-digital synthesis dds. the dac5686 provides three modes of operation: dual-channel, single-sideband, and quadrature modulation. in dual-channel mode, interpolation filtering increases the dac update rate, which reduces sinx/x rolloff and enables the use of relaxed analog post-filtering. single-sideband mode provides an alternative interface to the analog quadrature modulators. channel carrier selection is performed at baseband by mixing in the asic/fpga. baseband i and q from the asic/fpga are input to the dac5686, which in turn performs a complex mix resulting in hilbert transform pairs at the outputs of the dac5686's two dacs. an external rf quadrature modulator then performs the final single-sideband up-conversion. the dac5686's complex mixing frequencies are flexibly chosen with the 32-bit programmable nco. unmatched gains and offsets at the rf quadrature modulator result in unwanted sideband and local oscillator feedthrough. each dac in the dac5686 has an 11-bit offset adjustment and 12-bit gain adjustment, which compensate for quadrature modulator input imbalances, thus reducing rf filtering requirements. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. powerpad is a trademark of texas instruments. all other trademarks are the property of their respective owners. production data information is current as of publication date. copyright ? 2003?2004, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. www .ti.com
dac5686 slws147b ? april 2003 ? revised august 2004 in quadrature modulation mode, on-chip mixing provides baseband-to-if up-conversion. mixing frequencies are flexibly chosen with a 32-bit programmable nco. channel carrier selection is performed at baseband by complex mixing in the asic/fpga. baseband i and q from the asic/fpga are input to the dac5686, which interpolates the low data-rate signal to higher data rates. the single dac output from the dac5686 is the final if single-sideband spectrum presented to rf. the 2, 4, 8, and 16 interpolation filters are implemented as a cascade of half-band 2 interpolation filters. unused filters for interpolation rates of less than 16 are shut off to reduce power consumption. the dac5686 provides a full bypass mode, which enables the user to bypass all the interpolation and mixing. the dac5686 pll clock multiplier controls all internal clocks for the digital filters and the dac cores. the differential clock input and internal clock circuitry provides for optimum jitter performance. sine wave clock input signal is supported. the pll can be bypassed by an external clock running at the dac core update rate. the clock divider of the pll ensures that the digital filters operate at the correct clock frequencies. the dac5686 operates with an analog supply voltage of 3.3 v and a digital supply voltage of 1.8 v. digital i/os are 1.8-v and 3.3-v cmos compatible. power dissipation is 950 mw at maximum operating conditions. the dac5686 provides a nominal full-scale differential current output of 20 ma, supporting both single-ended and differential applications. the output current can be directly fed to the load with no additional external output buffer required. the device has been specifically designed for a differential transformer-coupled output with a 50-w doubly terminated load. for a 20-ma full-scale output current, both a 4:1 impedance ratio (resulting in an output power of 4 dbm) and 1:1 impedance ratio transformer (?2-dbm output power) are supported. the dac5686 operational modes are configured by programming registers through a serial interface. the serial interface can be configured to either a 3- or 4-pin interface allowing it to communicate with many industry-standard microprocessors and microcontrollers. data (i and q) can be input to the dac5686 as separate parallel streams on two data buses, or as a single interleaved data stream on one data bus. an accurate on-chip 1.2-v temperature-compensated band-gap reference and control amplifier allows the user to adjust the full-scale output current from 20 ma down to 2 ma. this provides 20-db gain range control capabilities. alternatively, an external reference voltage can be applied for maximum flexibility. the device features a sleep mode, which reduces the standby power to approximately 10 mw, thereby minimizing the system power consumption. the dac5686 is available in a 100-pin htqfp package. the device is characterized for operation over the industrial temperature range of ?40c to 85c. ordering information t a package devices 100 htqfp (1) (pzp) powerpad? plastic quad flatpack ?40c to 85c DAC5686IPZP (1) thermal pad size: 6 mm 6 mm 2 www .ti.com
functional block diagram dac5686 slws147b ? april 2003 ? revised august 2004 block diagram of the dac5686 3 www .ti.com 2 2 2 2 2 2 2 2 clk1 clk1c lpf plllock clkvdd clkgnd dvdd dgnd pll vdd pllgnd sleep fir1 fir2 sin iovdd iognd a vdd agnd phstr nco cos resetb 100-pin htqfp extioextlo 1.2 v reference biasjiout a1 iout a2 16-bit fir5 ioutb1ioutb2 fir3 x sin(x) txenable da[15:0] db[15:0] demux fir4 clk2 clk2c sif sclk sdenb sdo sdio dac 16-bit dac 2 16 f d a t a internal clock generation 2 16 pll clock multiplier x sin(x) f d a t a a gain b gain a offset b offset
pin assignments for the dac5686 device information dac5686 slws147b ? april 2003 ? revised august 2004 terminal functions terminal i/o description name no. agnd 1, 4, 7, 9, i analog ground return 12, 17, 19, 22, 25 avdd 2, 3, 8, 10, i analog supply voltage 14, 16, 18, 23, 24 4 www .ti.com 12 3 4 5 6 7 8 9 10 1 1 1213 14 15 16 17 18 19 20 7574 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 100 9998 97 96 9594 93 92 91 90 89 88 87 86 85 84 83 82 2627 28 29 30 31 32 33 34 35 36 37 38 39 40 2122 23 24 25 4142 43 44 45 46 47 48 49 50 5554 53 52 51 8179 78 77 76 dac5686 t op v iew 100 htqfp dvdd dgnd qflag testmode sleepresetb phstr dgnd db15 (msb) db14db13 dvdd dgnd db12 db1 1 db10db9 db8 dvdd dgnd iovdd iognd db7db6 db5 dvdd dgnd sdenb sclk sdio sdo txenable da15 (msb) da14da13 dvdd dgnd da12 da1 1 da10 da9da8 dvdd dgnd iovdd iognd da7da6 da5 a vdd a vdd a vdd agnd iout a1 iout a2 agnd a vdd agnd a vdd extlo agnd biasj agnd extio a vdd agnd a vdd agnd ioutb2 ioutb1 agnd a vdd a vdd agnd 80 da4 da3 da2 da1 da0 (lsb) dvdd dgnd clkgnd clk1 clk1c clkvdd clk2 clk2c clkgnd pllgnd lpf pll vdd dvdd dgnd plllock db0 (lsb) db1 db2 db3 db4 dvdd
dac5686 slws147b ? april 2003 ? revised august 2004 device information (continued) terminal functions (continued) terminal i/o description name no. biasj 13 i/o full-scale output current bias clk1 59 i external clock input; data clock input clk1c 60 i complementary external clock input; data clock input clk2 62 i external clock input; sample clock for the dac (optional if pll disabled) clk2c 63 i complementary external clock input; sample clock for the dac (optional if pll disabled) clkgnd 58, 64 ground return for internal clock buffer clkvdd 61 internal clock buffer supply voltage da[15:0] 34?36, i a-channel data bits 0 through 15 39?43, da15 is most significant data bit (msb). 48?55 da0 is least significant data bit (lsb). db[0:15] 71?78, i b-channel data bits 0 through 15 83?87, db15 is most significant data bit (msb). 90?92 db0 is least significant data bit (lsb). note: the order of the b data bus can be reversed by register rev_bbus. dgnd 27, 38, 45, digital ground return 57, 69, 81, 88, 93, 99 dvdd 26, 32, 37, digital supply voltage 44, 56, 68, 82, 89, 100 extio 11 i used as external reference input when internal reference is disabled (i.e., extlo connected to avdd). used as internal reference output when extlo = agnd, requires a 0.1-mf decoupling capacitor to agnd when used as reference output extlo 15 i internal reference ground. connect to avdd to disable the internal reference iouta1 21 o a-channel dac current output. full scale when all input bits are set to 1 iouta2 20 o a-channel dac complementary current output. full scale when all input bits are set to 0 ioutb1 5 o b-channel dac current output. full scale when all input bits are set to 1 ioutb2 6 o b-channel dac complementary current output. full scale when all input bits are set to 0 iognd 47, 79 digital i/o ground return iovdd 46, 80 digital i/o supply voltage lpf 66 i/o pll loop filter connection. can be left open or connected to gnd if pll is not used (pllvdd = 0 v). phstr 94 i the phstr pin has two functions. when the sync_phstr register is 0, a high on the phstr pin resets the nco phase accumulator. when the sync_phstr register is 1, a phstr pin low-to-high transition sets the divided clock phase in external clock mode, and a high on the phstr pin resets the nco phase accumulator. pllgnd 65 ground return for internal pll pllvdd 67 pll supply voltage. when pllvdd is 0 v, the pll is disabled. plllock 70 o pll lock status bit. in pll clock mode, plllock is high when pll is locked to the input clock. in external clock mode, plllock outputs the input rate clock. qflag 98 o used in the interleaved data input mode: when the qflag register bit is 1, the qflag pin is used as an output to identify the interleaved data sequence. qflag high identifies the data as channel b. pin can be left open when not used. resetb 95 i resets the chip when low sclk 29 i serial interface clock sdenb 28 i active-low serial data enable, always an input to the dac5686 sdio 30 i/o bidirectional serial-port data in the three-pin serial interface mode. input-only serial data in the four-pin serial interface mode. sdo 31 o high-impedance state (the pin is not used) in the three-pin serial interface mode. serial-port output data in the four-pin serial interface mode. sleep 96 i asynchronous hardware power-down input. active high. internal pulldown testmode 97 i testmode is dgnd for the user. 5 www .ti.com
absolute maximum ratings electrical characteristics (dc specifications) (1) dac5686 slws147b ? april 2003 ? revised august 2004 device information (continued) terminal functions (continued) terminal i/o description name no. txenable 33 i txenable is used in interleaved mode. the rising edge of txenable synchronizes the data of channels a and b. the first data after the rising edge of txenable is treated as a data, while the next data is treated as b data and so on. in any mode, txenable being low sets dac outputs to midscale. internal pulldown over operating free-air temperature range (unless otherwise noted) (1) unit avdd (2) ?0.5 v to 4 v dvdd (3) ?0.5 v to 2.3 v supply voltage range clkvdd (2) ?0.5 v to 4 v iovdd (2) ?0.5 v to 4 v pllvdd (2) ?0.5 v to 4 v voltage between agnd, dgnd, clkgnd, pllgnd, and iognd ?0.5 v to 0.5 v avdd to dvdd ?0.5 v to 2.6 v da[15:0] (3) ?0.5 v to iovdd + 0.5 v db[15:0] (3) ?0.5 v to iovdd + 0.5 v sleep (3) ?0.5 v to iovdd + 0.5 v clk1, clk2, clk1c, clk2c (3) ?0.5 v to clkvdd + 0.5 v supply voltage range resetb (3) ?0.5 v to iovdd + 0.5 v lpf (3) ?0.5 v to pllvdd + 0.5 v iout1, iout2 (2) ?1 v to avdd + 0.5 v extio, biasj (2) ?0.5 v to avdd + 0.5 v extlo (2) ?0.5 v to iovdd + 0.5 v peak input current (any input) 20 ma operating free-air temperature range, t a : dac5686i ?40c to 85c storage temperature range ?65c to 150c lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds 260c (1) stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) measured with respect to agnd (3) measured with respect to dgnd over operating free-air temperature range, avdd = 3.3 v, clkvdd = 3.3 v, pllvdd = 3.3 v, iovdd = 3.3 v, dvdd = 1.8 v, iout fs = 20 ma (unless otherwise noted) parameter test conditions min typ max unit resolution 16 dc accuracy (2) inl integral nonlinearity 1 lsb = iout fs /216, t min to t max 12 lsb 1.84e?4 iout fs dnl differential nonlinearity 9 lsb 1.37e?4 iout fs (1) specifications subject to change without notice. (2) measured differential across iouta1 and iouta2 or ioutb1 and ioutb2 with 25 w each to avdd 6 www .ti.com
dac5686 slws147b ? april 2003 ? revised august 2004 electrical characteristics (dc specifications) (continued) over operating free-air temperature range, avdd = 3.3 v, clkvdd = 3.3 v, pllvdd = 3.3 v, iovdd = 3.3 v, dvdd = 1.8 v, iout fs = 20 ma (unless otherwise noted) parameter test conditions min typ max unit analog output coarse gain linearity (inl) lsb = 1/10 th of full scale 0.016 lsb fine gain linearity (inl) 3 lsb offset error mid-code offset 0.003 %fsr without internal reference 0.7 gain error %fsr with internal reference 0.7 gain mismatch with internal reference, dual dac, ?2 2 %fsr ssb mode full-scale output current (3) 2 20 ma output compliance range (4) iout fs = 20 ma avdd ? 0.5 avdd + 0.5 v output resistance 300 kw output capacitance 5 pf reference output reference voltage 1.14 1.2 1.26 v reference output current (5) 100 na reference input v extio input voltage range 0.1 1.25 v input resistance 1 mw small-signal bandwidth 2.5 khz input capacitance 100 pf temperature coefficients ppm of offset drift 3 fsr/c without internal reference 15 ppm of gain drift fsr/c with internal reference 40 reference voltage drift 25 ppm/c power supply avdd analog supply voltage 3 3.3 3.6 v dvdd digital supply voltage 1.65 1.8 1.95 v clkvdd clock supply voltage 3 3.3 3.6 v iovdd i/o supply voltage 1.65 3.6 v pllvdd pll supply voltage 3 3.3 3.6 v single (quad) dac mode; including output current through 30 load resistor, mode 7 i avdd analog supply current ma dual dac mode; including output current through load resistor, 55 mode 11 i dvdd digital supply current 242 ma i clkvdd clock supply current 10 ma f data = 125 msps, ssb mode, f update = 500 msps, 40-mhz if i pllvdd pll supply current 28 ma i iovdd io supply current < 3 ma (3) nominal full-scale current, iout fs , equals 16 the ibias current. (4) the upper limit of the output compliance is determined by the cmos process. exceeding this limit may result in transistor breakdown, resulting in reduced reliability of the dac5686 device. the lower limit of the output compliance is determined by the load resistors and full-scale output current. exceeding the upper limit adversely affects distortion performance and integral nonlinearity. (5) use an external buffer amplifier with high-impedance input to drive any external load. 7 www .ti.com
electrical characteristics (ac specifications) (1) dac5686 slws147b ? april 2003 ? revised august 2004 electrical characteristics (dc specifications) (continued) over operating free-air temperature range, avdd = 3.3 v, clkvdd = 3.3 v, pllvdd = 3.3 v, iovdd = 3.3 v, dvdd = 1.8 v, iout fs = 20 ma (unless otherwise noted) parameter test conditions min typ max unit i avdd sleep mode, avdd supply current 1 ma i dvdd sleep mode, dvdd supply current 4 ma i clkvdd sleep mode, clkvdd supply 2 ma current sleep mode i pllvdd sleep mode, pllvdd supply 0.5 ma current i iovdd sleep mode, iovdd supply current 0.25 ma mode 1 (6) avdd = 3.3 v, 215 dvdd = 1.8 v mode 2 (7) avdd = 3.3 v, 495 dvdd = 1.8 v mode 5 (8) avdd = 3.3 v, 445 dvdd = 1.8 v p d power dissipation mw mode 7 (9) avdd = 3.3 v, 754 dvdd = 1.8 v mode 9 (10) avdd = 3.3 v, 547 dvdd = 1.8 v mode 11 (11) avdd = 3.3 v, 855 950 dvdd = 1.8 v apsrr power supply rejection ratio ?0.2 0.2 %fsr/v dpsrr power supply rejection ratio ?0.2 0.2 %fsr/v (6) mode 1: dual dac mode, fully bypassed, f dac = 160 msps, f out = 20 mhz (7) mode 2: dual dac mode, 2 interpolation, f dac = 320 msps, f out = 20 mhz (8) mode 5: quadrature modulation mode, 4 interpolation, fs/4 mixing, f dac = 320 msps, f out = 100 mhz (9) mode 7: quadrature modulation mode, 4 interpolation, nco running at 320 mhz, f dac = 320 msps, f out = 100 mhz (10) mode 9: ssb modulation mode, 4 interpolation, fs/4 mixing, f dac = 320 msps, f out = 100 mhz (11) mode 11: ssb modulation mode, 4 interpolation, nco running at 320 mhz, f out = 100 mhz, maximum operating condition over operating free-air temperature range, avdd = 3.3 v, clkvdd = 3.3 v, pllvdd = 0 v, iovdd = 3.3 v, dvdd = 1.8 v, iout fs = 20 ma, external clock mode, differential transformer-coupled output, 50-w doubly terminated load (unless otherwise noted) parameter test conditions min typ max unit analog output f clk maximum output update rate 500 msps t s(dac) output settling time to 0.1% mid-scale transition 12 ns t pd output propagation delay 2.5 ns t r(iout) (2) output rise time 10% to 90% 2.5 ns t f(iout) (2) output fall time 90% to 10% 2.5 ns ac performance?1:1 impedance-ratio transformer first nyquist zone < f data /2, 4 interpolation, dual dac mode, 89 f data = 52 msps, f out = 14 mhz, t a = 25c first nyquist zone < f data /2, 4 interpolation, dual dac mode, f data = 160 msps, f out = 20 mhz, full bypass,t a = t min to 68 79 t max for min, 25c for typ, iovdd = 1.8 v for typ sfdr spurious free dynamic range dbc 2 interpolation, dual dac mode, f data = 160 msps, f out = 72 41 mhz, t a = 25c, iovdd = 1.8 v 2 interpolation, dual dac mode, f data = 160 msps, f out = 68 61 mhz, t a = 25c, iovdd = 1.8 v (1) specifications subject to change without notice (2) measured single-ended into 50-w load 8 www .ti.com
electrical characteristics (digital specifications) (1) dac5686 slws147b ? april 2003 ? revised august 2004 electrical characteristics (ac specifications) (continued) over operating free-air temperature range, avdd = 3.3 v, clkvdd = 3.3 v, pllvdd = 0 v, iovdd = 3.3 v, dvdd = 1.8 v, iout fs = 20 ma, external clock mode, differential transformer-coupled output, 50-w doubly terminated load (unless otherwise noted) parameter test conditions min typ max unit first nyquist zone < f data /2, f data = 100 msps, 80 f out = 5 mhz, iovdd = 1.8 v, f dac = 400 msps snr signal-to-noise ratio db first nyquist zone < f data /2, f data = 78 msps, f out = 15.6 mhz, 15.8 mhz, 16.2 mhz, 16.4 mhz, 72 iovdd = 1.8 v, f dac = 314 msps single carrier w-cdma with 3.84-mhz bw, 5-mhz spacing, centered at if, testmodel 1, 10 ms, f data = 122.88 msps, 72 baseband, dual dac, 2 interpolation, f out = 245 msps single carrier w-cdma with 3.84-mhz bw, 5-mhz spacing, centered at if, testmodel 1, 10 ms, f data = 76.8 msps, if 77 = 19.2 mhz, dual dac, 2 interpolation, f out = 153.6 msps single carrier w-cdma with 3.84-mhz bw, 5-mhz spacing, centered at if, testmodel 1, 10 ms, f data = 122.88 msps, 76 if = 30.72 mhz, dual dac, 2 interpolation, f dac = 245 msps aclr adjacent channel power ratio db single carrier w-cdma with 3.84-mhz bw, 5-mhz spacing, centered at if, testmodel 1, 10 ms, f data = 61.44 msps, 73 if = 61.44 mhz, quad mode, fs/4, 4 interpolation, f dac = 245 msps two-carrier w-cdma with 3.84-mhz bw, 5-mhz spacing, centered at if, testmodel 1, 10 ms, f data = 122.88 msps, 72 if = 30.72 mhz, dual dac, 2 interpolation, f dac = 245 msps four-carrier w-cdma with 3.84-mhz bw, 5-mhz spacing, centered at if, testmodel 1, 10 ms, f data = 121.88 msps, 64 complex if - 30.72 mhz, quad mode, fs/4, 4 interpolation, if = 92.16 mhz f data = 160 msps, f out = 60.1 and 61.1 mhz, 2 interp- olation, 74 320 msps, iovdd = 1.8 v, each tone at ?6 dbfs third-order two-tone imd3 dbc intermodulation f data = 100 msps, f out = 15.1 and 16.1 mhz, 2 interp- olation, 84 200 msps, iovdd = 1.8 v, each tone at ?6 dbfs f data = 100 msps, f out = 15.6 mhz, 15.8 mhz, 16.2 mhz, imd four-tone intermodulation 16.4 mhz, 4 interpolation, 400 msps, iovdd = 1.8 v, each 85 dbc tone at ?12 dbfs over operating free-air temperature range, avdd = 3.3 v, clkvdd = 3.3 v, pllvdd = 3.3 v, iovdd = 3.3 v, dvdd = 1.8 v, iout fs = 20 ma (unless otherwise noted) parameter test conditions min typ max unit cmos interface v ih high-level input voltage 2 3 v v il low-level input voltage 0 0 0.8 v i ih high-level input current ?40 40 a i il low-level input current ?40 40 a input capacitance 5 pf i l = ?100 a iovdd ? 0.2 high-level output voltage, v oh v plllock, sdo, sdio (i/o) i l = ?8 ma 0.8 iovdd (1) specifications subject to change without notice. 9 www .ti.com
dac5686 slws147b ? april 2003 ? revised august 2004 electrical characteristics (digital specifications) (continued) over operating free-air temperature range, avdd = 3.3 v, clkvdd = 3.3 v, pllvdd = 3.3 v, iovdd = 3.3 v, dvdd = 1.8 v, iout fs = 20 ma (unless otherwise noted) parameter test conditions min typ max unit i l = 100 a 0.2 low-level output voltage, v ol v plllock, sdo, sdio (i/o) i l = 8 ma 0.22 iovdd pll input data rate supported 1 160 msps at 600-khz offset, measured at dac output, 25-mhz 0-dbfs tone, 128 f data = 125 msps, 4 interpolation phase noise dbc/hz at 6-mhz offset, measured at dac output, 25-mhz 0-dbfs tone, f data 151 = 125 msps, 4 interpolation vco minimum frequency pll_rng = 00 (nominal) 120 mhz vco maximum frequency pll_rng = 00 (nominal) 500 mhz nco nco clock (dac update rate) 320 mhz serial port timing setup time, sdenb to rising edge t su(sdenb) 20 ns of sclk setup time, sdio valid to rising t su(sdio) 10 ns edge of sclk hold time, sdio valid to rising t h(sdio) 5 ns edge of sclk t sclk period of sclk 100 ns t sclkh high time of sclk 40 ns t sclkl low time of sclk 40 ns data output delay after falling t d(data) 10 ns edge of sclk parallel data input timing (pll mode, clk1 input) setup time, data valid to rising t su(data) 0.3 ?0.4 ns edge of clk1 hold time, data valid after rising t h(data) 1.2 0.6 ns edge of clk1 parallel data input timing (dual clock mode, clk1 and clk2 input) setup time, data valid to rising t su(data) ?0.4 ns edge of clk1 hold time, data valid after rising t h(data) 0.6 ns edge of clk1 timing parallel data input (external clock mode, clk2 input) high-impedance load on plllock. setup time, data valid to rising t su(data) note that t su increases with a 4.6 3 ns edge of plllock lower-impedance load. high-impedance load on plllock. hold time, data valid after rising note that t h decreases (becomes t h(data) ?0.8 ?2.4 ns edge of plllock more negative) with a lower-impedance load. high-impedance load on plllock. delay from clk2 rising edge to note that plllock delay in- t d(plllock) 2.5 4.2 6.5 ns plllock rising edge creases with a lower-impedance load. 10 www .ti.com
typical characteristics dac5686 slws147b ? april 2003 ? revised august 2004 integral nonlinearity vs input code figure 1. differential nonlinearity vs input code figure 2. 11 www .ti.com ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 0 10000 20000 30000 40000 50000 60000 70000 input code inl integral nonlinearity error lsb ?1 1 3 5 7 9 11 13 15 0 10000 20000 30000 40000 50000 60000 70000 input code dnl differential nonlinearity error lsb
dac5686 slws147b ? april 2003 ? revised august 2004 typical characteristics (continued) in-band spurious-free dynamic range vs single-tone spectrum output frequency figure 3. figure 4. out-of-band spurious-free dynamic range vs output frequency single-tone spectrum figure 5. figure 6. 12 www .ti.com f frequency mhz ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 0 50 100 150 200 250 f d a t a = 125 msps f i n = 20 mhz dual dac mode4 interpolation power dbm 50 55 60 65 70 75 80 85 90 10 15 20 25 30 35 40 45 50 f o output frequency mhz f d a t a = 125 msps dual dac mode4 interpolation in-band = 062.5 mhz sfdr in-band spurious-free dynamic range dbc 0 dbf s 12 dbf s 6 dbf s f o output frequency mhz 40 45 50 55 60 65 70 75 80 10 15 20 25 30 35 40 45 50 f d a t a = 125 msps dual dac mode4 interpolation out-of-band = 62.5 mhz250 mhz sfdr out-of-band spurious-free dynamic range dbc 0 dbf s 12 dbf s 6 dbf s f frequency mhz ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 0 25 50 75 100 125 150 f d a t a = 75 msps f i n = none nco onf o u t = 100 mhz quad mode4 interpolation power dbm
dac5686 slws147b ? april 2003 ? revised august 2004 typical characteristics (continued) two-tone imd3 vs output frequency two-tone imd performance figure 7. figure 8. two-tone imd3 vs output frequency two-tone imd performance figure 9. figure 10. 13 www .ti.com f o output frequency mhz 65 70 75 80 85 90 95 10 15 20 25 30 35 40 45 50 55 60 t wo-t one imd3 dbc 0.5 mhz 2 mhz f d a t a = 150 msps dual dac mode2 interpolation f frequency mhz ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 15 20 25 30 power dbm f d a t a = 150 msps f i n 1 = 19.5 mhz f i n 2 = 20.5 mhz dual dac mode2 interpolation f o output frequency mhz 55 60 65 70 75 80 85 90 10 30 50 70 90 110 130 150 f d a t a = 80 msps nco onquad mode 4 interpolation t wo-t one imd3 dbc 0.5 mhz 2 mhz f frequency mhz ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 60 65 70 75 80 f d a t a = 80 msps f i n 1 = 0.5 mhz f i n 2 = 0.5 mhz nco = 70 mhzquad mode 4 interpolation power dbm
dac5686 slws147b ? april 2003 ? revised august 2004 typical characteristics (continued) two-tone imd performance wcdma test model 1: single carrier figure 11. figure 12. wcdma test model 1: dual carrier wcdma test model 1: dual carrier figure 13. figure 14. 14 www .ti.com f frequency mhz ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 140 145 150 155 160 f d a t a = 80 msps f i n 1 = 0.5 mhz f i n 2 = 0.5 mhz nco = 150 mhzquad mode 4 interpolation power dbm f frequency mhz ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 18 22 26 30 34 38 42 power dbm f d a t a = 122.88 msps f i n = 30.72 mhz aclr = 78.6 db4 interpolation dual dac mode f frequency mhz ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 15 20 25 30 35 40 45 power dbm f d a t a = 122.88 msps f i n = 30.72 mhz aclr = 71.69 db4 interpolation dual dac mode f frequency mhz ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 46 51 56 61 66 71 76 power dbm f d a t a = 122.88 msps f i n = baseband complex aclr = 69.08 db2 interpolation quad mode
dac5686 slws147b ? april 2003 ? revised august 2004 typical characteristics (continued) wcdma test model 1: four carrier wcdma test model 1: dual carrier figure 15. figure 16. vco gain vs vco frequency figure 17. 15 www .ti.com f frequency mhz ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 72 77 82 87 92 97 102 107 112 power dbm f d a t a = 122.88 msps f i n = 30.72 mhz complex aclr = 63.29 db4 interpolation quad mode f frequency mhz ?110 ?90 ?70 ?50 ?30 ?10 138 143 148 153 158 163 168 power dbm f d a t a = 122.88 msps f i n = 30.72 mhz complex aclr = 58.58 db4 interpolation quad mode f v c o vco frequency mhz 0 100 200 300 400 500 600 0 100 200 300 400 500 600 700 g v c o vco gain mhz/v boost for 45% boost for 15% boost for 30% boost for 0%
detailed description dual-channel mode single-sideband mode dac5686 slws147b ? april 2003 ? revised august 2004 in dual-channel mode, interpolation filtering increases the dac update rate, thereby reducing sinx/x rolloff and enabling relaxed analog post-filtering, and is useful for baseband i and q modulation or two-channel low-if signals. the dual-channel mode is set by mode[1:0] = 00 in the config_lsb register. figure 18 shows the data path architecture in dual-channel mode. the a- and b-data paths, which are independent, consist of four cascaded half-band interpolation filters, followed by an optional inverse sinc filter. interpolation filtering is selected as 2, 4, 8, or 16 by sel[1:0] in the config_lsb register. magnitude spectral responses of each filter are presented following in the section on digital filtering. full bypass of all the interpolation filters is selected by fbypass in the config_lsb register. the inverse sinc filter is intended for use in single-sideband and quadrature modulation modes and is of limited benefit in dual-channel mode. figure 18. data path in dual-channel mode single-sideband (ssb) mode provides optimum interfacing to analog quadrature modulators. the ssb mode is selected by mode[1:0] = 01 in the config_lsb register. figure 19 shows the data path architecture in single-sideband mode. complex baseband i and q are input to the dac5686, which in turn performs a complex mix, resulting in hilbert transform pairs at the outputs of the dac5686's two dacs. nco mixing frequencies are programmed through 32-bit freq (4 registers); 16-bit phase adjustments are programmed through phase (2 registers). the nco operates at the dac update rate; thus, increased amounts of interpolation allow for higher ifs. more details for the nco are provided as follows. for mixing to f dac /4, dac5686 provides a specific architecture that exploits the {? ?1 0 1 0 ?} resultant streams from sin and cos; the nco is shut off in this mode to conserve power. f dac /4 mix mode is implemented by deasserting nco in register config_msb while in single-sideband or quadrature modulation mode. 16 www .ti.com fir1 fir2 fir3 fir4 ioutb1ioutb2 iout a1 iout a2 16-bit dac fir5 x sin(x) da[15:0]db[15:0] 2f d a t a 2 16 f d a t a 8f d a t a 4f d a t a 16f d a t a f d a t a 2 a gain a offset fir1 fir2 fir3 fir4 16-bit dac fir5 x sin(x) 2f d a t a 8f d a t a 4f d a t a 16f d a t a 2 b offset b gain demux
dac5686 slws147b ? april 2003 ? revised august 2004 detailed description (continued) figure 19. data path in ssb mode figure 20 shows the dac5686 interfaced to an rf quadrature modulator. the outputs of the complex mixer stage can be expressed as: a(t) = i(t)cos(w c t) ? q(t)sin(w c t) = m(t) b(t) = i(t)sin(w c t) + q(t)cos(w c t) = m h (t) where m(t) and m h (t) connote a hilbert transform pair. upper single-sideband up-conversion is achieved at the output of the analog quadrature modulator, whose output is expressed as: if(t) = a(t)cos(w c + w 1 )t ? b(t)sin(w c + w 1 )t flexibility is provided to the user by allowing for the selection of ?b(t) out, which results in lower-sideband up-conversion. this option is selected by ssb in the config_msb register. figure 21 depicts the magnitude spectrum along the signal path during single-sideband up-conversion for real input. further flexibility is provided to the user by allowing for the inverse of sin to be used in the complex mixer by programming rspect in the config_usb register. the four combinations of rspect and ssb allow the user to select one of four complex spectral bands to input to a quadrature modulator (see figure 22 ). 17 www .ti.com iout a1 iout a2 16-bit dac da[15:0] db[15:0] 2 16 f d a t a f d a t a 2 16 a gain a offset fir5 x sin(x) a cos sin 2 16 ++/? ioutb1ioutb2 16-bit dac b gain b offset x sin(x) b sin cos ++ demux
dac5686 slws147b ? april 2003 ? revised august 2004 detailed description (continued) figure 20. dac5686 in ssb mode with quadrature modulator figure 21. spectrum after first and second up-converson for real input 18 www .ti.com ++ + ? i q dac dac ab lo quadrature modulator dac5686 cos( w c t) sin( w c t) sin( w c t) cos( w c t) a(t) = i(t)cos( w c t) q(t)sin( w c t) b(t) = i(t)sin( w c t) q(t)cos( w c t) cos( w l o t) sin( w l o t) 0 90 if(t) = i(t)cos( w c + w l o )t q(t)sin( w c + w l o )t 0 0 w c w w w w l o w l o w c w l o + w c real input spectrum to dac5686 complex input spectrum to quadrature modulator output spectrum to quadrature modulator
dac gain and offset control quadrature modulation mode dac5686 slws147b ? april 2003 ? revised august 2004 detailed description (continued) figure 22. spectrum after first and second up-converson for complex input to compensate for the sinx/x rolloff of the zero-order hold of the dacs, the dac5686 provides an inverse sinc fir, which provides high-frequency boost. the magnitude spectral response of this filter is presented in the digital filters section. unmatched gains and offsets at the rf quadrature modulator result in unwanted sideband and local-oscillator feedthrough. gain and offset imbalances between the two dacs are compensated for by programming daca_gain, dacb_gain, daca_offset, and dacb_offset in registers 0x0a through 0x0f (see the following register descriptions). the dac gain value controls the full-scale output current. the dac offset value adds a digital offset to the digital data before digital-to-analog conversion. care must be taken when using the offset by restricting the dynamic range of the digital signal to prevent saturation when the offset value is added to the digital signal. in quadrature modulation mode, on-chip mixing of complex i and q inputs provides the final baseband-to-if up-conversion. quadrature modulation mode is selected by mode[1:0] = 10 in the config_lsb register. figure 23 shows the data path architecture in quadrature modulation mode. complex baseband i and q from the asic/fpga are input to the dac5686, which in turn quadrature modulates i and q to produce the final if single-sideband spectrum. dac a is held constant, while dac b presents the dac5686 quadrature modulator mode output. 19 www .ti.com complex input spectrums to quadrature modulator 0 w w c w c 0 w 0 w 0 w 0 w rspect = 0 ssb = 0 rspect = 1 ssb = 0 rspect = 1 ssb = 1 rspect = 0 ssb = 1 complex input spectrum to dac5686 w c w c w c w c w c w c
serial interface dac5686 slws147b ? april 2003 ? revised august 2004 detailed description (continued) nco mixing frequencies are programmed through 32-bit freq (4 registers); 16-bit phase adjustments are programmed through phase (2 registers). the nco operates at the dac update rate; thus, increased amounts of interpolation allow for higher ifs. more details for the nco are provided in the nco section. for mixing to f dac /4, the dac5686 provides a specific architecture that exploits the {? ?1 0 1 0 ?} resultant streams from sin and cos; the nco is shut off in this mode to conserve power. f dac /4 mix mode is implemented by deasserting nco in register config_msb while in single-sideband or quadrature modulation mode. figure 23. data path in quadrature modulation mode in quadrature modulation mode, only one output from the complex mixer stage is routed to the b dac. the output can be expressed as: b(t) = i(t)sin(w c t) + q(t)cos(w c t) or b(t) = i(t)cos(w c t) ? q(t)sin(w c t) single-sideband up-conversion is achieved when i and q are hilbert transform pairs. upper- or lower-sideband up-conversion is selected by ssb in the config_msb register, which selects the output from the mixer stage that is routed out. the offset and gain features for the b dac, as previously described, are functional in the quadrature mode. the serial port of the dac5686 is a flexible serial interface that communicates with industry-standard microprocessors and microcontrollers. the interface provides read/write access to all registers used to define the operating modes of the dac5686. it is compatible with most synchronous transfer formats and can be configured as a 3- or 4-pin interface by sif4 in register config_msb. in both configurations, sclk is the serial-interface input clock and sdenb is the serial-interface enable. for the 3-pin configuration, sdio is a bidirectional pin for both data-in and data-out. for the 4-pin configuration, sdio is data-in only and sdo is data-out only. 20 www .ti.com fir1 fir2 fir3 fir4 ioutb1ioutb2 16-bit dac da[15:0]db[15:0] 2 16 f d a t a f d a t a 2 b gain b offset fir1 fir2 fir3 fir4 2 2 2 2 2 2 2 fir5 x sin(x) + +/? cos sin sin cos demux
serial-port timing diagrams dac5686 slws147b ? april 2003 ? revised august 2004 detailed description (continued) each read/write operation is framed by signal sdenb (serial data enable bar) asserted low for 2 to 5 bytes, depending on the data length to be transferred (1?4 bytes). the first frame byte is the instruction cycle, which identifies the following data transfer cycle as read or write, how many bytes to transfer, and the address to/from which to transfer the data. table 1 indicates the function of each bit in the instruction cycle and is followed by a detailed description of each bit. frame bytes 2 through 5 comprise the data to be transferred. table 1. instruction byte of the serial interface msb lsb bit 7 6 5 4 3 2 1 0 description r/w n1 n0 ? a3 a2 a1 a0 r/w: identifies the following data transfer cycle as a read or write operation. a high indicates a read operation from the dac5686 and a low indicates a write operation to the dac5686. n[1:0]: identifies the number of data bytes to be transferred per table 2 . data is transferred msb-first. table 2. number of transferred bytes within one communication frame n1 n0 description 0 0 transfer 1 byte 0 1 transfer 2 bytes 1 0 transfer 3 bytes 1 1 transfer 4 bytes a4: unused a[3:0]: identifies the address of the register to be accessed during the read or write operation. for multibyte transfers, this address is the starting address and the address decrements. note that the address is written to the dac5686 msb-first. figure 24 shows the serial-interface timing diagram for a dac5686 write operation. sclk is the serial-interface clock input to the dac5686. serial data enable sdenb is an active-low input to the dac5686. sdio is serial data-in. input data to the dac5686 is clocked on the rising edges of sclk. 21 www .ti.com
dac5686 slws147b ? april 2003 ? revised august 2004 figure 24. serial-interface write timing diagram figure 25 shows the serial-interface timing diagram for a dac5686 read operation. sclk is the serial-interface clock input to the dac5686. serial data enable sdenb is an active-low input to the dac5686. sdio is serial data-in during the instruction cycle. in the 3-pin configuration, sdio is data-out from the dac5686 during the data transfer cycle(s), while sdo is in a high-impedance state. in the 4-pin configuration, sdo is data-out from the dac5686 during the data transfer cycle(s). sdo is never placed in the high-impedance state in the four-pin configuration. figure 25. serial-interface read timing diagram 22 www .ti.com r/w t s c l k l sdenb sclk sdio n1 n0 ? a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 sdenb sclk sdio instruction cycle data t ransfer cycle(s) t s ( s d e n b ) t s c l k t h ( s d i o ) t s ( s d i o ) t s c l k h r/w d7 sdenb sclk sdio n1 n0 ? a3 a2 a1 a0 d6 d5 d4 d3 d2 d0 0 instruction cycle data t ransfer cycle(s) sdo d7 d6 d5 d4 d3 d2 d1 d0 0 3-pin configuration output 4-pin configuration output sdenb sclk sdio data n data n?1 sdo t d ( d a t a ) d1
clock generation dac5686 slws147b ? april 2003 ? revised august 2004 in the dac5686, the internal clocks (1, 2, 4, 8, and 16, as needed) for the logic, fir interpolation filters, and dac are derived from a clock at either the input data rate using an internal pll (pll clock mode) or the dac output sample rate (external clock mode). power for the internal pll blocks (pllvdd and pllgnd) is separate from power for the other clock generation blocks (clkvdd and clkgnd), thus minimizing phase noise within the pll. the dac5686 has three clock modes for generating the internal clocks (1, 2, 4, 8, and 16, as needed) for the logic, fir interpolation filters, and dacs. the clock mode is set using the pllvdd pin and dual_clk in register config_usb. a block diagram for the clock generation circuit is shown in figure 27 . 1. pllvdd = 0v and dual_clk = 0: external clock mode in external clock mode, the user provides a clock signal at the dac output sample rate through clk2/clk2c. clk1/clk1c and the internal pll are not used, so the lpf circuit is not applicable. the input data rate clock and interpolation rate are selected by the registers sel[1:0], and are output through the plllock pin. it is common to use the plllock clock to drive the chip that sends the data to the dac; otherwise, there is phase ambiguity regarding how the dac divides down to the input sample rate clock and an external clock divider divides down. (for a divide by n, there are n possible phases.) the phase ambiguity can also be solved by using phstr pin with a synchronization signal. 2. pllvdd = 3.3v (dual_clk can be 0 or 1 and is ignored): pll clock mode power for the internal pll blocks (pllvdd and pllgnd) is separate from power for the other clock generation blocks (clkvdd and clkgnd), thus minimizing pll phase noise. in pll clock mode, the dac is driven at the input sample rate (unless the data is multiplexed) through clk1/clk1c. clk2/clk2c is not used. in this case, there is no phase ambiguity on the clock. the dac generates the higher speed dac sample rate clock using an internal pll/vco. in pll clock mode, the user provides a differential external reference clock on clk1/clk1c. a type-4 phase-frequency detector (pfd) in the internal pll compares this reference clock to a feedback clock and drives the pll to maintain synchronization between the two clocks. the feedback clock is generated by dividing the vco output by 1, 2, 4, or 8 as selected by the prescaler (div[1:0]). the output of the prescaler is the dac sample rate clock and is divided down to generate clocks at ?2, ?4, ?8, and ?16. the feedback clock is selected by the registers sel[1:0], an then is fed back to the pfd for synchronization to the input clock. the feedback clock is also used for the data input rate, so the ratio of dac output clock to feedback clock sets the interpolation rate of the dac5686. the plllock pin is an output that indicates when the pll has achieved lock. an external rc low-pass pll filter is provided by the user at pin lpf. see the low-pass filter section for filter setting calculations. this is the only mode where the lpf filter applies. 3. pllvdd = 0v and dual_clk = 1: dual clock mode in dual clock mode, the dac is driven at the dac sample rate through clk2/clk2c and at the input data rate through clk1/clk1c. the dual clock mode has the advantage of a clean external clock for the dac sampling without the phase ambiguity. the edges of clk1 and clk2 must be aligned to within t _align (see figure 26 ), defined as where f clk2 is the clock frequency of clk2. for example, t _align = 0.5 ns at f clk2 = 500 mhz and 1.5 ns at f clk2 = 250 mhz. 23 www .ti.com t _ a l i g n 1 2 f c l k 2 0 . 5 n s
dac5686 slws147b ? april 2003 ? revised august 2004 figure 26. dac and data clock mode the cdc7005 from texas instruments is recommended for providing phase-aligned clocks at different frequencies for this application. table 3 provides a summary of the clock configurations with corresponding data rate ranges. figure 27. clock-generation architecture table 3. clock-mode configuration clock mode pllvdd div[1:0] sel[1:0] data rate (msps) plllock pin function non-interleaved input data; internal pll off; da[15:0] data rate matches db[15:0] data rate. external 2 0 v xx 00 dc to 160 external clk2/clk2c clock ? 2 external 4 0 v xx 01 dc to 125 external clk2/clk2c clock ? 4 external 8 0 v xx 10 dc to 62.5 external clk2/clk2c clock ? 8 external 16 0 v xx 11 dc to 31.25 external clk2/clk2c clock ? 16 external dual clock 2 0 v xx 00 dc to 160 none - held low external dual clock 4 0 v xx 01 dc to 125 none - held low 24 www .ti.com t h clk2clk1 d[0:15] d < t a l i g n t s t0002-01 pll vdd pllgnd clkgnd clkvdd pfd charge pump vco /1/2 /4 /8 clk_16xdac sample clock d[15:0] div[1:0] pll vdd sel[1:0] pll vdd plllock lpf data s 1 0 clk_2x /2 /2 /2 /2 clk_1x clk_4x clk_8x clk1 clk1c clk buffer clk2 clk2c clk buffer
dac5686 slws147b ? april 2003 ? revised august 2004 table 3. clock-mode configuration (continued) clock mode pllvdd div[1:0] sel[1:0] data rate (msps) plllock pin function external dual clock 8 0 v xx 10 dc to 62.5 none - held low external dual clock 16 0 v xx 11 dc to 31.25 none - held low interleaved input data on the da[15:0] input pins; internal pll off external 2 0 v xx 00 dc to 80 external clk2/clk2c clock ? 2 external 4 0 v xx 01 dc to 80 external clk2/clk2c clock ? 4 external 8 0 v xx 10 dc to 62.5 external clk2/clk2c clock ? 8 external 16 0 v xx 11 dc to 31.25 external clk2/clk2c clock ? 16 external dual clock 2 0 v xx 00 dc to 80 none - held low external dual clock 4 0 v xx 01 dc to 62.5 none - held low external dual clock 8 0 v xx 10 dc to 31.25 none - held low external dual clock 16 0 v xx 11 dc to 15.625 none - held low non-interleaved input data; internal pll on; da[15:0] data rate matches db[15:0] data rate. internal 2 3.3 v 00 00 125 to 160 internal pll lock indicator internal 2 3.3 v 01 00 62.5 to 125 internal pll lock indicator internal 2 3.3 v 10 00 31.25 to 62.5 internal pll lock indicator internal 2 3.3 v 11 00 15.63 to 31.25 internal pll lock indicator internal 4 3.3 v 00 01 62.5 to 125 internal pll lock indicator internal 4 3.3 v 01 01 31.25 to 62.5 internal pll lock indicator internal 4 3.3 v 10 01 15.63 to 31.25 internal pll lock indicator internal 4 3.3 v 11 01 7.8125 to 15.625 internal pll lock indicator internal 8 3.3 v 00 10 31.25 to 62.5 internal pll lock indicator internal 8 3.3 v 01 10 15.63 to 31.25 internal pll lock indicator internal 8 3.3 v 10 10 7.8125 to 15.625 internal pll lock indicator internal 8 3.3 v 11 10 3.9 to 7.8125 internal pll lock indicator internal 16 3.3 v 00 11 15.625 to 31.25 internal pll lock indicator internal 16 3.3 v 01 11 7.8125 to 15.625 internal pll lock indicator internal 16 3.3 v 10 11 3.9062 to 7.8125 internal pll lock indicator interleaved input data on the da[15:0] input pins; internal pll on internal 2 3.3 v 00 00 not recommended internal pll lock indicator internal 2 3.3 v 01 00 62.5 to 80 internal pll lock indicator internal 2 3.3 v 10 00 31.25 to 62.5 internal pll lock indicator internal 2 3.3 v 11 00 15.625 to 31.25 internal pll lock indicator internal 4 3.3 v 00 01 62.5 to 80 internal pll lock indicator internal 4 3.3 v 01 01 31.25 to 62.5 internal pll lock indicator internal 4 3.3 v 10 01 15.625 to 31.25 internal pll lock indicator internal 4 3.3 v 11 01 7.8125 to 15.625 internal pll lock indicator internal 8 3.3 v 00 10 31.25 to 62.5 internal pll lock indicator internal 8 3.3 v 01 10 15.625 to 31.25 internal pll lock indicator internal 8 3.3 v 10 10 7.8125 to 15.625 internal pll lock indicator internal 8 3.3 v 11 10 3.9062 to 7.8125 internal pll lock indicator internal 16 3.3 v 00 11 15.625 to 31.25 internal pll lock indicator internal 16 3.3 v 01 11 7.8125 to 15.625 internal pll lock indicator internal 16 3.3 v 10 11 3.9062 to 7.8125 internal pll lock indicator internal 16 3.3 v 11 11 1.9531 to 3.9062 internal pll lock indicator 25 www .ti.com
dual-bus mode dac5686 slws147b ? april 2003 ? revised august 2004 in dual-bus mode, two separate parallel data streams (i and q) are input to the dac5686 on data bus da and data bus db. dual-bus mode is selected by setting interl to 0 in the config_msb register. figure 28 shows the dac5686 data path in dual-bus mode. the dual-bus mode timing diagram is shown in figure 29 for the pll clock mode and in figure 30 for the external clock mode. figure 28. dual-bus mode data path figure 29. dual-bus mode timing diagram (pll mode) figure 30. dual-bus mode timing diagram (external clock mode) 26 www .ti.com ioutb1ioutb2 iout a1 iout a2 16-bit dac da[15:0]db[15:0] 2f d a t a 2 16 f d a t a f d a t a 2 16-bit dac 2f d a t a 2 fir1 edge t riggered input latches ? ? ? ? ? ? demux clk1 da[15:0] db[15:0] t s ( d a t a ) t h ( d a t a ) a 0 a 1 a 2 a n a n + 1 a 3 b 0 b 1 b 2 b n b n + 1 b 3 clk2 da[15:0] db[15:0] t s ( d a t a ) t h ( d a t a ) a 0 a 1 a 2 a n a n + 1 a 3 b 0 b 1 b 2 b n b n + 1 b 3 plllock t d ( p l l l o c k )
interleave bus mode dac5686 slws147b ? april 2003 ? revised august 2004 in interleave bus mode, one parallel data stream with interleaved data (i and q) is input to the dac5686 on data bus da. interleave bus mode is selected by setting interl to 1 in the config_msb register. figure 31 shows the dac5686 data path in interleave bus mode. the interleave bus mode timing diagram is shown in figure 32 . figure 31. interleave bus mode data path figure 32. interleave bus mode timing diagram using txenable interleaved user data on data bus da is alternately multiplexed to internal data channels a and b. data channels a and b can be synchronized using either the qflag pin or the txenable pin. when qflag in register config_usb is 0, transitions on txenable identify the interleaved data sequence. the first data after the rising edge of txenable is latched with the rising edge of clk as channel-a data. data is then alternately distributed to b and a channels with successive rising edges of clk. when qflag is 1, the qflag pin is used as an output to identify the interleaved data sequence. qflag high identifies data as channel b (see figure 33 ). 27 www .ti.com ioutb1ioutb2 iout a1 iout a2 16-bit dac 2f d a t a 2 16 f d a t a f d a t a 2 16-bit dac 2f d a t a 2 fir1 edge t riggered input latches ? ? ? ? ? ? da[15:0] demux da[15:0] t s ( d a t a ) t h ( d a t a ) a 0 b 0 a 1 a n b n b 1 txenable t s ( t x e n a b l e ) clk1 or plllock
clock synchronization using the phstr pin in external clock mode dac5686 slws147b ? april 2003 ? revised august 2004 figure 33. interleave bus mode timing diagram using qflag the dual-clock mode is selected by setting dualclk high in the config_usb register. in this mode, the dac5686 uses both clock inputs; clk1/clk1c is the input data clock, and clk2/clk2c is the external clock. the edges of the two input clocks must be phase-aligned within 500 ps to function properly. in external clock mode, the dac5686 is clocked at the dac output sample frequency (clk2 and clk2c). for an interpolation rate n, there are n possible phases for the dac input clock on the plllock pin (see figure 34 for n = 4). figure 34. four possible plllock phases for n = 4 in external clock mode to synchronize plllock input clocks across multiple dac5686 chips, a sync signal on the phstr pin is used. during configuration of the dac5686 chips, address sync_phstr in config_msb is set high to enable the phstr input pin as a sync input to the clock dividers generating the input clock. a simultaneous low-to-high transition on the phstr pin for each dac5686 then forces the input clock on plllock to start in phase on each dac. see figure 35 . 28 www .ti.com da[15:0] t s ( d a t a ) t h ( d a t a ) a 0 b 0 a 1 a n b n b 1 qflag clk1 or plllock t0001-01 clk2 plllock clk2c t0003-01
digital filters dac5686 slws147b ? april 2003 ? revised august 2004 figure 35. using phstr to synchronize plllock input clock for multiple dacs in external clock mode the phstr transition has a setup and hold time relative to the dac output sample clock (t s_phstr and t h_phstr ) equal to 50% of the dac output sample clock period up to a maximum of 1 ns. at 500 mhz, the setup and hold times are therefore 0.5 ns. the phstr signal can remain high after synchronization, or can return low. a new low-to-high transition resynchronizes the input clock. note that the phstr transition also resets the nco accumulator. figure 36 through figure 39 show magnitude spectrum responses for 2, 4, 8, and 16 fir interpolation filtering. the transition band is from 0.4 to 0.6 f data with < 0.002-db pass-band ripple and > 80-db stop-band attenuation for all four configurations. the filters are linear phase. the sel field in register config_lsb selects the interpolation filtering rate as 2, 4, 8, or 16; interpolation filtering can be completely bypassed by setting fullbypass in register config_lsb. figure 40 shows the spectral correction of the dac sinx/x rolloff achieved with use of inverse sinc filtering. pass-band ripple from 0 to 0.4 f data is < 0.03 db. inverse sinc filtering is enabled by sinc in register config_msb. 29 www .ti.com phstr d[0:15] plllock dac1 clk2 clk2c t h _ p h s t r 1/f p l l l o c k = n/f c l k 2 t s _ p h s t r t d _ c l k t h t s t0004-01
dac5686 slws147b ? april 2003 ? revised august 2004 magnitude magnitude vs vs frequency frequency figure 36. magnitude spectrum for figure 37. magnitude spectrum for 2 interpolation (db) 4 interpolation (db) magnitude magnitude vs vs frequency frequency figure 38. magnitude spectrum for figure 39. magnitude spectrum for 8 interpolation (db) 16 interpolation (db) 30 www .ti.com f/f d a t a ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 magnitude db f/f d a t a ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 magnitude db f/f d a t a ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 magnitude db f/f d a t a ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 0 1 2 3 4 5 6 7 8 magnitude db
dac5686 slws147b ? april 2003 ? revised august 2004 magnitude vs frequency figure 40. magnitude spectrum for inverse sinc filtering the filter taps for interpolation filters fir1 - fir4 and inverse sinc filter fir5 are listed in table 4 . table 4. filter taps for fir1?fir5 fir1 fir2 fir3 fir4 fir5 (invsinc) 8 9 31 -33 1 0 0 0 0 ?3 ?24 ?58 ?219 289 9 0 0 0 512 ?34 58 214 1212 289 400 0 0 2048 0 ?34 ?120 ?638 1212 ?33 9 0 0 0 ?3 221 2521 ?219 1 0 4096 0 ?380 2521 31 0 0 619 ?638 0 0 -971 214 0 0 1490 ?58 0 0 ?2288 9 0 3649 0 ?6628 0 31 www .ti.com f/f d a c ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 0.0 0.1 0.2 0.3 0.4 0.5 magnitude db rolloff fir corrected
nco dac5686 slws147b ? april 2003 ? revised august 2004 table 4. filter taps for fir1?fir5 (continued) fir1 fir2 fir3 fir4 fir5 (invsinc) 20750 32768 20750 0 ?6628 0 3649 0 ?2288 0 1490 0 ?971 0 619 0 ?380 0 221 0 ?120 0 58 0 ?24 0 8 the dac5686 uses a numerically controlled oscillator (nco) with a 32-bit frequency register and a 16-bit phase register. the nco is used in quadrature-modulation and single-sideband modes to provide sin and cos for mixing. the nco tuning frequency is programmed in registers 0x1 through 0x4. phase offset is programmed is registers 0x5 and 0x6. a block diagram of the nco is shown in figure 41 . figure 41. block diagram of the nco 32 www .ti.com frequency register 32 accumulator 32 reset clk phstr 32 32 phase register 16 16 16 look-up t able sin cos s s 16 16 f d a c
register bit allocation map register descriptions dac5686 slws147b ? april 2003 ? revised august 2004 the nco accumulator is reset to zero when the phstr pin is high and remains at zero until phstr is set low. frequency word freq in the frequency register is added to the accumulator every clock cycle. the output frequency of the nco is: while the maximum clock frequency of the dacs is 500 msps, the maximum clock frequency the nco can operate at is 320 mhz; mixing at dac rates higher than 320 msps requires using the fs/4 mixing option. name r/w ad- bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dress chip_ver r/w 0x00 atest[4:0] version[2:0] read only freq_lsb r/w 0x01 freq_int[7:0] freq_lmidsb r/w 0x02 freq_int[15:8] freq_umidsb r/w 0x03 freq_int[23:16] freq_msb r/w 0x04 freq_int[31:24] phase_lsb r/w 0x05 phase_int[7:0] phase_msb r/w 0x06 phase_int[15:8] config_lsb r/w 0x07 mode[1:0] div[1:0] sel[1:0] counter fbypass config_msb r/w 0x08 ssb interl sinc dith sync_phstr nco sif4 twos config_usb r/w 0x09 dual clk dds_gain[1:0] rspect qflag pll_rng[1:0] rev_bbus daca_offset_lsb r/w 0x0a daca_offset[7:0] daca_gain_lsb r/w 0x0b daca_gain[7:0] daca_offset_gain_ r/w 0x0c daca_offset[10:8] sleepa daca_gain[11:8] msb dacb_offset_lsb r/w 0x0d dacb_offset[7:0] dacb_gain_lsb r/w 0x0e dacb_gain[7:0] dacb_offset_gain_ r/w 0x0f dacb_offset[10:8] sleepb dacb_gain[11:8] msb register name: chip_ver msb lsb atest[4:0] chip_ver[2:0] read only 0 0 0 0 0 1 0 1 chip_ver[3:0]: chip_ver [3:0] stores the device version, initially 0x5. the user can find out which version of the dac5686 is in the system by reading this byte. a_test[4:0]: must be 0 for proper operation. register name: freq_lsb msb lsb freq_int[7:0] 0 0 0 0 0 0 0 0 33 www .ti.com f n c o f r e q f d a c 2 3 2
dac5686 slws147b ? april 2003 ? revised august 2004 freq_int[7:0]: the lower 8 bits of the frequency register in the dds block register name: freq_lmidsb msb lsb freq_int[15:8] 0 0 0 0 0 0 0 0 freq_int[15:8]: the lower mid 8 bits of the frequency register in the dds block register name: freq_umidsb msb lsb freq_int[23:16] 0 0 0 0 0 0 0 0 freq_int[23:16]: the upper mid 8 bits of the frequency register in the dds block register name: freq_msb msb lsb freq_int[31:24] 0 0 1 0 0 0 0 0 freq_int[31:24]: the most significant 8 bits of the frequency register in the dds block register name: phase_lsb msb lsb phase_int[7:0] 0 0 0 0 0 0 0 0 phase_int[7:0]: the lower 8 bits of the phase register in the dds block register name: phase_msb msb lsb phase_int[15:8] 0 0 0 0 0 0 0 0 phase_int[15:8]: the most significant 8 bits of the phase register in the dds block register name: config_lsb msb lsb mode[1:0] div[1:0] sel[1:0] counter full_bypass 0 0 0 0 0 0 0 1 mode[1:0]: controls the mode of the dac5686; summarized in table 5 . table 5. dac5686 modes mode[1:0] dac5686 mode 00 dual-dac 01 single-sideband 10 quadrature 11 dual-dac 34 www .ti.com
dac5686 slws147b ? april 2003 ? revised august 2004 div[1:0]: controls the pll divider value; summarized in table 6 . table 6. pll divide ratios div[1:0] pll divide ratio 00 1 divider 01 2 divider 10 4 divider 11 8 divider sel[1:0]: controls the selection of interpolating filters used; summarized in table 7 . table 7. dac5686 filter configuration sel[1:0] interp. fir setting 00 2 01 4 10 8 11 16 counter: when asserted, the dac5686 goes into counter mode and uses an internal counter as a ramp input to the dac. the count range is determined by the a-side input data da[2:0], as summarized in table 8 . table 8. dac5686 counter mode count range da[2:0] count range 000 all bits d[15:0] 001 lower 7 bits d[6:0] 010 mid 4 bits d[10:7] 100 upper 5 bits d[15:11] full_bypass: when asserted, the interpolation filters and mixer logic are bypassed and the data inputs da[15:0] and db[15:0] go straight to the dac inputs. register name: config_msb msb lsb ssb interl sinc dith sync_phstr nco sif4 twos 0 0 0 0 0 0 0 0 ssb: in single-sideband mode, assertion inverts the b data; in quadrature modulation mode, assertion routes the a data path to dacb instead of the b data path. interl: when asserted, data input to the dac5686 on channel da[15:0] is interpreted as a single interleaved stream (i/q); channel db[15:0] is unused. sinc: assertion enables the invsinc filter. dith: assertion enables dithering in the pll. sync_phstr: assertion enables the phstr input as a sync input to the clock dividers in external single-clock mode. nco: assertion enables the nco. sif4: when asserted, the sif interface becomes a 4-pin interface instead of a 3-pin interface. the sdio pin becomes an input only and the sdo is the output. twos: when asserted, the chip interprets the input data as 2s complement form instead of binary offset. 35 www .ti.com
dac5686 slws147b ? april 2003 ? revised august 2004 register name: config_usb msb lsb dualclk dds_gain[1:0] rspect qflag pll_rng[1:0] rev_bbus 0 0 0 0 0 0 0 0 dualclk: when asserted, the dac5686 uses both clock inputs; clk1/clk1c is the input data clock and clk2/clk2c is the dac output clock. these two clocks must be phase-aligned within 500 ps to function properly. when deasserted, clk2/clk2c is the dac output clock and is divided down to generate the input data clock, which is output on plllock. dual clock mode is only available when pllvdd = 0. dds_gain[1:0]: controls the gain of the dds so that the overall gain of the dds is unity. it is important to ensure that max(abs(cos(wt) + sin(wt))) < 1. at different frequencies, the summation produces different maximum outputs and must be reduced. the simplest is fs/4 mode where the maximum is 1 and the gain multiply should be 1 to maintain unity. however, due to the fact that the digital logic does a divide-by-two in this summation, the gain necessary to achieve unity must be double (dds_gain[1:0] = 01). table 9 shows the digital gain necessary and the actual signal gain needed to make the above equation have a maximum value of 1. table 9. digital gain for dds dds_gain [1:0] digital gain signal gain for unity 00 1.40625 0.703125 01 2 1 10 1.59375 0.7936 11 1.40625 0.703125 rspect: when asserted, the sin term is negated before being used in mixing. this gives the reverse spectrum in single-sideband mode. qflag: when asserted, the qflag pin is used during interleaved data input mode to identify the q sample. when deasserted, the txenable pin transition is used to start an internal toggling signal, which is used to interpret the interleaved data sequence; the first sample clocked into the dac5686 after txenable goes high is routed through the a data path. pll_rng[1:0]: increases the pll vco vtoi current, summarized in table 10 . see figure 17 for the effect on vco gain and range. table 10. pll vco vtol current increase pll_rng[1:0] vtoi current increase 00 nominal 01 15% 10 30% 11 45% rev_bbus[1:0]: when asserted, pin 92 changes from db15 to db0, pin 91 changes from db14 to db1, etc., reversing the order of the db[15:0] pins. register name: daca_offset_lsb (2s complement) msb lsb daca_offset[7:0] 0 0 0 0 0 0 0 0 36 www .ti.com
dac5686 slws147b ? april 2003 ? revised august 2004 daca_offset[7:0]: the lower 8 bits of the daca offset register name: daca_gain_lsb (2s complement) msb lsb daca_gain[7:0] 0 0 0 0 0 0 0 0 daca_gain[7:0]: the lower 8 bits of the daca gain control register. these lower 8 bits are for fine gain control. this word is a 2s complement value that adjusts the full-scale output current over an approximate 4% to ?4% range. register name: daca_offset_gain_msb (2s complement) msb lsb daca_offset[10:8] sleepa daca_gain[11:8] 0 0 0 0 0 0 0 0 daca_offset[10:8]: the upper 3 bits of the daca _offset sleepa: when asserted, daca is put into the sleep mode. daca_gain[11:8]: coarse gain control for daca; the full-scale output current is: where gaincode is the decimal equivalent of daca_gain [11:8] {0?15} and the finegain is daca_gain [1:0] as 2s complement [?127?128]. register name: dacb_offset_lsb (2s complement) msb lsb dacb_offset[7:0] 0 0 0 0 0 0 0 0 dacb_offset[7:0]: the lower 8 bits of the dacb offset register name: dacb_gain_lsb (2s complement) msb lsb dacb_gain[7:0] 0 0 0 0 0 0 0 0 dacb_gain[7:0]: the lower 8 bits of the dacb gain control register. these lower 8 bits are for fine gain control. this word is a 2s complement value that adjusts the full-scale output current over an approximate 4% to ?4% range. register name: dacb_offset_gain_msb (2s complement) msb lsb dacb_offset[10:8] sleepb dacb_gain[11:8] 0 0 0 0 0 0 0 0 37 www .ti.com i f u l l s c a l e 1 6 v e x t i o r b i a s j ( g a i n c o d e 1 ) 1 6 1 f i n e g a i n 3 0 7 2
digital inputs clock input and timing dac5686 slws147b ? april 2003 ? revised august 2004 dacb_offset[10:8]: the upper 3 bits of the daca _offset sleepb: when asserted, dacb is put into the sleep mode. dacb_gain[11:8]: coarse gain control for dacb; the full-scale output current is: where gaincode is the decimal equivalent of dacb_gain [11:8] {0?15} and the finegain is dacb_gain [1:0] as 2s complement [?127?128]. figure 42 shows a schematic of the equivalent cmos digital inputs of the dac5686. da[0:15], db[0:15], sleep, phstr, txenable, qflag, sdio, sclk, and sdenb have pulldown resistors and resetb has a pullup resistor internal to the dac5686. see the specification table for logic thresholds. figure 42. cmos/ttl digital equivalent input figure 43 shows an equivalent circuit for the clock input. figure 43. clock input equivalent circuit 38 www .ti.com i f u l l s c a l e 1 6 v e x t i o r b i a s j ( g a i n c o d e 1 ) 1 6 1 f i n e g a i n 3 0 7 2 da[15:0]db[15:0] sleep phstr txenable qflag sdio sclk sdenb internaldigital in iovdd iognd resetb internaldigital in iovdd iognd clk internal digital in clkc clkgnd r110 k w clkvdd r1 10 k w r2 10 k w r210 k w clkvdd clkvdd
dac5686 slws147b ? april 2003 ? revised august 2004 clock input and timing (continued) figure 44 , figure 45 , and figure 46 show various input configurations for driving the differential clock input (clk/clkc). figure 44. preferred clock input configuration figure 45. driving the dac5686 with a single-ended ttl/cmos clock source figure 46. driving the dac5686 with a differential ecl/pecl clock source 39 www .ti.com r t 200 w clk 1:4 clkc t ermination resistor swing limitation optional, may be bypassed for sine w ave input c a c 0.1 m f r o p t 22 w clk 1:1 clkc optional, reduces clock feed-through c a c 0.01 m f ttl/cmos source r o p t 22 w clk clkc node clkc internally biased to clkvdd 2 ttl/cmos source 0.01 m f r t 130 w c a c 0.1 m f c a c 0.1 m f r t 130 w v t t differential ecl or (l v)pecl source + clkclkc r t 82.5 w r t 82.5 w 100 w
dac transfer function reference operation dac5686 slws147b ? april 2003 ? revised august 2004 clock input and timing (continued) the cmos dacs consist of a segmented array of nmos current sources, capable of delivering a full-scale output current up to 20 ma. differential current switches direct the current of each current source to either one of the complementary output nodes iout1 or iout2. complementary output currents enable differential operation, thus canceling out common-mode noise sources (digital feed-through, on-chip, and pcb noise), dc offsets, even-order distortion components, and increasing signal output power by a factor of two. the full-scale output current is set using external resistor r bias in combination with an on-chip band-gap voltage reference source (1.2 v) and control amplifier. current i bias through resistor r bias is mirrored internally to provide a full-scale output current equal to 16 times i bias . the full-scale current can be adjusted from 20 ma down to 2 ma. the dac5686 delivers complementary output currents iout1 and iout2. output current iout1 equals the approximate full-scale output current when all bits (after the digital processing) are high. full-scale output current flows through terminal iout2 when all input bits are low. the relation between iout1 and iout2 can thus be expressed as: iout1 = iout fs ? iout2 where iout fs is the full-scale output current. the output currents can be expressed as: where code is the decimal representation of the dac data input word. output currents iout1 and iout2 drive resistor loads r l or a transformer with equivalent input load resistance (r l ). this translates into single-ended voltages vout1 and vout2 at terminals iout1 and iout2, respectively, of: the differential output voltage vout diff can thus be expressed as: the latter equation shows that applying the differential output results in doubling of the signal power delivered to the load. because the output currents iout1 and iout2 are complementary, they become additive when processed differentially. note that care should be taken not to exceed the compliance voltages at nodes iout1 and iout2, which would lead to increased signal distortion. the dac5686 comprises a band-gap reference and control amplifier for biasing the full-scale output current. the full-scale output current is set by applying an external resistor r bias . the bias current i bias through resistor r bias is defined by the on-chip band-gap reference voltage and control amplifier. the full-scale output current equals 16 times this bias current. the full-scale output current iout fs can thus be expressed as (coarse gain = 15, fine gain = 0): , where v extio is the voltage at terminal extio. the band-gap reference voltage delivers an accurate voltage of 1.2 v. this reference is active when terminal extlo is connected to agnd. an external decoupling capacitor 40 www .ti.com i o u t 1 i o u t f s c o d e 6 5 5 3 6 i o u t 2 i o u t f s ( 6 5 5 3 6 c o d e ) 6 5 5 3 6 v o u t 1 i o u t 1 r l c o d e 6 5 5 3 6 i o u t f s r l v o u t 2 i o u t 2 r l ( 6 5 5 3 6 c o d e ) 6 5 5 3 6 i o u t f s r l v o u t d i f f i o u t 1 v o u t 2 ( 2 c o d e 6 5 5 3 6 ) 6 5 5 3 6 i o u t f s r l i o u t f s 1 6 v e x t i o r b i a s
analog current outputs dac5686 slws147b ? april 2003 ? revised august 2004 clock input and timing (continued) c ext of 0.1 mf should be connected externally to terminal extio for compensation. the band-gap reference additionally can be used for external reference operation. in that case, an external buffer with a high-impedance input should be used in order to limit the band-gap load current to a maximum of 100 na. the internal reference can be disabled and overridden by an external reference by connecting extlo to avdd. capacitor c ext may hence be omitted. terminal extio serves as either input or output node. the full-scale output current can be adjusted from 20 ma down to 2 ma by varying resistor r bias or changing the externally applied reference voltage. the internal control amplifier has a wide input range supporting the full-scale output current range of 20 db. figure 47 shows a simplified schematic of the current source array with corresponding switches. differential switches direct the current of each individual nmos current source to either the positive output node iout1 or its complementary negative output node iout2. the output impedance is determined by the stack of the current sources and differential switches, and is typically >300 kw in parallel with an output capacitance of 5 pf. the external output resistors are terminated to avdd. the maximum output compliance at nodes iout1 and iout2 is limited to avdd + 0.5 v, determined by the cmos process. beyond this value, transistor breakdown can occur, resulting in reduced reliability of the dac5686 device. the minimum output compliance voltage at nodes iout1 and iout2 equals avdd ? 0.5 v. exceeding the minimum output compliance voltage adversely affects distortion performance and integral nonlinearity. the optimum distortion performance for a single-ended or differential output is achieved when the maximum full-scale signal at iout1 and iout2 does not exceed 0.5 v. figure 47. equivalent analog current output the dac5686 can be easily configured to drive a doubly terminated 50-w cable using a properly selected rf transformer. figure 48 and figure 49 show the 50-w doubly terminated transformer configuration with 1:1 and 4:1 impedance ratios, respectively. note that the center tap of the primary input of the transformer must be connected to avdd to enable a dc current flow. applying a 20-ma full-scale output current would lead to a 0.5-vpp output for a 1:1 transformer and a 1-vpp output for a 4:1 transformer. 41 www .ti.com iout1 iout2 s(1) s(1)c r l o a d r l o a d s(2) s(2)c s(n) s(n)c a vdd
sleep mode power-up sequence dac5686 slws147b ? april 2003 ? revised august 2004 clock input and timing (continued) figure 48. driving a doubly terminated 50-w cable using a 1:1 impedance-ratio transformer figure 49. driving a doubly terminated 50-w cable using a 4:1 impedance-ratio transformer the dac5686 features a power-down mode that turns off the output current and reduces the supply current to less than 5 ma over the supply range of 3 v to 3.6 v and temperature range of ?40c to 85c. the power-down mode is activated by applying a logic level 1 to the sleep pin (e.g., by connecting pin sleep to iovdd). an internal pulldown circuit at node sleep ensures that the dac5686 is enabled if the input is left disconnected. power-up and power-down activation times depend on the value of the external capacitor at node sleep. for a nominal capacitor value of 0.1 mf, it takes less than 5 ms to power down and approximately 3 ms to power up. in all conditions, bring up dvdd first. if pllvdd is powered (pll on), clkvdd should be powered before or simultaneously with pllvdd. avdd, clkvdd and iovdd can be powered simultaneously or in any order. within avdd, the multiple avdd pins should be powered simultaneously. 42 www .ti.com iout1 1:1 iout2 50 w 50 w r l o a d 50 w 100 w a vdd (3.3 v) a vdd (3.3 v) iout1 4:1 iout2 100 w 100 w r l o a d 50 w a vdd (3.3 v) a vdd (3.3 v)
dac5686 evaluation board appendix a. pll loop filter components dac5686 slws147b ? april 2003 ? revised august 2004 there is a combination evm board for the dac5686 digital-to-analog converter for evaluation. this board allows the user the flexibility to operate the dac5686 in various configurations. possible output configurations include transformer-coupled, resistor-terminated, inverting/non-inverting and differential amplifier outputs. the digital inputs are designed to be driven directly from various pattern generators with the onboard option to add a resistor network for proper load termination. for the external second-order filter shown in figure 50 , the components r, c1, and c2 are calculated for a desired phase margin and loop bandwidth. resistor r3 = 200 w and capacitor c3 = 8 pf are internal to the dac5686. figure 50. dac5686 loop filter the vco gain (gvco) as a function of vco frequency for the dac5686 is shown in figure 17 . for a desired vco frequency, the loop filter values can be calculated using the following equations. nominal pll design parameters include: charge pump current: iqp = 1 ma vco gain: k vco = 2p g vco rad/a pll divide ratio interpolation: n = {2, 4, 8, 16, 32} phase detector gain: k d = iqp (2pn) ?1 a/rad let desired loop bandwidth = w d desired phase margin = f d 43 www .ti.com r3 c3 r1 c1 c2 external internal s0006-01
dac5686 slws147b ? april 2003 ? revised august 2004 dac5686 evaluation board (continued) then where example: f d = 70, w d = 1 mhz, g vco = 300e6 mhz/a n r (w) c1 (mf) c2 (pf) 2 43 0.02 670 4 86 0.01 335 8 173 0.005 167 16 346 0.002 84 32 692 0.001 42 the calculated phase margin and loop bandwidth can be verified by plotting the gain and phase of the open-loop transfer function given by figure 51 shows the open-loop gain and phase for the dac5686 evaluation-board loop filter. figure 51. open-loop phase and gain plots for dac5686 evaluation board 44 www .ti.com c 1 1 1 2 3 c 2 1 2 3 r 3 2 1 ( 3 2 ) 1 k d k v c o 2d ( tan d sec d ) 2 1 d ( tan d sec d ) 3 tan d sec d d h ( s ) k v c o k d ( 1 s r c 1 ) s 3 r c 1 c 2 s 2 ( c 1 c 2 ) f ? frequency ? mhz gain ? db 0.01 0.1 1 100 10 60 4020 0 ?20 ?40 ?60 n = 2, 4, 8, 16, 32 ?180 ?160 ?140 ?120 ?100 f ? frequency ? mhz phase ? 0.01 0.1 1 100 10 g005
dac5686 slws147b ? april 2003 ? revised august 2004 the phase error (f err ) phase and frequency step responses are given by the following equations and are plotted in figure 52 for the dac5686 evaluation-board loop filter. figure 52. phase and frequency step responses for dac5686 evaluation board 45 www .ti.com e r r [ 1 n t ( n t ) 2 ] e n t p h a s e s t e p r e s p o n s e e r r n [ n t ( n t ) 2 ] e n t f r e q u e n c y s t e p r e s p o n s e 0.0 0.2 0.4 0.6 0.8 1.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 t ? t ime ? m s normalized phase error response to a frequency step at t ime 0 n = 2, 4, 8, 16, 32 increasing n g006 t ? t ime ? m s ?0.5 0.0 0.5 1.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 normalized phase error response to a phase step at t ime 0 n = 2, 4, 8, 16, 32 increasing n
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