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description the cxa1372bq/bs is a bipolar ic developed for rf signal processing (focus ok, mirror, defect detection, efm comparator) and various servo control. features dual 5v and single 5v power supplies low power consumption fewer external parts disc defect countermeasure circuit fully compatible with the cxa1182 for microcomputer software functions auto asymmetry control focus ok detection circuit mirror detection circuit defect detection, countermeasure circuit efm comparator focus servo control tracking servo control sled servo control structure bipolar silicon monolithic ic absolute maximum ratings (ta = 25?) supply voltage v cc ?v ee 12 v operating temperature topr ?0 to +75 ? storage temperature tstg ?5 to +150 ? allowable power dissipation p d 457 (cxa1372bq) mw 833 (CXA1372BS) mw recommended operating conditions v cc ?v ee 3.6 to 11 v v cc ?d gnd 3.6 to 5.5 v ?1 cxa1372bq/bs e95927a67-ps rf signal processing servo amplifier for cd player sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. cxa1372bq 48 pin qfp (plastic) CXA1372BS 48 pin sdip (plastic)
?2 cxa1372bq/bs block diagram 35 34 30 31 32 33 25 26 27 28 29 ?iil ?ttl 20 21 22 23 24 19 13 14 15 16 17 18 ?i set ?f set tm6 tm5 tm4 tm3 tm7 12 11 10 9 8 7 6 5 4 3 2 1 fs3 fs2 fs1 ?focus phase compensation 48 47 46 45 44 43 42 41 40 39 37 dfct ?bpf ?window comparator dfct tg1 ?tracking phase compensation ?iil data register ?output decoder ?input shift register ?address decoder ?fs1 to 4 tg1 to 2 tm1 to 7 ps1 to 3 ?ttl ?iil dvcc cc2 cc1 fok efm asy dfct mirr dgnd sens c. out xrst data xlt clk lock dirc av ee sstop iset fset sl slo sl+ ta tao av cc tg2 tgu srch fe feo flb fs3 fgd vc fdfct fe fzc atsc tdfct te tzc dv ee rfo rfi cp cb 36 tm1 fs4 tg2 tm2 ?ttl ?iil 38
?3 cxa1372bq/bs pin configuration cxa1372bq 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 1 cb cp rfi rfo dv ee tzc te tdfct atsc fzc fe fdfct data xlt clk lock dirc av ee sstop iset fset sl slo sl+ vc fgd fs3 flb feo fe srch tgu tg2 avcc tao ta dvcc cc2 cc1 fok efm asy dfct mirr dgnd sens c. out xrst cxa1372bq CXA1372BS 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 1 te tdfct atsc tzc fe fdfct vc fgd fs3 flb feo fe srch tgu tg2 avcc tao ta sl+ slo sl fset iset sstop tzc dv ee rfo rfi cp cb dvcc cc2 cc1 fok efm asy dfct mirr dgnd sens c. out xrst data xlt clk lock dirc av ee CXA1372BS
?4 cxa1372bq/bs pin description pin no. symbol i/o equivalent circuit description vc i center voltage input. for dual power supplies: gnd for single power supply: (v cc + gnd)/2 fgd i connects a capacitor between this pin and pin 3 to cut high-frequency gain. fs3 i the high-frequency gain of the focus servo is switched through fs3 on and off. flb i external time constant to boost the low frequency of the focus servo. feo o tao o slo o focus drive output. tracking drive output. sled drive output. 1 2 3 4 5 11 14 6 7 8 9 10 11 17 20 12 fe i inverted input for focus amplifier. 147 40k 90k 2.5a 6 5 11 14 250a 2.5a 40k 4 2 vcc v ee 147 48k 130k 20a 3 46k 580k q s
?5 cxa1372bq/bs external time constant for forming the focus search waveforms. external time constant for selecting the tracking high-frequency gain. external time constant for selecting the tracking high-frequency gain. inverted input for tracking amplifier. non-inverted input for sled amplifier. inverted input for sled amplifier. pin no. symbol i/o equivalent circuit description srch i tgu i tg2 i ta i sl+ i 13 14 15 18 19 21 7 8 9 12 13 15 sl i 147 22a 3a 15 10k 13 147 90k 11a 3a 12 147 50k 11a 3.5a 7 20k 110k 82k 8 470k 147 9 qs
?6 cxa1372bq/bs serial data transfer clock input from cpu. (no pull-up resistor) serial data input from cpu. (no pull-up resistor) reset input, reset at "low". (no pull-up resistor) latch input from cpu. (no pull-up resistor) track number count signal output. outputs fzc, as, tzc and sstop through command from cpu. sets the peak frequency of focus tracking phase compensation. current is input to determine focus search, track jump, and sled kick level. used for 1-track jump. contains a 47k pull-up resistor. at "low" sled overrun prevention circuit operates. contains a 47k pull-up resistor. limit sw on/off signal detection for disc innermost track detection. pin no. symbol i/o equivalent circuit description fset i iset i sstop i dirc i lock i 22 23 24 26 27 33 16 17 18 20 21 clk i 28 22 xlt i 29 23 data i 30 24 xrst i 31 25 27 sens o 32 26 c. out o 100k 147 20k 26 27 147 47k 15a 20 21 22 23 24 25 147 15k 15k 16 147 17 147 7a 18 q s
?7 cxa1372bq/bs input for defect bottom hold output with capacitance coupled. pin no. symbol i/o equivalent circuit description 29 mirr o 38 cp i mirr comparator output. (dc voltage: 10k load connected) connects mirr hold capacitor. non-inverted input for mirr comparator. 34 cc1 o 35 cc2 i 30 dfct o 37 cb i 31 asy i auto asymmetry control input. 32 efm o efm comparator output. (dc voltage: 10k load connected) 33 35 44 40 41 36 43 37 38 39 fok o fok comparator output. (dc voltage: 10k load connected) 147 33 20k 4.8k current source depending on power supply (v cc to d gnd ) 32 147 31 147 147 20k 29 38 147 37 147 35 147 34 147 30 defect bottom hold output. connects defect bottom hold capacitor. defect comparator output. (dc voltage: 10k load connected) qs
?8 cxa1372bq/bs input for rf summing amplifier output with capacitance coupled. tracking zero-cross comparator input. connects a capacitor for time constant during defect. tracking error input. window comparator input for atsc detection. focus zero-cross comparator input. focus error input. connects a capacitor for time constant during defect. pin no. symbol i/o equivalent circuit description rfi i tzc i te i atsc i fzc i 45 48 1 3 4 5 39 rf summing amplifier output. check point of eye pattern. rfo o 46 40 42 43 tdfct i 2 44 45 46 47 fe i 6 48 fdfct i 147 147 470k 47 48 147 46 1.2k 60k 330k 45 vcc v ee 470k 47p 147 39 40 147 40k 42 147 75k 7a 147 147 43 44 470k q s
?9 cxa1372bq/bs electrical characteristics (ta = 25?, v cc = 2.5v, v ee = ?.5v, d. gnd = ?.5v) no. current consumption current consumption o o o o o o s1 s2 s3 s4 s5 s6 s7 s8 s9 e1 e2 e3 e4 sd measure- ment point description of output waveform and measurement method 10, 36 19, 41 5 5 5 5 5 5 5 5 27 11 11 11 11 11 11 11 11 unit max. typ. min. item symbol bias condition sw condition 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 dc voltage gain feedthrough max. output voltage max. output voltage max. output voltage max. output voltage search output voltage search output voltage fzc threshold value dc voltage gain feedthrough max. output voltage max. output voltage max. output voltage max. output voltage jump output voltage jump output voltage i cc i ee g feo v feof v fe01 v fe02 v fe03 v fe04 v srch1 v srch2 v fzc g teo v teof v te01 v te02 v te03 v te04 v jump1 v jump2 o o o o o o 00 00 08 00 08 08 08 08 02 03 00 25 00 25 25 25 25 2c 28 8 ?4 18.0 2.0 1.2 ?40 360 39 11.6 2.0 1.2 ?40 360 19 ?7 21.0 50 13.3 27 ? 24.0 ?5 ?.0 ?.2 ?60 640 61 17.6 ?9 ?.0 ?.2 ?60 640 ma ma db db v v v v mv mv mv db db v v v v mv mv v 1 = 10hz, 100mvp-p g feo = 20 log (vout/vin) sg = 10khz, 40mvp-p difference in gain when sd = 00 and sd = 08 v 1 = 0.5v dc v 1 = ?.5v dc v 1 = 0.5v dc v 1 = ?.5v dc * (v cc + dgnd)/2 = sens value when e4 is varied. v 2 = 10hz, ?00mvp-p g teo = 20 log (vout/vin) v 2 = 10khz, 40mvp-p difference in gain when sd = 00 and sd = 25 v 2 = ?.5v dc v 2 = 0.5v dc v 2 = ?.5v dc v 2 = 0.5v dc focus servo tracking servo *
?10 cxa1372bq/bs no. o o s1 s2 s3 s4 s5 s6 s7 s8 s9 e1 e2 e3 e4 sd measure- ment point description of output waveform and measurement method 27 27 27 14 14 14 14 14 14 14 14 27 27 26 33 33 33 33 unit max. typ. min. symbol bias condition sw condition 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 10 10 20 25 00 25 25 25 25 23 22 30 ?5 7 ?0 50 2.0 2.0 ?50 450 ?0 ?00 2.2 45 ?6 26 0 ?5 ?56 ? 45 20 ?4 ?.0 ?.0 ?50 750 ?0 ?.0 ?.0 ?30 ?.8 mv mv mv db db v v v v mv mv mv v v mv v v khz * (v cc + dgnd)/2 = sens value when e3 is varied. * (v cc + dgnd)/2 = sens value when e2 is varied. v 5 = 10hz, 20mvp-p open loop gain v 5 = 10khz, 100mvp-p difference in gain when sd = 00 and sd = 25 v 5 = 1.0v dc v 5 = ?.0v dc v 5 = 1.0v dc v 5 = ?.0v dc * (v cc + dgnd)/2 = sens value when e1 is varied. (v cc + dgnd)/2 = value between pins 39 and 40 when v 4 is varied. v 4 = 1vp-p ?375mv dc fok atsc threshold value atsc threshold value tzc threshold value dc voltage gain feedthrough max. output voltage max. output voltage max. output voltage max. output voltage kick output voltage kick output voltage sstop threshold value sens low level cout low level fok threshold value high level voltage low level voltage max. operating frequency v atsc1 v atsc2 v tzc g slo v slof v sl01 v sl02 v sl03 v sl04 v kick1 v kick2 v sstop v sens v cout v fokt v fokh v fokl f fok sled servo tracking servo * * * item
?11 cxa1372bq/bs s1 s2 s3 s4 s5 s6 s7 s8 s9 e1 e2 e3 e4 sd measure- ment point description of output waveform and measurement method 29 29 29 29 29 30 30 30 30 30 30 31 31 32 32 a a unit max. typ. min. symbol bias condition sw condition 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 high level voltage low level voltage max. operating frequency min. input operating voltage max. input operating voltage high level output voltage low level output voltage min. operating frequency max. operating frequency min. input operating voltage max. input operating voltage duty 1 duty 2 high level output voltage low level output voltage min. input operating voltage max. input operating voltage v mirh v mirl f mir v mir1 v mir2 v dfcth v dfctl f dfct1 f dfct2 v dfct1 v dfct2 d efm1 d efm2 v efmh v efml v efm1 v efm2 o o o o o o 1.8 30 1.8 1.8 2.5 1.8 ?0 0 1.2 1.8 0 50 ?.0 0.3 ?.0 1 0.5 50 100 ?.2 0.12 v v khz vp-p vp-p v v khz khz vp-p vp-p mv mv v v vp-p vp-p v 4 = 10khz 1.0vp-p ?0.4v dc v 4 = 800mvp-p ?0.4v dc v 4 = 10khz ?0.4v dc v 4 = 0.8vp-p + 375mv dc v 4 = 50hz + 375mv dc (square wave) v 4 = 750khz, 0.7vp-p v 4 = 750khz, 0.7vp-p + 0.25v dc v 4 = 750khz, 0.7vp-p v 4 = 750khz defect efm mirror item no. o o
?12 cxa1372bq/bs electric characteristics measurement circuit gnd 0.1 s1 gnd 1000p 130 13k s3 100k 200k s2 s4 0.033 avcc gnd 130 s6 100k 200k s5 gnd 13k gnd v5 ac 130 13k s7 60k 5.1k gnd 510k vcc 240k av ee vcc vcc gnd e1 clk xlt data 10k vcc vcc 10k vcc 10k dgnd 10k dgnd s8 s9 0.01 1k a dgnd 1m dgnd 10k vcc 10k 3300p a dvcc 1000p dgnd 3300p dgnd v4 ac gnd v3 ac gnd dv ee gnd e2 v2 ac gnd gnd 0.1 gnd e3 gnd e4 v1 ac gnd 0.1 gnd 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 1 cb cp rfi rfo dv ee tzc te tdfct atsc fzc fe fdfct data xlt clk lock dirc av ee sstop iset fset sl slo sl+ vc fgd fs3 flb feo fe srch tgu tg2 avcc tao ta dvcc cc2 cc1 fok efm asy dfct mirr dgnd sens c. out xrst dgnd dgnd + gnd + + + a a a
?13 cxa1372bq/bs description of functions focus servo fzc 1.2k 56k fe 22k fzc focus phase compensation 48k 510k 0.1 fset flb 40k fgd 10k dfct 2200p fe 470k 0.1 fdfct fs3 580k 46k 100k focus coil fe 120k 11 22 iset fs1 50k 40k 4.7 srch 10k fs2 0.01 feo 0.1 20k fs4 fs3 120k 46 47 48 2 3 4 16 7 17 6 5 dgnd the above figure shows a block diagram of the focus servo. ordinarily the fe signal is input to the focus phase compensation circuit through a 20k and 48k resistance; however, when dfct is detected, the fe signal is switched to pass through a low-pass filter formed by the internal 470k resistance and the capacitance connected to pin 48. when this dfct countermeasure circuit is not used, leave pin 48 open. when fs3 is on, the high-frequency gain can be cut by forming a low-frequency time constant through a capacitor connected between pins 2 and 3 and the internal resistor. the capacitor connected between pin 4 and gnd is a time constant to boost the low frequency in the normal playback state. the peak frequency of the focus phase compensation is approximately 1.2khz when a resistance of 510k is connected to pin 16. the focus search level is approximately 1.1vp-p when using the constants indicated in the above figure. this level is inversely proportional to the resistance connected between pin 17 and gnd. however, changing this resistance also changes the level of the track jump and sled kick as well. the fzc comparator inverted input is set to 2% of v cc and vc (pin 1); (v cc ?vc) 2%. * 510k resistance is recommended for pin 16.
?14 cxa1372bq/bs tracking sled servo 42 tzc tzc 0.022 45 0.047 atsc bpf 100k 1k 1k 100k atsc 43 44 te 22k 0.1 te tdfct 470k dfct 680k tg1 tg1 680k 10k tm1 66p tracking phase compensation 8 9 0.033 tgu tg2 20k tg2 470k 10k 90k tm7 11 12 ta 13 sl+ 14 15 slo sl tracking coil 100k 82k 22 3.3 15k 8.2k 0.015 m sled motor 120k 100k sstop sstop 100k 1k 10k tm2 tm6 tm5 22a 22a tm4 tm3 11a 11a 16 510k 0.01 fset tao 18 the above figure shows a block diagram of the tracking and sled servo. the capacitor connected between pins 8 and 9 is a time constant to cut the high-frequency gain when tg2 is off. the peak frequency of the tracking phase compensation is approximately 1.2khz when a 510k resistance connected to pin 16. to jump tracks in fwd and rev directions, turn tm3 or tm4 on. during this time, the peak voltage applied to the tracking coil is determined by the tm3 or tm4 current and the feedback resistance from pin 12. to be more specific, track jump peak voltage = tm3 (or tm4) current feedback resistance the fwd and rev sled kick is performed by turning tm5 or tm6 on. during this time, the peak voltage applied to the sled motor is determined by the tm5 or tm6 current and the feedback resistance from pin 15; sled kick peak voltage = tm5 ( or tm6) current feedback resistance the values of the current for each switch are determined by the resistance connected between pin 17 and gnd. when this resistance is 120k : tm3 ( or tm4) = 11a, and tm5 (or tm6) = 22a. this current value is almost inversely proportional to the resistance and the variable range is approximately 5 to 40a at tm3. sstop is the on/off detection signal for the limit sw of the linear motor's innermost track. as is the case with the fe signal, the te signal is switched to pass through a low-pass filter formed by the internal resistance (470k ) and the capacitor connected to pin 44. tm-1 was on at dfct in the cxa1082 and cxa1182, but it does not operate in the cxa1372.
?15 cxa1372bq/bs focus ok circuit 15k 92k vg 54k 20k v cc 0.625v rfo rfi fok 1 focus ok amp focus ok comparator rf signal 33 39 40 c5 0.01 the focus ok circuit creates the timing window okaying the focus servo from the focus search state. the hpf output is obtained at pin 39 from pin 40 (rf signal), and the lpf output (opposite phase) of the focus ok amplifier output is also obtained. the focus ok output reverses when v rfi ?v rfo ? ?.37v. note that, c5 determines the time constants of the hpf for the efm comparator and mirror circuit and the lpf of the focus ok amplifier. ordinarily, with a c5 equal to 0.01f selected, the fc is equal to 1khz, and block error rate degradation brought about by rf envelope defects caused by scratched discs can be prevented. efm comparator efm comparator changes rf signal to a binary value. the asymmetry generated due to variations in disc manufacturing cannot be eliminated by the ac coupling alone. therefore, the reference voltage of efm comparator is controlled through 1 and 0 that are in approximately equal numbers in the binary efm signals. as this comparator is a current sw type, each of the high and low levels is not equal to the power supply voltage. a feedback has to be applied through the cmos buffer. r8, r9, c8, and c9 form a lpf to obtain (v cc + dgnd)/2v. when fc (cut-off frequency) exceeds 500hz, the efm low-frequency components leak badly, and the block error rate worsens. 31 c8 c9 asy r8 r9 cmos buffer cxd2500 100k 20k vc vcc 40k 40k auto asymmetry buffer auto asymmetry control amp 39 rfi efm comparator 32 efm dgnd = 0v 6
?16 cxa1372bq/bs defect circuit after inversion, rfi signal is bottom held by means of the long and short time constants. the long time- constant bottom hold keeps the mirror level prior to the defect. the short time-constant bottom hold responds to a disc mirror defect in excess of 0.1ms, and this is differentiated and level-shifted through the ac coupling circuit. the long and short time-constant signals are compared to generate at mirror defect detection signal. rfo a 2 b defect amp cc1 cc2 dfct cb 0.01 0.033 defect comparator defect bottom hold e c d e d c b a bottom hold (1); solid line cc1 defect amp rfo defect bottom hold (2); dotted line cc2 h l 34 35 37 40 30
?17 cxa1372bq/bs mirror circuit the mirror circuit performs peak and bottom hold after the rfi signal has been amplified. for the peak hold, a time constant can follow a 30khz traverse, and, for the bottom hold, one can follow the rotation cycle envelope fluctuation. through differential amplification of the peak and bottom hold signals h and i, mirror output can be obtained by comparing an envelope signal j (demodulated to dc) to signal k for which peak holding at a level 2/3 that of the maximum was performed with a large time constant. in other words, mirror output is low for tracks on the disc and high for the area between tracks (the mirr areas). in addition, a high signal is output when a defect is detected. the mirror hold time constant must be sufficiently large in comparison with the traverse signal. 20k 0.033 rfo rfi cp mirror comparator peak & bottom hold 2.2 k mirror hold amp j h i 1 g mirror amp mirr dgnd 29 38 39 rfo h l 0v 0v 0v 0v g (rfi) h (peak hold) i (bottom hold) (mirror hold) j k mirr
?18 cxa1372bq/bs commands the input data to operate this ic is configured as 8-bit data; however, below, this input data is represented by 2-digit hexadecimal numerals in the form $xx, where x is a hexadecimal numeral between 0 and f. commands for the cxa1372 can be broadly divided into four groups ranging in value from $0x to $3x. 1. $0x (?zc?at sens (pin 27)) these commands are related to focus servo control. the bit configuration is as shown below. d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 fs4 fs3 fs2 fs1 four focus-servo related switches exist: fs1 to fs4 corresponding to d0 to d3, respectively. $00 when fs1 = 0, pin 7 is charged to (22a ?11a) 50k = 0.55v. if fs2 = 0, this voltage is no longer transferred, and the output at pin 5 becomes 0v. $02 from the state described above, the only fs2 becomes 1. when this occurs, a negative signal is output to pin 5. this voltage level is obtained by equation 1 below. (22a ?11a) 50k . . . . equation 1 $03 from the state described above, fs1 becomes 1, and a current source of +22a is split off. then, a cr charge/discharge circuit is formed, and the voltage at pin 7 decreases with the time as shown in fig. 1 below. this time constant is obtained with the 50k resistance and an external capacitor. by alternating the commands between $02 and $03, the focus search voltage can be constructed. (fig. 2) 0v 0v $0002030203 0200 fig. 1. voltage at pin 7 when fs1 gose from 0 ? 1 fig. 2. constructing the search voltage by alternating between $02 and $03 (voltage at pin 5) resistance between pins 5 and 6 50k
?19 cxa1372bq/bs the instant the signal is brought into focus. $08 $03 ($00) $02 (20ms) (200ms) drive voltage focus error sens pin (fzc) focus ok 1-1. fs4 this switch is provided between the focus error input (pin 47) and the focus phase compensation, and is in charge of turning the focus servo on and off. $00 ? $08 focus off ? focus on 1-2. procedure of focus activation for description, suppose that the polarity is as described below. a) the lens is searching the disc from far to near; b) the output voltage (pin 5) is changing from negative to positive; and c) the focus s-curve is varying as shown below. the focus servo is activated at the operating point indicated by a in fig. 3. ordinarily, focus searching and turning the focus servo switch on are performed when the focus s-curve transits the point a indicated in fig. 3. to prevent misoperation, this signal is anded with the focus ok signal. in this ic, fzc (focus zero cross) signal is output from the sens pin (pin 27) as the point a transit signal. focus ok is output as a signal indicating that the signal is in focus (can be in focus in this case). following the line of the above description, focusing can be well obtained by observing the following timing chart. * the broken lines in the figure indicate the voltage assuming the signal is not in focus. t a fig. 3. s-curve fig. 4. focus on timing chart
?20 cxa1372bq/bs 1-3. sens (pin 27) the output of the sens pin differs depending on the input data as shown below. $0x: fzc $1x: as $2x: tzc $3x: sstop $4x to 7x: high-z 2. $1x (?s?at sens (pin 27)) these commands deal with switching tg1 and tg2 on/off. the bit configuration is as follows d7 d6 d5 d4 d3 d2 d1 d0 0001 anti break tg2 tg1 shock circuit on/off on/off tg1, tg2 the purpose of these switches is to switch the tracking servo gain up/normal. the brake circuit (tm7) is to prevent the frequently occurred phenomena where the merely 10-track jump has been performed actually though a 100-track jump was intended to be done due to the extremely degraded actuator settling caused by the servo motor exceeding the linear range after a 100 or 10-track jump. when the actuator travels radially; that is, when it traverses from the inner track to the outer track of the disc and vice versa, the brake circuit utilizes the fact that the phase relationship between the rf envelope and the tracking error is 180?out-of-phase to cut the unneeded portion of the tracking error and apply braking. note that the time from the high to low transition of fzc to the time command $08 is asserted must be minimized. to do this, the software sequence shown in b is better than the sequence shown in a. fzc ? no yes f. ok ? no transfer $08 latch fzc ? no f. ok ? no transfer $08 latch (a) (b) yes yes yes fig. 5. poor and good software command sequences
?21 cxa1372bq/bs envelope detection [ * b] [ * e] rfi (tzc) tracking error (latch) q d ck (mirr) [ * c] [ * f] [ * g] brk d2 tm7 low: open high: make [ * a] [ * d] waveform shaping waveform shaping edge detection 39 42 [ * h] fig. 6. tm7 operation (brake circuit) from inner to outer track 0v from outer to inner track ("mirr") ("tzc") braking is applied from here. [ * a] [ * b] [ * c] [ * d] [ * e] [ * f] [ * g] [ * h] fig. 7. internal waveform 3. $2x (?zc?at sens (pin 27)) these commands deal with turning the tracking servo and sled servo on/off, and creating the jump pulse and fast forward pulse during access operations. d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 0 tracking sled control control 00: off 00: off 01: servo on 01: servo on 10: f-jump 10: f-fast forward 11: r-jump 11: r-fast forward tm1, tm3, tm4 tm2, tm5, tm6
?22 cxa1372bq/bs dirc (pin 20) and 1 track jump normally, an acceleration pulse is applied for a 1-track jump. then a deceleration pulse is given for a specified time observing the tracking error from the moment it passes point 0, and tracking servo is turned on again. for the 100-track jump to be explained in the next item, as long as the number of tracks is about 100 there is no problem. however a 1-track jump must be performed here, which requires the above complicated procedure. for the 1-track jump in cd players, both the acceleration and deceleration take about 300 to 400s. when software is used to execute this operation, it turns out as shown in the flow chart of fig. 9. actually, it takes some time to transfer data. acceleration pulse waveform tracking error deceleration aaa aaa $2c transfer latch $28 transfer only tzc ? no yes latch timer (0.3ms) $25 transfer latch tr: rev sl: off tr: fwd sl: off execute execute tr: on sl: on execute aaaa aaaa $2c transfer latch tzc ? no yes dirc = l timer (0.3ms) dirc = h tr: rev sl: off tr: fwd sl: off execute tr: on sl: on fig. 9. 1-track jump not using dirc (pin 20) fig. 10. 1-track jump with dirc (pin 20) fig. 8. pulse waveform and tracking error of 1-track jump the dirc (direct control) pin was provided in this ic to facilitate the 1-track jump operation. conduct the following process to perform 1-track jump using dirc (normal high). (a) acceleration pulse is output. ($2c for rev or $28 for fwd). (b) with tzc (or tzc - ), set dirc to low. (sens pin 27 outputs "tzc"). as the jump pulse polarity is inverted, deceleration is applied. (c) set dirc to high after a specific time. both the tracking servo and sled servo are switched on automatically. as a result, the track jump turns out as shown in the flow chart of fig. 10 and the two serial data transfers can be omitted.
?23 cxa1372bq/bs 4. $3x this command selects the focus search and sled kick levels. d0, d1 ..... sled, normal feed, high-speed feed d2, d3 ..... focus search level selection d7 d6 d5 d4 0011 focus search level sled kick level relative value d3 (ps4) 0 0 1 1 d2 (ps3) 0 1 0 1 d1 (ps2) 0 0 1 1 d0 (ps1) 0 1 0 1 ? ? ? ?
?24 cxa1372bq/bs parallel direct interface 1. dirc $28 latch $2c latch on off on off off on on off xlt dirc fwd jump rev jump track servo sled servo on off on off down up lock sled servo tg1, tg2 tracking gain 2. lock (sled overrun prevention circuit)
?25 cxa1372bq/bs cpu serial interface timing chart t wck d0 d1 d2 d3 d4 d5 d6 d7 t wck t su 1/fck t h t wl t d data clk xlt item clock frequency clock pulse width setup time hold time delay time latch pulse width symbol fck fwck t su t h t d t wl min. 500 500 500 1000 1000 typ. max. unit mhz ns ns ns ns ns 1 (dv cc ?dgnd = 4.5 to 5.5v) system control focus control tracking control tracking mode select d7 d6 d5 d4 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 fs4 focus on anti-shock ps4 focus search + 2 ps3 focus search + 1 ps2 sled kick + 2 ps1 sled kick + 1 fs3 gain down brake on fs2 search on tg2 gain set * 1 fs1 search up tg1 fzc a. s tzc sstop tracking mode * 2 sled mode * 3 address d3 d2 d1 d0 data sens output * 2 tracking mode fwd jump rev jump d3 0 0 1 1 d2 0 1 0 1 off on * 3 sled mode fwd move rev move d1 0 0 1 1 d0 0 1 0 1 off on item * 1 gain set tg1 and tg2 can be set independently. when the anti-shock is at 1 (00011xxx), both tg1 and tg2 are inverted when the internal anti-shock is at high.
?26 cxa1372bq/bs serial data truth table focus control tracking control tracking mode dirc = 1 dirc = 0 dirc = 1 tm = 654321 654321 654321 as = 0 as = 1 tg = 2 1 tg = 2 1 hex. function fs = 4 3 2 1 $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0a $0b $0c $0d $0e $0f $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1a $1b $1c $1d $1e $1f serial data 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 1 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 1 0 0 0 1 0 1 1 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 0 0 0 1 1 0 1 0 0 0 0 1 1 0 1 1 0 0 0 1 1 1 0 0 0 0 0 1 1 1 0 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 0 1 0 0 1 1 1 0 0 0 0 1 1 0 1 1 0 1 0 0 0 1 1 0 1 000000 001000 000011 000010 001010 000011 010000 011000 100001 100000 101000 100001 000001 000100 000011 000011 000110 000011 010001 010100 100001 100001 100100 100001 000100 001000 000011 000110 001010 000011 010100 011000 100001 100100 101000 100001 001000 000100 000011 001010 000110 000011 011000 010100 100001 101000 100100 100001 $20 $21 $22 $23 $24 $25 $26 $27 $28 $29 $2a $2b $2c $2d $2e $2f 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 0 0 1 0 0 1 1 1 0 0 1 0 1 0 0 0 0 0 1 0 1 0 0 1 0 0 1 0 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 0 1 1 0 0 0 0 1 0 1 1 0 1 0 0 1 0 1 1 1 0 0 0 1 0 1 1 1 1
?27 cxa1372bq/bs gnd c26 gnd gnd wfck xraof gnd fok fsw mon mdp mds lock nc vcoo vcoi test pdo v ss nc nc nc vpco vcki filo fili pco av ss cltv av dd rf 2 5 6 7 8 9 10 11 12 13 14 15 16 18 19 20 21 22 23 1 sbso scor wfck emph dout md2 c16m c4m fstt xtsl xtao xtai v ss aptl aptr mnt0 mnt1 mnt2 mnt3 xraof c2po rfck gfs xplck 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 bias asyi asyo asye nc pssl wdck (48) lrck (48) v dd data (48) bclk (48) data (64) bclk (64) lrck (64) gtop xugf 13 14 15 16 17 18 19 20 21 23 sl+ sl0 sl fset iset sstop av ee dirc lock clk xlt data 28 29 30 36 35 34 31 32 33 dv cc cc2 cc1 fok efm asy dfct mirr dgnd sens c.out xrst fdfct fe fzc atsc tdfct te tzc dv ee rfo rfi cp cb 40 39 38 37 41 42 43 44 45 46 47 48 gnd gnd gnd gnd 200p 1m av dd gnd gnd v ss gnd v cc c2po mute bclk data wdck lrck demp gnd mnt0 mnt1 mnt2 mnt3 gnd gtop ugfs gfs rfck xplck dout gnd gnd gnd v dd mute scor sqck subq gfs clk xlt data xrst sens fok ldon dfct mirr fe te rf ldon v cc v o v cc c17 gnd gnd c15 c16 gnd c14 c13 c11 c12 gnd gnd rv2 rv1 rf te fe gnd c9 gnd c10 gnd c23 track-d gnd focus-d gnd sled-d gnd spind-d gnd sstop gnd r1 gnd c28 gnd c27 r6 r7 gnd r3 r4 spd sld fd td gnd gnd r10 gnd r12 cxd2500aq vc fgd fs3 flb feo fe srch tgu tg2 av cc ta0 ta 2 3 4 5 6 7 8 9 10 11 12 1 cxa1372bq r1 r1 70 69 68 67 65 66 71 72 73 74 75 76 77 78 79 80 mirr clko xlto dato cnin sein clok v dd xlat data xrst sens mute sqck sqso exck 22 24 4 3 17 gnd gnd 41 42 43 44 45 46 47 48 49 50 51 53 54 55 56 57 58 59 60 63 64 61 62 27 25 26 24 gnd r14 r13 gnd gnd 52 pcm application circuit application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
?28 cxa1372bq/bs notes on operation 1. connection of the power supply pin 2. fset pin the fset pin determines the cut-off frequency fc for the focus and tracking high-frequency phase compensation. 3. iset pin iset current = 1.27v/r = focus search current = tracking jump current = 1/2 sled kick current 4. the tracking amplifier input is clamped at 1v be to prevent overinput. 5. fe (focus error) and te (tracking error) gain changing method (1) high gain: resistance between fe pins (pins 5 and 6) 100k ? large resistance between ta pins (pins 11 and 12) 100k ? large (2) low gain: a signal, whose resistance is divided, is input to fe and te. 6. input voltage of microcomputer interface pins 20 to 25, should be set as follows. v ih v cc 90% or more v il v cc 10% or less 7. focus ok circuit (1) refer to the "description of operation" for the time constant setting of the focus ok amplifier lpf and the mirror amplifier hpf. (2) the equivalent circuit of fok output pin is as follows. v cc 20k 50k 100k dgnd r l fok v cc dgnd 33 fok comparator output is: output voltage high: v fokh near vcc output voltage low: v fokl vsat (npn) + dgnd dual 5v power supplies +5v 0v vc +5v ?v 0v single 5v power supplies vcc v ee vc fe te
?29 cxa1372bq/bs 8. mirror circuit (1) the equivalent circuit of mirr output pin is as follows. mirr comparator output is: output voltage high: v mirh v cc ?vsat (lpnp) output voltage low: v mirl near dgnd 9. efm comparator (1) note that efm duty varies when the cxa1372 vcc differs from that of dsp ic (such as the cxd2500). (2) the equivalent circuit of the efm output pin is as follows. * when the power supply current between vcc and dgnd is 5v. efm comparator output is: output voltage high: v efmh v cc ?v be (npn) output voltage low: v efml v cc ?4.8 (k ) 700 (a) ?v be (npn) 700a * 4.8k 50 2ma * 32 efm r l dgnd vcc v ee dgnd 20k mirr r l dgnd 29
?30 cxa1372bq/bs standard circuit design data for focus/tracking internal phase compensation s1 s2 s3 s4 s5 s6 s7 s8 s9 e1 e2 e3 e4 sd measure- ment point description of output waveform and measurement method 5 5 5 5 11 11 11 11 08 08 0c 0c 25 25 25 13 25 13 unit max. typ. min. symbol bias condition sw condition 1.2khz gain 1.2khz phase 1.2khz gain 1.2khz phase 1.2khz gain 1.2khz phase 2.7khz gain 2.7khz phase o o o o 21.5 63 16 63 13 ?25 26.5 ?30 db deg db deg db deg db deg when c flb = 0.1f tracking focus item mode o o o o
?31 cxa1372bq/bs example of representative characteristics 40 35 30 25 20 15 10 5 10 1 10 2 10 3 10 4 10 5 ?80 ?35 ?0 ?5 0 45 90 135 180 f ?frequency [hz] g ?gain [db] f ?phase [degree] focus frequency characteristics 40 30 20 10 0 ?0 ?0 10 1 10 2 10 3 10 4 10 5 f ?frequency [hz] g ?gain [db] f ?phase [degree] tracking frequency characteristics f g f g 0 180 120 60 0 ?0 ?20 ?80 c tgu = 0.033 gain up normal c fgd = 0.1 c flb = 0.1 gain down normal
?32 cxa1372bq/bs package outline unit: mm cxa1372bq CXA1372BS sony code eiaj code jedec code m package structure package material lead treatment lead material package weight epoxy resin solder / palladium plating copper / 42 alloy 48pin qfp (plastic) 15.3 0.4 12.0 ?0.1 + 0.4 0.8 0.3 ?0.1 + 0.15 0.12 13 24 25 36 37 48 112 2.2 ?0.15 + 0.35 0.9 0.2 0.1 ?0.1 + 0.2 13.5 0.15 0.15 ?0.05 + 0.1 qfp-48p-l04 * qfp048-p-1212-b 0.7g 48pin sdip (plastic) 600mil 13.0 + 0.3 ?0.1 4.6 + 0.4 ?0.1 0.25 + 0.1 ?0.05 48 25 124 1.778 15.24 0?to 15 0.5 0.1 0.9 0.15 3.0 min 0.5 min sony code eiaj code jedec code package structure package material lead treatment lead material package weight epoxy resin solder plating copper / 42 alloy 5.1g sdip-48p-02 sdip048-p-0600-a 43.2 + 0.4 ?0.1

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