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CY62146ESL mobl ? 4-mbit (256k x 16) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-43142 rev. ** revised january 04, 2008 features very high speed: 45 ns wide voltage range: 2.2v?3.6v and 4.5v?5.5v ultra low standby power ? typical standby current: 1 a ? maximum standby current: 7 a ultra low active power ? typical active current: 2 ma at f = 1 mhz easy memory expansion with ce and oe features automatic power down when deselected cmos for optimum speed and power available in pb-free 44-pin tsop ii package functional description the CY62146ESL is a high performance cmos static ram organized as 256k words by 16 bits. this device features advanced circuit design to provide ultra low active current. this is ideal for providing more battery life ? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power down feature th at reduces power consumption when addresses are not toggling. placing the device into standby mode reduces power consumption by more than 99% when deselected (ce high). the input and output pins (io 0 through io 15 ) are placed in a high impedance state when: deselected (ce high) outputs are disabled (oe high) both byte high enable and byte low enable are disabled (bhe , ble high) write operation is active (ce low and we low) to write to the device, take chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from io pins (io 0 through io 7 ) is written into the location specified on the address pins (a 0 through a 17 ). if byte high enable (bhe ) is low, then data from io pins (io 8 through io 15 ) is written into the location s pecified on the address pins (a 0 through a 17 ). to read from the device, take chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins appears on io 0 to io 7 . if byte high enable (bhe ) is low, then data from memory appears on io 8 to io 15 . see the ?truth table? on page 10 for a complete description of read and write modes. for best practice recommendat ions, refer to the cypress application note an1064, sram system guidelines . logic block diagram 256k x 16 ram array io 0 ?io 7 row decoder a 8 a 7 a 6 a 5 a 2 column decoder a 11 a 12 a 13 a 14 a 15 sense amps data in drivers oe a 4 a 3 io 8 ?io 15 ce we bhe a 16 a 0 a 1 a 9 a 10 ble a 17 [+] feedback www.datasheet.in
CY62146ESL mobl ? document #: 001-43142 rev. ** page 2 of 12 pin configuration figure 1. 44-pin tsop ii (top view) [1] product portfolio product range v cc range (v) [2] speed (ns) power dissipation operating i cc , (ma) standby, i sb2 ( a) f = 1mhz f = f max typ [3] max typ [3] max typ [3] max CY62146ESL industrial 2.2v?3.6v and 4.5v?5.5v 45 2 2.5 15 20 1 7 1 2 3 4 5 6 7 8 9 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 a 5 18 17 20 19 27 28 25 26 22 21 23 24 a 6 a 7 a 4 a 3 a 2 a 1 a 0 a 15 a 16 a 8 a 9 a 10 a 11 a 13 a 14 a 12 oe bhe ble ce we io 0 io 1 io 2 io 3 io 4 io 5 io 6 io 7 io 8 io 9 io 10 io 11 io 12 io 13 io 14 io 15 v cc v cc v ss v ss nc 10 a 17 notes 1. nc pins are not connected on the die. 2. datasheet specifications are not guaranteed for v cc in the range of 3.6v to 4.5v. 3. typical values are included for reference only and are no t guaranteed or tested. typical values are measured at v cc = 3v, and v cc = 5v, t a = 25c. [+] feedback www.datasheet.in
CY62146ESL mobl ? document #: 001-43142 rev. ** page 3 of 12 maximum ratings exceeding the maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature .................................. ?65c to +150c ambient temperature with power applied ........................ .................... ?55c to +125c supply voltage to ground potent ial........... .......?0.5v to 6.0v dc voltage applied to outputs in high-z state [4, 5] ...........................................?0.5v to 6.0v dc input voltage [4, 5] ........................................?0.5v to 6.0v output current into outputs (l ow)............................. 20 ma static discharge voltage............................................ >2001v (mil-std-883, method 3015) latch up current...................................................... >200 ma operating range device range ambient temperature v cc [6] CY62146ESL industrial ?40c to +85c 2.2v?3.6v, and 4.5v?5.5v electrical characteristics over the operating range parameter description test conditions 45 ns unit min typ [3] max v oh output high voltage 2.2 < v cc < 2.7 i oh = ?0.1 ma 2.0 v 2.7 < v cc < 3.6 i oh = ?1.0 ma 2.4 4.5 < v cc < 5.5 i oh = ?1.0 ma 2.4 v ol output low voltage 2.2 < v cc < 2.7 i ol = 0.1 ma 0.4 v 2.7 < v cc < 3.6 i ol = 2.1ma 0.4 4.5 < v cc < 5.5 i ol = 2.1ma 0.4 v ih input high voltage 2.2 < v cc < 2.7 1.8 v cc + 0.3 v 2.7 < v cc < 3.6 2.2 v cc + 0.3 4.5 < v cc < 5.5 2.2 v cc + 0.5 v il input low voltage 2.2 < v cc < 2.7 ?0.3 0.6 v 2.7 < v cc < 3.6 ?0.3 0.8 4.5 < v cc < 5.5 ?0.5 0.8 i ix input leakage current gnd < v i < v cc ?1 +1 a i oz output leakage current gnd < v o < v cc , output disabled ?1 +1 a i cc v cc operating supply current f = f max = 1/t rc v cc = v ccmax i out = 0 ma, cmos levels 15 20 ma f = 1 mhz 2 2.5 i sb1 automatic ce power down current ? cmos inputs ce > v cc ? 0.2v, v in > v cc ? 0.2v or v in < 0.2v, f = f max (address and data only), f = 0 (oe , bhe , ble and we ), v cc = v cc(max) 17 a i sb2 automatic ce power down current ? cmos inputs ce > v cc ? 0.2v, v in > v cc ? 0.2v or v in < 0.2v, f = 0, v cc = v cc(max) 17 a notes 4. v il (min) = ?2.0v for pulse durations less than 20 ns. 5. v ih (max) = v cc + 0.75v for pulse durations less than 20 ns. 6. full device ac operation assumes a 100 s ramp time from 0 to v cc (min) and 200 s wait time after v cc stabilization. [+] feedback www.datasheet.in
CY62146ESL mobl ? document #: 001-43142 rev. ** page 4 of 12 capacitance tested initially and after any design or proce ss changes that may affect these parameters. parameter description test conditions max unit c in input capacitance t a = 25c, f = 1 mhz, v cc = v cc(typ) 10 pf c out output capacitance 10 pf thermal resistance tested initially and after any design or proce ss changes that may affect these parameters. parameter description test conditions tsop ii unit ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, two-layer printed circuit board 77 c/w jc thermal resistance (junction to case) 13 c/w ac test loads and waveforms parameters 2.5v 3.0v 5.0v unit r1 16667 1103 1800 r2 15385 1554 990 r th 8000 645 639 v th 1.20 1.75 1.77 v v cc v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v equivalent to: th venin equivalent all input pulses r th r1 th [+] feedback www.datasheet.in
CY62146ESL mobl ? document #: 001-43142 rev. ** page 5 of 12 data retention characteristics over the operating range parameter description conditions min typ [3] max unit v dr v cc for data retention 1.5 v i ccdr data retention current ce > v cc ? 0.2v, v in > v cc ? 0.2v or v in < 0.2v v cc = 1.5v 1 7 a t cdr [7] chip deselect to data retention time 0ns t r [8] operation recovery time t rc ns data retention waveform notes 7. tested initially and after any design or proce ss changes that may affect these parameters. 8. full device operation requires linear v cc ramp from v dr to v cc(min) > 100 s or stable at v cc(min) > 100 s. v cc(min) v cc(min) t cdr v dr > 1.5v data retention mode t r v cc ce [+] feedback www.datasheet.in
CY62146ESL mobl ? document #: 001-43142 rev. ** page 6 of 12 switching characteristics over the operating range [9] parameter description 45 ns unit min max read cycle t rc read cycle time 45 ns t aa address to data valid 45 ns t oha data hold from address change 10 ns t ace ce low to data valid 45 ns t doe oe low to data valid 22 ns t lzoe oe low to low-z [10] 5ns t hzoe oe high to high-z [10, 11] 18 ns t lzce ce low to low-z [10] 10 ns t hzce ce high to high-z [10, 11] 18 ns t pu ce low to power up 0 ns t pd ce high to power down 45 ns t dbe ble /bhe low to data valid 22 ns t lzbe ble /bhe low to low-z [10] 5ns t hzbe ble /bhe high to high-z [10, 11] 18 ns write cycle [12] t wc write cycle time 45 ns t sce ce low to write end 35 ns t aw address setup to write end 35 ns t ha address hold from write end 0 ns t sa address setup to write start 0 ns t pwe we pulse width 35 ns t bw ble /bhe low to write end 35 ns t sd data setup to write end 25 ns t hd data hold from write end 0 ns t hzwe we low to high-z [10, 11] 18 ns t lzwe we high to low-z [10] 10 ns notes 9. test conditions for all parameters other than tri-state paramete rs assume signal transition time of 3 ns or less, timing refe rence levels of 1.5v, input pulse levels of 0 to 3v, and output loading of the specified i ol /i oh as shown in the ac test loads and waveforms on page 4 . 10. at any temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any device. 11. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the outputs enter a high-impedance state. 12. the internal write time of the memory is defined by the overlap of we , ce = v il , bhe , ble or both = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing must be referenced to the edge of the sig nal that terminates the write. [+] feedback www.datasheet.in
CY62146ESL mobl ? document #: 001-43142 rev. ** page 7 of 12 switching waveforms figure 2. read cycle no.1: address transition controlled . [13, 14] figure 3. read cycle no. 2: oe controlled [14, 15] previous data valid data valid rc t aa t oha t rc address data out 50% 50% data valid t rc t ace t lzbe t lzce t pu high impedance i cc t hzoe t hzce t pd t hzbe t lzoe t dbe t doe impedance high i sb data out oe ce v cc supply current bhe /ble address notes 13. the device is continuously selected. oe , ce = v il , bhe , ble , or both = v il . 14. we is high for read cycle. 15. address valid before or similar to ce , bhe , ble transition low. [+] feedback www.datasheet.in
CY62146ESL mobl ? document #: 001-43142 rev. ** page 8 of 12 figure 4. write cycle no 1: we controlled [12, 16, 17] figure 5. write cycle 2: ce controlled [12, 16, 17] switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t wc t hzoe data in note 18 t bw t sce data io address ce we oe bhe /ble t hd t sd t pwe t ha t aw t sce t wc t hzoe data in t bw t sa ce address we data io oe bhe /ble note 18 notes 16. data io is high impedance if oe = v ih . 17. if ce goes high simultaneously with we = v ih , the output remains in a high impedance state. 18. during this period, the ios are in output state. do not apply input signals. [+] feedback www.datasheet.in
CY62146ESL mobl ? document #: 001-43142 rev. ** page 9 of 12 figure 6. write cycle 3: we controlled, oe low [17] figure 7. write cycle 4: bhe /ble controlled, oe low [17] switching waveforms (continued) data in t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe t bw note 18 ce address we data io bhe /ble t hd t sd t sa t ha t aw t wc data in t bw t sce t pwe t hzwe t lzwe note 18 data io address ce we bhe /ble [+] feedback www.datasheet.in
CY62146ESL mobl ? document #: 001-43142 rev. ** page 10 of 12 truth table ce we oe bhe ble inputs/outputs mode power h x x x x high-z deselect/power down standby (i sb ) l x x h h high-z output disabled active (i cc ) l h l l l data out (io 0 ?io 15 ) read active (i cc ) lhlhldata out (io 0 ?io 7 ); io 8 ?io 15 in high-z read active (i cc ) l h l l h data out (io 8 ?io 15 ); io 0 ?io 7 in high-z read active (i cc ) l h h l l high-z output disabled active (i cc ) l h h h l high-z output disabled active (i cc ) l h h l h high-z output disabled active (i cc ) l l x l l data in (io 0 ?io 15 ) write active (i cc ) l l x h l data in (io 0 ?io 7 ); io 8 ?io 15 in high-z write active (i cc ) l l x l h data in (io 8 ?io 15 ); io 0 ?io 7 in high-z write active (i cc ) ordering information speed (ns) ordering code package diagram package type operating range 45 CY62146ESL-45zsxi 51-85087 44-pin thin smal l outline package type ii (pb-free) industrial [+] feedback www.datasheet.in
CY62146ESL mobl ? document #: 001-43142 rev. ** page 11 of 12 package diagrams figure 8. 44-pin tsop ii, 51-85087 51-85087-*a [+] feedback www.datasheet.in
document #: 001-43142 rev. ** revised january 04, 2008 page 12 of 12 mobl is a registered trademark and more battery life is a trademark of cypress semiconductor. all product and company names men tioned in this document are the trademarks of their respective holders. CY62146ESL mobl ? document history page document title: CY62146ESL mobl ? 4-mbit (256k x 16) static ram document number: 001-43142 rev. ecn no. issue date orig. of change description of change ** 1875228 see ecn vkn/aesa new data sheet [+] feedback www.datasheet.in

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