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? 2000 in?eon technologies corp. ?optoelectronics division ?san jose, ca www.in?eon.com/opto ?1-888-in?eon (1-888-463-4636) osram opto semiconductors gmbh & co. ohg ?regensburg, germany www.osram-os.com ?+49-941-202-7178 1 march 23, 2000-16 features eight 0.145" (3.68 mm) high 5 x 5 dot matrix characters in red, yellow, high ef?iency red, green, or high ef?iency green built-in 2 page, 256 character rom. both pages mask programmable for custom fonts built-in decoders, multiplexers and drivers wide viewing angle, x axis ?0 , y axis ?5 programmable features: ? individual flashing character ? full display blinking ? multi-level dimming and blanking ?clear function ?lamp test internal or external clock end stackable dual-in-line plastic package low power: 20% less power consumption than 5 x 7 format red PLCD5580 yellow plcd5581 high efficiency red plcd5582 green plcd5583 high efficiency green plcd5584 low power 0.145" 8-character 5 x 5 dot matrix parallel input alphanumeric intelligent display devices description the PLCD5580 (red), plcd5581 (yellow), plcd5582 (high ef?iency red), plcd5583 (green), and plcd5584 (high ef?iency green) are eight digit, 5 x 5 dot matrix, alphanumeric intelligent display devices. the 0.145 inch high digits are packaged in a rugged, high quality, opti- cally transparent, standard 0.6 inch 28 pin plastic dip. the on-board cmos has a built-in two page, 256 character rom. both pages are mask programmable for 256 custom characters. the ?st page of rom of the standard product contains 128 characters including ascii, selected european and scienti? symbols. the sec- ond page contains katakana japanese characters, more european characters, avionics, and other graphic symbols. the plcd558x is designed for standard microprocessor interface techniques and is fully ttl compatible. the clock i/o and clock select pins allow the user to synchronize multiple display modules. 1.680 (42.67) max. 0.210 (5.34) 0.105 (2.67) 0.386 (9.8) 0.771 (19.58) 0.600 (15.24) 0.086 (2.19) 0.012 (0.30) typ. 0.100 (2.54) typ. 0.018 typ. (.46) 0.160 .020 (4.06 .50) 0.209 (5.31) plcd558x osram ww z 1 part number pin 1 indicator eia date code intensity code color bin (for yellow only) 0.145 (3.68) 0.189 (4.79) dimensions in inches (mm)
? 2000 in?eon technologies corp. ?optoelectronics division ?san jose, ca PLCD5580/1/2/3/4 www.in?eon.com/opto ?1-888-in?eon (1-888-463-4636) osram opto semiconductors gmbh & co. ohg ?regensburg, germany www.osram-os.com ?+49-941-202-7178 2 march 23, 2000-16 maximum ratings dc supply voltage ............................................ ?.5 to +7.0 vdc input voltage levels relative to ground ............................................... ?.5 to v cc +0.5 vdc operating temperature ..................................... ?0 c to +85 c storage temperature....................................... ?0 c to +100 c maximum solder temperature 0.063" below seating plane, t<5.0 s ........................................ 260 c relative humidity at 85 c ...................................................85% note: maximum voltage is with no leds illuminated. figure 1. enlarged character font figure 2. write cycle timing diagram notes: 1. all input voltages are v il =0.8 v, v ih =2.0 v. 2. these wave forms are not edge triggered. 3. t bw = t as + t ah 0.100 (2.54) 0.033 (0.84) typ. 0.011 (0.28) typ. 0.022 (0.56) typ. 0.145 (3.68) r0 r1 r2 r3 r4 c0 c1 c2 c3 c4 dimensions in inches (mm) tolerance: .xxx=?010 (.25) tas tah tceh tces tw tdh tds tbw ce d7-d0 wr fl, a3-a0 see notes tacc see notes see notes see notes switching speci?ations (over operating temperature range and v cc =4.5 v) notes: 1) wait 300 ns min. after the reset function is turned off. 2) t acc = t as + t w + t ah 3) the clear cycle time may be shortened by writing a second control word with the clear bit disabled, 160 ns after the ?st control word that enabled the clear bit. the flash ram and character ram may not be accessed until the clear cycle is complete. symbol description min. units t bw time between writes 30 ns t acc (2) display access time 130 ns t as address setup time 10 ns t ces chip enable setup time 0 ns t ah address hold time 20 ns t ceh chip enable hold time 0 ns t w write active time 100 ns t ds data valid prior to rising edge of write 50 ns t dh data hold time 20 ns t rc (1) reset active time 300 ns t clr (3) clear cycle time 3.0 s data wait data write control word-clear bit enabled wait 130 ns write control word-clear bit enabled
? 2000 in neon technologies corp. optoelectronics division san jose, ca PLCD5580/1/2/3/4 www.in neon.com/opto 1-888-in neon (1-888-463-4636) osram opto semiconductors gmbh & co. ohg regensburg, germany www.osram-os.com +49-941-202-7178 3 march 23, 2000-16 optical characteristics at 25 c ( v cc =5.0 v at full brightness) red PLCD5580 yellow plcd5581 high ef?iency red plcd5582 green plcd5583 high ef?iency green plcd5584 note: 1) peak luminous intensity is measured at t a = t j =25 c. no time is allowed for the device to warm up prior to measurement. description symbol min. typ. units peak luminous intensity (1) i v peak 70 90 cd/dot peak wavelength peak 660 nm dominant wavelength dom 639 nm description symbol min. typ. units peak luminous intensity (1) i v peak 130 210 cd/dot peak wavelength peak 583 nm dominant wavelength dom 585 nm description symbol min. typ. units peak luminous intensity (1) i v peak 150 330 cd/dot peak wavelength peak 630 nm dominant wavelength dom 626 nm description symbol min. typ. units peak luminous intensity (1) i v peak 150 260 cd/dot peak wavelength peak 565 nm dominant wavelength dom 570 nm description symbol min. typ. units peak luminous intensity (1) i v peak 200 510 cd/dot peak wavelength peak 568 nm dominant wavelength dom 574 nm
? 2000 in neon technologies corp. optoelectronics division san jose, ca PLCD5580/1/2/3/4 www.in neon.com/opto 1-888-in neon (1-888-463-4636) osram opto semiconductors gmbh & co. ohg regensburg, germany www.osram-os.com +49-941-202-7178 4 march 23, 2000-16 electrical characteristics at 25 c notes: 1) average i cc measured at full brightness. peak i cc = 5 8 x i avg i cc (# displayed). 2) internal/external frequency duty factor is 50%. parameters limits conditions min. typ. max. units v cc 4.5 5.0 5.5 v i cc blank 0.5 1.0 ma v cc =5.0 v, v in =5.0 v i cc 8 digits (1) 16 dots/character 240 290 ma v cc =5.0 v, ??displayed in all eight digits i ip current (with pull-up) ?118 a v cc =5.0 v, v in =0 v to v cc (wr , ce , fl , rst , clksel ) i i input leakage current (no pull-up) ?.0 a v cc =5.0 v, v in =0 v to v cc (clk i/o, a0-a3, d0-d7) v ih input voltage high 2.0 v cc +0.3 v v cc =4.5 v to 5.5 v v il input voltage low gnd ?.3 0.8 v v cc =4.5 v to 5.5 v v ol output voltage low (clock pin) 0.4 v v cc =4.5 v to 5.5 v, i ol =1.6 ma v oh output voltage high (clock pin) 2.4 v v cc =4.5 v to 5.5 v, i oh =40 a i oh output current high (clock i/o) ?.9 ma v cc =4.5 v, v oh =2.4 v i ol output current low (clock i/o) 1.6 2 ma v cc =4.5 v, v ol =0.4 v jc thermal resistance junction to case ?5 c/w f ext external clock input frequency (2) 28 81.14 khz v cc =5.0 v, clksel =0 f osc internal clock output frequency (2) 28 81.14 khz v cc =5.0 v, clksel =1 clock i/o buss loading 240 pf clock out rise time 500 ns v cc =4.5 v, v oh =2.4 v clock out fall time 500 ns v cc =4.5 v, v ol =0.4 v fm, digit multiplex frequency 125 256 362.5 hz blinking rate 0.98 2.0 2.83 hz
? 2000 in neon technologies corp. optoelectronics division san jose, ca PLCD5580/1/2/3/4 www.in neon.com/opto 1-888-in neon (1-888-463-4636) osram opto semiconductors gmbh & co. ohg regensburg, germany www.osram-os.com +49-941-202-7178 5 march 23, 2000-16 figure 3. top view pin assignments figure 4. cascading the plcd558x displays pin function pin function 1 rst 28 d7 2fl 27 d6 3a0 26d5 4a1 25d4 5 a2 24 d3 6 a3 23 d2 7 substr. bias 22 no pin 8 21 9 20 d1 10 no connect 19 d0 11 clksel 18 no connect 12 clk i/o 17 ce 13 wr 16 gnd (logic) 14 v cc 15 gnd (supply) 114 28 15 wr fl rst clk i/o clksel d0-d7 a0-a4 ce display d0-d7 a0-a4 ce up to14 more displays in between address decode chip 1 to 14 address data i/o wr fl rst v cc a6 a7 a8 a9 address decoder wr fl rst clk i/o clksel 0 15 display pin de?itions pin function de?ition 1 rst used for initialization of a display and sychronization of blinking for multiple displays 2fl low input accesses the flash ram 3 a0 address input lsb 4 a1 address input 5 a2 address input msb 6 a3 mode selector 7 substr. bias optional connection to v cc . cant be used to supply power to display. 8 9 10 no connect 11 clksel selects internal/external clock source 12 clk i/o outputs master clock or inputs external clock 13 wr a low will write data into the display if ce is low 14 v cc positive power supply input 15 gnd analog ground for led drivers 16 gnd digital ground for internal logic 17 ce enables access to the display 18 no connect 19 d0 data input lsb 20 d1 data input 21 no pin 22 23 d2 data input 24 d3 25 d4 26 d5 27 d6 28 d7 data input msb, selects rom, page 1 or 2
? 2000 in neon technologies corp. optoelectronics division san jose, ca PLCD5580/1/2/3/4 www.in neon.com/opto 1-888-in neon (1-888-463-4636) osram opto semiconductors gmbh & co. ohg regensburg, germany www.osram-os.com +49-941-202-7178 6 march 23, 2000-16 figure 5. character set?om page 1 figure 6. character set?om page 2 ascii code d0 d1 d2 d3 d6 d5 d4 hex 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 notes: 1. d7=0 2. high=1 level. low=0 level. ascii code d0 d1 d2 d3 d6 d5 d4 hex 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 notes: 1. d7=0 2. high=1 level. low=0 level.
? 2000 in neon technologies corp. optoelectronics division san jose, ca PLCD5580/1/2/3/4 www.in neon.com/opto 1-888-in neon (1-888-463-4636) osram opto semiconductors gmbh & co. ohg regensburg, germany www.osram-os.com +49-941-202-7178 7 march 23, 2000-16 figure 7. block diagram functional description the plcd558x block diagram is comprised of the following major blocks and registers. display memory consists of a 8 x 8 bit ram block. each of the eight 8-bit words holds the 7-bit ascii data (bit d0-d6). the 8th bit, d7 selects 1 of the 2 pages of character rom. d7=0 selects page 1 of the rom and d7=1 selects page 2 of the rom. a3=1. rst can be used to initialize display operation upon power up or during normal operation. when activated, rst will clear the flash ram and control word register (00h) and reset the internal counter. all eight display memory locations will be set to 20h to show blanks in all digits. fl pin enables access to the flash ram. the flash ram will set (d0=1) or reset (d0=0) ?shing of the character addressed by a0?2. the 1 x 8 bit control word ram is loaded with attribute data if a3=0. the control word logic decodes attribute data for proper implementation. character rom is designed for two pages of 128 characters each. both pages of the rom are mask programmable for cus- tom fonts. on the standard product page one contains standard ascii, selected european characters and some scienti? sym- bols. page two contains katakana characters, more european characters, avionics, and other graphic symbols. the clock source could either be the internal oscillator (clksel =1) of the device or an external clock (clksel =0) could be an input from another plcd558x display for the syn- chronization of blinking for multiple displays. 0 1 2 3 4 5 6 7 display rows 0 to 9 columns 0 to 19 column data row control logic & row drivers blink rate + 128 counter + 7 counter + 32 counter osc d6 d5 d4 d3 d2 d1 d0 d7 control word decode logic display memory 7 bit ascii code a0 a1 a2 a3 wr ce fl address decoder flash ram (8 x 1 bit) address lines row decoder rom 1 rom 2 128x7 bit ascii character decode (4.48k bits) 128x7 bit ascii character decode (4.48k bits) timing and control logic master slave latches digit 0 to 8 column drivers for digit 0 to 8 latches column decoder control word mux rate rst clk i/o clksel 8 x 8 bits the display multiplexer controls the row drivers so no addi- tional logic is required for a display system. the display has eight digits. each digit has 25 leds clustered into a 5 x 5 dot matrix. theory of operation the plcd558x programmable display is designed to work with all major microprocessors. data entry is via an eight bit parallel bus. three bits of address route the data to the proper digit location in the ram. standard control signals like wr and ce allow the data to be written into the display. d0?7 data bits are used for both ascii and control word data input. a3 acts as the mode selector. if a3=0, d0?7 load the ram with control word data. if a3=1, d0?7 will load the ram with ascii and page select data. in the later mode, d7=0 selects page 1 of character rom and d7=1 selects page 2 of character rom. for normal operation fl pin should be held high. when fl is held low, flash ram is accessed to set character blinking. the seven bit ascii code is decoded by the character rom to generate column data. twenty columns worth of data is sent out each display cycle and it takes fourteen display cycles to write into eight digits. the rows are being multiplexed in two sets of ?e rows each. the internal timing and control logic synchronizes the turning on of rows and presentation of column data to assure proper display operation.
? 2000 in neon technologies corp. optoelectronics division san jose, ca PLCD5580/1/2/3/4 www.in neon.com/opto 1-888-in neon (1-888-463-4636) osram opto semiconductors gmbh & co. ohg regensburg, germany www.osram-os.com +49-941-202-7178 8 march 23, 2000-16 data input commands x=dont care power up sequence upon power up display will come on at random. thus the display should be reset on power-up. the reset will clear the flash ram, control word register and reset the internal counter. all the dig- its will show blanks and display brightness level will be 100%. microprocessor interface the interface to a microprocessor is through the 8-bit data bus (d0-d7), the 4-bit address bus (a0?3) and control lines fl , ce and wr . to write data (ascii/control word) into the display ce should be held low, address and data signals stable and wr should be brought low. the control word is decoded by the control word decode logic. each code has a different function. the code for display brightness changes the duty cycle for the column drivers. the peak led current stays the same but the average led current diminishes depending on the intensity level. signals ce wr fl a3 a2 a1 a0 operation 1 x x 1 x x x x x x x x x x no operation no operation 0010000 write control register 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 digit 0 (left) digit 1 digit 2 digit 3 digit 4 digit 5 digit 6 digit 7 (right) write display data to user ram and page select register d0?6=ascii data d7=0 select rom 1 d7=1 select rom 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 digit 0 (left) digit 1 digit 2 digit 3 digit 4 digit 5 digit 6 digit 7 (right) write flash ram register d0=0 flashing character off d0=1 flashing character on d1?7=x the character flash enable causes 2.0 hz coming out of the counter to be anded with column drive signal and makes the column driver to cycle at 2.0 hz. thus the character ?shes at 2.0 hz. the display blink works the same way as the flash enable but causes all twenty column drivers to cycle at 2.0 hz thereby making all eight digits to blink at 2.0 hz. the lamp test causes the column drivers to run at 1/2 duty cycle thus all the leds in all eight digits turn on at 50% inten- sity. clear bit clears the character ram and writes a blank into the display memory. it however does not clear the control word. ascii data or control word data can be written into the display at this point. for multiple display operation, clk i/o must be properly selected. clk i/o will output the internal clock if clksel =1, or will allow input from an external clock if clksel =0.
? 2000 in neon technologies corp. optoelectronics division san jose, ca PLCD5580/1/2/3/4 www.in neon.com/opto 1-888-in neon (1-888-463-4636) osram opto semiconductors gmbh & co. ohg regensburg, germany www.osram-os.com +49-941-202-7178 9 march 23, 2000-16 control word format display brightness the display can be programmed to vary between blank, 13%, 20%, 27%, 40%, 53%, 80%, and full brightness. bits d0, d1 and d2 control the display brightness. x=dont care flash ram function character flash is controlled by fl pin, bit d0 and control word bit d3. combination of fl being low, proper digit address and d0 being high will write a ?sh bit into the flash ram register. in the control word mode when d3 is brought high, the above mentioned character will ?sh. setting the flash bit x=dont care a=selected address character flash control word x=dont care b=selected brightness display blinking blinking function is independent of flash function. when d4 is held high, entire display blinks at 2.0 hz. x=dont care b=selected brightness lamp test bit d6 when brought high will cause all the leds in all eight digits to light up at 53% brightness. selecting or de-selecting lamp test has no effect on the display memory. x=dont care ce wr fl a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 display brightness 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 100% brightness 80% brightness 53% brightness 40% brightness 27% brightness 20% brightness 13% brightness blank display ce wr fl a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 operation 0 0 0 0 0 0 x x a a a a a a x x x x x x x x x x x x x x 0 1 flash ram disabled flash ram enabled ce wr fl a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 operation 0 0 0 0 1 1 0 0 x x x x x x 0 0 0 0 x x 0 0 0 1 b b b b b b disable flashing char. enabled flashing char. ce wr fl a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 operation 0 0 0 0 1 1 0 0 x x x x x x 0 0 0 0 x x 0 1 0 0 b b b b b b display blinking disabled display blinking enabled ce wr fl a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 operation 0 0 0 0 1 1 0 0 x x x x x x 0 0 0 0 x x 0 0 x 0 x x x x x x lamp test disabled lamp test enabled
? 2000 in neon technologies corp. optoelectronics division san jose, ca PLCD5580/1/2/3/4 www.in neon.com/opto 1-888-in neon (1-888-463-4636) osram opto semiconductors gmbh & co. ohg regensburg, germany www.osram-os.com +49-941-202-7178 10 march 23, 2000-16 clear function clear function will clear the display. the flash ram will be set to all zeros. an ascii blank code (20h) will be written into t he display memory. the user must wait 3.0 s or write a new control word to the display with control word bit d7=0 to disable clear before writing any data to the display memory, otherwise all new data to the display memory will remain cleared. see switching speci? a- tions for clear function timing. x=dont care control word format d7 d6 d5 d4 d3 d2 d1 d0 d2 d1 d0 brightness 0 0 0 100% 00180% 01053% 01140% 10027% 10120% 11013% 1 1 1 0% blank d3 flash enable 0 disable flashing character 1 enable flashing character d4 blinking display 0 disable blinking display 1 enable blinking display d6 lamp test 0 disable lamp test 1 enable lamp test (all dots on at 53% brightness) d7 clear enable 0 disable clear 1 enable clear (clear data ram, page ram, flash ram) ce wr fl a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 operation 0 0 0 0 1 1 0 0 x x x x x x 0 1 x x x x x x x x x x x x x x clear disabled clear user ram, page ram, ?sh ram and dis- play clear enable lamp test not used blink enable flash enable brightness control
? 2000 in neon technologies corp. optoelectronics division san jose, ca PLCD5580/1/2/3/4 www.in neon.com/opto 1-888-in neon (1-888-463-4636) osram opto semiconductors gmbh & co. ohg regensburg, germany www.osram-os.com +49-941-202-7178 11 march 23, 2000-16 electrical and mechanical considerations voltage transient suppression for best results power the display and the components that interface with the display to avoid logic inputs higher than v cc . additionally, the leds may cause transients in the power sup- ply line while they change display states. the common practice is to place a parallel combination of a .01 f and a 22 f capac- itor between v cc and gnd for all display packages. esd protection the input protection structure of the PLCD5580/1/2/3/4 pro- vides signi?ant protection against esd damage. it is capable of withstanding discharges greater than 2.0 kv. take all the stan- dard precautions, normal for cmos components. these include properly grounding personnel, tools, tables, and transport carri- ers that come in contact with unshielded parts. if these condi- tions are not, or cannot be met, keep the leads of the device shorted together or the parts in anti-static packaging. soldering considerations the PLCD5580/1/2/3/4 can be hand soldered with sn63 solder using a grounded iron set to 260 c. wave soldering is also possible following these conditions: pre- heat that does not exceed 93 c on the solder side of the pc board or a package surface temperature of 85 c. water soluble organic acid ?x (except carboxylic acid) or rosin-based rma ?x without alcohol can be used. wave temperature of 245 c ? c with a dwell between 1.5 sec. to 3.0 sec. exposure to the wave should not exceed tempera- tures above 260 c for ?e seconds at 0.063" below the seating plane. the packages should not be immersed in the wave. post solder cleaning procedures the least offensive cleaning solution is hot d.i. water (60 c) for less than 15 minutes. addition of mild saponi?rs is accept- able. do not use commercial dishwasher detergents. for faster cleaning, solvents may be used. exercise care in choosing solvents as some may chemically attack the nylon package. maximum exposure should not exceed two minutes at elevated temperatures. acceptable solvents are tf (tri- chorotri?orethane), ta, 111 trichloroethane, and unheated acetone. (1) note: 1) acceptable commercial solvents are: basic tf, arklone, p. genesolv, d. genesolv da, blaco-tron tf, blaco-tron ta, and freon ta. unacceptable solvents contain alcohol, methanol, methylene chloride, ethanol, tp35, tcm, tmc, tms+, te, or tes. since many commercial mixtures exist, contact a solvent vendor for chemical composition information. some major solvent manufacturers are: allied chemical corporation, specialty chemical division, morristown, nj; baron-blakeslee, chi- cago, il; dow chemical, midland, mi; e.i. dupont de nem- ours & co., wilmington, de. for further information refer to appnotes 18 and 19 at www.in?eon.com/opto. an alternative to soldering and cleaning the display modules is to use sockets. naturally, 28 pin dip sockets .600" wide with .100" centers work well for single displays. multiple display assemblies are best handled by longer sip sockets or dip sock- ets when available for uniform package alignment. socket man- ufacturers are aries electronics, inc., frenchtown, nj; garry manufacturing, new brunswick, nj; robinson-nugent, new albany, in; and samtec electronic hardward, new albany, in. for further information refer to appnote 22 at www.in?- eon.com/opto. optical considerations the .145" high character of the plcd588x gives readability six to eight feet. proper ?ter selection enhances readability over this distance. using ?ters emphasizes the contrast ratio between a lit led and the character background. this will increase the discrimina- tion of different characters. the only limitation is cost. take into consideration the ambient lighting environment for the best cost/bene? ratio for ?ters. incandescent (with almost no green) or ?orescent (with almost no red) lights do not have the ?t spectral response of sunlight. plastic band-pass ?ters are an inexpensive and effec- tive way to strengthen contrast ratios. the plcd5880/5882 are red/high ef?iency red displays and should be matched with long wavelength pass ?ter in the 570 nm to 590 nm range. the plcd5881/5883/5884 should be matched with a yellow-green band-pass ?ter that peaks at 565 nm. for displays of multiple colors, neutral density grey ?ters offer the best compromise. additional contrast enhancement is gained by shading the dis- plays. plastic band-pass ?ters with built-in louvers offer the next step up in contrast improvement. plastic ?ters can be improved further with anti-re?ctive coatings to reduce glare. the trade-off is fuzzy characters. mounting the ?ters close to the display reduces this effect. take care not to overheat the plastic ?ter by allowing for proper air ?w. optimal ?ter enhancements are gained by using circular polar- ized, anti-re?ctive, band-pass ?ters. the circular polarizing fur- ther enhances contrast by reducing the light that travels through the ?ter and re?cts back off the display to less than 1%. several ?ter manufacturers supply quality ?ter materials. some of them are: panelgraphic corporation, w. caldwell, nj; sgl homalite, wilmington, de; 3m company, visual products division, st. paul, mn; polaroid corporation, polarizer division, cambridge, ma; marks polarized corporation, deer park, ny, hoya optics, inc., fremont, ca. one last note on mounting ?ters: recessing displays and bezel assemblies is an inexpensive way to provide a shading effect in overhead lighting situations. several bezel manufacturers are: r.m.f. products, batavia, il; nobex components, grif?h plas- tic corp., burlingame, ca; photo chemical products of califor- nia, santa monica, ca; i.e.e.-atlas, van nuys, ca.

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