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1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. http://www.intersil.com or 407-727-9207 | copyright ? intersil corporation 1999 august 1997 cdp68hc68t1 cmos serial real-time clock with ram and power sense/control features ? spi (serial peripheral interface) ? full clock features - seconds, minutes, hours (12/24, am/pm), day of week, date, month, year (0-99), automatic leap year ? 32 word x 8-bit ram ? seconds, minutes, hours alarm ? automatic power loss detection ? low minimum standby (timekeeping) voltage . . . 2.2v ? selectable crystal or 50/60hz line input ? buffered clock output ? battery input pin that powers oscillator and also connects to v dd pin when power fails ? three independent interrupt modes - alarm - periodic - power-down sense description the cdp68hc68t1 real-time clock provides a time/calendar function, a 32 byte static ram, and a 3 wire serial peripheral interface (spi bus). the primary function of the clock is to divide down a frequency input that can be supplied by the on-board oscillator in conjunction with an external crystal or by an external clock source. the internal oscillator can operate with a 32khz, 1mhz, 2mhz, or 4mhz crystal. an external clock source with a 32khz, 1mhz, 2mhz, 4mhz, 50hz or 60hz frequency can be used to drive the cdp68hc68t1. the time registers hold seconds, minutes, and hours, while the calendar registers hold day-of- week, date, month, and year information. the data is stored in bcd format. in addition, 12 or 24 hour operation can be selected. in 12 hour mode, an am/pm indicator is provided. the t1 has a programmable output which can provide one of seven outputs for use elsewhere in the system. computer handshaking is controlled with a wired-or interrupt output. the interrupt can be programmed to provide a signal as the result of: 1) an alarm programmed to occur at a predetermined combination of seconds, minutes, and hours; 2) one of 15 periodic interrupts ranging from sub- second to once per day frequency; 3) a power fail detect. the pse output and the v sys input are used for external power control. the cpur output is available to reset the processor under power-down conditions. cpur is enabled under software control and can also be activated via the cdp68hc68t1s watchdog. if enabled, the watchdog requires a periodic toggle of the ce pin without a serial transfer. pinouts cdp68hc68t1 (pdip, sbdip, soic) top view cdp68hc68t1 (soic) top view ordering information part number temp. range ( o c) package pkg. no. cdp68hc68t1e -40 to 85 16 ld pdip e16.3 CDP68HC68T1D -40 to 85 16 ld sbdip d16.3 cdp68hc68t1m -40 to 85 20 ld soic m20.3 cdp68hc68t1m2 -40 to 85 16 ld soic m16.3 cdp68hc68t1w -40 to 85 die note: pin number references throughout this speci?cation refer to the 16 lead pdip/sbdip/soic. see pinouts for cross reference. 9 10 11 12 13 14 16 15 8 7 6 5 4 3 2 1 clkout cpur int sck mosi miso v ss ce v dd xtal in v batt v sys xtal out line por pse 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 clk out cpur int nc sck mosi ce miso v ss pse vdd xtal in nc v batt xtal out v sys nc nc line por file number 1547.3
2 absolute maximum ratings thermal information supply voltage, v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +7v input voltage, v in . . . . . . . . . . . . . . . . . . . . v ss -0.3v to v dd +0.3v current drain per input pin excluding v dd and v ss , i . . . . . . 10ma current drain per output pin, i. . . . . . . . . . . . . . . . . . . . . . . . . 40ma operating conditions voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.0v to +6.0v standby (timekeeping) voltage . . . . . . . . . . . . . . . . +2.2v to +6.0v temperature range CDP68HC68T1D (sbdip package) . . . . . . . . . . . -55 o c to 125 o c cdp68hc68t1e (pdip package) . . . . . . . . . . . . . -40 o c to 85 o c cdp68hc68t1m/m2 (soic packages) . . . . . . . . . -40 o c to 85 o c input high voltage . . . . . . . . . . . . . . . . . . . . . . . (0.7 x v dd ) to v dd input low voltage . . . . . . . . . . . . . . . . . . . . . . . . . .0v to (0.3 x v dd ) serial clock frequency (f sck ) . . . . . . . . . . . . . . . . . +3.0v to +6.0v thermal resistance (typical, note 1) q ja ( o c/w) q jc ( o c/w) 16 ld pdip . . . . . . . . . . . . . . . . . . . . . 90 n/a 16 ld soic . . . . . . . . . . . . . . . . . . . . . 100 n/a 20 ld soic . . . . . . . . . . . . . . . . . . . . . 100 n/a 16 ld sbdip . . . . . . . . . . . . . . . . . . . . 75 24 maximum junction temperature (hermetic) . . . . . . . . . . . . . . . 175 o c maximum junction temperature (plastic) . . . . . . . . . . . . . . . 150 o c maximum storage temperature range (t stg ) . . . .-65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 o c (soic, lead tips only) caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not im plied. note: 1. q ja is measured with the component mounted on an evaluation pc board in free air. static electrical speci?cations at t a = -40 o c to +85 o c, v dd = v batt = 5v 5%, except as noted. parameter conditions limits units cdp68hc68t1 min (note 2) typ max quiescent device current i dd -1 10 m a output voltage high level v oh i oh = -1.6ma, v dd = 4.5v 3.7 - - v output voltage low level v ol i ol = 1.6ma, v dd = 4.5v - - 0.4 output voltage high level v oh i oh 10 m a, v dd = 4.5v 4.4 - - output voltage low level v ol i ol 10 m a, v dd = 4.5v - - 0.1 input leakage current i in -- 1 m a three-state output leakage current i out -- 10 operating current (note 3) (i d + i b ) v dd = v b = 5v crystal operation 32khz - 0.08 0.01 ma 1mhz - 0.5 0.6 2mhz - 0.7 0.84 4mhz - 1 1.2 pin 14 external clock (squarewave) (note 3) (i d + i b ) v dd = v s = 5v 32khz - 0.02 0.024 1mhz - 0.1 0.12 2mhz - 0.2 0.24 4mhz - 0.4 0.5 standby current (note 3) i b v s = 3v crystal operation 32khz - 20 25 m a 1mhz - 200 250 2mhz - 300 360 4mhz - 500 600 cdp68hc68t1
3 operating current (note 3) v dd = 5v, v b = 3v crystal operation i d i b i d i s ma 32khz - 25 15 30 20 1mhz - 0.08 0.15 0.1 0.18 2mhz - 0.15 0.25 0.18 0.3 4mhz - 0.3 0.4 0.36 0.5 standby current (note 3) i b v b = 2.2v crystal operation 32khz - 10 12 m a input capacitance c in v in = 0, t a = 25 o c-- 2pf maximum rise and fall times t r , t f (except xtal input and por pin 10) -- 2 m s input voltage (line input pin only, power sense mode) 0 10 12 v v sys > v b v t (for v b not internally connected to v dd ) - 0.7 - v power-on reset ( por) pulse width 100 75 - ns notes: 2. typical values are for t a = 25 o c and nominal v dd . 3. clock out (pin 1) disabled, outputs open circuited. no serial access cycles. static electrical speci?cations at t a = -40 o c to +85 o c, v dd = v batt = 5v 5%, except as noted. (continued) parameter conditions limits units cdp68hc68t1 min (note 2) typ max cdp68hc68t1
4 cdp68hc68t1 functional block diagram freeze circuit ce line 50/60hz am - pm and hour logic day/day of week oscillator xtal in xt al out v batt prescale second minute hour calendar logic month prescale select clock select clock control register interrupt control register clock and int logic clock out int v dd v ss power sense control int status register line pse v sys por cpur sck miso mosi comparator second latch minute latch hour latch 32 x 8 ram serial interface year 8-bit data bus figure 1. real time clock functional diagram
5 table 1. clock/calendar and alarm data modes address location (h) function decimal range bcd data range (note 4) bcd date example 20 seconds 0-59 00-59 18 21 minutes 0-59 00-59 49 22 hours 12 hour mode (note 5) 1-12 81-92 (am) a1-b2 (pm) a3 hours 24 hour mode 0-23 00-23 15 23 day of the week (sunday = 1) 1-7 01-07 03 24 day of the month (date) 1-31 01-31 29 25 month jan = 1, dec = 12 1-12 01-12 10 26 years 0-99 00-99 85 28 alarm seconds 0-59 00-59 18 29 alarm minutes 0-59 00-59 49 2a alarm hours (note 6) 12 hour mode 1-12 01-12 (am) 21-32 (pm) 23 alarm hours 24 hour mode 0-23 00-23 15 notes: 4. example: 3:49:18, tuesday. oct. 29,1985. 5. most significant bit, d7, is 0 for 24 hours, and 1 for 12 hour mode. data bit d5 is 1 for p.m. and 0 for a.m. in 12 h our mode. 6. alarm hours. data bit d5 is 1 for p.m. and 0 for a.m. in 12 hour mode. data bits d7 and d6 are dont care. seconds minutes hours day of week date month years not used sec alarm min alarm hrs alarm not used not used not used not used not used status register control register interrupt control register 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 $20 $21 $22 $23 $24 $25 $26 $27 $28 $29 $2a $2b $2c $2d $2e $2f $30 $31 $32 clock/calendar 13 bytes unused test mode 32 ram locations $00 $1f $20 $32 $33 $3f $55 85 63 51 50 32 31 0 r = readable w = writable r, w r, w r, w r, w r, w r, w r, w w w w r r, w r, w figure 2. address map cdp68hc68t1
6 programmers model - clock registers name write/read registers hex address tens 0-5 tens 0-5 12 hr 24 x pm/am tens 0-2 db7 xxxx tens 0-3 tens 0-1 tens 0-9 units 0-9 units 0-9 units 0-9 units 1-7 units 0-9 units 0-9 units 0-9 76543210 76543210 write only registers tens 0-5 tens 0-5 units 0-9 units 0-9 units 0-9 pm/am tens 0-2 xx 765 432 1 0 db0 seconds (00-59) minutes (00-59) db7, 1 = 12 hr., 0 = 24 hr. db = 1 pm, 0 = am hours (01-12 or 00-23 date day of month month (01-12) jan = 1 dec = 12 years (00-99) control interrupt alarm seconds (00-59) alarm minutes (00-59) alarm hours (01-12 or 00-23) plus am/pm in 12 hr. mode pm = 1, am = 0 read only registers status 7654321 0 bit hex address 00-1f 20 21 22 23 24 25 26 31 32 28 29 2a 30 ram data byte 01-28 29 30 31 note: x = dont care writes, x = 0 when read. x day of wk (01-07) sunday = 1 d7 d6 d5 d4 d3 d2 d1 d0 cdp68hc68t1
7 functional description the spi real-time clock consists of a clock/calendar and a 32 x 8 ram. communications is established via the spi (serial peripheral interface) bus. in addition to the clock/cal- endar data from seconds to years, and system ?exibility pro- vided by the 32-byte ram, the clock features computer handshaking with an interrupt output and a separate square- wave clock output that can be one of 7 different frequencies. an alarm circuit is available that compares the alarm latches with the seconds, minutes and hours time counters and acti- vates the interrupt output when they are equal. the clock is speci?cally designed to aid in power-down/up applications and offers several pins to aid the designer of battery backup systems. mode select the voltage level that is present at the v sys input pin at the end of power-on-reset selects the device to be in the single supply or battery backup mode. single-supply mode if v sys is a logic high when power-on-reset is completed, clk out, pse and cpur will be enabled and the device will be completely operational. cpur will be placed low if the logic level at the v sys pin goes low. if the output signals clk out, pse and cpur are disabled due to a power- down instruction, v sys brought to a logic low and then to a logic high will re-enable these outputs. an example of the single-supply mode is where only one supply is available and v dd , v batt and v sys are tied together to the supply. battery backup mode if v sys is a logic low at the end of power-on-reset, clk out, pse and cpur will be disabled (clk out, pse and cpur low). this condition will be held until v sys rises to a threshold (about 0.7v) above v batt . the outputs clk out, pse and cpur will then be enabled and the device will be operational. if v sys falls below a threshold above v batt the outputs clk out, pse and cpur will be disabled. an example of battery backup operation occurs if v sys is tied to v dd and v dd is not connected to a supply when a battery is connected to the v batt pin. (see pin functions, v batt for battery backup operation.) clock/calendar (see figure 1 and figure 2) the clock/calendar portion of this device consists of a long string of counters that is toggled by a 1hz input. the 1hz input is generated by a prescaler driven by an on-board oscillator that utilizes one of four possible external crystals or that can be driven by an external clock source. the 1hz trig- ger to the counters can also be supplied by a 50hz or 60hz input source that is connected to the line input pin. the time counters offer seconds, minutes and hours data in 12 hour or 24 hour format. an am/pm indicator is available that once set, toggles every 12 hours. the calendar counters consist of day (day of week), date (day of month), month and years information. data in the counters is in bcd format. the hours counter utilizes bcd for hour data plus bits for 12/24 hour and am/pm. the 7 time counters are accessed serially at addresses 20h through 26h. (see table 1). ram the real-time clock also has a static 32 x 8 ram that is located at addresses 00-1fh. transmitting the address/con- trol word with bit-5 low selects ram access. bits 0 through 4 select the ram location. alarm the alarm is set by accessing the three alarm latches and loading the required data. the alarm latches consist of sec- onds, minutes and hours registers. when their outputs equal the values in the seconds, minutes and hours time counters, an interrupt is generated. the interrupt output will go low if the alarm bit in the interrupt control register is set high. the alarm interrupt bit in the status register is set when the interrupt occurs (see pin functions, int pin). to preclude a false interrupt when loading the time counters, the alarm interrupt bit should be set low in the interrupt control regis- ter. this procedure is not required when the alarm time is set. watchdog function (see figure 6) when bit 7 in the interrupt control register is set high, the clocks ce (chip enable) pin must be toggled at a regular interval without a serial data transfer. if the ce is not toggled, the clock will supply a cpu reset pulse and bit 6 in the sta- tus register will be set. typical service and reset times are listed below. clock out the value in the 3 least signi?cant bits of the clock control register selects one of seven possible output frequencies. (see clock control register). this squarewave signal is available at the clk out pin. when power-down operation is initiated, the output is set low. control registers and status registers the operation of the real-time clock is controlled by the clock control and interrupt control registers. both registers are read-write registers. another register, the status reg- ister, is available to indicate the operating conditions. the status register is a read only register. power control power control is composed of two operations, power sense and power down/up. two pins are involved in power sens- ing, the line input pin and the int output pin. two additional pins are utilized during power-down/up operation. they are the pse (power supply enable) output pin and v sys input pin. 50hz 60hz xtal min max min max min max service time - 10ms - 8.3ms - 7.8ms reset time 20 40ms 16.7 33.3ms 15.6 31.3ms cdp68hc68t1
8 power sensing (see figure 3) when power sensing is enabled (bit 5 = 1 in interrupt con- trol register), ac transitions are sensed at the line input pin. threshold detectors determine when transitions cease. after a delay of 2.68ms to 4.64ms, plus the external input circuit rc time constant, an interrupt is generated and a bit is set in the status register. this bit can then be sampled to see if system power has turned back on. see pin functions, line pin. the power-sense circuitry operates by sensing the level of the voltage presented at the line input pin. this voltage is cen- tered around v dd and as long as it is either plus or minus a threshold (about 1v) from v dd a power-sense failure will not be indicated. with an ac signal present, remaining in this v dd window longer than a minimum of 2.68ms will activate the power-sense circuit. the larger the amplitude of the ac signal, the less time it spends in the v dd window, and the less likely a power failure will be detected. a 60hz, 10v p-p sine- wave voltage is an applicable signal to present at the line input pin to setup the power sense function. power down (see figure 4) power down is a processor-directed operation. a bit is set in the interrupt control register to initiate operation. 3 pins are affected. the pse (power supply enable) output, normally high, is placed low. the clk out is placed low. the cpur output, connected to the processors reset input is also placed low. in addition, the serial interface is disabled. power up (see figure 5 and figure 6) two conditions will terminate the power-down mode. the ?rst condition (see figure 5) requires an interrupt. the inter- rupt can be generated by the alarm circuit, the programma- ble periodic interrupt signal, or the power sense circuit. the second condition that releases power down occurs when the level on the v sys pin rises about 0.7v above the level at the v batt input, after previously falling to the level of v batt (see figure 6) in the battery backup mode or v sys falls to logic low and returns high in the single supply mode. figure 3. power-sensing functional diagram figure 4. power-down functional diagram figure 5. power-up functional diagram (initiated by interrupt signal xtal in xtal out line v dd real-time clock cdp68hc68t1 status register int int cpu cdp68hc05c16b v dd 0v i v sys interrupt control register i serial interface clk out cpur real-time clock cdp68hc68t1 pse osc reset cpu cdp68hc05c4b miso mosi from system power to system power control power sense or alarm circuit serial interface periodic interrupt signal power up real-time clock cdp68hc68t1 pse cpur clk out int miso mosi cdp68hc68t1
9 clk out clock output pin. one of seven frequencies can be selected (or this output can be set low) by the levels of the three lsbs in the clock-control register. if a frequency is selected, it will toggle with a 50% duty cycle except 2hz in the 50hz time base mode. (ex, if 1hz is selected, the output will be high for 500ms and low for the same period). during power-down operation (bit 6 in interrupt control register set to 1), the clock-output pin will be set low. cpur cpu reset output pin. this pin functions as an n-channel only, open-drain output and requires an external pull-up resistor. int interrupt output pin. this output is driven from a single nfet pulldown transistor and must be tied to an external pull-up resistor. the output is activated to a low level when: 1. power-sense operation is selected (b5 = 1 in interrupt control register) and a power failure occurs. 2. a previously set alarm time occurs. the alarm bit in the status register and interrupt-out signal are delayed 30.5 m s when 32khz operation is selected and 15.3 m s for 2mhz and 7.6 m s for 4mhz. 3. a previously selected periodic interrupt signal activates. the status register must be read to set the interrupt output high after the selected periodic interval occurs. this is also true when conditions 1 and 2 activate the interrupt. if power down had been previously selected, the interrupt will also reset the power-down functions. sck, mosi, miso see serial peripheral interface (spi) section in this data sheet. ce a positive chip-enable input. a low level at this input holds the serial interface logic in a reset state. this pin is also used for the watchdog function. v ss the negative power-supply pin that is connected to ground. pse power-supply enable output pin. this pin is used to control power to the system. the pin is set high when: 1. v sys rises above the v batt voltage after v sys was placed low by a system failure. 2. an interrupt occurs. 3. a power-on reset (if v sys is a logic high). the pse pin is set low by writing a high into bit 6 (power- down bit) in the interrupt control register. por power-on reset. a schmitt-trigger input that generates a power-on internal reset signal using an external r-c net- work. both control registers and frequency dividers for the oscillator and line input are reset. the status register is reset except for the ?rst time up bit (b4), which is set. single supply or battery backup operation is selected at the end of por. line this input is used for two functions. when not used it should be connected to v dd via a 10k w resistor. the ?rst function utilizes the input signal as the frequency source for the timekeeping counters. this function is selected by setting bit 6 in the clock control register. the second function enables the line input to sense a power failure. threshold detectors operating above and below v dd sense an ac voltage loss. bit 5 must be set to 1 in the interrupt control register and crystal or external clock source operation is required. bit 6 in the clock control register must be low to select xtal operation. oscillator circuit the cdp68hc68t1 has an on-board 150k resistor that is switched in series with its internal inverter when 32khz is selected via the clock control register. note: when ?rst powered up the series resistor is not part of the oscillator circuit. (the cdp68hc68t1 sets up for a 4mhz oscillator). miso v batt real-time clock pse cpur clk out serial interface v sys cdp68hc68t1 mosi figure 6. power-up functional diagram (initiated by a rise in voltage on the v sys pin) cdp68hc68t1
10 v sys this input is connected to the system voltage. after the cpu initiates power down by setting bit 6 in the interrupt control register to 1, the level on this pin will terminate power down if it rises about 0.7v above the level at the v batt input pin after previously falling below v batt +0.7v. when power down is terminated, the pse pin will return high and the clock output will be enabled. the cpur output pin will also return high. the logic level present at this pin at the end of por determines the cdp68hc68t1s operating mode. v batt the oscillator power source. the positive terminal of the bat- tery should be connected to this pin. when the level on the v sys pin falls below v batt +0.7v, the v batt pin will be internally connected to the v dd pin. when the voltage on v sys rises a threshold above (0.7v) the voltage on v batt , the connection from v batt to the v dd pin is opened. when the line input is used as the frequency source, v batt may be tied to v dd or v ss . the xtal in pin must be at v ss if v batt is at v ss . if v batt is connected to v dd , the xtal in pin can be tied to v ss or v dd . xtal in, xtal out these pins are connected to a 32,768hz. 1.048576mhz, 2.097152mhz or 4.194304mhz crystal. if an external clock is used, it should be connected to xtal in with xtal out left open. v dd the positive power-supply pin. clock control register start-stop a high written into this bit will enable the counter stages of the clock circuitry. a low will hold all bits reset in the divider chain from 32hz to 1hz. a clock out selected by bits 0, 1 and 2 will not be affected by the stop function except the 1hz and 2hz outputs. llne-xtal when this bit is set high, clock operation will use the 50 or 60-cycle input present at the line input pin. when the bit is low, the crystal input will generate the 1hz time update. xtal select one of 4 possible crystals is selected by value in these two bits: 0 = 4.194304mhz 2 = 1.048576mhz 1 = 2.097152mhz 3 = 32,768hz 50-60hz 50hz is selected as the line input frequency when this bit is set high. a low will select 60hz. the power-sense bit in the interrupt control register must be set low for line frequency operation. clock out the three bits specify one of the 7 frequencies to be used as the squarewave clock output: 0 = xtal 4 = disable (low output) 1 = xtal/2 5 = 1hz 2 = xtal/4 6 = 2hz 3 = xtal/8 7 = 50hz or 60hz xtal operation = 64hz all bits are reset by a power-on reset. therefore, the xtal is selected as the clock output at this time. interrupt control register watchdog when this bit is set high, the watchdog operation will be enabled. this function requires the cpu to toggle the ce pin periodically without a serial-transfer requirement. in the event this does not occur, a cpu reset will be issued. status register must be read before re-enabling watchdog. power down a high in this location will initiate a power down. a cpu reset will occur, the clk out and pse output pins will be set low and the serial interface will be disabled. xtal in 22m t1 xtal out r (note 8) crystal c2 10 - 40pf c1 5 - 30pf notes: 7. all frequencies recommended oscillator circuit. c1, c2 values crystal dependent. 8. r used for 32khz operation only. 100k - 300k range as specified by crystal manufacturer. figure 7. oscillator circuit clock control register (write/read) - address 31h d7 d6 d5 d4 d3 d2 d1 d0 start line xtal xtal 50hz clk out clk out clk out sel sel st op xt al 1 0 60hz 2 1 0 cdp68hc68t1
11 power sense this bit is used to enable the line input pin to sense a power failure. it is set high for this function. when power sense is selected, the input to the 50hz to 60hz prescaler is discon- nected. therefore, crystal operation is required when power sense is enabled. an interrupt is generated when a power failure is sensed and the power sense and interrupt true bit in the status register are set. when power sense is acti- vated, a 0 must be written to this location followed by a 1 to re-enable power sense. alarm the output of the alarm comparator is enabled when this bit is set high. when a comparison occurs between the sec- onds, minutes and hours time and alarm counters, the inter- rupt output is activated. when loading the time counters, this bit should be set low to avoid a false interrupt. this is not required when loading the alarm counters. see pin func- tions, int for explanation of alarm delay. periodic select the value in these 4 bits will select the frequency of the peri- odic output. (see table 2). interrupt control register (write/read) - address 32h d7 d6 d5 d4 d3 d2 d1 d0 watchdog power down power sense alarm periodic select note: all bits are reset by power-on reset. table 2. periodic interrupt output d0 - d3 value periodic interrupt output frequency frequency time base xtal line 0 disable 1 2048hz x 2 1024hz x 3 512hz x 4 256hz x 5 128hz x 6 64hz x 50 or 60hz x 7 32hz x 8 16hz x 9 8hz x 10 4hz x 11 2hz x x 12 1hz x x 13 minute x x 14 hour x x 15 day x x cdp68hc68t1
12 watchdog if this bit is set high, the watchdog circuit has detected a cpu failure. test mode when this bit is set high, the device is in the test mode. first-time up power-on reset sets this bit high. this signi?es that data in the ram and clock is not valid and should be initialized. interrupt true a high in this bit signi?es that one of the three interrupts (power sense, alarm, and clock) is valid. power-sense interrupt this bit set high signi?es that the power-sense circuit has generated an interrupt. alarm interrupt when the seconds, minutes and hours time and alarm counter are equal, this bit will be set high. status register must be read before loading interrupt control register for valid alarm indication after alarm activates. clock interrupt a periodic interrupt will set this bit high. all bits are reset by a power-on reset except the first- time up which is set. all bits except the power-sense bit are reset after a read of this register. pin signal description sck (serial clock input, note 11) this input causes serial data to be latched from the mosi input and shifted out on the miso output. mosi (master out/slave in, note 11) data bytes are shifted in at this pin, most signi?cant bit (msb) ?rst. miso (master in/slave out) data bytes are shifted out at this pin, most signi?cant bit (msb) ?rst. ce (chip enable, note 12) a positive chip-enable input. a low level at this input holds the serial interface logic in a reset state, and disables the output driver at the miso pin. notes: 11. these inputs will retain their previous state if the line driving them goes into a high-z state. 12. the ce input has as internal pull down device, if the input is in a low state before going to high z, the input can be left in a high z. functional description the serial peripheral interface (spi) utilized by the cdp68hc68t1 is a serial synchronous bus for address and data transfers. the clock, which is generated by the micro- computer is active only during address and data transfers. in systems using the cdp68hc05c4 or cdp68hc05d2, the status register (read only) - address 30h d7 d6 d5 d4 d3 d2 d1 d0 0 watchdog test mode first time up interrupt true power sense interrupt alarm interrupt clock interrupt truth table mode signal ce sck (note 9) mosi miso disable reset l input disabled input disabled high z write h cpol = 1 cpol = 0 data bit latch high z read h cpol = 1 cpol = 0 x next data bit shifted out (note 10) notes: 9. when interfacing to cdp68hc05 microcontrollers, serial clock phase bit, cpha, must be set = 1 in the microcomputers control register. 10. miso remains at a high z until 8-bits of data are ready to be shifted out during a read. it remains at a high z during the e ntire write cycle. cdp68hc68t1
13 inactive clock polarity is determined by the cpol bit in the microcomputers control register. a unique feature of the cdp68hc68t1 is that it automatically determines the level of the inactive clock by sampling sck when ce becomes active (see figure 8). input data (mosi) is latched internally on the internal strobe edge and output data (miso) is shifted out on the shift edge, as de?ned by figure 8. there is one clock for each data bit transferred (address, as well as data bits are transferred in groups of 8). address and data format there are three types of serial transfer: 1. address control - figure 9. 2. read or write data - figure 10. 3. watchdog reset (actually a non-transfer) figure 11. the address/control and data bytes are shifted msb ?rst, into the serial data input (mosi) and out of the serial data output (miso). any transfer of data requires an address/control byte to specify a write or read operation and to select a clock or ram location, followed by one or more bytes of data. data is transferred out of miso for a read and into mosi for a write operation. address/control byte - figure 9 it is always the ?rst byte received after ce goes true. to transmit a new address, ce must ?rst go false and then true again. bit 5 is used to select between clock and ram loca- tions. shift internal strobe internal strobe shift ce sck cpol = 1 sck ce cpol = 0 mosi msb msb -1 note: cpol is a bit that is set in the microcomputers control register. figure 8. serial ram clock (sck) as a function of mcu clock polarity (cpol) bit 7 6 5 4 3 2 1 0 w/ r 0 clk ram a4 a3 a2 a1 a0 04 a0-a4 selects 5-bit hex address of ram or specifies clock register. most significant address bit. if equal to 1, a0 through a4 selects a clock register. if equal to 0, a0 through a4 selects one of 32 ram locations. must be set to 0 when not in test mode 7w/r w/r = 1 initiates one or more write cycles.w/r = 0, initiates one or more read cycles. 5 clk ram 60 7 w/r note: sck can be either polarity. figure 9. address/control byte-transfer waveforms a2 a1 a0 a3 a4 clock 0 w/ r mosi ram sck (note) ce cdp68hc68t1
14 read/write data (see figure 10) read/write data follows the address/control byte. watchdog reset - (see figure 11) when watchdog operation is selected, ce must be toggled periodically or a cpu reset will be outputted. address and data data transfers can occur one byte at a time (figure 12) or in a multibyte burst mode (figure 13). after the real-time clock enabled, an address/control word is sent to set the clock or ram and select the type of operation (i.e., read or write). for a single-byte read or write, one byte is trans- ferred to or from the clock register or ram location speci- ?ed in the address/control byte and the real-time clock is then disabled. write cycle causes the latched clock register or ram address to automatically increment. incrementing continues after each transfer until the device is disabled. after incrementing to 1fh the address will wrap to 00h and continue. therefore, when the ram is selected the address will wrap to 00h and when the clock is selected the address will wrap 20h. d7 d6 d5 d4 d3 d2 d1 d0 7 6543210 bit d2 d1 d0 d3 d4 d5 d6 d7 d2 d1 d0 d3 d4 d5 d6 d7 ce sck (note) mosi miso note: sck can be either polarity. figure 10. read/write data transfer waveforms ce service time service time sck cpur figure 11. watchdog operation waveforms cdp68hc68t1
15 figure 12. single-byte transfer waveforms figure 13. multiple-byte transfer waveforms ce sck mosi write read mosi miso read data address byte address byte write data data byte write data byte ce sck data byte address byte mosi data byte data byte +1 w/ r address address byte mosi miso read data byte + (n-1) data byte data byte data byte cdp68hc68t1
16 dynamic electrical speci?cations bus timing v dd 10%, v ss = 0v dc , t a = 40 o c to 85 o c ident. no parameter limits (all types) units v dd = 3.3v v dd = 5v min max min max 1 chip enable setup time t evcv 200 - 100 - ns 2 chip enable after clock hold time t cvex 250 - 125 - ns 3 clock width high t wh 400 - 200 - ns 4 clock width low t wl 400 - 200 - ns 5 data in to clock setup time t dvcv 200 - 100 - ns 7 clock to data propagation delay t cvdv - 200 - 100 ns 8 chip disable to output high z t exqz - 200 - 100 ns 11 output rise time t r - 200 - 100 ns 12 output fall time t f - 200 - 100 ns a data in after clock hold time t cvdx 200 - 100 - ns b clock to data out active t cvqx - 200 - 100 ns c clock recovery time t rec 200 - 200 - ns cdp68hc68t1
17 timing diagrams figure 14. write-cycle timing waveforms figure 15. read-cycle timing waveforms system diagrams note: example of a system in which power is always on. clock circuit driven by line input frequency. figure 16. power-on always system diagram 5 a 5 i 2 3 4 c mosi ce sck w/ r a6 a0 d7 o d6 o d1 n do n 12 11 8 a 5 7 8 2 c i 4 3 mosi miso ce sck w/ r a6 a0 d7 o d6 o di n do n v dd irq cdp68hc05c8b reset port sck mosi miso por v dd int v sys line cdp68hc68t1 ce v batt cpur sck mosi miso xtal in bridge regulator v dd ac line cdp68hc68t1
18 note: example of a system in which the power is controlled by an external source. the line input pin can sense when the switch o pens by use of the power-sense interrupt. the cdp68hc68t1 crystal drives the clock input to the cpu using the clk out pin. on power down wh en v sys < v batt + 0.7v. v batt will power the cdp68hc68t1. a threshold detect activates a p-channel switch, connecting v batt to v dd . v batt always supplies power to the oscillator, keeping voltage frequency variation to a minimum. figure 17. externally controlled power system diagram a procedure for power-down operation might consist of the following: 1. set power sense operation by writing bit 5 high in the interrupt control register. 2. when an interrupt occurs, the cpu reads the status register to determine the interrupt source. 3. sensing a power failure, the cpu does the necessary housekeeping to prepare for shutdown. 4. the cpu reads the status register again after several milliseconds to determine validity of power failure. 5. the cpu sets power-down bit 6 and disables all interrupts in the interrupt control register when power down is veri?ed. this causes the cpu reset and clock out to be held low and disconnects the serial interface. 6. when power returns and v sys rises above v batt , power down is terminated. the cpu reset is released and serial communi- cation is established. system diagrams (continued) por v dd v sys line cdp68hc68t1 ce cpur miso mosi sck v batt clk out int v dd cdp68hc05c8b port (e.g., pco) reset miso mosi sck osc 1 irq bridge generator ac line v dd v dd cdp68hc68t1
19 figure 18. example of a system with a battery backup system diagrams (continued) ac line regulator por v dd v sys v batt pse cpur int clk xtal line out ce spi v ss 20k 1k 0.047 v dd rtc 22m r charge 0.1 100k v dd 3 nc v dd reset cdp68hc05c4b irq osc1 port spi v ss (eps) enabled power supply cdp68hc68t1
20 example of an automotive system. the v sys and line inputs can be used to sense the ignition turning on and off. an external switch is included to activate the system without turning on the ignition. also, the cmos cpu is not powered down with the syst em v dd , but is held in a low power reset mode during power down. when restoring power the cdp68hc68t1 will enable the clk out pin and set the pse and cpur high. important application note: those units with a code of 6pg have delayed alarm interrupts of 8.3ms regardless of cdp68hc68t1s operating frequency. (see pin functions, int.) in addition, reading the status register before delayed alarm acti - vates will disable alarm signal. figure 19. automotive system diagram system diagrams (continued) xtal line v dd v sys v batt por 2mhz pse cpur clk out spi ce int t1 v ss v dd reset osc1 irq spi port cdp68hc05c4b v ss port 5v reg + - 12v ignition 3 clock button enabled power cdp68hc68t1
21 cdp68hc68t1 dual-in-line plastic packages (pdip) c l e e a c e b e c seating base plane plane -c- d1 b1 b e d d1 a a2 l a1 0.010 (0.25) c a m b s notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions, the inch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the mo series symbol list in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are measured with the package seated in je- dec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be perpendic- ular to datum . 7. e b and e c are measured at the lead tips with the leads unconstrained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- e16.3 (jedec ms-001-bb issue d) 16 lead dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.210 - 5.33 4 a1 0.015 - 0.39 - 4 a2 0.115 0.195 2.93 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.045 0.070 1.15 1.77 8, 10 c 0.008 0.014 0.204 0.355 - d 0.735 0.775 18.66 19.68 5 d1 0.005 - 0.13 - 5 e 0.300 0.325 7.62 8.25 6 e1 0.240 0.280 6.10 7.11 5 e 0.100 bsc 2.54 bsc - e a 0.300 bsc 7.62 bsc 6 e b - 0.430 - 10.92 7 l 0.115 0.150 2.93 3.81 4 n16 169 rev. 0 12/93
22 cdp68hc68t1 ceramic dual-in-line metal seal packages (sbdip) notes: 1. index area: a notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturers identification shall not be used as a pin one identification mark. 2. the maximum limits of lead dimensions b and c or m shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. 4. corner leads (1, n, n/2, and n/2 +1) may be configured with a partial lead paddle. for this configuration dimension b3 replaces dimension b2. 5. dimension q shall be measured from the seating plane to the base plane. 6. measure dimension s1 at all four corners. 7. measure dimension s2 from the top of the ceramic body to the nearest metallization or lead. 8. n is the maximum number of terminal positions. 9. braze fillets shall be concave. 10. dimensioning and tolerancing per ansi y14.5m - 1982. 11. controlling dimension: inch. bbb c a - b s c q l a seating base d plane plane s s -d- -a- -c- e a -b- aaa c a - b m d s s ccc c a - b m d s s d e s1 b2 b a e m c1 b1 (c) (b) section a-a base lead finish metal e a/2 s2 m a d16.3 mil-std-1835 cdip2-t16 (d-2, configuration c) 16 lead ceramic dual-in-line metal seal package symbol inches millimeters notes min max min max a - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 d - 0.840 - 21.34 - e 0.220 0.310 5.59 7.87 - e 0.100 bsc 2.54 bsc - ea 0.300 bsc 7.62 bsc - ea/2 0.150 bsc 3.81 bsc - l 0.125 0.200 3.18 5.08 - q 0.015 0.060 0.38 1.52 5 s1 0.005 - 0.13 - 6 s2 0.005 - 0.13 - 7 a 90 o 105 o 90 o 105 o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - m - 0.0015 - 0.038 2 n16 168 rev. 0 4/94
23 cdp68hc68t1 small outline plastic packages (soic) index area e d n 123 -b- 0.25(0.010) c a m b s e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m a notes: 1. symbols are defined in the mo series symbol list in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.00 6 inch) per side. 4. dimension e does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. l is the length of terminal for soldering to a substrate. 7. n is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width b, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.02 4 inch) 10. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. m16.3 (jedec ms-013-aa issue c) 16 lead wide body small outline plastic package symbol inches millimeters notes min max min max a 0.0926 0.1043 2.35 2.65 - a1 0.0040 0.0118 0.10 0.30 - b 0.013 0.0200 0.33 0.51 9 c 0.0091 0.0125 0.23 0.32 - d 0.3977 0.4133 10.10 10.50 3 e 0.2914 0.2992 7.40 7.60 4 e 0.050 bsc 1.27 bsc - h 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 l 0.016 0.050 0.40 1.27 6 n16 167 a 0 o 8 o 0 o 8 o - rev. 0 12/93
24 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/o r speci?cations at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of p atents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see web site http://www.intersil.com sales of?ce headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (407) 724-7000 fax: (407) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil (taiwan) ltd. taiwan limited 7f-6, no. 101 fu hsing north road taipei, taiwan republic of china tel: (886) 2 2716 9310 fax: (886) 2 2715 3029 cdp68hc68t1 small outline plastic packages (soic) index area e d n 123 -b- 0.25(0.010) c a m b s e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m a notes: 1. symbols are defined in the mo series symbol list in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension e does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. l is the length of terminal for soldering to a substrate. 7. n is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width b, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. m20.3 (jedec ms-013-ac issue c) 20 lead wide body small outline plastic package symbol inches millimeters notes min max min max a 0.0926 0.1043 2.35 2.65 - a1 0.0040 0.0118 0.10 0.30 - b 0.013 0.0200 0.33 0.51 9 c 0.0091 0.0125 0.23 0.32 - d 0.4961 0.5118 12.60 13.00 3 e 0.2914 0.2992 7.40 7.60 4 e 0.050 bsc 1.27 bsc - h 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 l 0.016 0.050 0.40 1.27 6 n20 207 a 0 o 8 o 0 o 8 o - rev. 0 12/93

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