rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad9617 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1999 low distortion, precision, wide bandwidth op amp features usable closed-loop gain range: 6 1 to 6 40 low distortion: C67 dbc (2nd) at 20 mhz small signal bandwidth: 190 mhz (a v = +3) large signal bandwidth: 150 mhz at 4 v p-p settling time: 10 ns to 0.1%; 14 ns to 0.02% overdrive and output short circuit protected fast overdrive recovery dc nonlinearity 10 ppm applications driving flash converters d/a current-to-voltage converters if, radar processors baseband and video communications photodiode, ccd preamps pin configuration 1 2 3 4 nc * ad9617 Cinput +input Cv s +v s output ** nc = no connect * optional +v s ** optional Cv s note: for best settling time and distortion performance, use optional supply connections. performance indicated in specifications is based on supply connections to these pins. 8 7 6 5 general description the ad9617 is a current feedback amplifier which utilizes a proprietary architecture to produce superior distortion and dc precision. it achieves this along with fast settling, very fast slew rate, wide bandwidth (both small signal and large signal) and exceptional signal fidelity. the device achieves C67 dbc 2nd harmonic distortion at 20 mhz while maintaining 190 mhz small signal and 150 mhz large signal bandwidths. these attributes position the ad9617 as an ideal choice for driving flash adcs and buffering the latest generation of dacs. optimized for applications requiring gain between 1 to 15, the ad9617 is unity gain stable without external compensation. the ad9617 offers outstanding performance in high fidelity, wide bandwidth applications in instrumentation ranging from network and spectrum analyzers to oscilloscopes, and in military systems such as radar, sigint and esm systems. the superior slew rate, low overshoot and fast settling of the ad9617 allow the device to be used in pulse applications such as communications receivers and high speed ate. most monolithic op amps suffer in these precision pulse applications due to slew rate limiting. the ad9617j operates over the range of 0 c to +70 c and is available in either an 8-lead plastic dip or an 8-1ead plastic small outline package (soic).
C2C rev. b ad9617Cspecifications dc electrical characteristics test ad9617jn/jr ad9617aq/sq* ad9617bq/tq* parameter conditions temp level min typ max min typ max min typ max units input offset voltage 1, 2 +25 c i C1.1 +0.5 +2.2 C1.1 +0.5 +2.2 +0.0 +0.5 +1.35 mv input offset voltage tc 2 full iv C4 +3 +25 C4 +3 +25 C4 +3 +25 m v/ c input bias current 2 inverting +25 c i C50 0 +50 C50 0 +50 C25 0 +25 m a noninverting +25 c i C25 +5 +35 C25 +5 +35 C15 +5 +20 m a input bias current tc 2 noninverting full iv C50 +30 +125 C50 +30 +125 C50 +30 +125 na/ c inverting full iv C50 +50 +150 C50 +50 +150 C50 +50 +150 na/ c input resistance noninverting +25 c v 60 60 60 k w input capacitance noninverting +25 c v 1.5 1.5 1.5 pf common-mode input range 3 t = t max ? ii 1.4 1.5 1.4 1.5 1.4 1.5 v t = t min to +25 c ? ii 1.7 1.8 1.7 1.8 1.7 1.8 v common-mode rejection ratio 4 t = t min to t max ? ii 44 48 44 48 44 48 db t = t min to +25 c ? ii 48 51 48 51 48 51 db power supply rejection ratio d v s = 5% full ii 48 51 48 51 48 51 db open loop gain t o at dc +25 c v 500 500 500 k w nonlinearity at dc +25 c iv 10 10 10 ppm output voltage range +25 cii 3.4 3.8 3.4 3.8 3.4 +3.8 v output impedance at dc +25 c v 0.07 0.07 0.07 w output current (50 w load) t = +25 c to t max ? ii 60 60 60 ma t = t min ? ii 50 50 50 ma notes *pending obsoletion: last-time buy october 25, 1999. 1 measured with respect to the inverting input. 2 typical is defined as the mean of the distribution. 3 measured in voltage follower configuration. 4 measured with v in = +0.25 v. specifications subject to change without notice. absolute maximum ratings 1 supply voltages ( v s ) . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 v common-mode input voltage . . . . . . . . . . . . . . . . . . . . . vs differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3 v continuous output current 2 . . . . . . . . . . . . . . . . . . . . . 70 ma operating temperature ranges ad9617jn/jr . . . . . . . . . . . . . . . . . . . . . . . . 0 c to +70 c storage temperature ad9617jn/jr . . . . . . . . . . . . . . . . . . . . . C65 c to +125 c junction temperature 3 ad9617jn/jr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150 c lead soldering temperature (10 seconds) . . . . . . . . . +300 c notes 1 absolute maximum ratings are limiting values to be applied individually and beyond which the serviceability of the circuit may be impaired. functional operability is not necessarily implied. exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 output is short circuit protected to ground, but not to supplies. continuous short circuit to ground may affect device reliability. 3 typical thermal impedances (part soldered onto board): plastic dip: q ja = 140 c/w; q jc = 30 c/w. soic package: q ja = 155 c/w; q jc = 40 c/w. (unless otherwise noted, a v = +3; 6 v s = 6 5 v; r f = 400 v ; r load = 100 v )
C3C rev. b ad9617 ac electrical characteristics test ad9617jn/jr ad9617aq/sq* ad9617bq/tq* parameter conditions temp level min typ max min typ max min typ max units frequency domain bandwidth (C3 db) small signal v out 2 v p-p full ii 135 190 145 190 145 190 mhz large signal v out = 4 v p-p full iv 150 115 150 115 150 mhz bandwidth variation vs. a v a v = C1 to 15 +25 c v 40 40 40 mhz amplitude of peaking (<50 mhz) t = t min to +25 c ? ii 0 0 0.3 0 0.3 db t = t max ? ii 0 0 0.6 0 0.6 db amplitude of peaking (>50 mhz) t = t min to +25 c ? ii 0 0 0.8 0 0.8 db t = t max ? ii 0 0 1.0 0 1.0 db amplitude of roll-off (<60 mhz) full ii 0.1 0.1 0.6 0.1 0.6 db phase nonlinearity dc to 75 mhz +25 c v 0.5 0.5 0.5 degree 2nd harmonic distortion 2 v p-p; 4.3 mhz full iv C86 C78 C86 C78 C86 C78 dbc 2 v p-p; 20 mhz full iv C67 C59 C67 C59 C67 C59 dbc 2 v p-p; 60 mhz full ii C51 C43 C51 C43 C51 C43 dbc 3rd harmonic distortion 2 v p-p; 4.3 mhz full iv C83 C75 C83 C75 C83 C75 dbc 2 v p-p; 20 mhz full iv C69 C61 C69 C61 C69 C61 dbc 2 v p-p; 60 mhz full ii C54 C46 C54 C46 C54 C46 dbc input noise voltage 10 mhz +25 c v 1.2 1.2 1.2 nv/ ? hz inverting input noise current 10 mhz +25 c v 29 29 29 pa/ ? hz average equivalent integrated input noise voltage 0.1 mhz to 200 mhz +25 c v 55 55 55 m v, rms time domain slew rate v out = 4 v step full iv 1400 1100 1400 1100 1400 v/ m s rise/fall time v out = 2 v step full iv 2.0 2.0 2.5 2.0 2.5 ns v out = 4 v step t = +25 c to t max ? iv 2.4 2.4 3.3 2.4 3.3 ns v out = 4 v step t = t min ? iv 2.4 2.4 3.5 2.4 3.5 ns overshoot v out = 2 v step full iv 3 3 14 3 14 % settling time to 0.1% v out = 2 v step full iv 10 10 15 10 15 ns to 0.02% v out = 2 v step full iv 14 14 23 14 23 ns to 0.1% v out = 4 v step full iv 11 11 16 11 16 ns to 0.02% v out = 4 v step full iv 16 16 24 16 24 ns 2 overdrive recovery to 2 mv of final value v in = 1.7 v step +25 c v 50 50 50 ns propagation delay +25 cv 2 2 2 ns differential gain 1 full v <0. 01 <0. 01 <0 .01 % differential phase 1 full v 0.01 0.01 0.01 degree power supply requirements quiescent current +i s full ii 34 48 34 48 34 48 ma Ci s full ii 34 48 34 48 34 48 ma notes *pending obsoletion: last-time buy october 25, 1999. 1 frequency = 4.3 mhz; r l = 150 w ; a v = +3. specifications subject to change without notice. (unless otherwise noted, a v = +3; 6 v s = 6 5 v; r f = 400 v ; r load = 100 v )
ad9617 C4C rev. b explanation of test levels test level i - 100% production tested. ii - 100% production tested at +25 c and sample tested at specified temperatures. ac testing of j grade devices done on sample basis. iii - sample tested only. iv - parameter is guaranteed by design and characterization testing. v - parameter is a typical value only. vi - all devices are 100% production tested at +25 c. 100% production tested at temperature extremes for extended temperature devices; sample tested at temperature ex- tremes for commercial/industrial devices. ordering guide temperature package package model range description option ad9617jn 0 c to +70 c plastic dip n-8 ad9617jr 0 c to +70 c soic so-8 ad9617jr-reel 0 c to +70 c 13" tape and reel so-8 die connections +v s Cv s Cv s Cinput +input +v s output top view (not to scale) die size = 53 3 67 3 15 mils
ad9617 C5C rev. b typical performance characteristics (a v = +3; 6 v s = 6 5 v; r f = 400 v, unless otherwise noted) frequency C mhz 3 0 magnitude C db 40 80 120 160 200 2 1 0 C1 C2 C3 C4 C5 C6 C7 45 0 C45 C90 C135 C180 90 135 180 a v = +5 a v = +1 a v = +20 phase C degrees figure 1. noninverting frequency response frequency C mhz 3 0 magnitude C db 40 80 120 160 200 2 1 0 C1 C2 C3 C4 C5 C6 C7 45 0 C45 C90 C135 C180 90 135 180 phase C de g rees a v = C5 a v = C1 a v = C20 figure 2. inverting frequency response frequency C hz 120 10k gain C db 100k 1m 10m 100m 1g 105 90 75 60 45 30 15 0 90 120 150 180 210 240 60 30 0 gain phase relative phase C de g rees 100 v test circuit figure 3. open loop transimpedance gain [ t(s) relative to 1 w ] frequency C hz 10 100 db 1k 10k 100k 1m 100m 15 20 25 30 35 40 45 50 55 60 cmrr psrr 10m figure 4. cmrr and psrr time C m s 0.1 0 settling percentage C % 816243240 0.08 0.06 0.04 0.02 0 C0.02 C0.04 C0.1 v out = 4v step 100 v test circuit 6pf C0.06 C0.08 figure 5. settling time time C m s 0.1 0 settling percentage C % 246810 0.08 0.06 0.04 0.02 0 C0.02 C0.04 C0.1 v out = 4v step 100 v test circuit 6pf C0.06 C0.08 figure 6. long term settling time
ad9617 C6C rev. b frequency C mhz 40 0 Cdbc 24610 50 60 70 80 100 100 v load 90 500 v load 20 40 60 100 v out = 2v p-p = 2nd harmonic = 3rd harmonic 8 figure 7. harmonic distortion frequency C mhz 3 0 magnitude C db 40 80 120 160 200 2 1 0 C1 C2 C3 C4 C5 C6 C7 45 0 C45 C90 C135 C180 90 135 180 r l = 500 v phase C de g rees r l = 100 v r l = 50 v figure 8. frequency response vs. r load frequency C mhz 115 100 pa/ hz 1k 10k 100k 100 85 70 55 40 25 4 3 2 1 5 6 7 nv/ hz nv/ hz pa/ hz (inverting) figure 9. equivalent input noise frequency C mhz 50 0 intercept C +dbm 30 60 90 120 150 40 30 20 50 v test circuit 50 v figure 10. intermodulation distortion (imd) 10ns/div 2.5 analog input C volts 2.0 1.5 1.0 0.5 0 C0.5 C1.0 C1.5 C2.0 C2.5 a v = +3 a v = C3 100 v test circuit 6pf figure 11. large signal pulse response 10ns/div analog input C volts 1.0 0.5 0 C0.5 C1.0 a v = +3 a v = C3 100 v test circuit 6pf figure 12. small signal pulse response
ad9617 C7C rev. b theory of operation the ad9617 has been designed to combine the key attributes of traditional low frequency precision amplifiers with exceptional high frequency characteristics that are independent of closed- loop gain. previous high frequency closed-loop amplifiers have low open loop gain relative to precision amplifiers. this results in relatively poor dc nonlinearity and precision, as well as exces- sive high frequency distortion due to open loop gain roll-off. operational amplifiers use two basic types of feedback correc- tion, each with advantages and disadvantages. voltage feedback topologies exhibit an essentially constant gain bandwidth prod- uct. this forces the closed-loop bandwidth to vary inversely with closed-loop gain. moreover, this type design typically slew rate limits in a way that causes the large signal bandwidth to be much lower than its small signal characteristics. a newer approach is to use current feedback to realize better dynamic performance. this architecture provides two key at- tributes over voltage feedback configurations: (1) avoids slew rate limiting and therefore large signal bandwidth can approach small signal performance; and (2) low bandwidth variation ver- sus gain settings, due to the inherently low open loop inverting input resistance (r s ). the ad9617 uses a new current feedback topology that over- comes these limitations and combines the positive attributes of both current feedback and voltage feedback designs. these devices achieve excellent high frequency dynamics (slew, bw and distortion) along with excellent low frequency linearity and good dc precision. dc gain characteristics a simplified equivalent schematic is shown below. when operat- ing the device in the inverting mode, the input signal error current (i e ) is amplified by the open loop transimpedance gain (t o ). the output signal generated is equal to t o i e . negative feedback is applied through r f such that the device operates at a gain (g) equal to Cr f /r i . noninverting operation is similar, with the input signal applied to the high impedance buffer (noninverting) input. as before, an output (buffer) error current (i e ) is generated at the low imped- ance inverting input. the signal generated at the output is fed back to the inverting input such that the external gain is (l + r f / r i ). the feedback mechanics are identical to the voltage feed- back topology when exact equations are used. t o v n v i r i c i + C i e r s l s c c v o r f figure 13. equivalent circuit the major difference lies in the front end architecture. a voltage feedback amplifier has symmetrical high resistance (buffered) inputs. a current feedback amplifier has a high noninverting resistance (buffered) input and a low inverting (buffer output) input resistance. the feedback mechanics can be easily devel- oped using current feedback and transresistance open loop gain t(s) to describe the i/o relationship. (see typical specification chart.) dc closed-loop gain for the ad9617 can be calculated using the following equations: g = v o v i ? - r f / r i 1 + 1/ lg inverting (1) g = v o v n ? 1 + r f / r i 1 + 1/ lg noninverting (2) where 1 lg ? r s r f + r s i r i () ts () r s i r i () (3) because the noninverting input buffer is not ideal, input resis- tance r s (at dc) is gain dependent and is typically higher for noninverting operation than for inverting operation. r s will approach the same value ( < 7 w ) for both at input frequencies above 50 mhz. below the open loop corner frequency, the noninverting r s can be approximated as: r s noninverting () ? 7 + ts () a o = 7 + t o a o dc (4) where: a o = open loop voltage gain < g 600 inverting r s below the open loop corner frequency can be ap- proximated as: r s inverting () ? 7 + ts () a o = 7 + t o a o dc (5) where: a o = 40,000. the ad9617 approaches this condition. with t o = 1 10 6 w , r l = 500 w and r s = 25 w (dc), a gain error no greater than 0.05% typically results for g = C1 and 0.15% for g = C40. moreover, the architecture linearizes the open loop gain over its operating voltage range and temperature resulting in 3 16 bits of linearity. v out C volts C2 error relative to fs 0.0002%/division 0% C1 0 12 r l = 100 v figure 14. dc nonlinearity vs. v out
ad9617 C8C rev. b ac gain characteristics closed-loop bandwidth at high frequencies is determined pri- marily by the roll-off of t(s). but circuit layout is critical to minimize external parasitics which can degrade performance by causing premature peaking and/or reduced bandwidth. the inverting and noninverting dynamic characteristics are similar. when driving the noninverting input, the inverting input capaci- tance (c i ) will cause the noninverting closed-loop bandwidth to be higher than the inverting bandwidth for gains less than two (2). in the remaining cases, inverting and noninverting responses are nearly identical. for best overall dynamic performance, the value of the feedback resistor (r f ) should be 400 ohms. although bandwidth reduces as closed-loop gain increases, the change is relatively small due to low equivalent series input impedance, z s . (see typical performance charts.) the simplified equations governing the devices dynamic performance are shown below. closed-loop gain vs. frequency: (noninverting operation) v o v i ? 1 + r f r i s t 1 + r s r i ? ? ? ? ? + 1 (6) where: t = r f c c = 0.9 ns ( r f = 400 w ) slew rate ? d v o r f kc c e -t / r f kc c (7) where: k = 1 + r s r i increasing bandwidth at low gains by reducing r f , wider bandwidth and faster pulse response can be attained beyond the specified values, although increased overshoot, settling time and possible ac peaking may result. as a rule of thumb, overshoot and bandwidth will increase by 1% and 8%, respectively, for a 5% reduction in r f at gains of 10. lower gains will increase these sensitivities. equations 6 and 7 are simplified and do not accurately model the second order (open loop) frequency response term which is the primary contributor to overshoot, peaking and nonlinear bandwidth expansion. (see open loop bode plots.) the user should exercise caution when selecting r f values much lower than 400 w . note that a feedback resistor must be used in all situations, including those in which the amplifier is used in a noninverting unity gain configuration. increasing bandwidth at high gains closed loop bandwidth can be extended at high closed loop gain by reducing r f. bandwidth reduction is a result of the feedback current being split between r s and r i . as the gain increases (for a given r f ), more feedback current is shunted through r i , which reduces closed loop bandwidth (see equation 6). to maintain specified bw, the following equations can be used to approxi- mate r f and r i for any gain from l to 15. r f = 424 8 g (8) (+ for inverting and C for noninverting) r i ? 424 - 8 g g - 1 (noninverting) (9) r i ? 424 + 8 g g - 1 (inverting) (10) g = closed loop gain . bandwidth reduction the closed loop bandwidth can be reduced by increasing r f. equations 6 and 7 can be used to determine the closed loop bandwidth for any value r f . do not connect a feedback capaci- tor across r f , as this will degrade dynamic performance and possibly induce oscillation. dc precision and noise output offset voltage results from both input bias currents and input offset voltage. these input errors are multiplied by the noise gain term (1 + r f /r i ) and algebraically summed at the output as shown below. v o = v io 1 + r f r i ? ? ? ? ibn r n 1 + r f r i ? ? ? ? ibi r f (11) since the inputs are asymmetrical, ibi and ibn do not correlate. canceling their output effects by making r n = r f i r i will not reduce output offset errors, as it would for voltage feedback amplifiers. typically, ibn is 5 m a and v io is +0.5 mv (i sigma = 0.3 mv), which means that the dc output error can be reduced by making r n ? 100 w . note that the offset drift will not change significantly because the ibn tc is relatively small. (see specifi- cation table.) ibi ibn r i r n r f v out figure 15. output offset voltage 10 C55 8 c ibi/ibn C m a 5 0 C5 C10 25 8 c 125 8 c 0 0.5 1.0 C0.5 C1.0 v io C ma ibi v io ibn figure 16. dc accuracy
ad9617 C9C rev. b the effective noise at the output of the amplifier can be deter- mined by taking the root sum of the squares of equation 11 and applying the spectral noise values found in the typical graph section. this applies to noise from the op amp only. note that both the noise figure and equivalent input offset voltages im- prove as the closed loop gain is increased (by keeping r f fixed and reducing r i with r n = 0 w ). cli in 400 v r series r l 500 v cl figure 17. capacitive load figure capacitive load considerations due to the low inverting input resistance (r s ) and output buffer design, the ad9617 can directly handle input and/or output load capacitances of up to 20 pf. see the chart below. a small series resistor can be used at the output of the amplifier and outside of the feedback loop to facilitate driving larger ca- pacitive loads or for obtaining faster settling time. for capacitive loads above 20 pf, r series should be considered. input capacitance C cli 5pf 4pf/div 25pf input capacitance C cl 10pf 4pf/div 30pf r series = 0 v 35 30 25 20 15 10 v out = 4v step cl = 0pf settling time to 0.02% C ns v out = 4v step cli = 0pf figure 18. input/output capacitance comparisons cl C p f 25 0 r series C v 20 15 10 5 0 20 40 60 80 100 figure 19. recommended r series vs. cl applying the ad9617 the superior frequency and time domain specifications of the ad9617 make it an obvious choice for driving flash converters and buffering the outputs of high speed dacs. its outstanding distortion and noise performance make it well suited as a driver for analog to digital converters (adcs) with resolutions as high as 16 bits. typical circuits for inverting and noninverting applications are shown in figures 20 and 21. closed-loop gain for noninverting configurations is determined by the value of ri according to the equation: g = 1 + r f r i (12) 0.1 m f 0.1 m f 0.1 m f 0.1 m f 3.3 m f 3.3 m f Cv s +v s ad9617 v out 400 v r in v in r i figure 20. noninverting operation 0.1 m f 0.1 m f 0.1 m f 0.1 m f 3.3 m f 3.3 m f Cv s +v s ad9617 v out 400 v r term v in r i figure 21. inverting operation
ad9617 C10C rev. b outline dimensions dimensions shown in inches and (mm). small outline package (so-8) 85 4 1 0.198 (5.00) 0.188 (4.74) 0.244 (6.200) 0.228 (5.80) pin 1 0.158 (4.00) 0.150 (3.80) 0.050 (1.27) bsc 0.069 (1.75) 0.053 (1.35) seating plane 0.010 (0.25) 0.004 (0.10) 0.018 (0.46) 0.014 (0.36) 0.015 (0.38) 0.007 (0.18) 0.045 (1.15) 0.020 (0.50) 8 8 0 8 0.205 (5.20) 0.181 (4.60) plastic dip (n-8) seating plane 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.022 (0.558) 0.014 (0.356) 0.200 (5.05) 0.125 (3.18) 0.070 (1.77) 0.045 (1.15) 0.150 (3.81) min 8 14 5 pin 1 0.280 (7.11) 0.240 (6.10) 0.100 (2.54) bsc 0.430 (10.92) 0.348 (8.84) 0.015 (0.381) 0.008 (0.204) 0.325 (8.25) 0.300 (7.62) 0 8 C15 8 layout considerations as with all high performance amplifiers, printed circuit layout is critical in obtaining optimum results with the ad9617. the ground plane in the area of the amplifier should cover as much of the component side of the board as possible. each power supply trace should be decoupled close to the package with at least a 3.3 m f tantalum and a low inductance, 0.1 m f ceramic capacitor. all lead lengths for input, output and the feedback resistor should be kept as short as possible. all gain setting resistors should be chosen for low values of parasitic capacitance and inductance, i.e., microwave resistors and/or carbon resistors. stripline techniques should be used for lead lengths in excess of one inch. sockets should be avoided if possible because of their stray inductance and capacitance. c1353bC0C9/99 printed in u.s.a.
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