[AKD7780] 2007/09 - 1 - general description the AKD7780 is an evaluation board fo r ak7780, which is a highly int egrated audio processor including two 24-bit stereo adc?s, a mono adc and a stereo s rc. this board is composed of a main board and a sub board. AKD7780 has spdif input/output port, 2 pairs of stereo analog i nput ports, 1 mono analog input port, 4 pairs of stereo anal og output ports and this helps to the evaluation of ak7780. ? ordering guide AKD7780 --- evaluation board for ak7780 cable for c onnecting with printer port of ibm-at compatible pc and control software and driver for windows 2000/xp are packed with this. this control software does not operate on window nt. windows 2000/ xp needs an installation of driver. in case of windows 95/98/me, the installation is not needed. function ? register setting / download / read back function to/from pc ? digital interface by spdif i/o ? digital interface by general audio data header(x2) ? analog interface of adc 5ch / dac 8ch (note: there is no dac within ak7780. 8ch dac ak4359 is equipped.) ak7780 ak4359 ( 8ch dac ) ak4114 ( dir / dit ) analog out analog in path controller (fpga) digital in / out AKD7780 main board pc printer port digital port digital port (note) ak4114 has dir, dit and x?tal oscillator. figure 1. AKD7780 block diagram ak7780 evaluation board rev.0 AKD7780
[AKD7780] 2007/09 - 2 - evaluation board diagram ? board diagram ain selector (jp12-jp18) smux2 smux1 jtag dac1 dac2 dac3 dac4 ain2 ain1 adcm clock (jp5) ak7780 sub-board ak 7780 clock (jp1) power supply (jp2-3, jp5-6, jp9-10, jp22) +12v gnd -12v ak 4114 ak4359 optical out optical in pc i/f path controller (fpga) figure 2. ak7780 board diagram ? description (1) ain/dac/adcm rca jack. white is for lch and red is for rch. yellow one is for mono input. (2) optical in optical input connector. it supports sampling frequencies from 32hz to 48hz. it is used as digital data source for ak7780. when ak7780 is operated in slave mode , this input signal is always necessary. (3) optical out optical output connector . it can be selected from sdout1-6 or adouta1. (4) power supply supply +12v, gnd, -12v for each terminal. curre nt consumption is a bout 500ma in operation. (5) clock (jumper) clock source jumper. select clock source between ?ext? and ?xtl? for ak4114 or ak7780. (6) other jumper pins? setting according to table 1. / table 2. (7) pc/if connect to pc printer port (parallel port) with attached cable. input signals are pull-upped with 10k-ohm resistance. output signals are 0-5v swing.
[AKD7780] 2007/09 - 3 - pin i/o function pin i/o function 2 i ncs3 for ak4114 10 o (not used) 3 i init_reset 11 o (not used) 4 i (not used) 12 o rdy 5 i i2csel 13 o so 6 i sclk 15 o (not used) 7 i si 8 i ncs for ak7780 9 i ncs2 for fpga (8) audio digital data port two of digital ports (smux1/smux2) are available. pin i/o function pin i/o function 1 i mclk 2 p gnd 3 i bitclk 4 p gnd 5 i lrclk 6 (nc) 7 i di 8 (nc) 9 p vdd 10 o do path controller the path controller manages i/o control for audio signal, selector, and ak7780 pin configuration. this controller has 3 words register and each register has 16bit. access is done by 18bit length as bellow format. ncs2 sclk si a1 a0 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 address=0 d[15] (test) set 0. d[14:12] sdout out put signal select. 000: sdout1 001: sdout2 -- 101: sdout6 110: sdouta1 111:low d[11:10] src select src master device. 00: ak4114 01: smux1 10: smux2 11: low d[9:8] sdin5 sdin5 pin input select 00: ak4114 01: smux1 10: smux2 11: low d[7:6] sdin4 sdin4 pin input select 00: ak4114 01: smux1 10: smux2 11: low d[5:4] sdin3 sdin3 pin input select 00: ak4114 01: smux1 10: smux2 11: low d[3:2] sdin2 sdin2 pin input select 00: ak4114 01: smux1 10: smux2 11: low d[1:0] sdin1 sdin1 pin input select 00: ak4114 01: smux1 10: smux2 11: low
[AKD7780] 2007/09 - 4 - address=1 d[6:4] ckm[2:0] ak7780 ckm pin setting d[3:2] selsrc[1:0] ak7780 selsrc pin setting 00: lrck 01:bick 10:test 11:test d[1:0] cad[1:0] ak7780 cad pin setting address=2 d[15] trxpdn ak4114 pdn pin setting d[14] dacpdn ak4359 reset pin setting d[13] srcrst ak7780 srcrst pin setting d[12] adrst ak7780 adrst pin setting d[11] dsprst ak7780 dsprst pin setting d[10] ckrst ak7780 ckrst pin setting d[9:8] master select master device for ak7780 00: ak4114 01: smux1 10: smux2 11: ak7780 d[6] (not used) d[5] test2 ak7780 test2i pin setting (normally 0) d[4] test1 ak7780 test1i pin setting (normally 0) d[3] srcmute ak7780 srcmute pin setting d[2] jx2 ak7780 jx2 pin setting d[1] jx1 ak7780 jx1 pin setting d[0] jx0 ak7780 jx0 pin setting
[AKD7780] 2007/09 - 5 - evaluation board manual ? operation sequence 1. set up the power supply lines. [+12v] (red) = +12v [-12v] (blue) = -12v [gnd] (black) = 0v each supply line should be distributed from the power supply unit. 2. set up the jumper pins (according to the follows). 3. connect the needed connector (according to the follows). 4. power on. 5. set up the register via pc (according to the follows). ? evaluation mode (1) adc with external dit 1. connection of connector for analog input, rca1(ain1l)/rca2(ain1r) or rca 3(ain2l)/rca4(ain2r) or rca5(ain mono) is available. for digital output, optical connector port2 (totx141) is available. 2. setting of jumper pins for analog output (jp12 ? jp18) according to table 3. / table 4. / table 5. 3. set up the fpga and ak7780 control register via pc. (2) src with external dir, dit 1. connection of connector for digital input, optical connector port1 (torx141) is available. for digital output optical connector port2 (totx141) is available. 2. set up the fpga and ak7780 control register via pc. ? register control it is possible to control AKD7780 via printer port (parallel port) of ibm-at compatible pc. connect the p1 port on board to pc with the packed cable. control software is packed with this board. the softwa re operation sequence is included in the evaluation board manual. ? indication for led [led] : u17 when power is supplied , led is lighted to red. monitor the pc_rq_n signal and change the color when the board is communicating with pc.
[AKD7780] 2007/09 - 6 - ? setting of jumper pins (main board) jumper setting (default) note jp01 (ak4114 clock) ?xtl? ?xtl?: xtl ?ext?: external clock jp02 (avdd) short ak7780 avdd jp03 (avdd_src) short ak7780 avdd_src jp05 (avss) short ak7780 avss jp06 (dvdd18) short ak7780 dvdd18 jp09 (dvss) short ak7780 dvss jp10 (dvdd) short ak7780 dvdd jp12 (ain1-lch) short ainln jp13 (ain1-rch) short ainrn jp18 (ain-mono) short ainm jp22 (p dvdd) short peripheral dvdd table 1. setting of jumper pins on main board (sub board) jumper setting (default) note jp4 (clko2) short short: clko1 output jp5 (ak7780 clock) ?xtl? ?xtl?: xtl ?ext?: external clock jp6 (clko1) short short: clko1 output table 2. setting of jumper pins on sub board
[AKD7780] 2007/09 - 7 - ? analog input circuit figure 3. ain1 analog input circuit figure 4. ain mono analog input circuit
[AKD7780] 2007/09 - 8 - figure 5. ain2 analog input circuit for analog input, rca1(ain1l)/ rca2(ain1r), rca3(ain2 l)/rca4(ain2r), rca5(ain mono) are available. the ak7780 supports single-ended input mode, monaural singl e-ended input mode and differential input mode. the input range of ain is 2.00vpp@3.3v. ~ setting of jumper pins of analog input circuit input pin jp12 jp13 jp14 jp15 ainln/ ainlp ainrn/ainrp short short 1-2 pin short 1-2 pin short default ainl2/ ainr2 open open 7-8 pin short 7-8 pin short ainl3/ ainr3 open open 5-6 pin short 5-6 pin short ainl4/ ainr4 open open 3-4 pin short 3-4 pin short ainl5/ ainr5 open open 9-10 pin short 9-10 pin short ainl6/ ainr6 open open 11-12 pin short 11-12 pin short ainl7/ ainr7 open open 13-14 pin short 13-14 pin short ainl8/ ainr8 open open 15-16 pin short 15-16 pin short table 3. setting of input when using ain1l/ain1r
[AKD7780] 2007/09 - 9 - input pin jp16 jp17 ainl2/ ainr2 7-8 pin short 7-8 pin short default ainl3/ ainr3 5-6 pin short 5-6 pin short ainl4/ ainr4 3-4 pin short 3-4 pin short ainl5/ ainr5 9-10 pin short 9-10 pin short ainl6/ ainr6 11-12 pin short 11-12 pin short ainl7/ ainr7 13-14 pin short 13-14 pin short ainl8/ ainr8 15-16 pin short 15-16 pin short table 4. setting of input when using ain2l/ain2r input pin jp18 ain mono short default table 5. setting of input when using ain mono
[AKD7780] 2007/09 - 10 - ? analog output circuit figure 6. dac1, dac2 analog output circuit
[AKD7780] 2007/09 - 11 - figure 7. dac3, dac4 analog output circuit there is no dac within ak7780. so 8ch dac ak4359 is equipped on board. for analog output, connector rca6(dac1l), rca7(dac1r), rca8(dac2l), rca9(dac2r), rca10(dac3l), rca11(dac3r), rca13(dac4l), rca12(dac4r) are available.
[AKD7780] 2007/09 - 12 - ? digital input circuit (external dir:port1) figure 8. digital input circuit (ak4114) for digital input, optical connector port1 is available. ? digital output circuit (external dit:port2) figure 9. digital output circuit (ak4114) for digital output, optical connector port2 is available.
[AKD7780] 2007/09 - 13 - control software manual ? set-up of the evaluation board and control software 1. set up the AKD7780 according to previous term. 2. connect ibm-at compatible pc with AKD7780 by 25 pin printer cable (packed with AKD7780). (please install the driver in the cd-rom when software is used on window 2000/xp. please refer ?installation manual of control software driver by akm device control software?. in case of windows95/98/me, this installation is not needed. this control software does not operate on windows nt . and the operation on windows vista has not been confirmed.) 3. insert the cd-rom labeled ?ak7780 evaluation kit? into the cd-rom drive. 4. access the cd-rom drive and double-click the icon of ?ak7780.exe? to set up the program. 5. then please evaluate acco rding to the follows. ? operation flow keep the following flow 1. set up the control program accord ing to the explanation above. 2. click ?board init? button to initialize the board. 3. select the needed dialogue to ev aluate by changing the setting. figure 10. the image of control software
[AKD7780] 2007/09 - 14 - control software supports program downl oad, register setting, pe ripheral logic setting and r unning script. these menus are changing at upper tab. fr equent used function are pl aced outside of main menu. (1) download figure 11. ? download dialogue push ?refer? button at source item and select source file. and then, push ?assemble? button, assembler runs and outputs result. automatically assembled file is selected as a pram file. push ?write? button, download process is done. ?assemble write? button do all of this process. in this menu, read back of download data, so-read function, jx setting, cram/ofram writing under operation are supported.
[AKD7780] 2007/09 - 15 - (2) register setting figure 12. ? reg1 dialogue reg1/reg2/reg3/test tabs are register setting window. (test items are inactivated.) check each button and control softwa re will write to each ak7780 register . when accessing to cont0 register, dsr_reset will automatically to l. the reference page of register s in datasheet is as follow: register reference page register reference page cont00 31 cont07 38 cont01 32 cont08 39 cont02 33 cont09 40 cont03 34 cont0a 41 cont04 35 cont0b 42 cont05 36 cont0c 43 cont06 37 cont0d 44 table 6. reference page of registers
[AKD7780] 2007/09 - 16 - (3) peripheral logic setting figure 13. ? xilinx dialogue in this menu, path controller and ak4114 setting are supported. ak7780 is set to ma ster mode and other devices are set to slave mode after start up.
[AKD7780] 2007/09 - 17 - (4) script figure 14. ? script dialogue select script file and runs . ?repeat? button runs current selected script once again. command description [script] script file header. if this header is missing, header error will occur. ;comment after semi-colon senten ce will be ignored as comment. w,, w,0xc0,0x00 ak7780 register access. wl,,,,? wl,0x82,0x0022,0x4000,0x4000,0x4000 ak7780 continuous data access. this is possible to use cram access in operating. command data is byte, following data are word length. d,, ak4114 register access. x,, fpga register access. p, display any message, and suspend script process. ri:h / ri:l rs:h / rs:l ra:h / ra:l rd:h / rd:l rc:h / rc:l ak7780 reset control. init_reset, src_reset, adc_reset, dsp_reset and ck_reset. t, t,50ms wait script process. unit is ms only. lp: download pram data lc: download cram data lo: download offset ram data table 7. script command
[AKD7780] 2007/09 - 18 - how to use (1) d-to-d digital to digital loop back. the ak4114 is master device, and the ak7780 operates in slave mode. please confirm that jp1 of main board is xtl side and jp5 of daughter board is ext side. (a) after starting up, push ?board initialize? button. (b) select script tab, and runs scriptmaster.txt. (c) push ?refer? button and select dtoad.txt file. (d) push ?assemble write? button. figure 15. ? d-to-d
[AKD7780] 2007/09 - 19 - (2) src operation confirmation the ak4114 is the master device of src, and the ak7780 operates as master device with crystal oscillation. input data from optical terminal goes via src, and dsp output will go to dac at fs=96khz. please confirm that jp1 of main board is xtl side and jp5 of daughter board is xtl side. (a) after starting up, push ?board initialize? button. (b) select script tab, and runs scriptsrc.txt. figure 16. ? src operation confirmation this script file will set each register setting, and dow nload src.obj automatically (src.obj is src-to-dsp output through program).
[AKD7780] 2007/09 - 20 - revision history important notice z these products and their specifications are subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei emd corporation (akemd) or authorized distributors as to current status of the products. z akemd assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of e xport pertaining to customs and tariffs, currency exchange, or strategic materials. z akemd products are neither intended nor au thorized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akemd assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akemd. as used here: note1) a critical component is one whose failure to func tion or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fi elds, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akemd pr oducts, who distributes, dis poses of, or otherwise places the product with a third party, to notify such third party in advance of the above cont ent and conditions, and the buyer or distributor agrees to assume any and all re sponsibility and liability for and hold akemd harmless from any and all claims arising from the use of said product in the absence of such notification. date (yy/mm/dd) manual revision board revision reason page contents 07/09/10 km090600 0 first edition
5 5 4 4 3 3 2 2 1 1 d d c c b b a a ainlp ainln ainl2 ainl3 ainl4 ainl5 ainl6 ainl7 ainl8 ainrp ainrn ainr2 ainr3 ainr4 ainr5 ainr6 ainr7 ainr8 ainm sdout5 sdout6 sdouta1 bitclk_i lrclk_i clko2 dac_pdn sdin1 sdin2 sdin3 sdin4 sdin5 src_bick src_lrck mclk srcset0 srcset1 jx0 jx1 jx2 ckm0 ckm1 ckm2 trx_pdn trx_bick trx_lrck tx_clk rx_clk rx_clk2 rx_dat tx_dat p_dsp_reset p_ad_reset p_ck_reset p_src_reset test1 test2 p_src_smute x_sclk x_si x_rq_n x_so x_sda sdout2 sdout2 sdout2 sdout2 sdout2 sdout2 sdout2 sdout2 sdout4 sdout4 sdout4 sdout4 sdout4 sdout4 sdout4 sdout4 sdout1 sdout1 sdout1 sdout1 sdout1 sdout1 sdout1 sdout1 sdout3 sdout3 sdout3 sdout3 sdout3 sdout3 sdout3 sdout3 lrclk_o bitclk_o bitclk_o bitclk_o bitclk_o clko1 clko1 clko1 clko1 pc_sclk pc_si pc_rq_n cs2_n i2csel pc_so led_ind ireset cs3_n rdy rdy rdy rdy sto sto title size document number rev date: sheet of a top a3 18 friday, july 07, 2006 title size document number rev date: sheet of a top a3 18 friday, july 07, 2006 title size document number rev date: sheet of a top a3 18 friday, july 07, 2006 xilinx xilinx sdin3 sdin2 sdin1 x_sda x_so ckm2 p_src_reset p_src_smute testi2 sdouta1 mclk srcset0 srcset1 clko2 i2csel testi1 pc_so jx2 led_ind jx1 jx0 dac_pdn clko1 trx_pdn cs2 cs3 pc_rq_n pc_si pc_sclk tx_clk rx_clk rx_clk2 tx_dat sdout5 sdout4 sdout3 sdout1 sdout2 rx_dat bitclk_o lrclk_o trx_lrck trx_bick src_bick ckm0 src_lrck ckm1 p_ck_reset p_ad_reset p_dsp_reset x_rq_n x_si x_sclk lrclk_i bitclk_i sdin5 sdin4 sdout6 ak7780 ak7780 ainl8 ainr8 ainl7 ainl6 ainr7 ainr6 ainl5 ainr5 ainm ainr4 ainl4 ainr3 ainl3 ainr2 ainl2 ainrn ainrp ainln ainlp sdout5 sdout4 sdout3 sdout2 sdout1 bitclk_o lrclk_o ckm1 ckm0 ckm2 mclk test1 i2csel srcset1 srcset0 clko1 sdin2 sdin3 sdin4 sdin5 bitclk_i lrclk_i ireset p_ck_reset p_ad_reset p_dsp_reset x_si x_sclk x_rq_n x_so test2 p_src_smute p_src_reset src_lrck src_bick sdin1 jx0 jx1 jx2 clko2 sdout6 sdouta1 sto rdy x_sda dac dac clko1 bitclk_o sdout1 lrclk_o sdout2 sdout3 sdout4 dac_pdn pcif pcif led_ind pc_so rdy ireset pc_sclk pc_si pc_rq_n cs2_n cs3_n i2csel sto ak4114 ak4114 rx_clk2 trx_bick trx_lrck rx_clk pc_sclk cs3 pc_si trx_pdn tx_dat rx_dat txclk power power analog ainm ainl4 ainl3 ainl2 ainl5 ainl6 ainl8 ainl7 ainlp ainln ainr4 ainr7 ainr8 ainr3 ainr2 ainr6 ainr5 ainrn ainrp
5 5 4 4 3 3 2 2 1 1 d d c c b b a a dif_rx dif_tx rx_clk2 trx_bick trx_lrck rx_clk pc_sclk cs3 pc_si trx_pdn tx_dat rx_dat txclk dvdd_3.3v dvdd_3.3v dvdd_3.3v dvdd_3.3v dvdd_3.3v avdd title size document number rev date: sheet of a3 28 friday, july 07, 2006 title size document number rev date: sheet of <doc> <revcode> <title> a3 28 friday, july 07, 2006 title size document number rev date: sheet of <doc> <revcode> <title> a3 28 friday, july 07, 2006 spdi/f optical in spdif-in spdi/f optical out spdif-out ext xtl default 1-2short r2 470 r2 470 r5 100 r5 100 c4 0.1uf c4 0.1uf x'tal1 12.288mhz x'tal1 12.288mhz + c9 10uf + c9 10uf r7 100 r7 100 1 2 3 jp1 header 3 jp1 header 3 out 1 vcc 3 gnd 2 port1 torx141 port1 torx141 c2 0.1uf c2 0.1uf + c13 10uf + c13 10uf rx4 1 nc1 2 rx5 3 test2 4 rx6 5 nc3 6 rx7 7 iic 8 p/sn 9 xtl0 10 xtl1 11 vin 12 tvdd 13 nc4 14 tx0 15 tx1 16 bout 17 cout 18 uout 19 vout 20 dvdd 21 dvss 22 mcko1 23 lrck 24 sdto 25 bick 26 mcko2 27 daux 28 xto 29 xti 30 pdn 31 cdto 32 cdti 33 cclk 34 csn 35 int0 36 int1 37 avdd 38 r 39 vcom 40 avss 41 rx0 42 nc5 43 rx1 44 test1 45 rx2 46 nc6 47 rx3 48 ak4114 u1 ak4114 ak4114 u1 ak4114 r8 100 r8 100 c6 22pf c6 22pf gnd 1 vcc 2 in 3 port2 totx141 port2 totx141 + c1 10uf + c1 10uf c10 0.1uf c10 0.1uf c11 0.1uf c11 0.1uf c7 22pf c7 22pf r3 100 r3 100 r1 18k r1 18k c8 0.1uf c8 0.1uf + c5 10uf + c5 10uf l2 10uh l2 10uh l1 10uh l1 10uh r6 100 r6 100 + c12 10uf + c12 10uf c3 0.1uf c3 0.1uf + c14 100uf/16v(a) + c14 100uf/16v(a) 1 tp1 tp(black) tp1 tp(black)
<br> 5 5 4 4 3 3 2 2 1 1 d d c c b b a a avdd_src avdd_ad avss_chip dvdd_chip dvdd18_chip dvss_chip ainl8 ainr8 ainl7 ainl6 ainr7 ainr6 ainl5 ainr5 ainm ainr4 ainl4 ainr3 ainl3 ainr2 ainl2 ainrn ainrp ainln ainlp sdout5 sdout4 sdout3 sdout2 sdout1 bitclk_o lrclk_o ckm1 ckm0 ckm2 mclk test1 i2csel srcset1 srcset0 clko1 sdin2 sdin3 sdin4 sdin5 bitclk_i lrclk_i ireset p_ck_reset p_ad_reset p_dsp_reset x_si x_sclk x_rq_n x_so test2 p_src_smute p_src_reset src_lrck src_bick sdin1 jx0 jx1 jx2 clko2 sdout6 sdouta1 sto rdy x_sda avdd dvdd dvdd18 title size document number rev date: sheet of <doc> a ak7780 header a3 38 friday, july 07, 2006 title size document number rev date: sheet of <doc> a ak7780 header a3 38 friday, july 07, 2006 title size document number rev date: sheet of <doc> a ak7780 header a3 38 friday, july 07, 2006 default short default short default short default short default short default short 1 2 jp6 header 2 jp6 header 2 + c19 10uf(a) + c19 10uf(a) + c18 10uf(a) + c18 10uf(a) + c17 10uf(a) + c17 10uf(a) 1 2 jp10 header 2 jp10 header 2 1 2 jp2 header 2 jp2 header 2 1 2 jp3 header 2 jp3 header 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 jp11 header 15x2 jp11 header 15x2 + c15 10uf(a) + c15 10uf(a) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 jp7 header 15x2 jp7 header 15x2 1 2 jp9 header 2 jp9 header 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 jp4 header 25x2 jp4 header 25x2 + c16 10uf(a) + c16 10uf(a) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 jp8 header 15x2 jp8 header 15x2 1 2 jp5 header 2 jp5 header 2
<br> 5 5 4 4 3 3 2 2 1 1 d d c c b b a a amp_pw+ amp_pw- amp_pw+ amp_pw- ainl3 ainl4 ainl6 ainl5 ainl2 ainl7 ainl8 amp_pw+ amp_pw- ainr4 ainr3 ainr2 ainr5 ainr6 ainr7 ainr8 amp_pw- amp_pw+ amp_pw- amp_pw+ ainm ainl4 ainl3 ainl2 ainl5 ainl6 ainl8 ainl7 ainlp ainln ainr4 ainr7 ainr8 ainr3 ainr2 ainr6 ainr5 ainrn ainrp amp_pw+ amp_pw- amp_pw+ amp_pw- amp_pw+ amp_pw- amp_pw- amp_pw+ amp_pw- amp_pw+ amp_pw- amp_pw+ title size document number rev date: sheet of <doc> a analog input a3 48 friday, july 07, 2006 title size document number rev date: sheet of <doc> a analog input a3 48 friday, july 07, 2006 title size document number rev date: sheet of <doc> a analog input a3 48 friday, july 07, 2006 default short default short 1-2 default short default short 7-8 default short default short 1-2 default short 7-8 5 6 7 8 4 + - u4b njm5532d + - u4b njm5532d + c30 22uf(a) + c30 22uf(a) r11 10k r11 10k r10 10k r10 10k c25 0.1uf c25 0.1uf + c26 10uf + c26 10uf 5 6 7 8 4 + - u5b njm5532d + - u5b njm5532d r24 10k r24 10k c55 0.1uf c55 0.1uf 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 jp14 header 8x2 jp14 header 8x2 r19 10k r19 10k 5 6 7 8 4 + - u3b njm5532d + - u3b njm5532d + c35 22uf(a) + c35 22uf(a) + c38 22uf(a) + c38 22uf(a) t b s rca2 mr-552ls(r) rca2 mr-552ls(r) c44 68pf(c/dip) c44 68pf(c/dip) 3 2 1 8 4 + - u6a njm5532d + - u6a njm5532d t b s rca5 mr-552ls(y) rca5 mr-552ls(y) c28 68pf(c/dip) c28 68pf(c/dip) 3 2 1 8 4 + - u2a njm5532d + - u2a njm5532d r21 10k r21 10k c32 68pf(c/dip) c32 68pf(c/dip) r22 10k r22 10k 5 6 7 8 4 + - u2b njm5532d + - u2b njm5532d r13 10k r13 10k + c56 10uf + c56 10uf c45 68pf(c/dip) c45 68pf(c/dip) r9 10k r9 10k r20 10k r20 10k t b s rca1 mr-552ls(w) rca1 mr-552ls(w) c52 0.1uf c52 0.1uf r17 10k r17 10k + c48 22uf(a) + c48 22uf(a) 5 6 7 8 4 + - u6b njm5532d + - u6b njm5532d 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 jp16 header 8x2 jp16 header 8x2 c42 0.1uf c42 0.1uf 1 2 jp13 header 2 jp13 header 2 + c57 100uf/16v(a) + c57 100uf/16v(a) + c23 22uf(a) + c23 22uf(a) c39 0.1uf c39 0.1uf c58 68pf(c/dip) c58 68pf(c/dip) r28 10k r28 10k + c54 22uf(a) + c54 22uf(a) + c20 22uf(a) + c20 22uf(a) 3 2 1 8 4 + - u3a njm5532d + - u3a njm5532d + c63 10uf + c63 10uf 1 2 jp18 header 2 jp18 header 2 c36 0.1uf c36 0.1uf c21 0.1uf c21 0.1uf c46 68pf(c/dip) c46 68pf(c/dip) 3 2 1 8 4 + - u4a njm5532d + - u4a njm5532d t b s rca4 mr-552ls(r) rca4 mr-552ls(r) + c53 10uf + c53 10uf + c40 10uf + c40 10uf c62 0.1uf c62 0.1uf r15 10k r15 10k r26 10k r26 10k 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 jp17 header 8x2 jp17 header 8x2 r16 10k r16 10k 1 tp2 tp(black) tp2 tp(black) + c24 22uf(a) + c24 22uf(a) + c60 100uf/16v(a) + c60 100uf/16v(a) + c41 22uf(a) + c41 22uf(a) + c61 22uf(a) + c61 22uf(a) c33 0.1uf c33 0.1uf + c22 10uf + c22 10uf r23 10k r23 10k c47 68pf(c/dip) c47 68pf(c/dip) 1 2 jp12 header 2 jp12 header 2 t b s rca3 mr-552ls(w) rca3 mr-552ls(w) c59 68pf(c/dip) c59 68pf(c/dip) r25 10k r25 10k 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 jp15 header 8x2 jp15 header 8x2 c49 0.1uf c49 0.1uf + c43 10uf + c43 10uf + c50 10uf + c50 10uf r27 10k r27 10k r12 10k r12 10k r14 10k r14 10k c29 68pf(c/dip) c29 68pf(c/dip) 3 2 1 8 4 + - u5a njm5532d + - u5a njm5532d + c37 10uf + c37 10uf + c27 22uf(a) + c27 22uf(a) r18 10k r18 10k c31 68pf(c/dip) c31 68pf(c/dip) + c51 22uf(a) + c51 22uf(a) + c34 10uf + c34 10uf
<br> 5 5 4 4 3 3 2 2 1 1 d d c c b b a a rout1 rout2 rout3 rout4 lout1 lout2 lout3 lout4 dac_mclk dac_bick dac_sdti1 dac_lrck dac_sdti2 dac_sdti3 dac_sdti4 dac_pdwn dac_vcom lout1 rout1 lout2 rout2 lout3 rout3 lout4 rout4 clko1 bitclk_o sdout1 lrclk_o sdout2 sdout3 sdout4 dac_pdn amp_pw- amp_pw+ amp_pw- amp_pw+ amp_pw- amp_pw+ amp_pw- amp_pw+ amp_pw- amp_pw+ amp_pw- amp_pw+ amp_pw- amp_pw+ amp_pw- amp_pw+ dvdd_dac dvdd_dac vdd_dac amp_pw+ amp_pw- amp_pw+ amp_pw- amp_pw+ amp_pw- amp_pw+ amp_pw- vdd_dac amp_pw+ dvdd_dac title size document number rev date: sheet of <doc> a dac a3 58 thursday, july 06, 2006 title size document number rev date: sheet of <doc> a dac a3 58 thursday, july 06, 2006 title size document number rev date: sheet of <doc> a dac a3 58 thursday, july 06, 2006 dac1 dac2 dac3 dac4 dac_gnd dac_gnd dac_gnd dac_gnd dac_gnd tab is vout dac 5v dac_gnd wired short + c117 10uf + c117 10uf c95 220pf(f/dip) c95 220pf(f/dip) c89 220pf(f/dip) c89 220pf(f/dip) c112 0.1uf c112 0.1uf c68 220pf(f/dip) c68 220pf(f/dip) + c70 22uf(a) + c70 22uf(a) t b s rca7 mr-552ls(r) rca7 mr-552ls(r) c87 0.1uf c87 0.1uf + c104 10uf + c104 10uf c109 220pf(f/dip) c109 220pf(f/dip) a1 2 a2 3 a3 4 a4 5 a5 6 a6 7 a7 8 a8 9 g1 1 g2 19 y1 18 y2 17 y3 16 y4 15 y5 14 y6 13 y7 12 y8 11 vcc 20 gnd 10 u12 74hct541 u12 74hct541 c77 220pf(f/dip) c77 220pf(f/dip) r35 4.7k r35 4.7k c94 0.1uf c94 0.1uf 3 2 1 8 4 + - u10a njm5532d + - u10a njm5532d r30 4.7k r30 4.7k + c106 22uf(a) + c106 22uf(a) + c80 22uf(a) + c80 22uf(a) r59 100 r59 100 t b s rca8 mr-552ls(w) rca8 mr-552ls(w) 1 tp3 tp(black) tp3 tp(black) r45 4.7k r45 4.7k + c110 10uf + c110 10uf r57 100 r57 100 5 6 7 8 4 + - u7b njm5532d + - u7b njm5532d c67 220pf(f/dip) c67 220pf(f/dip) r40 22k r40 22k + c103 22uf(a) + c103 22uf(a) + c84 22uf(a) + c84 22uf(a) + c65 10uf + c65 10uf 3 2 1 8 4 + - u9a njm5532d + - u9a njm5532d c100 220pf(f/dip) c100 220pf(f/dip) r50 4.7k r50 4.7k r29 4.7k r29 4.7k + c73 22uf(a) + c73 22uf(a) + c119 10uf + c119 10uf c88 220pf(f/dip) c88 220pf(f/dip) r39 4.7k r39 4.7k c99 0.1uf c99 0.1uf + c114 10uf + c114 10uf r44 4.7k r44 4.7k c105 0.1uf c105 0.1uf c122 0.1uf c122 0.1uf r51 22k r51 22k r58 100 r58 100 c76 220pf(f/dip) c76 220pf(f/dip) r55 100 r55 100 + c91 22uf(a) + c91 22uf(a) + c74 10uf + c74 10uf r49 4.7k r49 4.7k out 2 gnd 3 in 1 reg1 lm1117-5v reg1 lm1117-5v c64 220pf(f/dip) c64 220pf(f/dip) t b s rca12 mr-552ls(r) rca12 mr-552ls(r) 3 2 1 8 4 + - u8a njm5532d + - u8a njm5532d + c78 10uf + c78 10uf c85 220pf(f/dip) c85 220pf(f/dip) mclk 1 bick 2 sdti1 3 lrck 4 pdn 5 csn 6 cclk 7 cdti 8 sdti2 9 sdti3 10 sdti4 11 dif1 12 dem0 13 dvdd 14 dvss 15 i2c 16 rout4 17 lout4 18 rout3 19 lout3 20 rout2 21 lout2 22 ps 23 rout1 24 lout1 25 vcom 26 avss 27 avdd 28 dzf2 29 dzf1 30 u13 ak4359 u13 ak4359 + c108 22uf(a) + c108 22uf(a) t b s rca11 mr-552ls(r) rca11 mr-552ls(r) r33 22k r33 22k r38 22k r38 22k + c92 22uf(a) + c92 22uf(a) t b s rca6 mr-552ls(w) rca6 mr-552ls(w) + c96 22uf(a) + c96 22uf(a) + c69 22uf(a) + c69 22uf(a) 3 2 1 8 4 + - u7a njm5532d + - u7a njm5532d c101 220pf(f/dip) c101 220pf(f/dip) c66 0.1uf c66 0.1uf c115 0.1uf c115 0.1uf c102 220pf(f/dip) c102 220pf(f/dip) c111 0.1uf c111 0.1uf r34 22k r34 22k r48 4.7k r48 4.7k r37 4.7k r37 4.7k r56 100 r56 100 c118 0.1uf c118 0.1uf c120 0.1uf c120 0.1uf + c86 10uf + c86 10uf r43 4.7k r43 4.7k t b s rca9 mr-552ls(r) rca9 mr-552ls(r) r32 4.7k r32 4.7k + c113 10uf + c113 10uf c72 220pf(f/dip) c72 220pf(f/dip) 5 6 7 8 4 + - u9b njm5532d + - u9b njm5532d + c121 10uf + c121 10uf + c79 22uf(a) + c79 22uf(a) r52 22k r52 22k r60 100 r60 100 r47 4.7k r47 4.7k + c90 10uf + c90 10uf c97 220pf(f/dip) c97 220pf(f/dip) c82 0.1uf c82 0.1uf c81 220pf(f/dip) c81 220pf(f/dip) + c93 22uf(a) + c93 22uf(a) t b s rca13 mr-552ls(w) rca13 mr-552ls(w) wire1 wire wire1 wire r46 22k r46 22k r36 4.7k r36 4.7k r31 4.7k r31 4.7k + c83 22uf(a) + c83 22uf(a) + c107 22uf(a) + c107 22uf(a) c75 0.1uf c75 0.1uf r41 4.7k r41 4.7k r53 100 r53 100 t b s rca10 mr-552ls(w) rca10 mr-552ls(w) + c71 22uf(a) + c71 22uf(a) c116 0.1uf c116 0.1uf r54 10 r54 10 5 6 7 8 4 + - u10b njm5532d + - u10b njm5532d + c98 10uf + c98 10uf r42 22k r42 22k 5 6 7 8 4 + - u8b njm5532d + - u8b njm5532d
<br> 5 5 4 4 3 3 2 2 1 1 d d c c b b a a pc_rq_n pc_rq_n pcin1 pcin2 pcin3 pcin4 pcin5 pcin6 pcin7 pcin0 led_ind pc_so ireset pc_sclk pc_si pc_rq_n cs2_n cs3_n i2csel rdy sto dvdd_5v dvdd_3.3v dvdd_5v dvdd_5v dvdd_5v dvdd_3.3v dvdd_5v title size document number rev date: sheet of <doc> <revcode> <title> a3 68 friday, july 07, 2006 title size document number rev date: sheet of <doc> <revcode> <title> a3 68 friday, july 07, 2006 title size document number rev date: sheet of <doc> <revcode> <title> a3 68 friday, july 07, 2006 run/reset rdy sto r67 10k r67 10k 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 p1 d-sub25-female p1 d-sub25-female 1 tp4 tp(blue) tp4 tp(blue) r61 10k r61 10k r69 100 r69 100 r62 10k r62 10k c125 0.1uf c125 0.1uf r68 10k r68 10k r70 100 r70 100 r63 10k r63 10k r72 100 r72 100 c127 0.1uf c127 0.1uf green 1 red 3 com 2 u17 bicolor led u17 bicolor led 1 tp6 tp(black) tp6 tp(black) r71 100 r71 100 a1 2 a2 3 a3 4 a4 5 a5 6 a6 7 a7 8 a8 9 g1 1 g2 19 y1 18 y2 17 y3 16 y4 15 y5 14 y6 13 y7 12 y8 11 vcc 20 gnd 10 u14 74lvc541 u14 74lvc541 a1 2 a2 3 a3 4 a4 5 a5 6 a6 7 a7 8 a8 9 g1 1 g2 19 y1 18 y2 17 y3 16 y4 15 y5 14 y6 13 y7 12 y8 11 vcc 20 gnd 10 u15 74hct541 u15 74hct541 r64 10k r64 10k c123 0.1uf c123 0.1uf cext 6 rext/cext 7 a 9 b 10 clr 11 q 5 q 12 vcc 16 gnd 8 u16b 74hc221 u16b 74hc221 r73 100 r73 100 r79 100 r79 100 r65 10k r65 10k d1 led(red) d1 led(red) + c126 33uf(a) + c126 33uf(a) r76 100 r76 100 1 tp5 tp(blue) tp5 tp(blue) r74 100 r74 100 cext 14 rext/cext 15 a 1 b 2 clr 3 q 13 q 4 vcc 16 gnd 8 u16a 74hc221 u16a 74hc221 r66 10k r66 10k r80 100 r80 100 + c124 100uf/16v(a) + c124 100uf/16v(a) r77 470 r77 470 r78 10k r78 10k r75 100 r75 100
<br> 5 5 4 4 3 3 2 2 1 1 d d c c b b a a avdd dvdd amp_pw+ amp_pw- dvdd18 dvdd_3.3v dvdd_5v title size document number rev date: sheet of <doc> <revcode> <title> a3 78 wednesday, july 12, 2006 title size document number rev date: sheet of <doc> <revcode> <title> a3 78 wednesday, july 12, 2006 title size document number rev date: sheet of <doc> <revcode> <title> a3 78 wednesday, july 12, 2006 red(+12v) black(gnd) blue(-12v) wired short heat sink necessary tab is vout ak7780 3.3v dvdd ak7780 3.3v avdd tab is vout ak7780 1.8v dvdd peripheral 3.3v dvdd tab is vout peripheral 5v dvdd heat sink necessary tab is vout default short c137 0.1uf c137 0.1uf + c135 100uf/16v(a) + c135 100uf/16v(a) out 2 gnd 3 in 1 reg4 lm1117-3.3v reg4 lm1117-3.3v out 2 gnd 3 in 1 reg5 lm1084-5v reg5 lm1084-5v + c144 10uf + c144 10uf wire2 wire wire2 wire c138 0.1uf c138 0.1uf + c133 10uf + c133 10uf + c140 10uf + c140 10uf i 1 tm3 tj-563 tm3 tj-563 c145 0.1uf c145 0.1uf + c147 10uf + c147 10uf c141 0.1uf c141 0.1uf c129 0.1uf c129 0.1uf + c143 10uf + c143 10uf out 2 gnd 3 in 1 reg3 lm1117-1.8v reg3 lm1117-1.8v out 2 gnd 3 in 1 reg2 lm1084-3.3v reg2 lm1084-3.3v c132 0.1uf c132 0.1uf + c134 100uf/16v(a) + c134 100uf/16v(a) l3 10uh l3 10uh c146 0.1uf c146 0.1uf i 1 tm2 tj-563 tm2 tj-563 c142 0.1uf c142 0.1uf + c136 10uf + c136 10uf i 1 tm1 tj-563 tm1 tj-563 + c130 10uf + c130 10uf + c128 10uf + c128 10uf 1 2 jp22 header 2 jp22 header 2 + c139 10uf + c139 10uf c131 0.1uf c131 0.1uf
<br> 5 5 4 4 3 3 2 2 1 1 d d c c b b a a tck tdi tdo tms vdd_jtag smux_dvdd smux_dat2 smux_dat2 smux_dat2 smux_dat2 smux_mclk smux_mclk smux_mclk smux_mclk smux_bick smux_bick smux_bick smux_bick smux_lrck smux_lrck smux_dat1 smux_dat1 smux2_dat2 smux2_dat2 smux2_dat2 smux2_dat2 smux2_dat2 smux2_dat2 smux2_dat2 smux2_dat2 smux2_dat2 smux2_dat2 smux2_mclk smux2_bick smux2_lrck smux2_dat1 sdin3 sdin2 sdin1 x_sda x_so ckm2 p_src_reset p_src_smute testi2 sdouta1 sdout6 mclk srcset0 srcset1 clko2 testi1 pc_so jx2 led_ind jx1 jx0 dac_pdn clko1 trx_pdn cs2 cs3 pc_rq_n pc_si pc_sclk tx_clk rx_clk rx_clk2 tx_dat sdout5 sdout4 sdout3 sdout1 sdout2 rx_dat bitclk_o lrclk_o trx_lrck trx_bick src_bick ckm0 src_lrck ckm1 p_ck_reset p_ad_reset p_dsp_reset x_rq_n x_si x_sclk lrclk_i bitclk_i sdin5 sdin4 i2csel dvdd_3.3v dvdd_5v dvdd_5v dvdd_5v dvdd_3.3v title size document number rev date: sheet of <doc> <revcode> <title> a3 88 wednesday, july 12, 2006 title size document number rev date: sheet of <doc> <revcode> <title> a3 88 wednesday, july 12, 2006 title size document number rev date: sheet of <doc> <revcode> <title> a3 88 wednesday, july 12, 2006 (open) wired short smux port2 jtag port2 wired short smux port sda scl r85 100 r85 100 1 tp8 tp(blue) tp8 tp(blue) wire3 wire wire3 wire c153 0.1uf c153 0.1uf c155 0.1uf c155 0.1uf 1 2 3 4 5 6 7 8 9 10 jp20 header 5x2 jp20 header 5x2 r101 100 r101 100 r93 100 r93 100 + c149 10uf + c149 10uf r88 100 r88 100 + c154 10uf + c154 10uf r87 100 r87 100 c156 0.1uf c156 0.1uf c148 0.1uf c148 0.1uf r90 100 r90 100 c159 0.1uf c159 0.1uf r95 100 r95 100 i/o0 1 i/o1 6 i/o2 8 i/o3 9 i/o4 10 i/o5 11 i/o6 12 i/o7 13 i/o8 14 i/o9 15 i/o10 16 i/o11 17 i/o12 18 i/o13 20 i/o14 25 i/o15 28 i/o16 29 i/o17 30 i/o18 32 i/o19 33 i/o20 35 i/o21 36 i/o22 37 i/o23 39 i/o24 40 i/o25 41 i/o26 42 i/o27 49 i/o28 50 i/o29 52 i/o30 53 i/o31 54 i/o32 55 i/o33 56 i/o34 58 i/o35 59 i/o36 60 i/o37 61 i/o38 63 i/o39 64 i/o41 65 i/o40 66 i/o42 67 i/o43 68 i/o44 70 i/o45 71 i/o46 72 i/o47 74 i/o48 76 i/o49 77 i/o50 78 i/o51 79 i/o52 81 i/o53 82 i/o54 85 i/o55 86 i/o56 87 i/o57 89 i/o58 90 i/o59 91 i/o60 92 i/o61 93 i/o62 94 i/o63 95 i/o64 96 i/o65 97 gck1 22 gck2 23 gck3 27 gts1 3 gts2 4 gsr 99 tck 48 tdi 45 tdo 83 tms 47 vint0 5 vint1 57 vint2 98 vio0 26 vio1 38 vio2 51 vio3 88 gnd0 21 gnd1 31 gnd2 44 gnd3 62 gnd4 69 gnd5 75 gnd6 84 gnd7 100 nc0 2 nc1 7 nc2 19 nc3 24 nc4 34 nc5 43 nc6 46 nc7 73 nc8 80 u18 xc95108 u18 xc95108 c157 0.1uf c157 0.1uf 1 2 3 4 5 6 7 8 9 10 jp21 header 5x2 jp21 header 5x2 r84 100 r84 100 r97 100 r97 100 r100 100 r100 100 r94 100 r94 100 c150 0.1uf c150 0.1uf r82 100 r82 100 r86 100 r86 100 1 tp9 tp(black) tp9 tp(black) r89 100 r89 100 wire4 wire wire4 wire 1 tp7 tp(blue) tp7 tp(blue) c151 0.1uf c151 0.1uf r83 4.7k r83 4.7k + c158 10uf + c158 10uf r81 100 r81 100 r91 100 r91 100 1 2 3 4 5 6 7 8 9 10 jp19 header 5x2 jp19 header 5x2 r96 100 r96 100 c152 0.1uf c152 0.1uf r92 10k r92 10k
<br> 5 5 4 4 3 3 2 2 1 1 d d c c b b a a sdout2 avss_chip dvss_chip dvdd_chip sdout1 dvdd18_chip xti avss_chip src_lrck dvss_chip sdin2 sdin3 sdin4 sdin5 init_reset p_ckrst p_adrst p_dsprst so dvdd_chip avdd_src dvdd_chip dvss_chip avss_chip dvss_chip dvss_chip bitclk_o test2 p_src_rst sda dvdd18_chip avdd_ad dvss_chip lrclk_o clko2 src_bick xto dvdd18_chip dvdd18_chip avdd_ad dvss_chip dvdd18_chip avdd_src ckm2 dvdd_chip avss_chip ckm0 dvdd_chip sdin1 sto ckm1 clko1 bitclk_i bitclk_i bitclk_i bitclk_i dvss_chip test1 rdy dvdd18_chip dvdd18_chip jx0 sdouta1 sdout6 jx1 avdd_ad i2csel avdd_ad lrclk_i lrclk_i lrclk_i lrclk_i srcset1 dvdd_chip srcset0 jx2 dvss_chip sdout5 sdout5 dvdd18_chip dvss_chip dvdd_chip avss_chip avss_chip mclk vcom p_src_smute avss_chip dvdd18_chip dvss_chip dvdd_chip dvdd18_chip sdout4 testo ainl8 ainr8 ainl7 ainr7 ainl6 ainr6 ainl5 ainr5 ainlp ainln ainrp ainrn ainl2 ainl3 ainr3 ainl4 ainr4 ainm ainr2 avdd_src avdd_ad sdout3 rq_n rq_n rq_n rq_n rq_n rq_n rq_n rq_n rq_n rq_n rq_n rq_n rq_n rq_n rq_n rq_n rq_n rq_n rq_n rq_n rq_n rq_n rq_n rq_n rq_n rq_n rq_n rq_n rq_n rq_n rq_n rq_n si si si si si si si si si si si si si si si si si si si si si si si si si si si si si si si si sclk sclk sclk sclk sclk sclk sclk sclk title size document number rev date: sheet of <doc> nc chip a2 11 wednesday, july 12, 2006 title size document number rev date: sheet of <doc> nc chip a2 11 wednesday, july 12, 2006 title size document number rev date: sheet of <doc> nc chip a2 11 wednesday, july 12, 2006 (57,58) (68,69) (9,10) (9,10) (67,68) (18,19) (19,20) (29,30) (67,68) (30,31) (19,20) default 1-2short (38,39) (29,30) (38,39) (13,14) (56,57) (47,48) (47,48) (13,14) (56,57) (48,49) (18,19) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 jp1 header 25x2 jp1 header 25x2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 jp2 header 15x2 jp2 header 15x2 + c40 10uf + c40 10uf c13 8.2nf(dip) c13 8.2nf(dip) + c7 10uf + c7 10uf + c30 10uf + c30 10uf r2 1.5k(dip) r2 1.5k(dip) r3 100 r3 100 c36 0.1uf c36 0.1uf + c35 10uf + c35 10uf r1 1.5k(dip) r1 1.5k(dip) + c3 10uf + c3 10uf 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 jp3 header 15x2 jp3 header 15x2 1 2 jp4 header 2 jp4 header 2 + c27 100uf(a) + c27 100uf(a) 1 tp2 tp(black) tp2 tp(black) c31 0.1uf c31 0.1uf r12 100 r12 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 jp7 header 15x2 jp7 header 15x2 + c14 100uf(a) + c14 100uf(a) c4 0.1uf c4 0.1uf + c37 10uf + c37 10uf x'tal1 12.288mhz x'tal1 12.288mhz c22 0.1uf c22 0.1uf + c8 100uf(a) + c8 100uf(a) + c32 10uf + c32 10uf c33 0.1uf c33 0.1uf r11 100 r11 100 c11 47nf(dip) c11 47nf(dip) c16 22pf(dip) c16 22pf(dip) c28 0.1uf c28 0.1uf + c23 10uf + c23 10uf + c25 10uf + c25 10uf r8 100 r8 100 c21 0.1uf c21 0.1uf + c15 100uf(a) + c15 100uf(a) r6 100 r6 100 + c5 10uf + c5 10uf r13 100 r13 100 c18 0.1uf c18 0.1uf c12 1.5uf(dip) c12 1.5uf(dip) r5 100 r5 100 c10 0.1uf c10 0.1uf c6 0.1uf c6 0.1uf r10 0(dip) r10 0(dip) c29 0.1uf c29 0.1uf r7 100 r7 100 1 2 jp6 header 2 jp6 header 2 1 tp1 tp(blue) tp1 tp(blue) lflt 1 avss1 2 avdd1 3 test1 4 i2csel 5 srcset1 6 srcset0 7 bvss1 8 dvdd1 9 dvss1 10 xti 11 xto 12 dvss2 13 dvdd18_2 14 ckm1 15 ckm0 16 ckm2 17 dvdd18_3 18 dvss3 19 dvdd3 20 lrclk_o 21 bitclk_o 22 sdout1 23 sdout2 24 sdout3 25 sdout4 26 sdout5 27 clko1 28 dvdd_4 29 dvss_4 30 dvdd18_4 31 sdin2 32 sdin3 33 sdin4 34 sdin5 35 bitclk_i 36 lrclk_i 37 dvdd18_5 38 dvss_5 39 init_reset 40 p_ckrst 41 p_adrst 42 p_dsprst 43 rq_n/cad1 44 si/cad0 45 sclk/scl 46 dvdd18_6 47 dvss_6 48 dvdd_6 49 so 50 rdy 51 sto 52 sdouta1 53 sdout6 54 clko2 55 dvdd_7 56 dvss_7 57 dvdd18_7 58 jx2 59 jx1 60 jx0 61 sdin1 62 src_bick 63 src_lrck 64 sda 65 p_srcrst 66 dvdd18_8 67 dvss_8 68 dvdd_8 69 bvss2 70 p_srcsmute 71 test2 72 avdd2 73 avss2 74 src_lflt 75 testo 76 ainm 77 ainr4 78 ainl4 79 ainr3 80 ainl3 81 ainr2 82 ainl2 83 avdd3 84 vrefh 85 vcom 86 vrefl 87 avss3 88 ainrn 89 ainrp 90 ainln 91 ainlp 92 ainr5 93 ainl5 94 ainr6 95 ainl6 96 ainr7 97 ainl7 98 ainr8 99 ainl8 100 ak7780 u1 ak7780 ak7780 u1 ak7780 + c20 10uf + c20 10uf c39 0.1uf c39 0.1uf c24 0.1uf c24 0.1uf + c1 100uf(a) + c1 100uf(a) c38 0.1uf c38 0.1uf c34 0.1uf c34 0.1uf r4 100 r4 100 r9 100 r9 100 c26 0.1uf c26 0.1uf + c19 10uf + c19 10uf 1 2 3 jp5 header 3 jp5 header 3 c17 22pf(dip) c17 22pf(dip) c2 0.1uf c2 0.1uf + c9 10uf + c9 10uf
<br> 5 5 4 4 3 3 2 2 1 1 d d c c b b a a ainl8 ainr8 ainl7 ainr7 ainl6 ainr6 ainl5 ainr5 ainlp ainln ainrp ainrn ainl2 ainl3 ainr3 ainl4 ainr4 ainm ainr2 avdd_src avdd_ad avss_chip avss_chip avss_chip vcom dvss_chip sdin2 sdin3 sdin4 sdin5 init_reset p_ckrst p_adrst p_dsprst so dvdd_chip clko1 dvss_chip dvdd_chip dvdd18_chip dvss_chip dvss_chip dvdd18_chip dvdd18_chip dvdd_chip dvss_chip test1 dvdd18_chip i2csel srcset1 srcset0 sdout4 sdout3 sdout2 sdout1 bitclk_o lrclk_o ckm2 ckm0 ckm1 mclk xti xto sdout5 sdout5 avss_chip avdd_ad avdd_ad dvdd_chip dvss_chip dvdd18_chip bvss1 dvss_chip dvdd18_chip dvss_chip dvdd_chip avss_chip dvss_chip test2 p_src_rst sda dvdd18_chip clko2 sdouta1 sdout6 p_src_smute src_lrck src_bick sdin1 jx0 jx1 jx2 sto rdy bitclk_i bitclk_i lrclk_i lrclk_i rq_n si sclk dvdd18_chip dvss_chip dvdd_chip dvdd18_chip dvss_chip dvdd_chip testo avdd_src avss_chip avss_chip bvss2 avdd_ad avdd_src dvdd_chip dvdd18_chip avdd_ad title size document number rev date: sheet of <doc> nc socket a2 11 wednesday, july 12, 2006 title size document number rev date: sheet of <doc> nc socket a2 11 wednesday, july 12, 2006 title size document number rev date: sheet of <doc> nc socket a2 11 wednesday, july 12, 2006 default 1-2short (9,10) (9,10) (19,20) (19,20) (29,30) (48,49) (29,30) (56,57) (56,57) (68,69) (13,14) (13,14) (18,19) (18,19) (30,31) (38,39) (38,39) (47,48) (47,48) (57,58) (67,68) (67,68) default short default short c34 0.1uf c34 0.1uf 1 tp1 tp(blue) tp1 tp(blue) r10 100 r10 100 c44 0uf(dip) c44 0uf(dip) r5 0(dip) r5 0(dip) c2 0.1uf c2 0.1uf c36 0.1uf c36 0.1uf c14 8.2nf(dip) c14 8.2nf(dip) c12 1.5uf(dip) c12 1.5uf(dip) r15 100 r15 100 c16 0uf(dip) c16 0uf(dip) + c23 10uf + c23 10uf c45 0uf(dip) c45 0uf(dip) r13 0(dip) r13 0(dip) c48 0uf(dip) c48 0uf(dip) + c31 100uf(a) + c31 100uf(a) + c35 10uf + c35 10uf r18 0(dip) r18 0(dip) r11 100 r11 100 lflt 1 avss1 2 avdd1 3 test1 4 i2csel 5 srcset1 6 srcset0 7 bvss1 8 dvdd1 9 dvss1 10 xti 11 xto 12 dvss2 13 dvdd18_2 14 ckm1 15 ckm0 16 ckm2 17 dvdd18_3 18 dvss3 19 dvdd3 20 lrclk_o 21 bitclk_o 22 sdout1 23 sdout2 24 sdout3 25 sdout4 26 sdout5 27 clko1 28 dvdd_4 29 dvss_4 30 dvdd18_4 31 sdin2 32 sdin3 33 sdin4 34 sdin5 35 bitclk_i 36 lrclk_i 37 dvdd18_5 38 dvss_5 39 init_reset 40 p_ckrst 41 p_adrst 42 p_dsprst 43 rq_n/cad1 44 si/cad0 45 sclk/scl 46 dvdd18_6 47 dvss_6 48 dvdd_6 49 so 50 rdy 51 sto 52 sdouta1 53 sdout6 54 clko2 55 dvdd_7 56 dvss_7 57 dvdd18_7 58 jx2 59 jx1 60 jx0 61 sdin1 62 src_bick 63 src_lrck 64 sda 65 p_srcrst 66 dvdd18_8 67 dvss_8 68 dvdd_8 69 bvss2 70 p_srcsmute 71 test2 72 avdd2 73 avss2 74 src_lflt 75 testo 76 ainm 77 ainr4 78 ainl4 79 ainr3 80 ainl3 81 ainr2 82 ainl2 83 avdd3 84 vrefh 85 vcom 86 vrefl 87 avss3 88 ainrn 89 ainrp 90 ainln 91 ainlp 92 ainr5 93 ainl5 94 ainr6 95 ainl6 96 ainr7 97 ainl7 98 ainr8 99 ainl8 100 ak7780 u1 ak7780 ak7780 u1 ak7780 1 2 jp6 header 2 jp6 header 2 r3 100 r3 100 c21 0.1uf c21 0.1uf r14 100 r14 100 r1 1.5k(dip) r1 1.5k(dip) c26 0.1uf c26 0.1uf + c25 10uf + c25 10uf c17 0uf(dip) c17 0uf(dip) c20 22pf(dip) c20 22pf(dip) r17 0(dip) r17 0(dip) c39 0.1uf c39 0.1uf r21 0(dip) r21 0(dip) r20 0(dip) r20 0(dip) 1 2 3 jp7 header 3 jp7 header 3 c29 0.1uf c29 0.1uf + c8 100uf(a) + c8 100uf(a) + c27 10uf + c27 10uf c47 0uf(dip) c47 0uf(dip) 1 2 jp8 header 2 jp8 header 2 + c15 100uf(a) + c15 100uf(a) 1 2 jp4 header 2 jp4 header 2 c10 0.1uf c10 0.1uf + c40 10uf + c40 10uf 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 jp1 header 25x2 jp1 header 25x2 c42 0.1uf c42 0.1uf 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 jp5 header 15x2 jp5 header 15x2 + c9 10uf + c9 10uf r7 100 r7 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 jp2 header 15x2 jp2 header 15x2 r4 0(dip) r4 0(dip) c30 0.1uf c30 0.1uf r9 100 r9 100 c18 0uf(dip) c18 0uf(dip) c6 0.1uf c6 0.1uf c32 0.1uf c32 0.1uf c37 0.1uf c37 0.1uf c22 0.1uf c22 0.1uf c4 0.1uf c4 0.1uf c41 0.1uf c41 0.1uf + c13 100uf(a) + c13 100uf(a) r12 100 r12 100 r2 1.5k(dip) r2 1.5k(dip) + c3 10uf + c3 10uf 1 2 jp3 header 2 jp3 header 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 jp9 header 15x2 jp9 header 15x2 + c1 100uf(a) + c1 100uf(a) c24 0.1uf c24 0.1uf + c43 10uf + c43 10uf r16 100 r16 100 c46 0uf(dip) c46 0uf(dip) 1 tp2 tp(black) tp2 tp(black) c19 22pf(dip) c19 22pf(dip) r19 0(dip) r19 0(dip) + c38 10uf + c38 10uf + c5 10uf + c5 10uf + c7 10uf + c7 10uf + c33 10uf + c33 10uf c11 47nf(dip) c11 47nf(dip) r6 0(dip) r6 0(dip) + c28 10uf + c28 10uf x'tal1 12.288mhz x'tal1 12.288mhz r8 100 r8 100
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