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[ak7782] ms1337-e-00-pb 2011/11 - 1- general description the ak7782 is an audio digital signal processor with integrated 24bit 5ch adcs, an 8:2 stereo input selector and sample rate conver ters that support 2ch inputs and the frequency up to 96khz. the adc supports wide range of sampling fr equency from 7.35khz to 96khz. two integrated audio dsps have high performance processing speed of 2560step/fs (at 48khz sampling) , and two 6k-word delay rams allow surround processing, time alignment adjusti ng and fir filtering. as the ak7782 is a ram based dsp, it is programmable for various user r equirements. it is housed in a 100pin lqfp package. features [dsp1/dsp2] word length: 28-bits instruction cycle time: 8.1ns (2560fs, fs=48khz) processing step: 2560 steps (max) /fs= 48khz, 44.1khz (normal speed) 15360 steps (max) /fs= 8khz, 7.35khz 1280 steps (max) fs= 96kh z, 88.2khz (double speed) multiplier: 24 x 16 40-bits (double precision available) divider: 24 24 24-bits (floating point normalization function) alu: 44-bit arithmetic operation (with 4-bit overflow margin) 24-bit arithmetic and logic operation data shift: right shift after multiplicati on 1, 2, 4, 5, 8, 14, 15-bits right shift bus 1, 2, 3, 4, 8, 14, 15-bits left shift after multiplication 1, 2, 3, 4, 8, 15-bits left shift bus 1, 2, 3, 4, 6, 8, 15-bits indirect shifting function program ram (pram): 2048word x 36-bits coefficient ram (cram): 2048word x 16-bits data ram (dram): 2048word x 28-bits offset register (ofreg): 64word x 13-bits delay ram (dlram): 168kbit (four types) 6kword 28-bits 4kword 28-bits + 4kword 14-bits 3kword 28-bits + 6kword 14-bits 3kword 28-bits + 3kword 28-bits (linear) register: 44-bits x 4 (acc) [for alu] 28-bits x 12 (tmp) [dbus connection] 28-bits x 6 steps stack (ptmp) [dbus connection] dual audio dsp with 24bit 5ch adc & src ak7782
[ak7782] ms1337-e-00-pb 2011/11 - 2- [stereo adc, common for adc1 and adc2] 24-bit 2ch x 2 s/(n+d): 90db (fs=48khz) d-range: 96dba (fs=48khz) s/n: 96dba (fs=48khz) 8ch bidirectional analog input selector high-pass filter (hpf) for dc offset cancellation fs=7.35khz ~ 96khz [mono adc] 24bit 1ch s/(n+d) 88db (fs=48khz) d-range 95dba (fs=48khz) s/n 95dba (fs=48khz) high-pass filter (hpf) for dc offset cancellation fs=7.35khz ~ 96khz digital volume control [dsp1/dsp2 in/output digital interface] serial data input: 14ch (including adc block) serial data output: 16ch (each dsp outputs are 14ch) microcomputer interface: 1ch in/out or i 2 c-bus [src, common for src1 and src2] 2ch x 2 fs=7.35khz ~ 96khz [general] pll 3.3v0.3v, 1.8v 0.1v operational temperature: -40c ~ 85c 100pin lqfp
[ak7782] ms1337-e-00-pb 2011/11 - 3- block diagram figure 1. block diagram a inl+,ainr+ src2lrck src2bick psrcrstn psrcsmute sdout2(32bit) sdin5 pdsprstn initrstn pull down hi-z ctrl reg sw 2 4 vref 3 3 2 2 2 2 2 2 a inm a dc2 a dc1 a sel1[2:0] a sel2[2:0] vss1 vrefl vcom vrefh a vdd a dcm vol mux sdin3(32bit) sdin2(32bit) sdin1 sdin4(32bit) 3 lrclki 7 3 8 3 dvdd18 vss3 vss2 2 dvdd 6 i/o sdout1 sdout4(32bit) sdout3(32bit) sdout5 out5en out4en out2en out1en sto sdin6 / jx1 jx0 sdin7/jx2 dsp1 gpo10 gpo11 irpt1 p1sdin6 p1sdout6 p1sdin5 p1sdout5 p1sdin4 p1sdout4 p1sdin3 p1sdout3 p1sdin2 p1sdout2 p1sdin1 p1sdout1 dsp2 gpo20 irpt2 p2sdin6 p2sdout6 p2sdin5 p2sdout5 p2sdin4 p2sdout4 p2sdin1 p2sdout1 bitclki lflt clko1 jx22 jx21 jx20 jx20e jx21e jx22e jx12 jx11 jx10 jx10e jx11e jx12e p1sdin7 p2sdin7 0 2 1 3 p2sdin3 p2sdout3 p2sdin2 p2sdout2 gpo21 out3en sdout6 wdt1 wdt2 wdt1en wdt2en crce out6en 0 2 1 3 sdouta outaen 02 13 nc rsrc1smute rsrc1rstn srcbick srclrck src1 src1o src1i testo pckrstn smode controller xti xto lrclko bitclko (master="h",slave="l") testi2 ckm[2:0] 3 rckrstn rdsprstn testi1 padrstn radrstn ckrstn sresetn dsprstn adrstn sclk/scl so si/cad0 rqn/cad1 rdy sda i2csel micif src2 src2o src2i src2cki rsrc2smute 0 1 0 1 0 2 1 3 0 2 1 3 0 2 1 3 0 2 1 3 0 2 1 3 0 2 1 3 0 1 0 1 0 1 0 2 1 3 0 2 1 3 0 2 1 3 0 2 1 3 0 2 1 3 0 2 1 3 rsrcrst2n crc p1in7sel p1in6sel p1in5sel p1in1sel src2isel p2in7sel p2in6sel p2in5sel p2in4sel p2in3sel p2in2sel p2in1sel msel outasel1 outasel2 out6sel out5sel1 out4sel out3sel out2sel out1sel1 2 0 1 2 src1lrcki src1bicki src2lrcki src2bicki src1bicko src1lrcko src2cko 0 1 2 0 1 2 src2bicko src2lrcko lock1e lock2e src1unlock src2unlock p2sdout7 p1sdout7 2 3 sdout7 out7en 0 2 1 3 jx2 jx1 jx1 jx2 out7sel 0 2 1 3 0 2 1 3 a inl+,ainr+ a inl2, ainr2 a inl3, ainr3 ainl4, ainr4 a inl5, ainr5 ainl6 ainr6 ainl7, ainr7 a inl8, ainr8
[ak7782] ms1337-e-00-pb 2011/11 - 4- dsp block diagram (common for dsp1 and dsp2) cp0, cp1 cram 2048w x 16bit dp0, dp1 dram 2048w x 28bit mpx16 mpx24 ofreg 64w x 13bit x y multiply 16bit x 24bit 40bit micon i/f control pram 2048w x 36bit dec pc stack: 5level(max) mul dbus shift a b alu 44bit overflow margin: 4bit dr0-3 over flow data generator division 24 24 24 peak detector serial i/f cbus(16bit) dbus(28bit) 40bit 28bit 44bit 44bit 44bit sdout4 dlram 6kw x 28bit ptmp(lifo) 6 x 28bit dlp0, dlp1 etc 2 x 24/24.4bit sdin3 2 x 24/24.4bit sdin1 sdin2 sdin4 sdout2 2 x 24/20/16/32/24.4bit sdin5 2 x 24/24.4bit sdout5 44bit sdout3 sdout1 tmp 12 x 28bit 2 x 24/24.4bit sdin6 2 x 24/24.4bit sdout6 2 x 24/24.4bit 2 x 24/24.4bit sdin7 2 x 24/20/16/32/24.4bit 2 x 24/20/16/32/24.4bit 2 x 24/16/32/24.4bit 2 x 24/16/32/24.4bit 2 x 24/16/32/24.4bit 2 x 24/24.4bit sdout7
[ak7782] ms1337-e-00-pb 2011/11 - 5- ordering guide ak7782vq -40 +85 c 100pin lqfp (0.5mm pitch) AKD7782 evaluation board for ak7782 pin layout (top view) 100 p in lqf p n c psrcrstn so 76 77 78 79 80 81 82 83 84 85 87 88 86 89 91 92 90 93 94 95 97 98 96 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 39 38 40 37 35 34 36 33 32 31 29 28 30 27 26 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 sto sdouta1 sdout6 sdout7 dvdd vss3 dvdd18 sdin7/jx2 sdin6/jx1 jx0 sdin1 srcbick sr clrck sda dvdd18 rd y vss3 dvdd vss2 psrcsmute testi2 a vdd vss1 nc ainm ainr4 dvdd vss3 ainl4 ainl2 avdd vrefh vcom vref l ainr 5 ainr + ainl - ainl 6 ainr 7 ainr 8 ainl 8 avdd testi1 i2csel dvdd18 si /cad0 sclk/ scl pckrstn rqn/cad1 pdsprstn vss3 dvdd18 sdin5 bi tclki dvdd18 sdout5 src2bic k vss2 dvdd vss3 xti ckm[1 ] ckm[0] ckm[2] dvdd18 ainr3 ainl3 bitclko sdout1 sdin4 ainr2 lfl t sdout4 sdout3 padrstn ainr 6 ainl 5 vss1 ainr - sdin2 ainl 7 src2lrck sdout 2 sdin3 input output i/o power input output i/o power pin clko1 vss1 ainr + vss3 dvdd1 8 xto vss3 dvdd lrclko lrclki vss3 dvdd initrstn figure 2. pin layout
[ak7782] ms1337-e-00-pb 2011/11 - 6- pin/function no. pin name i/o function classification 1 lflt o filter connection pin for ak7782 core pll when using the pll function, connect with r (1.5k ) and c (47nf) in series and connected to analog ground (vss1) analog output 2 vss1 - ground pin 0v (silicon board potential) 3 avdd - power supply pin for analog block 3.3v (typ) power supply 4 testi1 i test pin (internal pull-down) connect to vss3 test 5 i2csel i i 2 c-bus select pin ?l?: normal microcomputer interface ?h?: i 2 c-bus selected mode. scl and sda are active. i2csel must be fixed to ?l? (vss3) or ?h? (dvdd). i 2 c select 6 src2lrck i lr clock input pin for src2 7 src2bick i bit clock input pin for src2 src2 8 vss2 - ground pin (silicon board potential) connect to vss1 power supply 9 dvdd - power supply pin for digital block 3.3v (typ) digital power supply 10 vss3 - ground pin 0v power supply 11 xti i crystal oscillator input pin connect a crystal oscillator between the xti pin and xto pin or input an external clock into the xti pin when not using a crystal oscillator. 12 xto o crystal oscillator output pin connect a crystal oscillator between the xti pin and xto pin or leave open when using an external clock source. system clock 13 vss3 - ground pin 0v 14 dvdd18 - power supply pin for digital block 1.8v (typ) power supply 15 ckm [1] i clock mode select pin 16 ckm [0] i clock mode select pin 17 ckm [2] i clock mode select pin mode select 18 dvdd18 - power supply pin for digital block 1.8v (typ) digital power supply 19 vss3 - ground pin 0v 20 dvdd - power supply pin for digital block 3.3v (typ) power supply
[ak7782] ms1337-e-00-pb 2011/11 - 7- no. pin name i/o function classification 21 lrclko o lr channel select pin master mode: outputs 1fs clock. slave mode: outputs lrclki clock. 22 bitclko o serial bit clock output pin master mode: outputs 64fs clock. slave mode: outputs bitclki clock system clock 23 sdout1 o dsp serial data output pin outputs ?l? during initial reset. the output data is selected by cont7 d3, d2. 24 sdout2 o dsp serial data output pin outputs ?l? during initial reset. the output data is selected by cont7 d5, d4. 25 sdout3 o dsp serial data output pin outputs ?l? during initial reset. the output data is selected by cont7 d7, d6. 26 sdout4 o dsp serial data output pin outputs ?l? during initial reset. the output data is selected by cont6 d1, d0. 27 sdout5 o dsp serial data output pin outputs ?l? during initial reset. the output data is selected by cont6 d3, d2. digital block serial data output 28 clko1 o clock output pin 1 output frequency can be set by control registers. outputs ?l? during initial reset. clock output 29 dvdd - power supply pin for digital block 3.3v (typ) digital power supply 30 vss3 - ground pin 0v 31 dvdd18 - power supply pin for digital block 1.8v (typ) power supply 32 sdin2 i dsp serial data input pin supports floating point input f24.4: msb 32-bit and 24-bit / lsb 24-bit, 20-bit and 16-bit. connect to vss3 when this pin is not used. 33 sdin3 i dsp serial data input pin supports floating point input f24.4: msb 32-bit and 24-bit / lsb 24-bit, 20-bit and 16-bit. connect to vss3 when this pin is not used. 34 sdin4 i dsp serial data input pin supports floating point input f24.4: msb 32-bit and 24-bit / lsb 24-bit, 20-bit and 16-bit. connect to vss3 when this pin is not used. digital block serial data input 35 sdin5 i dsp serial data input pin supports floating point input f24.4: msb 24-bit / lsb 24-bit, 20-bit and 16-bit. connect to vss3 when this pin is not used. digital block serial data input
[ak7782] ms1337-e-00-pb 2011/11 - 8- no. pin name i/o function classification 36 bitclki i serial bit clock input pin 37 lrclki i lr channel select input pin system clock 38 dvdd18 - power supply pin for digital block 1.8v (typ) digital power supply 39 vss3 - ground pin 0v power supply 40 initrstn i initial reset n pin (for device initialization) the ak7782 is initialized by the initrstn pin = ?l?. this pin must be ?l? upon power-up the ak7782. ckm[2:0] pin settings can be change when the initrstn pin = ?l?. 41 pckrstn i clock reset n pin the internal clock is reset by the pckrstn pin = ?l?. setting of ckm[2:0] can be changed by the pckrstn pin = ?l?, even if the initrstn pin is ?h?. 42 padrstn i adc reset n pin adc1, adc2 and adcm are reset by the padrstn pin = ?l?. control register radrstn bit= ?0 ? can also reset these blocks. the ak7782 is in system reset state when padrstn and pdsprstn pins = ?l?. 43 pdsprstn i dsp reset n pin dsp1 and dsp2 are reset by the pdsprstn= ?l?. control register rdsre bit = ?0? can also reset these blocks . the ak7782 is in system reset state when padrstn and pdsprstn pins = ?l?. reset rqn i microcomputer interface request n pin (i2csel= ?l?) set this pin to ?h? during initial reset or when not interfacing to a microcomputer. microcomputer i/f 44 cad1 i i 2 c-bus address pin 1 (i2csel= ?h?) i 2 c si i serial data input pin for microc omputer interface (i2csel= ?l?) set this pin to ?l? when not used. microcomputer i/f 45 cad0 i i 2 c-bus address pin 0 (i2csel= ?h?) i 2 c sclk i serial data clock pin for microc omputer interface (i2csel= ?l?) set this pin to ?h? when there is no clock input. microcomputer i/f 46 scl i scl i 2 c-bus interface pin (i2csel= ?h?) i 2 c 47 dvdd18 - power supply pin for digital block 1.8v (typ) digital power supply 48 vss3 - ground pin 0v power supply 49 dvdd - power supply pin for digital block 3.3v (typ) digital power supply 50 so o serial data output pin for microcomputer interface outputs ?hi-z? when the rqn pin = ?h?. outputs ?hi-z? during initial reset. microcomputer i/f
[ak7782] ms1337-e-00-pb 2011/11 - 9- no. pin name i/o function classification 51 rdy o data write ready pin for microcomputer interface microcomputer i/f 52 sto o status output pin ?h?: normal operation ?l?: wdt, crc error or srcunlock status ( figure 1 ) outputs ?h? during initial reset. status 53 sdouta1 o serial data output pin supports msb 24-bit. outputs ?l? during initial reset. 54 sdout6 o serial data output pin supports msb 24-bit. outputs ?l? during initial reset. 55 sdout7 o serial data output pin supports msb 24-bit. outputs ?l? during initial reset. digital block serial data output 56 dvdd - power supply pin for digital block 3.3v (typ) digital power supply 57 vss3 - ground pin 0v power supply 58 dvdd18 - power supply pin for digital block 1.8v (typ) digital power supply sdin7 i dsp serial data input pin connect to vss3 when this pin is not used. this pin supports 24-bit msb justified, floating point f24.4. digital block serial data input 59 jx2 i conditional jump pin connect to vss3 when this pin is not used. condition sdin6 i dsp serial data input pin connect to vss3 when this pin is not used. this pin supports 24-bit msb justified, floating point f24.4. digital block serial data input 60 jx1 i conditional jump pin connect to vss3 when this pin is not used. 61 jx0 i conditional jump pin connect to vss3 when this pin is not used. condition 62 sdin1 i dsp/src serial data input pin connect to vss3 when this pin is not used. this pin supports 24-bit msb justified, floating point f24.4. digital block serial data input 63 srcbick i src serial bit clock input pin 64 srclrck i src lr channel select input pin src1 o i2csel pin = ?l? outputs ?l?. 65 sda i/o i2csel pin= ?h? sda i 2 c-bus interface i 2 c 66 psrcrstn i src reset n pin src1 and src2 blocks are reset by the psrcrstn pin = ?l?. control register rsrcrstn bit = ?0? can also reset these blocks. reset 67 dvdd18 - power supply pin for digital block 1.8v (typ) digital power supply 68 vss3 - ground pin 0v power supply 69 dvdd - power supply pin for digital block 3.3v (typ) digital power supply 70 vss2 - ground pin 0v (silicon board potential) connect to vss1. power supply 71 psrc smute i src soft mute pin src1 and src2 blocks are soft muted by the psrcsmute pin = ?h?. control register rsrcsmute bit = ?1? can also soft mutes these blocks. src
[ak7782] ms1337-e-00-pb 2011/11 - 10- no. pin name i/o function classification 72 testi2 i test pin (internal pull-down) connect to vss3. test 73 avdd - power supply pin for analog block 3.3v (typ) analog power supply 74 vss1 - ground pin 0v (silicon board potential) power supply 75 nc - nc pin connect to vss1. nc 76 nc - nc pin connect to vss1. nc 77 ainm i adcm mono single-ended input pin 78 ainr4 i rch single-ended input pin for adc1 or adc2 79 ainl4 i lch single-ended input pin for adc1 or adc2 80 ainr3 i rch single-ended input pin for adc1 or adc2 81 ainl3 i lch single-ended input pin for adc1 or adc2 82 ainr2 i rch single-ended input pin for adc1 or adc2 83 ainl2 i lch single-ended input pin for adc1 or adc2 analog input 84 avdd - power supply pin for analog block 3.3v (typ) analog power supply 85 vrefh i reference voltage input pin for analog block connect this pin to a vdd, and connect a 0.1 f and 10 f capacitors between this pin and vss1. analog input 86 vcom o common voltage output pin for analog block connect a 0.1 f and 10 f capacitors between this pin and vss1. do not connect to external circuits. analog output 87 vrefl i reference voltage input pin for analog block normally, this pin is connected to vss1. analog input 88 vss1 - ground pin 0v (silicon board potential) power supply 89 ainr- i rch differential input pin for adc1 or adc2 90 ainr+ i rch differential input pin for adc1 or adc2 91 ainl- i lch differential input pin for adc1 or adc2 92 ainl+ i lch differential input pin for adc1 or adc2 93 ainr5 i rch single-ended input pin for adc1 or adc2 94 ainl5 i lch single-ended input pin for adc1 or adc2 95 ainr6 i rch single-ended input pin for adc1 or adc2 96 ainl6 i lch single-ended input pin for adc1 or adc2 97 ainr7 i rch single-ended input pin for adc1 or adc2 98 ainl7 i lch single-ended input pin for adc1 or adc2 99 ainr8 i rch single-ended input pin for adc1 or adc2 100 ainl8 i lch single-ended input pin for adc1 or adc2 analog input note 1. all digital input pins must not be allowed to float. note 2. if analog input pins (ainr-, ainr+, ainl-, ai nl+, ainl2~8, ainr2~8, ainm) are not used, leave them open. note 3. the i2csel pin should be fixed to ?l? (vss3) or ?h? (dvdd).
[ak7782] ms1337-e-00-pb 2011/11 - 11- handling of unused pins unused i/o pins must be connected appropriately. pin name setting analog ainl+, ainl-, ainr+, ainr-, ainl2, ainr2, ainl3, ainr3, ainl4, ainr4, ainl5, ainr5, ainl6, ainr6, ainl7, ainr7, ainl8, ainr8, ainm leave open xto, lrclko, bitclko, sdout1, sdout2, sdout3, sdout4, sdout5, clko1, so, rdy, sto, sdotua1, sdout6, sdout7, sda (i2csel= ?l?) leave open digital testi1, src2lrck, src2bick, xti, sdin2, sdin3, sdin4, sdin5, pckrstn, padrstn, sd in7/jx2, sdin6/jx1, jx0, sdin1, srcbick, srclrck, psrcrstn, ps rcsmute, testi2 connect to vss3 relationship between the i2csel pin and the sda i2csel initrstn sda normal microcomputer l l l interface l h l i 2 c-bus h l ?hi-z? pull-up h h function
[ak7782] ms1337-e-00-pb 2011/11 - 12- absolute maximum ratings (vss1=vss2=vss3=0v; note 4 ) parameter symbol min max unit power supply voltage analog (avdd) digital (dvdd) digital (dvdd18) |vss1(vss2) ? vss3| ( note 5 ) va vd vd18 gnd -0.3 -0.3 -0.3 -0.3 4.3 4.3 2.5 +0.3 v v v v input current (except for power supply pin) iin ? 10 ma analog input voltage ainl+, ainl-, ainr+, ainr-, ainl2~8, ainr2~8, ainm vrefh, vrefl vina -0.3 (va+0.3) 4.3 v digital input voltage vind -0.3 (vd+0.3) 4.3 v operational ambient temperature ta -40 85 c storage temperature tstg -65 150 c note 4. all voltages with respect to ground. note 5. vss1, vss2 and vss3 must be connected to the same ground plane. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operation condition (vss1=vss2=vss3=0v; note 4 ) parameter symbol min typ max unit power supply voltage avdd dvdd dvdd18 va vd vd18 3.0 3.0 1.7 3.3 3.3 1.8 3.6 3.6 1.9 v v v avdd-dvdd vdd -0.3 0 +0.3 v reference voltage (vref) vrefh ( note 6 ) vrefl ( note 7 ) vrh vrl va 0.0 v v note 4. all voltages with respect to ground. note 6. the vrefh pin is normally connected to avdd. note 7. the vrefl pin is normally connected to vss1. note 8. the analog input voltage is proportional to the (vrefh-vrefl) voltage. note 9. the power-up sequence between avdd, dvdd and dvdd18 is not critical. the initrstn pin should be held ?l? when power is supplied. the initrstn pin is allowed to be ?h? after all power supplies are applied and settled. note 10. do not turn off the power supply of the ak7782 when the power supplies of the surrounding device are turned on in i 2 c-bus mode (i2csel pin = ?h?). pull-up resistors at sda and scl pins must be connected to the dvdd voltage or less. (a diode exists fo r dvdd in the sda and scl pins.) warning: akm assumes no responsibility for the usage beyond the conditions in the datasheet.
[ak7782] ms1337-e-00-pb 2011/11 - 13- analog characteristics (1) analog characteristics 1-1) adc (ta=25 c; avdd=dvdd=3.3v; dvdd18=1.8v, vrefh=avdd, vrefl=vss1, bitclk=64fs; signal frequency 1khz; measurement frequency=20hz~20khz@48khz, 20hz~40khz@96khz; adc full differential input (adc1, adc2); ckm mode 0 (ckm[2:0]=000), during src reset, unless otherwise specified.) parameter min typ max unit resolution 24 bits dynamic characteristics s/(n+d) fs = 48khz (-1dbfs) note 11 ) fs = 96khz (-1dbfs) 82 90 87 db db dynamic range fs = 48khz (a-filter) note 11 , note 12 ) fs = 96khz 88 96 93 db db s/n fs = 48khz (a-filter) note 11 ) fs = 96khz 88 96 93 db db inter-channel isolation (f=1khz) note 13 ) 90 115 db dc accuracy channel gain mismatch 0.0 0.3 db analog input input voltage (differential input) note 14 ) 1.85 2.00 2.15 vp-p input voltage (single-ended input) note 15 ) 1.85 2.00 2.15 vp-p stereo adc adc1 adc2 input impedance note 16 ) 22 33 k ? resolution 24 bits dynamic characteristics s/(n+d) fs = 48khz (-1dbfs) fs = 96khz (-1dbfs) 78 88 87 db db dynamic range fs = 48khz (a-filter) note 12 ) fs = 96khz 87 95 92 db db s/n fs = 48khz (a-filter) fs = 96khz 87 95 92 db db analog input input voltage note 17 ) 1.85 2.00 2.15 vp-p mono adc adcm input impedance note 18 ) 22 33 k ? note 11. values are not guaran teed with single-ended inputs. note 12. s/(n+d) when -60db signal is applied. note 13. inter-channel isolation between l-ch annel and r-channel at ?1dbfs signal input. note 14. ainl+, ainl-, ainr+, and ainr- pins. the full scale for differential input voltage is ( fs= (vrefh-vrefl) x (2.0/3.3)). note 15. ainl2~l8, and ainr2~r8 pins. the full scale of single-ended input voltage (fs=(vrefh-vrefl) x (2.0/3.3)). note 16. ainl+, ainl-, ainr+, ainr-, ainl2~l8, and ainr2~r8 pins. note 17. ainm pin. the full scale of inpu t voltage is (fs=(vrefh-vrefl) x (2.0/3.3)). note 18. ainm pin.
[ak7782] ms1337-e-00-pb 2011/11 - 14- 1-2) src (ta=25 c; avdd = 3.3v; dvdd=3.3v; dvdd18=1.8v; data = 24bit; measurement bandwidth = 20hz fso/2, unless otherwise specified.) parameter symbol min typ max unit resolution 24 bits input sample rate fsi 7.35 96 khz output sample rate fso 7.35 96 khz thd+n (input= 1khz, 0dbfs) fso/fsi=44.1khz/48khz fso/fsi=44.1khz/96khz fso/fsi=48khz/44.1khz fso/fsi=48khz/96khz fso/fsi=48khz/8khz fso/fsi=8khz/48khz fso/fsi=8khz/44.1khz -112 -112 -112 -112 -111 -112 -100 -103 db db db db db db db dynamic range (input= 1khz, -60dbfs) fso/fsi=44.1khz/48khz fso/fsi=44.1khz/96khz fso/fsi=48khz/44.1khz fso/fsi=48khz/96khz fso/fsi=48khz/8khz fso/fsi=8khz/48khz fso/fsi=8khz/44.1khz dynamic range (input= 1khz, -60dbfs, a-weighted fso/fsi=44.1khz/48khz 109 113 113 113 113 112 113 113 115 db db db db db db db db ratio between input and output sample rate fso/fsi 0.167 6
[ak7782] ms1337-e-00-pb 2011/11 - 15- dc characteristics (ta=-40c~85c, avdd=dvdd=3.0~3.6v, dvdd18=1.7~1.9v) parameter symbol min typ max unit high level input voltage note 19 ) vih 80%dvdd v low level input voltage note 19 ) vil 20%dvdd v scl, sda high level input voltage vih 70%dvdd v scl, sda low level input voltage vil 30%dvdd v high level output voltage iout=-100 a voh dvdd-0.5 v low level output voltage iout=100 a note 20 ) vol 0.5 v sda low level output voltage iout=3ma vol 0.4 v input leak current note 21 ) input leak current (pull-down pin) note 22 ) input leak current (xti pin) iin iid iix 22 26 10 a a a note 19. except for the sda pin and the scl pin (when i2csel= ?1?). the sclk pin is included when i2csel = ?0?. note 20. except for the sda pin. note 21. except for the xti pin and pull-down pins. note 22. pull-down pins (typ. 150k ? ) are the testi1 and testi2 pins. power consumption (ta=25c, avdd=dvdd=3.0~3.6v(typ=3.3v, max=3.6v), dvdd18=1.7~1.9v(typ=1.8v, max=1.9v)) parameter min typ max unit power supply current ( note 23 ) 1) a) avdd 52 70 ma b) dvdd 8 15 ma c) dvdd18 140 210 ma note 23. the current of dvdd18 changes depending on the system frequency and contents of the dsp program.
[ak7782] ms1337-e-00-pb 2011/11 - 16- digital filter characteristics 1) adc1, adc2 (ta=-40c~85c; avdd=dvdd=3.0~3.6v; dvdd18=1.7~1.9v; fs=48khz ( note 24 )) parameter symbol min typ max unit passband (0.005db) ( note 25 ) (-0.02db) (-6.0db) pb 0 21.768 23.99 21.5 khz khz khz stopband sb 26.54 khz passband ripple ( note 25 ) pr 0.005 db stopband attenuation ( note 26 , note 27 ) sa 80 db group delay distortion gd 0 s group delay (ts=1/fs) gd 29 ts digital delay filter + analog filter amplitude characteristics 20hz~20.0khz 0.01 db note 24. frequency of each amplitude characteristic is in propo rtion to fs (sampling rate). the characteristic of the high pass filter is not included. note 25. the passband is from dc to 21.5khz when fs=48khz. note 26. the stopband is from 26.5khz to 3.0455mhz when fs = 48khz. note 27. when fs = 48 khz, the analog modulator samples the analog input at 3.072mhz. there is no attenuation of an input signal in band of integer times (n x 3.072mhz 21.99khz; n=0, 1, 2, 3?) of the sampling frequency by the digital filter. 2) adcm (ta=-40c ~85c; avdd=dvdd=3.0~3.6v; dvdd18=1.7~1.9v fs=48khz; ( note 24 )) parameter symbol min typ max unit passband (0.005db) ( note 25 ) (-0.02db) (-6.0db) pb 0 21.768 23.99 21.5 khz khz khz stopband sb 26.54 khz passband ripple ( note 25 ) pr 0.005 db stopband attenuation ( note 26 , note 27 ) sa 80 db group delay distortion gd 0 s group delay (ts=1/fs) ( note 28 ) gd 29 ts digital delay filter + analog filter amplitude characteristics 20hz~20.0khz 0.1 db note 24. frequency of each amplitude characteristic is in propo rtion to fs (sampling rate). the characteristic of the high pass filter is not included. note 25. the passband is from dc to 21.5khz when fs=48khz. note 26. the stopband is from 26.5khz to 3.0455mhz when fs = 48khz. note 27. when fs = 48 khz, the analog modulator samples the analog input at 3.072mhz. there is no attenuation of an input signal in band of integer times (n x 3.072mhz 21.99khz; n=0, 1, 2, 3?) of the sampling frequency by the digital filter. note 28. 1ts additional delay occurs in vol + mux path.
[ak7782] ms1337-e-00-pb 2011/11 - 17- 3) src (common for src1 and src2) (ta=-40c ~85c; avdd=dvdd=3.0~3.6v, dvdd18=1.7~1.9v) parameter symbol min typ max unit passband -0.01db 0.980 fso/fsi 6.000 pb 0 0.4583fsi khz 0.900 fso/fsi<0.990 pb 0 0.4167fsi khz 0.533 fso/fsi<0.909 pb 0 0.2182fsi khz 0.490 fso/fsi<0.539 pb 0 0.2177fsi khz 0.450 fso/fsi<0.495 pb 0 0.1948fsi khz 0.225 fso/fsi<0.455 pb 0 0.0917fsi khz 0.167 fso/fsi<0.227 pb 0 0.0917fsi khz stopband 0.980 fso/fsi 6.000 sb 0.5417fsi khz 0.900 fso/fsi<0.990 sb 0.5021fsi khz 0.533 fso/fsi<0.909 sb 0.2974fsi khz 0.490 fso/fsi<0.539 sb 0.2812fsi khz 0.450 fso/fsi<0.495 sb 0.2604fsi khz 0.225 fso/fsi<0.455 sb 0.1573fsi khz 0.167 fso/fsi<0.227 sb 0.1354fsi khz passband ripple 0.225 fso/fsi 6.000 pr 0.01 db 0.167 fso/fsi<0.227 pr 0.0612 db stopband attenuation 0.450 fso/fsi 6.000 sa 95.2 db 0.167 fso/fsi<0.455 sa 92.3 db group delay (ts=1/fs) ( note 29 ) gd 56 ts note 29. src delay time is calculated from the rising edge of srclrck just after data input to the rising edge of lrclko just after data output, when there is no phase difference between srclrck and lrclko.
[ak7782] ms1337-e-00-pb 2011/11 - 18- switching characteristics [#h indicates hexadecimal numbers. (#=0, 1, 2 ~ 9, a, b, c, d, e, f)] 1) system clock (ta=-40c~85c, avdd=dvdd=3.0~3.6v, dvdd18=1.7~1.9v) parameter symbol min typ max unit xti ckm[2:0] 0h, 1h, 2h, 3h a) with a crystal oscillator ckm[2:0]=0h, 2h fxti 11.2896 12.288 mhz ckm[2:0]=1h, 3h fxti 16.9344 18.432 mhz b) with an external clock duty cycle 40 50 60 % ckm[2:0]=0h, 2h fxti 11.0 12.4 mhz ckm[2:0]=1h, 3h fxti 16.5 18.6 mhz lrclki frequency ( note 30 ) fs 7.35 48 96 khz bitclki frequency high level width low level width tbclkh tbclkl 64 64 ns ns a) ckm[2:0]=2h, 3h fbclk 64 fs duty cycle 40 50 60 % ckm[2:0]=2h, 3h 0.23 6.2 mhz b) ckm[2:0]=4h, 5h ( note 31 ) fbclk 64 fs duty cycle 40 50 60 % ckm[2:0]=4h fbclk 2.75 3.1 mhz ckm[2:0]=5h fbclk 5.5 6.2 mhz note 30. lrclk frequency and sampling rate (fs) should be the same. note 31. bitclki is a source of master cl ock. it should be 64 times fs correctly. (ta=-40c ~85c, avdd=dvdd=3.0~3.6v, dvdd18=1.7~1.9v) parameter symbol min typ max unit srclrck frequency ( note 30 ) fs 7.35 48 96 khz srcbick frequency high level width low level width tbclkh tbclkl 64 64 ns ns ( note 32 ) fbclk 32 128 fs duty cycle 40 50 60 % 0.23 6.2 mhz note 30. lrclk frequency and sampling rate (fs) should be the same. note 32. the maximum value 128fs is achieved when fs 48khz.
[ak7782] ms1337-e-00-pb 2011/11 - 19- 2) reset (ta=-40c ~85c, avdd=dvdd=3.0~3.6v; dvdd18=1.7~1.9v) parameter symbol min typ max unit initrstn ( note 33 ) trst 600 ns pckrstn trst 600 ns padrstn trst 600 ns pdsprstn trst 600 ns psrcrstn trst 600 ns note 33. the initrstn pin must be ?l? when power-up the ak7782. 3) audio interface 3-1) sdin1~ sdin7, sdout1~ sdout7 and sdouta1 (supports up to fs=96khz) msb, lsb justified and i 2 s compatible format (ta=-40c ~85c, avdd=dvdd=3.0~3.6v, dvdd18=1.7~1.9v, cl=20pf) parameter symbol min typ max unit slave mode ckm[2:0]=2h, 3h, 4h, 5h delay time from bitclki ? ? to lrclki ( note 34 ) tblrd 20 ns delay time from lrclki to bitclki ? ? ( note 34 ) tlrbd 20 ns delay time from lrclki/o to serial data output tlrd 40 ns delay time from bitclki/o to seri al data output tbsod 40 ns serial data input latch setup time tbsids 40 ns serial data input latch hold time tbsidh 40 ns master mode ckm[2:0]=0h, 1h bitclko frequency fbclk 64 fs bitclko duty cycle 50 % delay time from bitclki ? ? to lrclko tmbl -20 40 ns delay time from lrclko to serial data output tlrd 40 ns delay time from bitclko to serial data output tbsod 40 ns serial data input latch setup time tbsids 40 ns serial data input latch hold time tbsidh 40 ns note 34. bitclki edge must not occur at the same time as lrclki edge. 3-2) sdin1 and sdin5 (src1i and src2 i inputs) (supports up to fs=96khz) (ta=-40c ~85c, avdd=dvdd=3.0~3.6v, dvdd18=1.7~1.9v) parameter symbol min typ max unit slave mode delay time from srcbick1 ? ? to srclrck1 ( note 35 ) tblrd 20 ns delay time from srclrck1 to srcbick1 ? ? ( note 35 ) tlrbd 20 ns serial data input latch setup time tbsids 40 ns serial data input latch hold time tbsidh 40 ns note 35. srcbick1 edge must not occur at the same time as srclrck1 edge.
[ak7782] ms1337-e-00-pb 2011/11 - 20- 4) microprocessor interface (ta=-40c ~85c, avdd=dvdd=3.0~3.6v; dvdd18=1.7~1.9v, cl=20pf) ak7782 microprocessor time from rqn ? ? to so hi-z release (iout=360 a) trqhr 600 ns time from rqn ? ? to so hi-z set (iout=360 a) trqhs 600 ns parameter symbol min typ max unit microprocessor interface signal sclk frequency fsclk 2.1 mhz sclk low level width tsclkl 200 ns sclk high level width tsclkh 200 ns microprocessor ak7782 time from pdsprstn, padrstn? ? to rqn? ? trew 500 ns time from rqn? ? to pdsprstn, padrstn? ? twre 500 ns rqn high level width twrqh 500 ns time from rqn? ? to sclk? ? twsc 500 ns time from sclk? ? to rqn? ? tscw 800 ns si latch setup time tsis 200 ns si latch hold time tsih 200 ns delay time from sclk ? ? to so output tsos 200 ns delay time from sclk ? ? to so output tsoh 200 ns
[ak7782] ms1337-e-00-pb 2011/11 - 21- 5) i 2 c-bus interface (ta=-40c ~85c, avdd=dvdd=3.0~3.6v, dvdd18=1.7~1.9v) parameter symbol min typ max unit i 2 c timing scl clock frequency fscl 400 khz bus free time between transmissions tbuf 1.3 s start condition hold time (prior to first clock pulse) thd:sta 0.6 s clock low time tlow 1.3 s clock high time thigh 0.6 s setup time for repeated start condition tsu:sta 0.6 s sda hold time from scl falling thd:dat 0 0.9 s sda setup time from scl rising tsu:dat 0.1 s rise time of both sda and scl lines tr 0.3 s fall time of both sda and scl lines tf 0.3 s setup time for stop condition tsu:sto 0.6 s pulse width of spike noise suppressed by input filter tsp 0 50 ns capacitive load on bus cb 400 pf note 36. i 2 c-bus is a trademark of nxp b.v.
[ak7782] ms1337-e-00-pb 2011/11 - 22- timing diagram 1) system clock figure 3. system clock 2) reset figure 4. reset tbclkl tbclkh 1/fbclk 1/fbclk vih vil bitclki srcbick tbclk=1/fbclk 1/fxti 1/fxti vih vil xti txti=1/fxti 1/fs 1/fs vih vil lrclki srclrck ts=1/fs vil trst initrstn padrstn pckrstn pdsprstn psrcrstn
[ak7782] ms1337-e-00-pb 2011/11 - 23- 3) audio interface figure 5. standard / i 2 c compatible format figure 6. src tbsidh tbsids tbsod tlrd tblrd tlrbd 50%dvdd 50%dvdd 50%dvdd 50%dvdd lrclki bitclki sdout * sdin * sdin * =sdin1, sdin2, sdin3, sdin4, sdin5, sdin6, sdin7 lrclko bitclko tmb tmbl sdout * =sdout1, sdout2, sdout3, sdout4, sdout5, sdout6, sdout7, sdouta1 tbsidh tbsids tblrd tlrbd 50%dvdd 50%dvdd 50%dvdd srclrck srclrck2 srcbick srcbick2 srci= sdin1,sdin5
[ak7782] ms1337-e-00-pb 2011/11 - 24- tsclkh tsclkl 1/fsclk 1/fsclk 4) microprocessor interface figure 7. microproces sor interface signal figure 8. microprocessor ak7782 figure 9. ak7782 microprocessor note 37. the timing diagram during run state is identical except pdsprstn and pasrstn are ?h?. rqn vih vil sclk vih vil twre padrstn rqn vil twrqh trew tsis tsih si vih vil vih twsc sclk tscw tscw twsc vil vih vil pdsprstn sclk vil vih tsos tsoh so vih vil
[ak7782] ms1337-e-00-pb 2011/11 - 25- figure 10. so output timing 5) i 2 c-bus interface figure 11. i 2 c-bus interface vih vil trqhr trqhs rqn so hi-z thigh scl sda vih tlow tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil vih vil tsp
[ak7782] ms1337-e-00-pb 2011/11 - 26- package 100-pin lqfp (unit: mm) package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatment : solder (pb free) plate 16.0 14.0 50 51 75 76 100 1 25 26 0.22 0.05 0.10 m 0.5 1.0 0.10 0.60 0.15 0 ~10 1.60 max. 0.10 0.05 0.09~0.20 16.0 14.0 s s
[ak7782] ms1337-e-00-pb 2011/11 - 27- marking ak7782vq x xxxxxx 1) pin #1 indication 2) date code: xxxxxxx(7 digits) 3) marking code: ak7782vq date (yy/mm/dd) revision reason page contents 11/11/02 00 first edition revision history
[ak7782] ms1337-e-00-pb 2011/11 - 28- important notice z these products and their specifications ar e subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. z descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. you are fully responsible for the incorporatio n of these external circuits, application circuits, software and other related information in the design of your equipments. akm assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein . akm assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. z any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor auth orized for use as critical components note1 ) in any safety, life support, or other hazard related device or system note2 ) , and akm assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akm. as used here: note1 ) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2 ) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm products, who distri butes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification. thank you for your access to akm product information. more detail product information is available, please contact our sales office or authorized distributors.

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