sy89809al 3.3v lvpecl/hstl to hstl 1:9 high- performance clock driver with lvttl clock select and enable precision edge is a register ed trademark of micrel, inc. micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 ( 408 ) 944-0800 ? fax + 1 (408) 474-1000 ? http://www.micrel.com july 2010 m9999-070110 hbwhelp@micrel.com or (408) 955-1690 general description the sy89809al is a high-performance bus clock driver with nine differential high-speed transceiver logic (hstl) output pairs. the part is designed for use in low-voltage (3.3v/1.8v) applications, which require a large number of outputs to drive precisely aligned, ultra-low skew signals to their destination. the input is multiplexed from either hstl or low-voltage positive-emitter-coupled logic (lvpecl) by the clk_sel pin. the output enable (oe) is synchronous so that t he outputs will only be enabled/disabled when they are already in the low state. this avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. the sy89809al features low pin-to-pin skew (15ps typical) and low part-to-part skew (100ps typical). the sy89809al is available in a single space-saving package, enabling a lower overall cost solution. datasheets and support documentation can be found on micrel?s web site at: www.micrel.com . block diagram precision edge ? features ? 3.3v core supply, 1.8v output supply for reduced power ? lvpecl and hstl inputs ? nine differential hstl (low-voltage swing) output pairs ? hstl outputs drive 50 ? -to-ground with no offset voltage ? 750mhz maximum clock frequency ? low part-to-part skew (100ps typical) ? low pin-to-pin skew (15ps typical) ? available in 32-pin tqfp applications ? high-performance pcs ? workstations ? parallel processor-based systems ? other high-performance computing ? communications level direction signal hstl input hstl_clk, /hstl_clk hstl output q0 ? q8, /q0 ? /q8 lvpecl input lvpecl_clk, /lvpecl_clk lvcmos/lvttl input clk_sel, oe table 1. signal groups oe (1) clk_sel q0 ? q8 /q0 ? /q8 0 0 low high 0 1 low high 1 0 hstl_clk /hstl_clk 1 1 lvpecl_clk /lvpecl_clk table 2. truth table note: 1. the oe (output enable) signal is synchronized with the low level of the hstl_clk and lvpecl_clk signal.
micrel, inc. sy89809al july 2010 2 m9999-070110 hbwhelp@micrel.com or (408) 955-1690 ordering information (1) part number package type operating range package marking lead finish sy89809altz (3) t32-1 commercial sy89809altz with pb-free bar-line indicator matte-sn pb-free SY89809ALTZTR (2, 3) t32-1 commercial sy89809altz with pb-free bar-line indicator matte-sn pb-free notes: 1. contact factory for die availability. dice are guaranteed at t a = 25c, dc electricals only. 2. tape and reel. 3. pb-free package is recommended for new designs. pin configuration 32-pin tqfp (t32-1) pin description pin number pin name type pin function 2, 3 hstl_clk, /hstl_clk hstl input differential clock input selected by clk_sel. can be left floating if not selected. floating input, if selected, produces a low at hstl_clk and a high at /hstl_clk. hstl input signal requires external termination 50 ? -to- ground. 5, 6 lvpecl_clk, /lvpecl_clk lvpecl input differential clock input selected by clk_sel. can be left floating if not selected. floating input, if selected, produces a low at lvpecl_clk and a high at /lvpecl_clk. non- inverted input has a 75k ? pull-down. inverted input has a 75k ? pull-down and a 37.5k ? pull-up. 4 clk_sel lvttl input selected hstl_clk input when low and lvpecl_clk output when high. 37.5k ? pull-up. 8 oe lvttl input enable input synchronized internally to prevent glitching of the q0-q8 and /q0-/q8 outputs. oe high-to-low transiti on ensures outputs remain disabled during the next clock cycle. oe low-to-high transition enables normal operation of the next input clock. 37.5k ? pull-up. 31, 29, 27, 23, 21, 19, 15, 13, 11 q0 ? q8 hstl output differential clock outputs from hstl_clk when clk_sel = low and and from lvpecl outputs when clk_sel = high. hstl outputs must be terminated with 50 ? to gnd. q0-q8 outputs are st atic low when oe = low. unused output pairs may be left floating.
micrel, inc. sy89809al july 2010 3 m9999-070110 hbwhelp@micrel.com or (408) 955-1690 pin description (continued) pin number pin name type pin function 30, 28, 26, 22, 20, 18, 14, 12, 10 /q0 ? /q8 hstl output differential clock outputs from hst l_clk when clk_sel = low and from lvpecl outputs when clk_sel = h igh. hstl outputs must be terminated with 50 ? to gnd. /q0-/q8 outputs are static high when oe = low. unused output pairs may be left floating. 1 vcci vcc core power core v cc connected to 3.3v supply. bypass with 0.1f in parallel with 0.01f low esr capacitors as close to v cci pin as possible. 9, 16, 17, 24, 25, 32 vcco vcc output power output buffer vcc connected to 1.8v supply. bypass with 0.1f in parallel with 0.01f low esr capacitors as close to v cco pins as possible. all v cco pins should be connected together on the pcb. 7 gnd ground ground.
micrel, inc. sy89809al july 2010 4 m9999-070110 hbwhelp@micrel.com or (408) 955-1690 absolute maximum ratings (1) input voltage (v in ) ........................................... ?0.5v to v cci v cc pin potential to ground pin (v cci , v cco ) ............................................ ?0.5v to +4.0v output current (i out ) ............................................................ continuous............................................................50ma surge ..................................................................100ma lead temperature (solde ring, 20sec .)....................... 260c storage temperature (t s ) .........................?65c to +150c operating ratings (2) supply voltage (v cci ) ...................................................... +3.0v to +3.6v (v cco )..................................................... +1.6v to +2.0v ambient temperature (t a ) .............................. 0c to +85c package thermal resistance tqfp ( ja ) ?still-ai r.......................................................50c/w ?500lfpm .....................................................42c/w tqfp ( jc ) .........................................................20c/w dc electrical characteristics t a = 0c to +85c, unless otherwise noted. symbol parameter condition min. typ. max. units power supply v cci v cc core 3.0 3.3 3.6 v v cco v cc output 1.6 1.8 2.0 v i cci i cc core 65 90 ma hstl v oh output high voltage (3) 1.0 1.2 v v ol output low voltage (3) 0.1 0.4 v v ih input high voltage v x +0.1 1.6 v v il input low voltage ?0.3 v x ? 0.1 v v x input crossover voltage 0.68 0.9 v i ih input high current ?350 20 a i il input low current ?500 a v ihcmr input high voltage common mode range( differential configuration) 0.6 1.6 v lvpecl v ih input high voltage v cci ? 1.145 v cci ? 0.895 v v il input low voltage v cci ? 1.945 v cci ? 1.695 v i ih input high current ?150 150 a i il input low current ?150 150 a v ihcmr input high voltage common mode range( differential configuration) (4) 1.2 v cci v notes: 1. exceeding the absolute maximum rating may damage the device. 2. the device is not guaranteed to function outside its operating rating. 3. outputs loaded with 50 ? to ground. 4. v ihcmr max varies 1:1 with v cci . the v ihcmr range is referenced to the most positiv e side of the differential input signal.
micrel, inc. sy89809al july 2010 5 m9999-070110 hbwhelp@micrel.com or (408) 955-1690 dc electrical characteristics t a = 0c to +85c, unless otherwise noted. symbol parameter condition min. typ. max. units lvcmos/lvttl v ih input high voltage 2.0 v v il input low voltage 0.8 v i ih input high current ?150 150 a i il input low current ?300 300 a ac electrical characteristics (5) t a = 0c to +85c, unless otherwise noted. 0 25c 85c symbol parameters min. typ. max. min. typ. max. min. typ. max. units v opp differential output voltage f out < 100mhz f out < 500mhz f out < 750mhz 600 600 450 800 700 510 600 600 450 800 700 510 600 600 450 800 700 510 mv t plh t phl propagation delay (differential configuration) lvpecl_clk to q hstl_clk to q 680 690 800 830 930 990 700 700 820 850 950 1000 780 790 920 950 1070 1110 ps t skew pin-to-pin skew (6) part-to-part skew (7) 15 100 25 200 15 100 25 200 15 100 25 200 ps t jitter random clock jitter ( rms) 1.4 3 1.4 3 1.4 3 ps v pp input voltage swing (8) lvpecl hstl 200 200 1900 200 200 1900 200 200 1900 mv t s oe set-up time (9) 0.5 0.5 0.5 ns t h oe hold time 0.5 0.5 0.5 ns t r, t f output rise/fall times (20% to 80%) q, /q 350 600 350 450 600 350 600 ps notes: 5. outputs loaded with 50 ? to ground. airflow 500lfpm. 6. the pin-to-pin skew is defined as the worst-case difference between any two similar delay paths within a single device opera ting at the same voltage and temperature. 7. the part-to-part skew is defined as the absolute worst-case difference between any two delay paths on any two devices operat ing at the same voltage and temperature. 8. v pp is the input voltage swing required to maintain ac characte ristics listed herein. it represents the input voltage swing for cl k or /clk. 9. oe set-up time is defined with respect to the rising edge of the clock. oe high-to-low transition ensures outputs remain dis abled during the next clock cycle.
micrel, inc. sy89809al july 2010 6 m9999-070110 hbwhelp@micrel.com or (408) 955-1690 output waveforms figure 1. 100mhz output waveform figure 2. 500mhz output waveform frequency vs. amplitude 0 100 200 300 400 500 600 700 800 900 0 100 200 300 400 500 600 700 800 900 1000 frequency (mhz) amplitude (mv)
micrel, inc. sy89809al july 2010 7 m9999-070110 hbwhelp@micrel.com or (408) 955-1690 figure 3. output enable timing diagram
micrel, inc. sy89809al july 2010 8 m9999-070110 hbwhelp@micrel.com or (408) 955-1690 package information 32-pin tqfp (t32-1) micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944-0800 fax +1 (408) 474-1000 web http://www.micrel.com the information furnished by micrel in this data sheet is belie ved to be accurate and reliable. however, no responsibility is a ssumed by micrel for its use. micrel reserves the right to change circuitry and specifications at any time without notification to the customer. micrel products are not designed or authori zed for use as components in life support app liances, devices or systems where malfu nction of a product can reasonably be expected to result in pers onal injury. life support devices or system s are devices or systems that (a) are in tended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significan t injury to the user. a purchaser?s use or sale of micrel produc ts for use in life support app liances, devices or systems is a purchaser?s own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 2010 micrel, incorporated.
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