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| 8 bit microcontroller tlcs-870/c series TMP86FS49AIFG
page 2 TMP86FS49AIFG the information contained herein is su bject to change without notice. 021023 _ d toshiba is continually working to improve the qual ity and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fa il due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products , to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that to shiba products are used within specified operating ranges as set forth in the most re cent toshiba products specifications. also, please keep in mind the precautio ns and conditions set forth in the ? handling guide for semiconductor devices, ? or ? toshiba semiconductor reliability handbook ? etc. 021023_a the toshiba products listed in this document are inte nded for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ( ? unintended usage ? ). unintended usage include atomic energy control instruments, airplane or spaceship instruments, tr ansportation instruments, traffic signal instruments, combustion control instruments, medical instrument s, all types of safety devices, etc. unintended usage of toshiba products listed in this document shall be made at the customer's own risk. 021023_b the products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohib ited under any applicable laws and regulations. 060106_q the information contained he rein is presented only as a guide for the applications of our products. no responsibility is assumed by tosh iba for any infringements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of toshiba or others. 021023_c the products described in this document may include products subject to the foreign exchange and foreign trade laws. 021023_f for a discussion of how the reliability of microcontro llers can be predicted, please refer to section 1.3 of the chapter entitled quality and reli ability assurance/hand ling precautions. 030619_s ? 2006 toshiba corporation all rights reserved TMP86FS49AIFG differences among products differences in functions note 1: the products with flash memory ( 86fs49a, 86fs49ai) contain the flash contro l register (flscr) at 0fffh in the dbr area. the products with mask rom or otp and the emulati on chip do not have the flscr register. in these devices, therefore, a program that accesses the flscr register cannot function properly (executes differently as in the case of a flash product). 86ch49 86cm49 86pm49 86cs49 86fs49a 86fs49ai rom 16 kbytes (mask) 32 kbytes (mask) 32 kbytes (otp) 60 kbytes (mask) 60 kbytes (flash) ram 512 bytes 1 kbyte 1 kbyte 2 kbytes 2 kbytes dbr(note1) 128 bytes (flash control register not contained) 128 bytes (flash control register contained) i/o 56 pins high-current port 13 pins (sink open drain) interrupt external: 5 interrupts, internal: 19 interrupts timer/counter 16-bit: 2 channels 8-bit: 4 channels uart 2 channels sio 2 channels i2c 1 channel key-on wake-up 4 channels 10-bit ad converter 16 channels structurer of test pin emulation chip tmp86c949xb package p-qfp64- 1414-0.80a p-qfp64-1414-0.80a p-lqfp64-1010-0.50d p-sdip64-750-1.78 p-qfp64-1414-0.80a p-lqfp64-1010-0.50d ? vdd r in r r without pull down resister without protect diode on the vdd side vdd r in r r vdd without pull down resister TMP86FS49AIFG differences in elect rical characteristics note 1: with the 86cs49, the operating temperature (topr) is -20 c to 85 c when the supply voltage vdd is less than 2.0 v. note 2: with the 86fs49a, the operating temperature (topr) is -20 c to 85 c when the supply voltage vdd is less than 3.0 v. note 3: with the 86fs49a and 86fs49ai, when a program is ex ecuting in the flash memory or when data is being read from the flash memory, the flash memory operates in an intermittent manner causing peak currents in the flash memory momentarily, as shown in figure. in this case, the supply current idd (in normal1, normal2 and slow1 modes) is defined as the sum of the average peak current and mcu current. 86ch49 86cm49 86pm49 86cs49 86fs49a 86fs49ai operat- ing condition (mcu mode) read/ fetch (a) 1.8 v to 5.5 v (-40 to 85 c) (a) 2.0 v to 5.5 v (-40 to 85 c) (b) 1.8 v to 2.0 v (-20 to 85 c) (a) 3.0 v to 5.5 v (-40 to 85 c) (b) 2.7 v to 3.0 v (-20 to 85 c) (a) 3.0 v to 5.5 v (-40 to 85 c) erase/ program ? ? (a) 4.5 v to 5.5 v (-10 to 40 c) operating condition (serial prom mode) ?? (a) 4.5 v to 5.5 v (-10 to 40 c) operating current operating current varies with each product. for details, refer to the datasheet (electrical char acteristics) of each product. (note 3) 5.5 4.5 3.0 3.6 2.7 1.8 0.030 0.034 1 4.2 8 16 [mhz] [v] (a) 5.5 4.5 3.0 3.6 2.7 1.8 0.030 0.034 1 4.2 8 16 [mhz] [v] 2.0 (a) (b) (note 1) 5.5 4.5 3.0 3.6 2.7 1.8 0.030 0.034 1 4.2 8 16 (a) (b) (note 2) [mhz] [v] 5.5 4.5 3.0 3.6 1.8 0.030 0.034 1 4.2 8 16 (a) [mhz] [v] 5.5 4.5 3.0 3.6 2.7 1.8 0.030 0.034 1 4.2 8 16 [mhz] [v] (a) 5.5 4.5 3.0 3.6 2.7 1.8 0.030 0.034 2 4.2 8 16 [mhz] [v] (a) TMP86FS49AIFG n program counter (pc) n+1 n+2 n+3 1 machine cycle (4/fc or 4/fs) mcu current i [ma] ddp-p typ. current momentary flash current max. current sum of average momentary flash current and mcu curren t intermittent operat ion of flash memory TMP86FS49AIFG revision history date revision 2007/1/31 1 first release i table of contents differences among products TMP86FS49AIFG 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 pin names and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2. operational description 2.1 cpu core functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.1 memory address map ............................................................................................................................... 9 2.1.2 program memory (flash) .......................................................................................................................... 9 2.1.3 data memory (ram) ............................................................................................................................... .. 9 2.2 system clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.1 clock generator ............................................................................................................................... ....... 10 2.2.2 timing generator ............................................................................................................................... ..... 12 2.2.2.1 configuration of timing generator 2.2.2.2 machine cycle 2.2.3 operation mode control circuit .............................................................................................................. 13 2.2.3.1 single-clock mode 2.2.3.2 dual-clock mode 2.2.3.3 stop mode 2.2.4 operating mode control ......................................................................................................................... 18 2.2.4.1 stop mode 2.2.4.2 idle1/2 mode and sleep1/2 mode 2.2.4.3 idle0 and sleep0 modes (idle0, sleep0) 2.2.4.4 slow mode 2.3 reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.3.1 external reset input ............................................................................................................................... 31 2.3.2 address trap reset ............................................................................................................................... ... 32 2.3.3 watchdog timer reset .............................................................................................................................. 32 2.3.4 system clock reset ............................................................................................................................... ... 32 3. interrupt control circuit 3.1 interrupt latches (il23 to il2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.2 interrupt enable register (eir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.2.1 interrupt master enable flag (imf) .......................................................................................................... 36 3.2.2 individual interrupt enable flags (ef23 to ef4) ...................................................................................... 37 note 3: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.3 interrupt sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.1 interrupt acceptance processing is packaged as follows. ....................................................................... 39 3.3.2 saving/restoring general-purpose registers ............................................................................................ 40 3.3.2.1 using push and pop instructions ii 3.3.2.2 using data transfer instructions 3.3.3 interrupt return ............................................................................................................................... ......... 41 3.4 software interrupt (intsw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.4.1 address error detection .......................................................................................................................... 42 3.4.2 debugging ............................................................................................................................... ............... 42 3.5 undefined instruction interrupt (intundef) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.6 address trap interrupt (intatrap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.7 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4. special function r egister (sfr) 4.1 sfr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.2 dbr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5. i/o ports 5.1 port p0 (p07 to p00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.2 port p1 (p17 to p10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.3 port p2 (p22 to p20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.4 port p3 (p37 to p30) (large current port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.5 port p4 (p47 to p40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.6 port p5 (p54 to p50) (large current port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.7 port p6 (p67 to p60) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.8 port p7 (p77 to p70) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6. watchdog timer (wdt) 6.1 watchdog timer configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.2 watchdog timer control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.2.1 malfunction detection methods using the watchdog timer ................................................................... 66 6.2.2 watchdog timer enable ......................................................................................................................... 67 6.2.3 watchdog timer disable ........................................................................................................................ 68 6.2.4 watchdog timer interrupt (intwdt) ...................................................................................................... 68 6.2.5 watchdog timer reset ........................................................................................................................... 69 6.3 address trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.3.1 selection of address trap in internal ram (atas) ................................................................................ 70 6.3.2 selection of operation at address trap (atout) .................................................................................. 70 6.3.3 address trap interrupt (intatrap) ....................................................................................................... 70 6.3.4 address trap reset ............................................................................................................................... . 71 7. time base timer (tbt) 7.1 time base timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.1.1 configuration ............................................................................................................................... ........... 73 7.1.2 control ............................................................................................................................... ..................... 73 7.1.3 function ............................................................................................................................... ................... 74 7.2 divider output (dvo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.2.1 configuration ............................................................................................................................... ........... 75 7.2.2 control ............................................................................................................................... ..................... 75 iii 8. 16-bit timercounter 1 (tc1) 8.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 8.2 timercounter control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 8.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 8.3.1 timer mode ............................................................................................................................... .............. 80 8.3.2 external trigger timer mode .................................................................................................................. 82 8.3.3 event counter mode ............................................................................................................................... 84 8.3.4 window mode ............................................................................................................................... .......... 85 8.3.5 pulse width measurement mode ............................................................................................................ 86 8.3.6 programmable pulse generate (ppg) output mode ............................................................................. 89 9. 16-bit timer/counter2 (tc2) 9.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 9.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 9.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 9.3.1 timer mode ............................................................................................................................... .............. 95 9.3.2 event counter mode ............................................................................................................................... . 97 9.3.3 window mode ............................................................................................................................... .......... 97 10. 8-bit timercounter (tc3, tc4) 10.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 10.2 timercounter control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 10.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 10.3.1 8-bit timer mode (tc3 and 4) ............................................................................................................ 105 10.3.2 8-bit event counter mode (tc3, 4) .................................................................................................... 106 10.3.3 8-bit programmable divider output (pdo) mode (tc3, 4) ................................................................. 106 10.3.4 8-bit pulse width modulation (pwm) output mode (tc3, 4) .............................................................. 109 10.3.5 16-bit timer mode (tc3 and 4) .......................................................................................................... 111 10.3.6 16-bit event counter mode (tc3 and 4) ............................................................................................ 112 10.3.7 16-bit pulse width modulation (pwm) output mode (tc3 and 4) ...................................................... 112 10.3.8 16-bit programmable pulse generate (ppg) output mode (tc3 and 4) ........................................... 115 10.3.9 warm-up counter mode ..................................................................................................................... 117 10.3.9.1 low-frequency warm-up counter mode (normal1 normal2 slow2 slow1) 10.3.9.2 high-frequency warm-up counter mode (slow1 slow2 normal2 normal1) 11. 8-bit timercounter (tc5, tc6) 11.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 11.2 timercounter control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 11.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 11.3.1 8-bit timer mode (tc5 and 6) ............................................................................................................ 125 11.3.2 8-bit event counter mode (tc5, 6) .................................................................................................... 126 11.3.3 8-bit programmable divider output (pdo) mode (tc5, 6) ................................................................. 126 11.3.4 8-bit pulse width modulation (pwm) output mode (tc5, 6) .............................................................. 129 11.3.5 16-bit timer mode (tc5 and 6) .......................................................................................................... 131 11.3.6 16-bit event counter mode (tc5 and 6) ............................................................................................ 132 11.3.7 16-bit pulse width modulation (pwm) output mode (tc5 and 6) ...................................................... 132 11.3.8 16-bit programmable pulse generate (ppg) output mode (tc5 and 6) ........................................... 135 11.3.9 warm-up counter mode ..................................................................................................................... 137 11.3.9.1 low-frequency warm-up counter mode iv (normal1 normal2 slow2 slow1) 11.3.9.2 high-frequency warm-up counter mode (slow1 slow2 normal2 normal1) 12. asynchronous serial interface (uart1 ) 12.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 12.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 12.3 transfer data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 12.4 transfer rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 12.5 data sampling method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 12.6 stop bit length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 12.7 parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 12.8 transmit/receive operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 12.8.1 data transmit operation .................................................................................................................... 144 12.8.2 data receive operation ..................................................................................................................... 144 12.9 status flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 12.9.1 parity error ............................................................................................................................... ........... 145 12.9.2 framing error ............................................................................................................................... ....... 145 12.9.3 overrun error ............................................................................................................................... ....... 145 12.9.4 receive data buffer full ..................................................................................................................... 146 12.9.5 transmit data buffer empty ............................................................................................................... 146 12.9.6 transmit end flag .............................................................................................................................. 147 13. asynchronous serial interface (uart2 ) 13.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 13.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 13.3 transfer data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 13.4 transfer rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 13.5 data sampling method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 13.6 stop bit length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 13.7 parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 13.8 transmit/receive operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 13.8.1 data transmit operation .................................................................................................................... 154 13.8.2 data receive operation ..................................................................................................................... 154 13.9 status flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 13.9.1 parity error ............................................................................................................................... ........... 155 13.9.2 framing error ............................................................................................................................... ....... 155 13.9.3 overrun error ............................................................................................................................... ....... 155 13.9.4 receive data buffer full ..................................................................................................................... 156 13.9.5 transmit data buffer empty ............................................................................................................... 156 13.9.6 transmit end flag .............................................................................................................................. 157 14. synchronous serial interface (sio1) 14.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 14.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 14.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 14.3.1 serial clock ............................................................................................................................... .......... 162 14.3.1.1 clock source 14.3.1.2 shift edge 14.3.2 transfer bit direction ........................................................................................................................... 164 14.3.2.1 transmit mode v 14.3.2.2 receive mode 14.3.2.3 transmit/receive mode 14.3.3 transfer modes ............................................................................................................................... .... 165 14.3.3.1 transmit mode 14.3.3.2 receive mode 14.3.3.3 transmit/receive mode 15. synchronous serial interface (sio2) 15.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 15.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 15.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 15.3.1 serial clock ............................................................................................................................... .......... 180 15.3.1.1 clock source 15.3.1.2 shift edge 15.3.2 transfer bit direction ........................................................................................................................... 182 15.3.2.1 transmit mode 15.3.2.2 receive mode 15.3.2.3 transmit/receive mode 15.3.3 transfer modes ............................................................................................................................... .... 183 15.3.3.1 transmit mode 15.3.3.2 receive mode 15.3.3.3 transmit/receive mode 16. serial bus interface(i2c bus) ver.-d (sbi) 16.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 16.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 16.3 software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 16.4 the data format in the i2c bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 16.5 i2c bus control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 16.5.1 acknowledgement mode specification ................................................................................................ 199 16.5.1.1 acknowledgment mode (ack = ?1?) 16.5.1.2 non-acknowledgment mode (ack = ?0?) 16.5.2 number of transfer bits ....................................................................................................................... 200 16.5.3 serial clock ............................................................................................................................... .......... 200 16.5.3.1 clock source 16.5.3.2 clock synchronization 16.5.4 slave address and address re cognition mode specification ............................................................... 201 16.5.5 master/slave selection ........................................................................................................................ 201 16.5.6 transmitter/receiver selection ............................................................................................................. 201 16.5.7 start/stop condition generation ........................................................................................................... 202 16.5.8 interrupt service request and cancel ................................................................................................... 202 16.5.9 setting of i2c bus mode ..................................................................................................................... 203 16.5.10 arbitration lost detection monitor ...................................................................................................... 203 16.5.11 slave address match detection monitor ............................................................................................ 204 16.5.12 general call detection monitor .................................................................................................. 204 16.5.13 last received bit monitor ................................................................................................................... 204 16.6 data transfer of i2c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 16.6.1 device initialization ............................................................................................................................. 2 05 16.6.2 start condition and slave address generation ..................................................................................... 205 16.6.3 1-word data transfer ............................................................................................................................ 20 5 16.6.3.1 when the mst is ?1? (master mode) 16.6.3.2 when the mst is ?0? (slave mode) 16.6.4 stop condition generation ................................................................................................................... 208 16.6.5 restart ............................................................................................................................... ................. 209 17. 10-bit ad converter (adc) 17.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 vi 17.2 register configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 17.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 17.3.1 software start mode ........................................................................................................................... 215 17.3.2 repeat mode ............................................................................................................................... ....... 215 17.3.3 register setting ............................................................................................................................... . 216 17.4 stop/slow modes during ad conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 17.5 analog input voltage and ad conversion result . . . . . . . . . . . . . . . . . . . . . . . 218 17.6 precautions about ad converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 17.6.1 restrictions for ad conversion interrupt (intadc) usage ................................................................. 219 17.6.2 analog input pin voltage range ........................................................................................................... 219 17.6.3 analog input shared pins .................................................................................................................... 219 17.6.4 noise countermeasure ....................................................................................................................... 219 18. key-on wakeup (kwu) 18.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 18.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 18.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 19. flash memory 19.1 flash memory control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 19.1.1 flash memory command sequence execution control (flscr vii 20.6.4 flash memory sum output mode (operation command: 90h) ......................................................... 248 20.6.5 product id code output mode (operation command: c0h) .............................................................. 249 20.6.6 flash memory status output mode (operation command: c3h) ...................................................... 251 20.6.7 flash memory read protection setting mode (operation command: fah) ...................................... 252 20.7 error code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 20.8 checksum (sum) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 20.8.1 calculation method ............................................................................................................................. 2 54 20.8.2 calculation data ............................................................................................................................... ... 255 20.9 intel hex format (binary) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 20.10 passwords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 20.10.1 password string ............................................................................................................................... . 257 20.10.2 handling of password error .............................................................................................................. 257 20.10.3 password management during program development .................................................................... 257 20.11 product id code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 20.12 flash memory status code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 20.13 specifying the erasure area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 20.14 flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 20.15 uart timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 21. input/output circuit 21.1 control pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 21.2 input/output ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 22. electrical characteristics 22.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 22.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 22.2.1 mcu mode (flash programming or erasing) ..................................................................................... 268 22.2.2 mcu mode (except flash progra mming or erasing) ......................................................................... 268 22.2.3 serial prom mode ............................................................................................................................. 2 69 22.3 dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 22.4 ad characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 22.5 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 22.6 flash characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 22.6.1 write/retention characteristics .......................................................................................................... 272 22.7 recommended oscillating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 22.8 handling precaution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 23. reference evaluation information 24. package dimensions this is a technical docu ment that describes the operat ing functions and electrical specifications of the 8-bit microc ontroller series tlcs-870/c (lsi). viii page 1 060116ebp TMP86FS49AIFG cmos 8-bit microcontroller ? the information contained herein is subject to change without notice. 021023_d ? toshiba is continually working to improve the quality and reli ability of its products. neverthel ess, semiconductor devices in general can malfunction or fail due to their inherent el ectrical sensitivity and vul nerability to physical stre ss. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of sa fety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, pleas e ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling gui de for semiconductor devices,? or ?toshiba se miconductor reliability handbook? etc. 021023_a ? the toshiba products listed in this document are intended for usage in general electronics applic ations (computer, personal eq uip- ment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neithe r intended nor warranted for usage in equipment that requires extr aordinarily high quality and/or re liability or a malfunctionor failure of which may cause loss of human life or bod ily injury (?unintended usage?). unintended us age include atomic energy control instru ments, airplane or spaceship instruments, transporta tion instruments, traffic signal instrume nts, combustion control instruments, medi cal instru- ments, all types of safety dev ices, etc. unintended usage of toshiba products li sted in this document shall be made at the cust omer's own risk. 021023_b ? the products described in this document shall not be used or embedded to any downstream products of which manufacture, use and /or sale are prohibited under any appl icable laws and regulations. 060106_q ? the information contained herein is present ed only as a guide for the applications of our products. no responsibility is assum ed by toshiba for any infringements of patents or other rights of the th ird parties which may result from its use. no license is gran ted by impli- cation or otherwise under any patent or patent rights of toshiba or others. 021023_c ? the products described in this document are subjec t to the foreign exchange and foreign trade laws. 021023_e ? for a discussion of how the reliability of microcontrollers c an be predicted, please refer to section 1.3 of the chapter entit led quality and reliability assurance/h andling precautions. 030619_s this product uses the super flash ? technology under the licence of silicon storage technology, inc. super flash ? is registered trademark of silicon storage technology, inc. TMP86FS49AIFG the TMP86FS49AIFG is a single-chip 8-bit high-speed and high-functionality microcomputer incorporating 61440 bytes of flash memory. it is pin-compatible wi th the tmp86ch49/cm49/cs49 (mask rom version). the TMP86FS49AIFG can realize operations equivalent to those of the tmp86ch49/cm49/cs49 by programming the on-chip flash memory. 1.1 features 1. 8-bit single chip microcomputer tlcs-870/c series - instruction execution time : 0.25 s (at 16 mhz) 122 s (at 32.768 khz) - 132 types & 731 basic instructions 2. 24interrupt sources (external : 5 internal : 19) 3. input / output ports (56 pins) large current output: 13pins (typ. 20ma), led direct drive 4. watchdog timer 5. prescaler - time base timer - divider output function 6. 16-bit timer counter: 1 ch - timer, external trigger, wi ndow, pulse width measurement, event counter, programmable pulse generate (ppg) modes 7. 16-bit timer counter: 1 ch - timer, event counter, window modes product no. rom (flash) ram package mask rom mcu emulation chip TMP86FS49AIFG 61440 bytes 2048 bytes qfp64-p-1414-0.80a tmp86ch49/cm49/ cs49 tmp86c949xb page 2 1.1 features TMP86FS49AIFG 8. 8-bit timer counter : 4 ch - timer, event counter, programmable divider output (pdo), pulse width modulation (pwm) output, programmable pulse generation (ppg) modes 9. 8-bit uart : 2 ch 10. high-speed sio: 2ch 11. serial bus interface(i 2 c bus): 1ch 12. 10-bit successive approximation type ad converter - analog input: 16 ch 13. key-on wakeup : 4 ch 14. clock operation single clock mode dual clock mode 15. low power consumption operation stop mode: oscillation stops. (battery/capacitor back-up.) slow1 mode: low power consumption operation usin g low-frequency clock.(high-frequency clock stop.) slow2 mode: low power consumption operation usin g low-frequency clock.(high-frequency clock oscillate.) idle0 mode: cpu stops, and only the time-based-tim er(tbt) on peripherals operate using high fre- quency clock. release by falling edge of th e source clock which is set by tbtcr page 3 TMP86FS49AIFG 1.2 pin assignment figure 1-1 pin assignment vss xout test vdd (xtin) p21 (xtout) p22 reset ( stop / int5 ) p20 ( int0 ) p00 (txd1) p02 (si1) p04 (int1) p03 (so1) p05 ( sck1 ) p06 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 p65(ain5/stop1) p67(ain7/stop3) p70(ain8) p72(ain10) p71(ain9) p74(ain12) p73(ain11) p66(ain6/stop2) p14 (tc4/ pdo4/pwm4/ppg4 ) p13 (tc3/ pdo3/pwm3 ) p12 ( ppg ) p11 ( dvo ) p10 (tc1) p47 p46 ( sck2 ) p45 (so2) (boot/rxd1) p01 xin p07(int2) avdd p60(ain0) p61(ain1) p64(ain4/stop0) p62(ain2) varef p63(ain3) p44 (si2) p43 p42 (txd2) p41 (rxd2) p40 p77 (ain15) p76 (ain14) p75 (ain13) (int3/tc2) p15 ( pdo5/pwm5 /tc5) p16 ( pdo6/pwm6/ppg6 /tc6) p17 (scl) p50 (sda) p51 p52 p53 p54 p30 p31 p32 p33 p34 p35 p36 p37 page 4 1.3 block diagram TMP86FS49AIFG 1.3 block diagram figure 1-2 block diagram page 5 TMP86FS49AIFG 1.4 pin names and functions the TMP86FS49AIFG has mcu mode, parallel prom mode , and serial prom mode. table 1-1 shows the pin functions in mcu mode. the serial prom mode is explained later in a separate chapter. table 1-1 pin names and functions(1/3) pin name pin number input/output functions p07 int2 17 io i port07 external interrupt 2 input p06 sck1 16 io io port06 serial clock input/output 1 p05 so1 15 io o port05 serial data output 1 p04 si1 14 io i port04 serial data input 1 p03 int1 13 io i port03 external interrupt 1 input p02 txd1 12 io o port02 uart data output 1 p01 rxd1 boot 11 io i i port01 uart data input 1 serial prom mode control input p00 int0 10 io i port00 external interrupt 0 input p17 tc6 pdo6/pwm6/ppg6 51 io i o port17 tc6 input pdo6/pwm6/ppg6 output p16 tc5 pdo5/pwm5 50 io i o port16 tc5 input pdo5/pwm5 output p15 tc2 int3 49 io i i port15 tc2 input external interrupt 3 input p14 tc4 pdo4/pwm4/ppg4 48 io i o port14 tc4 input pdo4/pwm4/ppg4 output p13 tc3 pdo3/pwm3 47 io i o port13 tc3 input pdo3/pwm3 output p12 ppg 46 io o port12 ppg output p11 dvo 45 io o port11 divider output p10 tc1 44 io i port10 tc1 input p22 xtout 7 io o port22 resonator connecting pins(32.768 khz) for inputting external clock p21 xtin 6 io i port21 resonator connecting pins(32.768 khz) for inputting external clock page 6 1.4 pin names and functions TMP86FS49AIFG p20 int5 stop 9 io i i port20 external interrupt 5 input stop mode release signal input p37 64 io port37 p36 63 io port36 p35 62 io port35 p34 61 io port34 p33 60 io port33 p32 59 io port32 p31 58 io port31 p30 57 io port30 p47 43 io port47 p46 sck2 42 io io port46 serial clock input/output 2 p45 so2 41 io o port45 serial data output 2 p44 si2 40 io i port44 serial data input 2 p43 39 io port43 p42 txd2 38 io o port42 uart data output 2 p41 rxd2 37 io i port41 uart data input 2 p40 36 io port40 p54 56 io port54 p53 55 io port53 p52 54 io port52 p51 sda 53 io io port51 i2c bus data p50 scl 52 io io port50 i2c bus clock p67 ain7 stop3 27 io i i port67 analog input7 stop3 input p66 ain6 stop2 26 io i i port66 analog input6 stop2 input p65 ain5 stop1 25 io i i port65 analog input5 stop1 input p64 ain4 stop0 24 io i i port64 analog input4 stop0 input table 1-1 pin names and functions(2/3) pin name pin number input/output functions page 7 TMP86FS49AIFG p63 ain3 23 io i port63 analog input3 p62 ain2 22 io i port62 analog input2 p61 ain1 21 io i port61 analog input1 p60 ain0 20 io i port60 analog input0 p77 ain15 35 io i port77 analog input15 p76 ain14 34 io i port76 analog input14 p75 ain13 33 io i port75 analog input13 p74 ain12 32 io i port74 analog input12 p73 ain11 31 io i port73 analog input11 p72 ain10 30 io i port72 analog input10 p71 ain9 29 io i port71 analog input9 p70 ain8 28 io i port70 analog input8 xin 2 i resonator connecting pins for high-frequency clock xout 3 o resonator connecting pins for high-frequency clock reset 8 i reset signal test 4 i test pin for out-going test. normally, be fixed to low. varef 18 i analog base voltage input pin for a/d conversion avdd 19 i analog power supply vdd 5 i +5v vss 1 i 0(gnd) table 1-1 pin names and functions(3/3) pin name pin number input/output functions page 8 1.4 pin names and functions TMP86FS49AIFG page 9 TMP86FS49AIFG 2. operational description 2.1 cpu core functions the cpu core consists of a cpu, a system cl ock controller, and an interrupt controller. this section provides a description of the cpu core, the program memory, the data memory, and the reset circuit. 2.1.1 memory address map the TMP86FS49AIFG memory is composed flash, ram, dbr(data buffer register) and sfr(special function register). they are al l mapped in 64-kbyte address space. figure 2-1 shows the TMP86FS49AIFG memory address map. figure 2-1 memory address map 2.1.2 program memory (flash) the TMP86FS49AIFG has a 61440 bytes (address 1000h to ffffh) of program memory (flash ). 2.1.3 data memory (ram) the TMP86FS49AIFG has 2048 bytes (address 0040h to 083fh) of internal ram. the first 192 bytes (0040h to 00ffh) of the internal ra m are located in the direct area; inst ructions with shorten operations are available against such an area. sfr 0000 h 64 bytes sfr: ram: special function register includes: i/o ports peripheral control registers peripheral status registers system control registers program status word random access memory includes: data memory stack 003f h ram 0040 h 2048 bytes 083f h dbr 0f80 h 128 bytes dbr: data buffer register includes: peripheral control registers peripheral status registers 0fff h 1000 h flash: program memory flash 61440 bytes ffb0 h vector table for interrupts (16 bytes) ffbf h ffc0 h vector table for vector call instructions (32 bytes) ffdf h ffe0 h vector table for interrupts (32 bytes) ffff h page 10 2. operational description 2.2 system clock controller TMP86FS49AIFG the data memory contents become un stable when the power supply is turned on; therefore, the data memory should be initialized by an initialization routine. 2.2 system clock controller the system clock controller consists of a clock generator, a timing generator, and a standby controller. figure 2-2 syst em colck control 2.2.1 clock generator the clock generator generates the basic clock which pr ovides the system clocks supplied to the cpu core and peripheral hardware. it contains two oscillation ci rcuits: one for the high-frequency clock and one for the low-frequency clock. power consumption can be reduced by switching of the standby controller to low-power operation based on the low-frequency clock. the high-frequency (fc) clock and low-frequency (fs) clock can easily be obtained by connecting a resonator between the xin/xout and xtin/xtout pins respectively. clock input from an exte rnal oscillator is also possible. in this case, external clock is applied to xin/xtin pin with xout/xtout pin not connected. example :clears ram to ?00h?. (TMP86FS49AIFG) ld hl, 0040h ; start address setup ld a, h ; initial value (00h) setup ld bc, 07ffh sramclr: ld (hl), a inc hl dec bc jrs f, sramclr tbtcr syscr2 syscr1 xin xout xtin xtout fc 0036 h 0038 h 0039 h fs timing generator control register timing generator standby controller system clocks clock generator control high-frequency clock oscillator low-frequency clock oscillator clock generator system control registers page 11 TMP86FS49AIFG figure 2-3 examples of resonator connection note:the function to monitor the basic clock directly at external is not provided for hardware, however, with dis- abling all interrupts and watchdog timers, the oscillation frequency can be adjusted by monitoring the pulse which the fixed frequency is outputted to the port by the program. the system to require the adjustment of the oscilla tion frequency should create the program for the adjust- ment in advance. xout xin (open) xout xin xtout xtin (open) xtout xtin (a) crystal/ceramic resonator (b) external oscillator (c) crystal (d) external oscillator high-frequency clock low-frequency clock page 12 2. operational description 2.2 system clock controller TMP86FS49AIFG 2.2.2 timing generator the timing generator generates the various system cloc ks supplied to the cpu core and peripheral hardware from the basic clock (fc or fs). the timing generator provides the following functions. 1. generation of main system clock 2. generation of divider output ( dvo ) pulses 3. generation of source clocks for time base timer 4. generation of source clocks for watchdog timer 5. generation of internal source clocks for timer/counters 6. generation of warm-up clocks for releasing stop mode 2.2.2.1 configuration of timing generator the timing generator consists of a 2-stage prescaler, a 21-stage divider, a main system clock generator, and machine cycle counters. an input clock to the 7th stage of the divider depends on the operating mode, syscr2 page 13 TMP86FS49AIFG note 1: in single clock mode, do not set dv7ck to ?1?. note 2: do not set ?1? on dv7ck while the low-frequency clock is not operated stably. note 3: fc: high-frequency clock [hz], fs : low-frequency clock [hz], *: don?t care note 4: in slow1/2 and sleep1/2 modes, the dv7ck setting is ineffective, and fs is input to the 7th stage of the divider. note 5: when stop mode is entered from normal1/2 mode, the dv 7ck setting is ineffective during the warm-up period after release of stop mode, and the 6th stage of the divider is input to the 7th stage during this period. 2.2.2.2 machine cycle instruction execution and peripheral hardware operat ion are synchronized with the main system clock. the minimum instruction execution uni t is called an ?machine cycle?. th ere are a total of 10 different types of instructions for the tlcs-870/c series: ra nging from 1-cycle instructions which require one machine cycle for execution to 10-cyc le instructions which require 10 machine cycles fo r execution. a machine cycle consists of 4 states (s0 to s3), and each state consists of one main system clock. figure 2-5 machine cycle 2.2.3 operation mode control circuit the operation mode control circuit starts and stops th e oscillation circuits for the high-frequency and low- frequency clocks, and switches the main system clock. there are three operating modes: single clock mode, dual clock mode and stop mode. these modes are cont rolled by the system cont rol registers (syscr1 and syscr2). figure 2-6 shows the operating mode transition diagram. 2.2.3.1 single-clock mode only the oscillation circuit for the high-frequenc y clock is used, and p21 (xtin) and p22 (xtout) pins are used as input/output ports . the main-system clock is obtained from the high-frequency clock. in the single-clock mode, the machine cycle time is 4/fc [s]. (1) normal1 mode in this mode, both the cpu core and on-chip pe ripherals operate using the high-frequency clock. the TMP86FS49AIFG is placed in this mode after reset. timing generator control register tbtcr (0036h) 76543210 (dvoen) (dvock) dv7ck (tbten) (tbtck) (initial value: 0000 0000) dv7ck selection of input to the 7th stage of the divider 0: fc/2 8 [hz] 1: fs r/w main system clock state machine cycle s3 s2 s1 s0 s3 s2 s1 s0 1/fc or 1/fs [s] page 14 2. operational description 2.2 system clock controller TMP86FS49AIFG (2) idle1 mode in this mode, the internal oscillation circuit remains active. the cpu and the watchdog timer are halted; however on-chip peripherals remain active (operate using the high-frequency clock). idle1 mode is started by syscr2 page 15 TMP86FS49AIFG switching back and forth between slow1 and slow2 modes are performed by syscr2 page 16 2. operational description 2.2 system clock controller TMP86FS49AIFG note 1: normal1 and normal2 modes are generically called no rmal; slow1 and slow2 are called slow; idle0, idle1 and idle2 are called idle; sleep0, sleep1 and sleep2 are called sleep. note 2: the mode is released by fa lling edge of tbtcr page 17 TMP86FS49AIFG note 1: always set retm to ?0? when transiting from normal mode to stop mode. always set retm to ?1? when transiting from slow mode to stop mode. note 2: when stop mode is released with reset pin input, a return is made to normal1 regardless of the retm contents. note 3: fc: high-frequency clock [hz], fs : low-frequency clock [hz], *; don?t care note 4: bits 0 and 1 in syscr1 are read as undefined data when a read instruction is executed. note 5: as the hardware becomes stop mode under outen = ?0?, input value is fixed to ?0?; therefore it may cause external interrupt request on account of falling edge. note 6: when the key-on wakeup is used, relm should be set to "1". note 7: port p20 is used as stop pin. therefore, when stop mode is started, outen does not affect to p20, and p20 becomes high-z mode. note 8: the warmig-up time should be set correctly for using oscillator. note 1: a reset is applied if both xen and xten are cleared to ?0?, xen is cleared to ?0? when sysck = ?0?, or xten is cleared to ?0? when sysck = ?1?. note 2: *: don?t care, tg: timing generator note 3: bits 3, 1 and 0 in syscr2 are always read as undefined value. note 4: do not set idle and tghalt to ?1? simultaneously. note 5: because returning from idle0/sleep0 to normal1/slow 1 is executed by the asynchronous internal clock, the period of idle0/sleep0 mode might be shorter than the period setting by tbtcr page 18 2. operational description 2.2 system clock controller TMP86FS49AIFG 2.2.4 operating mode control 2.2.4.1 stop mode stop mode is controlled by the system control register 1, the stop pin input and key-on wakeup input (stop3 to stop0) which are controlled by the stop mode release cont rol register (stopcr). the stop pin is also used both as a port p20 and an int5 (external interrupt input 5) pin. stop mode is started by setting syscr1 page 19 TMP86FS49AIFG figure 2-7 level-s ensitive release mode note 1: even if the stop pin input is low or the stop3 to stop0 pin inputs are high after warm-up start, the stop mode is not restarted. note 2: in this case of changing to the level-s ensitive mode from the edge-s ensitive mode, the release mode is not switched until a rising edge of the stop pin input is detected. (2) edge-sensitive release mode (relm = ?0?) in this mode, stop mode is released by a rising edge of the stop pin input. this is used in appli- cations where a relatively short pr ogram is executed repeat edly at periodic intervals. this periodic signal (for example, a clock from a low-power consumption oscillator) is input to the stop pin. in the edge-sensitive release mode, stop mode is started even when the stop pin input is high level. do not use any stop3 to stop0 pin inputs for releasing stop mode in edge-sensitive release mode. example 2 :starting stop mode from normal mode with an int5 interrupt. pint5: test (p2prd). 0 ; to reject noise, stop mode does not start if jrs f, sint5 port p20 is at high ld (syscr1), 01010000b ; sets up the level-sensitive release mode. di ; imf 0 set (syscr1). 7 ; starts stop mode sint5: reti example :starting stop mode from normal mode di ; imf 0 ld (syscr1), 10010000b ; starts after specified to the edge-sensitive release mode v ih normal operation warm up stop operation confirm by program that the stop pin input is low and start stop mode. always released if the stop pin input is high. stop pin xout pin stop mode is released by the hardware. normal operation page 20 2. operational description 2.2 system clock controller TMP86FS49AIFG figure 2-8 edge-sensitive release mode stop mode is released by the following sequence. 1. in the dual-clock mode, when returning to normal2, both the high-frequency and low- frequency clock oscillators are turned on; when returning to slow1 mode, only the low- frequency clock oscillator is turned on. in the single-clock mode, only the high-frequency clock oscillator is turned on. 2. a warm-up period is inserted to allow oscillation time to stabilize. during warm up, all internal operations remain halted. four differ ent warm-up times can be selected with the syscr1 page 21 TMP86FS49AIFG figure 2-9 stop mode start/release instruction address a + 4 0 instruction address a + 3 turn on turn on warm up 0 n halt set (syscr1). 7 turn off (a) stop mode start (example: start with set (syscr1). 7 instruction located at address a) a + 6 a + 5 a + 4 a + 3 a + 2 n + 2 n + 3 n + 4 a + 3 n + 1 instruction address a + 2 2 1 0 3 (b) stop mode release count up turn off halt oscillator circuit program counter instruction execution divider main system clock oscillator circuit stop pin input program counter instruction execution divider main system clock page 22 2. operational description 2.2 system clock controller TMP86FS49AIFG 2.2.4.2 idle1/2 mode and sleep1/2 mode idle1/2 and sleep1/2 modes are controlled by the system control register 2 (syscr2) and maskable interrupts. the following status is maintained during these modes. 1. operation of the cpu and watchdog timer (wdt) is halted. on-chip peripherals continue to operate. 2. the data memory, cpu registers, program status word and port output latches are all held in the status in effect before these modes were entered. 3. the program counter holds the address 2 ahead of th e instruction which starts these modes. figure 2-10 idle1/ 2 and sleep1/2 modes reset reset input ?0? ?1? (interrupt release mode) yes no no cpu and wdt are halted interrupt request imf interrupt processing normal release mode yes starting idle1/2 and sleep1/2 modes by instruction execution of the instruc- tion which follows the idle1/2 and sleep1/2 modes start instruction page 23 TMP86FS49AIFG ? start the idle1/2 and sleep1/2 modes after imf is set to "0", set the individual inte rrupt enable flag (ef) which releases idle1/2 and sleep1/2 modes. to start idle1/2 and sl eep1/2 modes, set syscr2 page 24 2. operational description 2.2 system clock controller TMP86FS49AIFG figure 2-11 idle1/2 and sleep1/2 modes start/release halt halt halt halt operate instruction address a + 2 a + 3 a + 2 a + 4 a + 3 a + 3 halt set (syscr2). 4 operate operate operate acceptance of interrupt ?r:w normal release mode ?s:w interrupt release mode main system clock interrupt request program counter instruction execution watchdog timer main system clock interrupt request program counter instruction execution watchdog timer main system clock interrupt request program counter instruction execution watchdog timer (a) idle1/2 and sleep1/2 modes start (example: star ting with the set instruction located at address a) (b) idle1/2 and sleep1/2 modes release page 25 TMP86FS49AIFG 2.2.4.3 idle0 and sleep0 modes (idle0, sleep0) idle0 and sleep0 modes are controlled by the system control register 2 (syscr2) and the time base timer control register (tbtcr). the following stat us is maintained during idle0 and sleep0 modes. 1. timing generator stops feeding clock to peripherals except tbt. 2. the data memory, cpu registers, program status word and port output latches are all held in the status in effect before idle0 and sleep0 modes were entered. 3. the program counter holds the address 2 ahead of the instru ction which starts idle0 and sleep0 modes. note: before starting idle0 or sleep0 mode, be sure to stop (disable) peripherals. figure 2-12 idle 0 and sleep0 modes yes (normal release mode) yes (interrupt release mode) no yes reset input cpu and wdt are halted reset tbt source clock falling edge tbtcr page 26 2. operational description 2.2 system clock controller TMP86FS49AIFG ? start the idle0 and sleep0 modes stop (disable) peripherals such as a timer counter. to start idle0 and sleep0 modes, set syscr2 page 27 TMP86FS49AIFG figure 2-13 idle0 and slee p0 modes start/release halt halt operate instruction address a + 2 halt operate set (syscr2). 2 halt operate acceptance of interrupt halt ?r:w normal release mode ?s:w interrupt release mode main system clock interrupt request program counter instruction execution watchdog timer main system clock tbt clock tbt clock program counter instruction execution watchdog timer main system clock program counter instruction execution watchdog timer a + 3 a + 2 a + 4 a + 3 a + 3 (a) idle0 and sleep0 modes start (example: starting with the set instruction located at address a (b) idle and sleep0 modes release page 28 2. operational description 2.2 system clock controller TMP86FS49AIFG 2.2.4.4 slow mode slow mode is controlled by the sy stem control register 2 (syscr2). the following is the methods to switch the mode with the warm-up counter. (1) switching from normal2 mode to slow1 mode first, set syscr2 page 29 TMP86FS49AIFG (2) switching from slow1 mode to normal2 mode note: after sysck is cleared to ?0?, executing the in structions is continiued by the low-frequency clock for the period synchronized with low-frequency and high-frequency clocks. first, set syscr2 page 30 2. operational description 2.2 system clock controller TMP86FS49AIFG figure 2-14 switching between the normal2 and slow modes set (syscr2). 7 normal2 mode clr (syscr2). 7 set (syscr2). 5 normal2 mode turn off (a) switching to the slow mode slow1 mode slow2 mode clr (syscr2). 5 (b) switching to the normal2 mode high- frequency clock low- frequency clock main system clock instruction execution sysck xen high- frequency clock low- frequency clock main system clock instruction execution sysck xen slow1 mode warm up during slow2 mode page 31 TMP86FS49AIFG 2.3 reset circuit the TMP86FS49AIFG has four types of re set generation procedures: an external reset input, an address trap reset, a watchdog timer reset and a system cloc k reset. of these reset, the address trap reset, the watchdog timer and the system clock reset are a malfunction re set. when the malfunction reset request is detected, reset occurs during the maximum 24/fc[s]. the malfunction reset circuit such as watchdog timer reset, address trap reset and system clock reset is not initial- ized when power is turned on. therefore, reset may occur during maximum 24/fc[s] (1.5 s at 16.0 mhz) when power is turned on. table 2-3 shows on-chip hardware initialization by reset action. 2.3.1 external reset input the reset pin contains a schmitt trigger (hysteresis) with an internal pull-up resistor. when the reset pin is held at ?l? level for at least 3 machin e cycles (12/fc [s]) wi th the power supply volt- age within the operating voltage range and oscillation stab le, a reset is applied and the internal state is initial- ized. when the reset pin input goes high, the reset operation is rele ased and the program execution starts at the vector address stored at addresses fffeh to ffffh. figure 2-15 reset circuit table 2-3 initializing internal status by reset action on-chip hardware initial value on-chip hardware initial value program counter (pc) (fffeh) prescaler and divider of timing generator 0 stack pointer (sp) not initialized general-purpose registers (w, a, b, c, d, e, h, l, ix, iy) not initialized jump status flag (jf) not initialized watchdog timer enable zero flag (zf) not initialized output latches of i/o ports refer to i/o port circuitry carry flag (cf) not initialized half carry flag (hf) not initialized sign flag (sf) not initialized overflow flag (vf) not initialized interrupt master enable flag (imf) 0 interrupt individual enable flags (ef) 0 control registers refer to each of control register interrupt latches (il) 0 ram not initialized internal reset reset vdd malfunction reset output circuit watchdog timer reset address trap reset system clock reset page 32 2. operational description 2.3 reset circuit TMP86FS49AIFG 2.3.2 address trap reset if the cpu should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip ram (when wdtcr1 page 33 TMP86FS49AIFG page 34 2. operational description 2.3 reset circuit TMP86FS49AIFG page 35 TMP86FS49AIFG 3. interrupt control circuit the TMP86FS49AIFG has a total of 24 interrupt sources excl uding reset. interrupts can be nested with priorities. four of the internal interrupt sources ar e non-maskable while the rest are maskable. interrupt sources are provided with interrupt latches (il) , which hold interrupt requests, and independent vectors. the interrupt latch is set to ?1? by th e generation of its interrupt request wh ich requests the cpu to accept its inter- rupts. interrupts are enabled or disabled by software using the interrupt master enable fl ag (imf) and in terrupt enable flag (ef). if more than one interrupts are generated simultaneously, interrup ts are accepted in order which is domi- nated by hardware. note 1: to use the address trap interrupt (intatrap), clear wdtcr1 page 36 3. interrupt control circuit 3.2 interrupt enable register (eir) TMP86FS49AIFG the interrupt latches are located on address 002eh, 003ch and 003dh in sfr area. each latch can be cleared to "0" individually by instruction. however, il2 and il3 sh ould not be cleared to "0" by software. for clearing the interrupt latch, load instruction should be used and then il2 and il3 should be set to "1". if the read-modify-write instructions such as bit manipulation or operation instru ctions are used, interrupt re quest would be cleared inade- quately if interrupt is requested while such instructions are executed. interrupt latches are not set to ?1? by an instruction. since interrupt latches can be read, the status fo r interrupt requests can be monitored by software. note: in main program, before manipulating the interrupt enable flag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf new ly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf becomes "0 " automatically, clearing imf need not execute normally on interrupt service routine. however, if using multiple inte rrupt on interrupt service routine, manipulating ef or il should be executed before setting imf="1". 3.2 interrupt enab le register (eir) the interrupt enable register (eir) enables and disables the acceptance of interrupts, except fo r the non-maskable interrupts (software interrupt, undefined instruction interr upt, address trap interrupt and watchdog interrupt). non- maskable interrupt is accepted regardless of the contents of the eir. the eir consists of an interrupt mast er enable flag (imf) and the individua l interrupt enable flags (ef). these registers are located on address 002ch, 003ah and 003bh in sfr area, and they can be read and written by an instructions (including read-modify-write instructions such as bit manipulation or operation instructions). 3.2.1 interrupt ma ster enable flag (imf) the interrupt enable register (imf ) enables and disables the acceptance of the whole maskable interrupt. while imf = ?0?, all maskable interrupts are not accepted regardless of the status on each individual interrupt enable flag (ef). by setting imf to ?1?, the interrupt becomes acceptable if the individuals are enabled. when an interrupt is accepted, imf is cleared to ?0? after the latest status on imf is stacked. thus the maskable inter- rupts which follow are disabled. by executing return interrupt instruction [reti/retn], the stacked data, which was the status before interrup t acceptance, is loaded on imf again. the imf is located on bit0 in eirl (address: 003ah in sfr), and can be read and written by an instruction. the imf is normally set and cl eared by [ei] and [di] instruction respectively. during reset, the imf is initial- ized to ?0?. example 1 :clears interrupt latches di ; imf 0 ldw (ill), 111010000011 1111b ; il12, il10 to il6 0 ei ; imf 1 example 2 :reads interrupt latches ld wa, (ill) ; w ilh, a ill example 3 :tests interrupt latches test (ill). 7 ; if il7 = 1 then jump jr f, sset page 37 TMP86FS49AIFG 3.2.2 individual interrupt enable flags (ef23 to ef4) each of these flags enables and disables the acceptan ce of its maskable interrupt . setting the corresponding bit of an individual interrupt enable flag to ?1? enables acceptan ce of its interrupt, and setting the bit to ?0? dis- ables acceptance. during reset, all the i ndividual interrupt enable flags (ef23 to ef4) ar e initialized to ?0? and all maskable interrupts are not accepted until they are set to ?1?. note:in main program, before manipulating the interrupt enable flag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf newly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf become s "0" automatically, clearing imf need not execute nor- mally on interrupt service routine. however, if using mult iple interrupt on interrupt service routine, manipulat- ing ef or il should be executed before setting imf="1". example 1 :enables interrupts individually and sets imf di ; imf 0 ldw : (eirl), 1110100010100000b ; ef15 to ef13, ef11, ef7, ef5 1 note: imf should not be set. : ei ; imf 1 example 2 :c compiler description example unsigned int _io (3ah) eirl; /* 3ah shows eirl address */ _di(); eirl = 10100000b; : _ei(); page 38 3. interrupt control circuit 3.2 interrupt enable register (eir) TMP86FS49AIFG note 1: to clear any one of bits il7 to il4, be sure to write "1" into il2 and il3. note 2: in main program, before manipulating the interrupt enable fl ag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf newly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf becomes "0" automatically, clear ing imf need not execute normally on inter- rupt service routine. however, if using multiple interrupt on interrupt service routine, mani pulating ef or il should be exe- cuted before setting imf="1". note 3: do not clear il with read-modify-w rite instructions such as bit operations. note 1: *: don?t care note 2: do not set imf and the interrupt enable flag (ef15 to ef4) to ?1? at the same time. note 3: in main program, before manipulating the interrupt enable fl ag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf newly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf becomes "0" automatically, clear ing imf need not execute normally on inter- rupt service routine. however, if using multiple interrupt on interrupt service routine, mani pulating ef or il should be exe- cuted before setting imf="1". interrupt latches (initial value: 00000000 000000**) ilh,ill (003dh, 003ch) 1514131211109876543210 il15 il14 il13 il12 il11 il10 il9 il8 il7 il6 il5 il4 il3 il2 ilh (003dh) ill (003ch) (initial value: 00000000) ile (002eh) 76543210 il23 il22 il21 il20 il19 il18 il17 il16 ile (002eh) il23 to il2 interrupt latches at rd 0: no interrupt request 1: interrupt request at wr 0: clears the interrupt request 1: (interrupt latch is not set.) r/w interrupt enable registers (initial value: 00000000 0000***0) eirh,eirl (003bh, 003ah) 1514131211109876543210 ef15 ef14 ef13 ef12 ef11 ef10 ef9 ef8 ef7 ef6 ef5 ef4 imf eirh (003bh) eirl (003ah) (initial value: 00000000) eire (002ch) 76543210 ef23 ef22 ef21 ef20 ef19 ef18 ef17 ef16 eire (002ch) ef23 to ef4 individual-interrupt enable flag (specified for each bit) 0: 1: disables the acceptance of each maskable interrupt. enables the acceptance of each maskable interrupt. r/w imf interrupt master enable flag 0: 1: disables the acceptance of all maskable interrupts enables the acceptance of all maskable interrupts page 39 TMP86FS49AIFG 3.3 interrupt sequence an interrupt request, which raised inte rrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to ?0? by resetting or an instruct ion. interrupt acceptance sequence requires 8 machine cycles (2 s @16 mhz) after the completion of the current instruction. the interrupt service task terminates upon execution of an interrupt return instruction [reti] (for maskable interrupts) or [retn] (for non-maskable interrupts). figure 3-1 shows the timing chart of interrupt acceptance processing. 3.3.1 interrupt acceptance proc essing is packaged as follows. a. the interrupt master enab le flag (imf) is cleared to ?0? in or der to disable the acceptance of any fol- lowing interrupt. b. the interrupt latch (il) for the interrupt source accepted is cleared to ?0?. c. the contents of the program coun ter (pc) and the program status word, including the interrupt master enable flag (imf), are saved (pushed) on the st ack in sequence of psw + imf, pch, pcl. mean- while, the stack pointer (s p) is decremented by 3. d. the entry address (interrupt vect or) of the corresponding interrupt service program, loaded on the vec- tor table, is transferred to the program counter. e. the instruction stored at the entry address of the inte rrupt service program is executed. note:when the contents of psw are saved on the stack, the contents of imf are also saved. note 1: a: return address, b: entry address, c: address which reti instruction is stored note 2: on condition that interrupt is enabled, it takes 38/fc [s ] or 38/fs [s] at maximum (if the interrupt latch is set at the first machine cycle on 10 cycle instruction) to start interrupt acceptance processing since its interrupt latch is set. figure 3-1 timing chart of interrupt acceptance/return in terrupt instruction example: correspondence be tween vector table address for inttbt an d the entry address of the interrupt service program figure 3-2 vector table address,entry address a b a c + 1 execute instruction sp pc execute instruction n n ? 2 n - 3 n ? 2n ? 1 n ? 1 n a + 2 a + 1 c + 2 b + 3 b + 2 b + 1 a + 1 a a ? 1 execute reti instruction interrupt acceptance execute instruction interrupt service task 1-machine cycle interrupt request interrupt latch (il) imf d2h 03h d203h d204h 06h vector table address entry address 0fh vector interrupt service program fff0h fff1h page 40 3. interrupt control circuit 3.3 interrupt sequence TMP86FS49AIFG a maskable interrupt is not accepted until the imf is set to ?1? even if th e maskable interrupt higher than the level of current servicing interrupt is requested. in order to utilize nested interrupt service, the imf is set to ?1? in the interrupt service program. in this case, acceptable interrupt sources are selectively en abled by the individual interrupt enable flags. to avoid overloaded nesting, clear the individual interrupt enable flag whose interrupt is currently serviced, before setting imf to ?1?. as for non-maskable interr upt, keep interrupt service shorten compared with length between interrupt requests; otherwise the status cannot be recovered as non-maskable interrupt would simply nested. 3.3.2 saving/restoring general-purpose registers during interrupt acceptance processing , the program counter (pc) and the program status word (psw, includes imf) are automati cally saved on the stack, but the accumulato r and others are not. these registers are saved by software if necessary. when multiple interrupt se rvices are nested, it is also necessary to avoid using the same data memory area for saving registers. the fo llowing methods are used to save/restore the general- purpose registers. 3.3.2.1 using push and pop instructions if only a specific register is saved or interrupts of the same source are nested , general-purpose registers can be saved/restored using the push/pop instructions. figure 3-3 save/restore register using push and pop instructions 3.3.2.2 using data transfer instructions to save only a specific register wi thout nested interrupts, data tran sfer instructions are available. example :save/restore register using push and pop instructions pintxx: push wa ; save wa register (interrupt processing) pop wa ; restore wa register reti ; return pcl pch psw at acceptance of an interrupt at execution of push instruction at execution of reti instruction at execution of pop instruction b-4 b-3 b-2 b-1 b pcl pch psw pcl pch psw sp address (example) sp sp sp a w b-5 page 41 TMP86FS49AIFG figure 3-4 saving/restoring general-purpose r egisters under interrupt processing 3.3.3 interrupt return interrupt return instructions [reti]/[retn] perform as follows. as for address trap interrupt (intatrap), it is requir ed to alter stacked data for program counter (pc) to restarting address, during interrupt service program. note:if [retn] is executed with the above data unaltered, the program returns to the address trap area and intatrap occurs again.when interrupt acceptance pr ocessing has completed, stacked data for pcl and pch are located on address (sp + 1) and (sp + 2) respectively. example :save/restore register us ing data transfer instructions pintxx: ld (gsava), a ; save a register (interrupt processing) ld a, (gsava) ; restore a register reti ; return [reti]/[retn] interrupt return 1. program counter (pc) and program status word (psw, includes imf) are restored from the stack. 2. stack pointer (sp) is incremented by 3. example 1 :returning from address trap interrupt (intatrap) service program pintxx: pop wa ; recover sp by 2 ld wa, return address ; push wa ; alter stacked data (interrupt processing) retn ; return interrupt acceptance interrupt service task restoring registers saving registers interrupt return saving/restoring general-purpose registers using push/pop data transfer instruction main task page 42 3. interrupt control circuit 3.4 software interrupt (intsw) TMP86FS49AIFG interrupt requests are sampled during the final cycle of the instruction being executed. thus, the next inter- rupt can be accepted immediat ely after the interrupt retu rn instruction is executed. note 1: it is recommended that stack pointer be return to rate before intatrap (increment 3 times), if return inter- rupt instruction [retn] is not utilized during inte rrupt service program under intatrap (such as example 2). note 2: when the interrupt processing time is longer than the interrupt request generation time, the interrupt service task is performed but not the main task. 3.4 software interrupt (intsw) executing the swi instruction generates a software interr upt and immediately starts interrupt processing (intsw is highest prioritized interrupt). use the swi instruction only for detection of the address error or for debugging. 3.4.1 address error detection ffh is read if for some cause such as noise the cpu attempts to fetch an instruction from a non-existent memory address during single chip mode. code ffh is th e swi instruction, so a software interrupt is gener- ated and an address error is detect ed. the address error detection range can be further expanded by writing ffh to unused areas of the program memory. address trap reset is generated in case that an instruction is fetched from ram, dbr or sfr areas. 3.4.2 debugging debugging efficiency can be increased by placing the swi instruction at the software break point setting address. 3.5 undefined instruct ion interrupt (intundef) taking code which is not defined as authorized instru ction for instruction causes intundef. intundef is gen- erated when the cpu fetches such a co de and tries to execute it. intundef is accepted even if non-maskable inter- rupt is in process. contemporary process is broken and intundef interrupt process starts, soon after it is requested. note: the undefined instruction interrupt (intundef) forces cpu to jump into vector address, as software interrupt (swi) does. 3.6 address trap interrupt (intatrap) fetching instruction from unauthorized area for instructio ns (address trapped area) cause s reset output or address trap interrupt (intatrap). intatrap is accepted even if non-maskable inte rrupt is in pro cess. contemporary process is broken and intatrap interrupt pr ocess starts, soon af ter it is requested. note: the operating mode under address trapped, whether to be reset output or interrupt processing, is selected on watchdog timer control register (wdtcr). example 2 :restarting without returning interrupt (in this case, psw (includes imf) befo re interrupt acceptance is discarded.) pintxx: inc sp ; recover sp by 3 inc sp ; inc sp ; (interrupt processing) ld eirl, data ; set imf to ?1? or clear it to ?0? jp restart address ; jump into restarting address page 43 TMP86FS49AIFG 3.7 external interrupts the TMP86FS49AIFG has 5 external interrupt inputs. these inputs are equipped with di gital noise reject circuits (pulse inputs of less than a certa in time are elimin ated as noise). edge selection is also possible with int1 to int3. the int0 /p00 pin can be configured as either an external inter- rupt input pin or an input/output port, and is configured as an input port during reset. edge selection, noise reject control and int0 /p00 pin function selection are performed by the external interrupt control register (eintcr). note 1: in normal1/2 or idle1/2 mode, if a signal with no noise is input on an external interrupt pin, it takes a maximum of "si g- nal establishment time + 6/fc[s]" from the input signal's edge to set the interrupt latch. note 2: when int0en = "0", il4 is not set even if a falling edge is detected on the int0 pin input. note 3: when a pin with more than one function is used as an out put and a change occurs in data or input/output status, an inter - rupt request signal is generated in a pseudo manner. in this ca se, it is necessary to perform appropriate processing such as disabling the interrupt enable flag. source pin enable conditions release edge digital noise reject int0 int0 imf ? ef4 ? int0en=1 falling edge pulses of less than 2/fc [s] are eliminated as noise. pulses of 7/fc [s ] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are consid- ered to be signals. int1 int1 imf ? ef6 = 1 falling edge or rising edge pulses of less than 15/fc or 63/fc [s] are elimi- nated as noise. pulses of 49/fc or 193/fc [s] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are considered to be signals. int2 int2 imf ? ef8 = 1 falling edge or rising edge pulses of less than 7/fc [s] are eliminated as noise. pulses of 25/fc [s] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are consid- ered to be signals. int3 int3 imf ? ef12 = 1 falling edge or rising edge pulses of less than 7/fc [s] are eliminated as noise. pulses of 25/fc [s] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are consid- ered to be signals. int5 int5 imf ? ef23 = 1 falling edge pulses of less than 2/fc [s] are eliminated as noise. pulses of 7/fc [s ] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are consid- ered to be signals. page 44 3. interrupt control circuit 3.7 external interrupts TMP86FS49AIFG note 1: fc: high-frequency clock [hz], *: don?t care note 2: when the system clock frequency is switched between high and low or when the external interrupt control register (eintcr) is overwritten, the noise canceller may not operat e normally. it is recommended that external interrupts are dis- abled using the interrupt enable register (eir). note 3: the maximum time from modifying int1 nc until a noise reject time is changed is 2 6 /fc. external interrupt control register eintcr76543210 (0037h) int1nc int0en - - int3es int2es int1es (initial value: 00** 000*) int1nc noise reject time select 0: pulses of less than 63/fc [s] are eliminated as noise 1: pulses of less than 15/fc [s] are eliminated as noise r/w int0en p00/ int0 pin configuration 0: p00 input/output port 1: int0 pin (port p00 should be set to an input mode) r/w int3 es int3 edge select 0: rising edge 1: falling edge r/w int2 es int2 edge select 0: rising edge 1: falling edge r/w int1 es int1 edge select 0: rising edge 1: falling edge r/w page 45 TMP86FS49AIFG 4. special function register (sfr) the TMP86FS49AIFG adopts the memory mapped i/o syst em, and all peripheral control and data transfers are performed through the special function register (sfr) or the data buffer register (dbr). the sfr is mapped on address 0000h to 003fh, dbr is mapped on address 0f80h to 0fffh. this chapter shows the arrangement of the special functi on register (sfr) and data buffer register (dbr) for TMP86FS49AIFG. 4.1 sfr address read write 0000h p0dr 0001h p1dr 0002h p2dr 0003h p3dr 0004h p4dr 0005h p5dr 0006h p6dr 0007h p7dr 0008h p0outcr 0009h p1cr 000ah p4outcr 000bh p0prd - 000ch p2prd - 000dh p3prd - 000eh p4prd - 000fh p5prd - 0010h tc1dral 0011h tc1drah 0012h tc1drbl 0013h tc1drbh 0014h ttreg3 0015h ttreg4 0016h ttreg5 0017h ttreg6 0018h pwreg3 0019h pwreg4 001ah pwreg5 001bh pwreg6 001ch adccr1 001dh adccr2 001eh adcdr2 - 001fh adcdr1 - 0020h sio1cr 0021h sio1sr - 0022h sio1rdb sio1tdb 0023h tc2cr 0024h tc2drl 0025h tc2drh page 46 4. special function register (sfr) 4.1 sfr TMP86FS49AIFG note 1: do not access reserved areas by the program. note 2: ? ; cannot be accessed. note 3: write-only registers and interrupt latches cannot use the read-modify-write instructions (bit manipulation instructions such as set, clr, etc. and logical operation instructions such as and, or, etc.). 0026h tc1cr 0027h tc3cr 0028h tc4cr 0029h tc5cr 002ah tc6cr 002bh sio2rdb sio2tdb 002ch eire 002dh reserved 002eh ile 002fh reserved 0030h reserved 0031h sio2cr 0032h sio2sr - 0033h reserved 0034h - wdtcr1 0035h - wdtcr2 0036h tbtcr 0037h eintcr 0038h syscr1 0039h syscr2 003ah eirl 003bh eirh 003ch ill 003dh ilh 003eh reserved 003fh psw address read write page 47 TMP86FS49AIFG 4.2 dbr address read write 0f80h reserved 0f81h reserved 0f82h reserved 0f83h reserved 0f84h reserved 0f85h reserved 0f86h reserved 0f87h reserved 0f88h reserved 0f89h reserved 0f8ah reserved 0f8bh reserved 0f8ch reserved 0f8dh reserved 0f8eh reserved 0f8fh reserved 0f90h sbisra sbicra 0f91h sbidbr 0f92h - i2car 0f93h sbisrb sbicrb 0f94h reserved 0f95h uart1sr uart1cr1 0f96h - uart1cr2 0f97h rd1buf td1buf 0f98h uart2sr uart2cr1 0f99h - uart2cr2 0f9ah rd2buf td2buf 0f9bh p6cr1 0f9ch p6cr2 0f9dh p7cr1 0f9eh p7cr2 0f9fh - stopcr address read write 0fa0h reserved : : : : 0fbfh reserved address read write 0fc0h reserved : : : : 0fdfh reserved page 48 4. special function register (sfr) 4.2 dbr TMP86FS49AIFG note 1: do not access reserved areas by the program. note 2: ? ; cannot be accessed. note 3: write-only registers and interrupt latches cannot use the read-modify-write instructions (bit manipulation instructions such as set, clr, etc. and logical operation instructions such as and, or, etc.). address read write 0fe0h reserved 0fe1h reserved 0fe2h reserved 0fe3h reserved 0fe4h reserved 0fe5h reserved 0fe6h reserved 0fe7h reserved 0fe8h reserved 0fe9h reserved 0feah reserved 0febh reserved 0fech reserved 0fedh reserved 0feeh reserved 0fefh reserved 0ff0h reserved 0ff1h reserved 0ff2h reserved 0ff3h reserved 0ff4h reserved 0ff5h reserved 0ff6h reserved 0ff7h reserved 0ff8h reserved 0ff9h reserved 0ffah reserved 0ffbh reserved 0ffch reserved 0ffdh reserved 0ffeh reserved 0fffh flscr page 49 TMP86FS49AIFG 5. i/o ports the TMP86FS49AIFG has 8 parallel input /output ports (56 pins) as follows. each output port contains a latch, which holds the output data. all input ports do not have latches, so the external input data should be externally held until the input data is read from outside or reading should be performed several timer before processing. figure 5-1 shows input/output timing examples. external data is read from an i/o port in the s1 state of the read cycle during execution of the read instruction. this timing cannot be recognized from outside, so that transient input such as chattering must be processed by the pro- gram. output data changes in the s2 state of the write cycle du ring execution of the instruct ion which writes to an i/o port. note: the positions of the read and write c ycles may vary, depending on the instruction. figure 5-1 input/output timing (example) primary function secondary functions port p0 8-bit i/o port external interrupt, serial prom mode cotrol input, serial interface input/output, uart input/output. port p1 8-bit i/o port external interrupt, ti mer counter input/output, divider output. port p2 3-bit i/o port low-frequency resonator connections, external interrupt input, stop mode release signal input. port p3 8-bit i/o port port p4 8-bit i/o port serial interface input/output and uart input/output. port p5 5-bit i/o port serial bus interface input/output. port p6 8-bit i/o port analog input and key-on wakeup input. port p7 8-bit i/o port analog input. data output data input new old example: ld a, (x) fetch cycle read cycle fetch cycle s0 s1 s2 s3 s0 s1 s2 s3 s0 s1 s2 s3 instruction execution cycle input strobe (a) input timing example: ld (x), a fetch cycle write cycle fetch cycle s0 s1 s2 s3 s0 s1 s2 s3 s0 s1 s2 s3 (b) output timing instruction execution cycle output strobe page 50 5. i/o ports 5.1 port p0 (p07 to p00) TMP86FS49AIFG 5.1 port p0 (p07 to p00) port p0 is an 8-bit input/output port. port p0 is also used as an external interrupt input, serial prom mode control input, a serial interface input/output and an uart input/output. when used as an input port, an exte rnal interrupt input , a serial interface input/output and an uart input/output, the corresponding output latch (p0dr) should be set to "1". during reset, the p0dr is initialized to "1", and the p0outcr is initialized to "0". it can be selected whether output circ uit of p0 port is a c-mos output or a sink open drain individually, by setting p0outcr. when a corresponding bit of p0outcr is "0". the output circuit is selected to a sink open drain and when a corresponding bit of p0outcr is "1", the output circuit is selected to a c-mos output. when used as an input port, an external interrupt inpu t, a serial interface input and an uart input, the corre- sponding output control (p0outcr) should be set to "0" after p0dr is set to "1". p0 port output latch (p0dr) and p0 port terminal input (p0prd) are located on their respective address. when read the output latch data, the p0dr should be read . when read the terminal input data, the p0prd register should be read. note: i = 7 to 0 figure 5-2 port 0 and p0outcr table 5-1 register programming for multi-function ports (p07 to p00) function programmed value p0dr p0outcr port input, external input, serial interface input or uart input, serial prom mode cotrol input ?1? ?0? port ?0? output ?0? programming for each applica- tions port ?1? output, serial interface output or uart output ?1? data output (p0dr) control output stop outen p0outcri dq p0i p0outcri input data input (p0prd) output latch read (p0dr) control input dq output latch page 51 TMP86FS49AIFG p0dr (0000h) r/w 76543210 p07 int2 p06 sck1 p05 so1 p04 si1 p03 int1 p02 txd1 p01 rxd1 boot p00 int0 (initial value: 1111 1111) p0outcr (0008h) (initial value: 0000 0000) p0outcr port p0 output circuit control (set for each bit individually) 0: sink open-drain output 1: c-mos output r/w p0prd (000bh) read only p07 p06 p05 p04 p03 p02 p01 p00 page 52 5. i/o ports 5.2 port p1 (p17 to p10) TMP86FS49AIFG 5.2 port p1 (p17 to p10) port p1 is an 8-bit input/output port which can be configured as an input or output in one-bit unit. port p1 is also used as a timer/counter input/output, an external interrupt input and a divider output. input/output mode is specified by the p1 control register (p1cr). during reset, the p1cr is initialized to "0" and port p1 becomes an input mode. and the p1dr is initialized to "0". when used as an input port, a timer/counter input and an external interrupt input, the corresponding bit of p1cr should be set to "0". when used as an output port, the corresponding bit of p1cr should be set to "1". when used as a timer/counter output and a divider output, p1dr is set to "1" beforehand and the corresponding bit of p1cr should be set to "1". when p1cr is "1", the content of the correspon ding output latch is read by reading p1dr. note: asterisk (*) indicates ?1? or ?0? either of which can be selected. note: i = 7 to 0 figure 5-3 port 1 and p1cr note: the port set to an input mode reads the terminal input data. therefore, when the input and output modes are used together, the content of the output latch which is s pecified as input mode might be changed by executing a bit manipulation instruction. table 5-2 register programming for multi-function ports function programmed value p1dr p1cr port input, timer/counter input or external interrupt input *?0? port ?0? output ?0? ?1? port ?1? output, a timer output or a divider output ?1? ?1? p1i dq dq stop outen p1cri p1cri input data input (p1dr) data output (p1dr) control output control input output latch page 53 TMP86FS49AIFG p1dr (0001h) r/w 76543210 p17 tc6 pwm6 pdo6 ppg6 p16 tc5 pwm5 pdo5 p15 tc2 int3 p14 tc4 pwm4 pdo4 ppg4 p13 tc3 pwm3 pdo3 p12 ppg p11 dvo p10 tc1 (initial value: 0000 0000) p1cr (0009h) 76543210 (initial value: 0000 0000) p1cr i/o control for port p1 (specified for each bit) 0: input mode 1: output mode r/w page 54 5. i/o ports 5.3 port p2 (p22 to p20) TMP86FS49AIFG 5.3 port p2 (p22 to p20) port p2 is a 3-bit input/output port. it is also used as an external interr upt, a stop mode release signal input, and low-frequency crys tal oscillator con- nection pins. when used as an input port or a secondary function pins, respective output latch (p2dr) should be set to ?1?. during reset, the p2dr is initialized to ?1?. a low-frequency crystal osci llator (32.768 khz) is connected to pins p21 (xtin) and p22 (xtout) in the dual- clock mode. in the single-clock mode, pins p21 and p22 can be used as normal input/output ports. it is recommended that pin p20 should be used as an exte rnal interrupt input, a stop mode release signal input, or an input port. if it is used as an output port, the in terrupt latch is set on the falling edge of the output pulse. p2 port output latch (p2dr) and p2 port terminal i nput (p2prd) are located on their respective address. when read the output latch data, the p2dr should be r ead and when read the termin al input data, the p2prd reg- ister should be read. if a read instruction is execute d for port p2, read data of bits 7 to 3 are unstable. figure 5-4 port 2 note: port p20 is used as stop pin. therefore, when stop mode is started, outen does not affect to p20, and p20 becomes high-z mode. p2dr (0002h) r/w 76543210 p22 xtout p21 xtin p20 int5 stop (initial value: **** *111) p2prd (000ch) read only p22 p21 p20 output latch osc. enable output latch dq p20 (int5, stop) dq output latch dq p21 (xtin) p22 (xtout) data input (p20prd) data input (p20) data output (p20) contorl input data input (p21prd) output latch read (p21) data output (p21) data input (p22prd) output latch read (p22) data output (p22) stop outen xten fs page 55 TMP86FS49AIFG 5.4 port p3 (p37 to p 30) (large c urrent port) port p3 is an 8-bit input/output port. when used as an input port, the corresponding output latch (p3dr) should be set to "1". during reset, the p3dr is initialized to "1". p3 port output latch (p3dr) and p3 port terminal input (p3prd) are located on their respective address. when read the output latch data, the p3dr should be read . when read the terminal input data, the p3prd register should be read. note: i = 7 to 0 figure 5-5 port 3 p3dr (0003h) 76543210 p37 p36 p35 p34 p33 p32 p31 p30 (initial value: 1111 1111) r/w p3prd (000dh) read only p37 p36 p35 p34 p33 p32 p31 p30 data output (p3dr) stop outen dq p3i data input (p3prd) output latch read (p3dr) page 56 5. i/o ports 5.5 port p4 (p47 to p40) TMP86FS49AIFG 5.5 port p4 (p47 to p40) port p4 is an 8-bit input/output port. port p4 is also used as a serial inte rface input/output and an uart input/output. when used as an input port, a serial interface input/out put and an uart input/output, the corresponding output latch (p4dr) should be set to "1". during reset, the p4dr is initialized to "1", and the p4outcr is initialized to "0". it can be selected whether output circ uit of p4 port is a c-mos output or a sink open drain individually, by setting p4outcr. when a corresponding bit of p4outcr is "0". the output circuit is selected to a sink open drain and when a corresponding bit of p4outcr is "1", the output circuit is selected to a c-mos output. when used as an input port, a serial interface inpu t and an uart input, the corresponding output control (p4outcr) should be set to "0" after p4dr is set to "1". p4 port output latch (p4dr) and p4 port terminal input (p4prd) are located on their respective address. when read the output latch data, the p4dr should be read . when read the terminal input data, the p4prd register should be read. note: i = 7 to 0 figure 5-6 port 4 table 5-3 register programming for multi-function ports (p47 to p40) function programmed value p4dr p4outcr port input uart input or serial interface input ?1? ?0? port ?0? output ?0? programming for each applica- tions port ?1? output uart output or serial interface output ?1? data output (p4dr) control output stop outen p4outcri dq p4i p4outcri input data input (p4prd) output latch read (p4dr) control input dq output latch page 57 TMP86FS49AIFG p4dr (0004h) r/w 76543210 p47 p46 sck2 p45 so2 p44 si2 p43 p42 txd2 p41 rxd2 p40 (initial value: 1111 1111) p4outcr (000ah) (initial value: 0000 0000) p4outcr port p4 output circuit control (set for each bit individually) 0: sink open-drain output 1: c-mos output r/w p4prd (000eh) read only p47 p46 p45 p44 p43 p42 p41 p40 page 58 5. i/o ports 5.6 port p5 (p54 to p50) (large current port) TMP86FS49AIFG 5.6 port p5 (p54 to p 50) (large c urrent port) port p5 is an 5-bit input/output port. port p5 is also used as an i 2 c bus input/output. when used as an input port and i 2 c bus input/output, the corresponding output latch (p5dr) should be set to "1". during reset, the p5dr is initialized to "1". p5 port output latch (p5dr) and p5 port terminal input (p5prd) are located on their respective address. when read the output latch data, the p5dr should be read . when read the terminal input data, the p5prd register should be read. if a read instruction is execu ted for port p5, read data of bit 7 to 5 are unstable. note: i = 4 to 0 figure 5-7 port 5 p5dr (0005h) r/w 76543210 p54p53p52p51 sda p50 scl (initial value: ***1 1111) p5prd (000fh) read only p54p53p52p51p50 data output (p5dr) control output stop outen dq p5i data input (p5prd) output latch read (p5dr) control input output latch page 59 TMP86FS49AIFG 5.7 port p6 (p67 to p60) port p6 is an 8-bit input/output port which can be configured as an input or output in one-bit unit. port p6 is also used as an analog input and key-on wakeup input. input/output mode is specified by the p6 control register (p6cr1) and p6 input control register (p6cr2). during reset, the p6cr1 is initialized to "0" the p6cr2 is initialized to "1" and port p6 becomes an input mode. and the p6dr is initialized to "0". when used as an output port, the corresponding bit of p6cr1 should be set to "1". when used as an input port , the corresponding bit of p6cr1 should be set to "0" and then, the corresponding bit of p6cr2 should be set to "1". when used as a key-on wakeup input , the corresponding bi t of p6cr1 should be set to "0" and then, the corre- sponding bit of stopken should be set to "1". when used as an analog input, the corresponding bit of p6cr1 should be set to "0" and then, the corresponding bit of p6cr2 should be set to "0". when p6cr1 is "1", the content of the corres ponding output latch is read by reading p6dr. note: asterisk (*) indicates ?1? or ?0? either of which can be selected. table 5-4 register programming for multi-function ports function programmed value p6dr p6cr1 p6cr2 stopken port input * ?0? ?1? * key-on wakeup input * "0" * "1" analog input * ?0? ?0? * port ?0? output ?0? ?1? * * port ?1? output ?1? ?1? * * table 5-5 values read from p6dr and register programming conditions values read from p6dr p6cr1 p6cr2 ?0? ?0? ?0? ?0? ?1? terminal input data ?1? ?0? output latch contents ?1? page 60 5. i/o ports 5.7 port p6 (p67 to p60) TMP86FS49AIFG note 1: i = 3 to 0, j = 7 to 4, k = 3 to 0 note 2: stop is bit7 in syscr1. note 3: sain is ad input select signal. note 4: stopken is input select signal in a key-on wakeup. figure 5-8 port 6, p6cr1 and p6cr2 p6i dq dq p6cr2i p6cr2i input p6cr1i p6cr1i input data input (p6dri) data output (p6dri) stop outten analog input ainds sain dq control input p6j dq dq p6cr2j p6cr2j input p6cr1j p6cr1j input data output (p6drj) stop outten analog input ainds stopken key-on wakeup dq data input (p6drj) a) p63 to p60 sain b) p67 to p64 page 61 TMP86FS49AIFG note 1: the port placed in input mode reads the pin input stat e. therefore, when the input and output modes are used together, the output latch contents for the port in input mode might be changed by executing a bi t manipulation instruction. note 2: when used as an analog inport, be sure to clear the corresponding bit of p6cr2 to disable the port input. note 3: do not set the output mode (p6cr1 = ?1?) for the pin used as an analog input pin. note 4: pins not used for analog input can be used as i/o ports. during ad conversion, output instructions should not be execute d to keep a precision. in addition, a variabl e signal should not be input to a port ad jacent to the analog input during ad con- version. p6dr (0006h) r/w 76543210 p67 ain7 stop3 p66 ain6 stop2 p65 ain5 stop1 p64 ain4 stop0 p63 ain3 p62 ain2 p61 ain1 p60 ain0 (initial value: 0000 0000) p6cr1 (0f9bh) 76543210 (initial value: 0000 0000) p6cr1 i/o control for port p6 (specified for each bit) 0: input mode 1: output mode r/w p6cr2 (0f9ch) 76543210 (initial value: 1111 1111) p6cr2 p6 port input control (specified for each bit) 0: analog input 1: port input r/w page 62 5. i/o ports 5.8 port p7 (p77 to p70) TMP86FS49AIFG 5.8 port p7 (p77 to p70) port p7 is an 8-bit input/output port which can be configured as an input or output in one-bit unit. port p7 is also used as an analog input. input/output mode is specified by the p7 control register (p7cr1) and p7 input control register (p7cr2). during reset, the p7cr1 is initialized to "0" the p7cr2 is initialized to "1" and port p7 becomes an input mode. and the p7dr is initialized to "0". when used as an output port, the corresponding bit of p7cr1 should be set to "1". when used as an input port, the corresponding bit of p7 cr1 should be set to "0" and then, the corresponding bit of p7cr2 should be set to "1". when used as an analog input, the corresponding bit of p7cr1 should be set to "0" and then, the corresponding bit of p7cr2 should be set to "0". when p7cr1 is "1", the content of the corres ponding output latch is read by reading p7dr. note: asterisk (*) indicates ?1? or ?0? either of which can be selected. table 5-6 register programming for multi-function ports function programmed value p7dr p7cr1 p7cr2 port input external interrupt input or key-on wakeup input *?0??1? analog input * ?0? ?0? port ?0? output ?0? ?1? * port ?1? output ?1? ?1? * table 5-7 values read from p7dr and register programming conditions values read from p7dr p7cr1 p7cr2 ?0? ?0? ?0? ?0? ?1? terminal input data ?1? ?0? output latch contents ?1? page 63 TMP86FS49AIFG note 1: i = 7 to 0 note 2: stop is bit7 in syscr1. note 3: sain is ad input select signal. figure 5-9 port 7, p7cr1 and p7cr2 note 1: the port placed in input mode reads the pin input stat e. therefore, when the input and output modes are used together, the output latch contents for the port in input mode might be changed by executing a bi t manipulation instruction. note 2: when used as an analog inport, be sure to clear the corresponding bit of p7cr2 to disable the port input. note 3: do not set the output mode (p7cr1 = ?1?) for the pin used as an analog input pin. note 4: pins not used for analog input can be used as i/o ports. during ad conversion, output instructions should not be execute d to keep a precision. in addition, a variabl e signal should not be input to a port ad jacent to the analog input during ad con- version. p7dr (0007h) r/w 76543210 p77 ain15 p76 ain14 p75 ain13 p74 ain12 p73 ain11 p72 ain10 p71 ain9 p70 ain8 (initial value: 0000 0000) p7cr1 (0f9dh) 76543210 (initial value: 0000 0000) p7cr1 i/o control for port p7 (specified for each bit) 0: input mode 1: output mode r/w p7cr2 (0f9eh) 76543210 (initial value: 1111 1111) p7cr2 p7 port input control (specified for each bit) 0: analog input 1: port input, external interrupt input or key-on wakeup input r/w p7i dq dq p7cr2i p7cr2i input p7cr1i p7cr1i input data input (p7dri) data output (p7dri) stop outten analog input ainds sain dq control input page 64 5. i/o ports 5.8 port p7 (p77 to p70) TMP86FS49AIFG page 65 TMP86FS49AIFG 6. watchdog timer (wdt) the watchdog timer is a fail-safe system to detect rapidl y the cpu malfunctions such as endless loops due to spu- rious noises or the deadlock conditions, and return the cpu to a sy stem recovery routine. the watchdog timer signal for detecting malfunctions can be programmed only once as ?reset request? or ?inter- rupt request?. upon the reset release, this signal is initialized to ?reset request?. when the watchdog timer is not used to detect malfunctions, it can be used as the timer to provide a periodic inter- rupt. note: care must be taken in system des ign since the watchdog timer functions are not be operated completely due to effect of disturbing noise. 6.1 watchdog timer configuration figure 6-1 watchdog timer configuration 0034 h overflow wdt output internal reset binary counters wdtout writing clear code writing disable code wdten wdtt 2 0035 h watchdog timer control registers wdtcr1 wdtcr2 intwdt interrupt request interrupt request reset request reset release clock clear 1 2 controller q sr s r q selector fc/2 23 or fs/2 15 fc/2 21 or fs/2 13 fc/2 19 or fs/2 11 fc/2 17 or fs/2 9 page 66 6. watchdog timer (wdt) 6.2 watchdog timer control TMP86FS49AIFG 6.2 watchdog timer control the watchdog timer is controlled by the watchdog timer control registers (wdtcr1 and wdtcr2). the watch- dog timer is automatically enabled after the reset release. 6.2.1 malfunction detection me thods using the watchdog timer the cpu malfunction is detected, as shown below. 1. set the detection time, select the output, and clear the binary counter. 2. clear the binary counter repeatedly within the specified detection time. if the cpu malfunctions such as en dless loops or the deadlock condition s occur for some reason, the watch- dog timer output is activated by the binary-counter overflow unless the binary counters are cleared. when wdtcr1 page 67 TMP86FS49AIFG note 1: after clearing wdtout to ?0?, the program cannot set it to ?1?. note 2: fc: high-frequency clock [hz], fs : low-frequency clock [hz], *: don?t care note 3: wdtcr1 is a write-only register and must not be used with any of read-modify-write instructions. if wdtcr1 is read, a don?t care is read. note 4: to activate the stop mode, disable the watchdog timer or clear the counter immediately before entering the stop mode. after clearing the counter, clear the counter again immediately after the stop mode is inactivated. note 5: to clear wdten, set the register in accordance wi th the procedures shown in ?1.2.3 watchdog timer disable?. note 1: the disable code is valid only when wdtcr1 page 68 6. watchdog timer (wdt) 6.2 watchdog timer control TMP86FS49AIFG 6.2.3 watchdog timer disable to disable the watchdog timer, set the register in accordance with the fo llowing procedures . setting the reg- ister in other procedures causes a malfunction of the microcontroller. 1. set the interrupt master flag (imf) to ?0?. 2. set wdtcr2 to the clear code (4eh). 3. set wdtcr1 page 69 TMP86FS49AIFG 6.2.5 watchdog timer reset when a binary-counter overflow occurs while wdt cr1 page 70 6. watchdog timer (wdt) 6.3 address trap TMP86FS49AIFG 6.3 address trap the watchdog timer control register 1 and 2 share the a ddresses with the control regi sters to generate address traps. 6.3.1 selection of address tr ap in internal ram (atas) wdtcr1 page 71 TMP86FS49AIFG 6.3.4 address trap reset while wdtcr1 page 72 6. watchdog timer (wdt) 6.3 address trap TMP86FS49AIFG page 73 TMP86FS49AIFG 7. time base timer (tbt) the time base timer generates time base for key scanning, dynamic displaying, etc. it also provides a time base timer interrupt (inttbt). 7.1 time base timer 7.1.1 configuration figure 7-1 time base timer configuration 7.1.2 control time base timer is controled by time base timer control register (tbtcr). note 1: fc; high-frequency clock [hz], fs ; low-frequency clock [hz], *; don't care time base timer control register 7 6543210 tbtcr (0036h) (dvoen) (dvock) (dv7ck) tbten tbtck (initial value: 0000 0000) tbten time base timer enable / disable 0: disable 1: enable tbtck time base timer interrupt frequency select : [hz] normal1/2, idle1/2 mode slow1/2 sleep1/2 mode r/w dv7ck = 0 dv7ck = 1 000 fc/2 23 fs/2 15 fs/2 15 001 fc/2 21 fs/2 13 fs/2 13 010 fc/2 16 fs/2 8 ? 011 fc/2 14 fs/2 6 ? 100 fc/2 13 fs/2 5 ? 101 fc/2 12 fs/2 4 ? 110 fc/2 11 fs/2 3 ? 111 fc/2 9 fs/2 ? fc/2 23 or fs/2 15 fc/2 21 or fs/2 13 fc/2 16 or fs/2 8 fc/2 14 or fs/2 6 fc/2 13 or fs/2 5 fc/2 12 or fs/2 4 fc/2 11 or fs/2 3 fc/2 9 or fs/2 tbtcr tbten tbtck 3 mpx source clock falling edge detector time base timer control register inttbt interrupt request idle0, sleep0 release request page 74 7. time base timer (tbt) 7.1 time base timer TMP86FS49AIFG note 2: the interrupt frequency (tbtck) must be selected with t he time base timer disabled (tbten="0"). (the interrupt fre- quency must not be changed with the disable from the enable state.) both frequency selection and enabling can be per- formed simultaneously. 7.1.3 function an inttbt ( time base timer interrupt ) is generated on the first falling edge of source clock ( the divider output of the timing generato which is selected by tbtck. ) after time base timer has been enabled. the divider is not cleared by the progra m; therefore, only the first interrupt may be generated ahead of the set interrupt period ( figure 7-2 ). figure 7-2 time base timer interrupt example :set the time base timer frequency to fc/2 16 [hz] and enable an inttbt interrupt. ld (tbtcr) , 00000010b ; tbtck 010 ld (tbtcr) , 00001010b ; tbten 1 di ; imf 0 set (eirl) . 7 table 7-1 time base timer interrupt frequency ( example : fc = 16.0 mhz, fs = 32.768 khz ) tbtck time base timer interrupt frequency [hz] normal1/2, idle1/2 mode normal1/2, idle1/2 mode slow1/2, sleep1/2 mode dv7ck = 0 dv7ck = 1 000 1.91 1 1 001 7.63 4 4 010 244.14 128 ? 011 976.56 512 ? 100 1953.13 1024 ? 101 3906.25 2048 ? 110 7812.5 4096 ? 111 31250 16384 ? source clock enable tbt interrupt period tbtcr page 75 TMP86FS49AIFG 7.2 divider output ( dvo ) approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric buzzer drive. divider output is from dvo pin. 7.2.1 configuration figure 7-3 divider output 7.2.2 control the divider output is controlled by the time base timer control register. note: selection of divider output frequency (dvock) must be made whil e divider output is disabled (dvoen="0"). also, in other words, when changing the state of the divider output frequen cy from enabled (dvoen="1") to disable(dvoen="0"), do not change the setting of the divider output frequency. time base timer control register 7654 321 0 tbtcr (0036h) dvoen dvock (dv7ck) (tbten) (tbtck) (initial value: 0000 0000) dvoen divider output enable / disable 0: disable 1: enable r/w dvock divider output ( dvo ) frequency selection: [hz] normal1/2, idle1/2 mode slow1/2 sleep1/2 mode r/w dv7ck = 0 dv7ck = 1 00 fc/2 13 fs/2 5 fs/2 5 01 fc/2 12 fs/2 4 fs/2 4 10 fc/2 11 fs/2 3 fs/2 3 11 fc/2 10 fs/2 2 fs/2 2 tbtcr output latch port output latch mpx dvoen tbtcr page 76 7. time base timer (tbt) 7.2 divider output (dvo) TMP86FS49AIFG example :1.95 khz pulse output (fc = 16.0 mhz) ld (tbtcr) , 00000000b ; dvock "00" ld (tbtcr) , 10000000b ; dvoen "1" table 7-2 divider output frequency ( exam ple : fc = 16.0 mhz, fs = 32.768 khz ) dvock divider output frequency [hz] normal1/2, idle1/2 mode slow1/2, sleep1/2 mode dv7ck = 0 dv7ck = 1 00 1.953 k 1.024 k 1.024 k 01 3.906 k 2.048 k 2.048 k 10 7.813 k 4.096 k 4.096 k 11 15.625 k 8.192 k 8.192 k page 77 TMP86FS49AIFG 8. 16-bit timercounter 1 (tc1) 8.1 configuration figure 8-1 timercounter 1 (tc1) :::? pin tc1 :w:?::? mett1 start capture clear source clock ppg output mode write to tc1cr 16-bit up-counter clear tc1drb selector tc1dra tc1cr tc1 control register match inttc1 interript tff1 acap1 tc1ck window mode set toggle q 2 toggle set clear q y a d b c s b a y s tc1s clear mppg1 ppg output mode internal reset s enable mcap1 s y a b tc1s 2 set clear command start decoder external trigger start edge detector note: function i/o may not operate depending on i/o port setting. for more details, see the chapter "i/o port". port (note) q pulse width measurement mode falling rising trigger external cmp 16-bit timer register a, b pulse width measurement mode port (note) fc/2 11, fs/2 3 fc/2 7 fc/2 3 page 78 8. 16-bit timercounter 1 (tc1) 8.2 timercounter control TMP86FS49AIFG 8.2 timercounter control the timercounter 1 is controlled by the timercounter 1 control register (tc1cr) and two 16-bit timer registers (tc1dra and tc1drb). note 1: fc: high-frequency clock [hz], fs: low-frequency clock [hz] note 2: the timer register consists of two shift registers. a va lue set in the timer register becomes valid at the rising edge o f the first source clock pulse that occurs after the upper byte (t c1drah and tc1drbh) is written. therefore, write the lower byte and the upper byte in this order (it is recommended to write the register with a 16-bit acce ss instruction). writing only the lower byte (tc1dral and tc1drbl) does not enable the setting of the timer register. note 3: to set the mode, source clock, ppg output control and time r f/f control, write to tc1cr1 during tc1s=00. set the timer f/f1 control until the first timer start after setting the ppg mode. timer register 1514131211109876543210 tc1dra (0011h, 0010h) tc1drah (0011h) tc1dral (0010h) (initial value: 1111 1111 1111 1111) read/write tc1drb (0013h, 0012h) tc1drbh (0013h) tc1drbl (0012h) (initial value: 1111 1111 1111 1111) read/write (write e nabled only in the ppg output mode) timercounter 1 control register tc1cr (0026h) 76543210 tff1 acap1 mcap1 mett1 mppg1 tc1s tc1ck tc1m read/write (initial value: 0000 0000) tff1 timer f/f1 control 0: clear 1: set r/w acap1 auto capture control 0:auto-capture disable 1:auto-capture enable r/w mcap1 pulse width measure- ment mode control 0:double edge capture 1:single edge capture mett1 external trigger timer mode control 0:trigger start 1:trigger start and stop mppg1 ppg output control 0:continuous pulse generation 1:one-shot tc1s tc1 start control timer extrig- ger event win- dow pulse ppg r/w 00: stop and counter clear oooooo 01: command start o????o 10: rising edge start (ex-trigger/pulse/ppg) rising edge count (event) positive logic count (window) ? ooooo 11: falling edge start (ex-trigger/pulse/ppg) falling edge count (event) negative logic count (window) ? ooooo tc1ck tc1 source clock select [hz] normal1/2, idle1/2 mode divider slow, sleep mode r/w dv7ck = 0 dv7ck = 1 00 fc/2 11 fs/2 3 dv9 fs/2 3 01 fc/2 7 fc/2 7 dv5 ? 10 fc/2 3 fc/2 3 dv1 ? 11 external clock (tc1 pin input) tc1m tc1 operating mode select 00: timer/external trigger timer/event counter mode 01: window mode 10: pulse width measurement mode 11: ppg (programmable pulse generate) output mode r/w page 79 TMP86FS49AIFG note 4: auto-capture can be used only in t he timer, event counter, and window modes. note 5: to set the timer registers, the following relationship must be satisfied. tc1dra > tc1drb > 1 (ppg output mode), tc1dra > 1 (other modes) note 6: set tff1 to ?0? in the mode except ppg output mode. note 7: set tc1drb after setting tc1m to the ppg output mode. note 8: when the stop mode is entered, the start control (tc1s) is cleared to ?00? automatically, and the timer stops. after the stop mode is exited, set the tc1s to use the timer counter again. note 9: use the auto-capture function in the operative condition of tc1. a captured value may not be fixed if it's read after th e execution of the timer stop or auto-capture disable. read the capture value in a capture enabled condition. note 10:since the up-counter value is captured into tc1drb by the source clock of up-counter after setting tc1cr page 80 8. 16-bit timercounter 1 (tc1) 8.3 function TMP86FS49AIFG 8.3 function timercounter 1 has six types of operating modes: timer, external trigger timer, event counter, window, pulse width measurement, programmable pulse generator output modes. 8.3.1 timer mode in the timer mode, the up-counter counts up using the internal clock. when a match between the up-counter and the timer register 1a (tc1dra) value is detected, an inttc1 interr upt is generated and the up-counter is cleared. after being cleared, the up-counter restarts counting. setting tc1cr page 81 TMP86FS49AIFG figure 8-2 timer mode timing chart match detect acap1 tc1drb tc1dra inttc1 interruput request source clock counter source clock counter ? (a) timer mode (b) auto-capture ? 7 6 345 0 timer start 12 3 2 1 4 0 counter clear capture n + 1 n n n m + 2 m + 1 m m capture m + 2 m + 1 n + 1 n m ? 1 m ? 1 m ? 2 n ? 1 n ? 1 n ? 1 page 82 8. 16-bit timercounter 1 (tc1) 8.3 function TMP86FS49AIFG 8.3.2 external trigger timer mode in the external trigger timer mode, the up-counter starts counting by the input pulse triggering of the tc1 pin, and counts up at the edge of the internal clock. for the trigger edge used to start counting, either the rising or falling edge is defined in tc1cr page 83 TMP86FS49AIFG figure 8-3 external tri gger timer mode timing chart inttc1 interrupt request source clock up-counter tc1dra tc1 pin input inttc1 interrupt request source clock up-counter tc1dra tc1 pin input 0 at the rising edge (tc1s = 10) at the rising edge (tc1s = 10) (a) trigger start (mett1 = 0) count start match detect count start 0 1 2 3 4 2 3 n (b) trigger start and stop (mett1 = 1) count start count start 0 1 2 3 m 0 n n 0 count clear note: m < n count clear 1 2 3 1 n m ? 1 n ? 1 match detect count clear page 84 8. 16-bit timercounter 1 (tc1) 8.3 function TMP86FS49AIFG 8.3.3 event counter mode in the event counter mode, the up-counter counts up at the edge of the input pulse to the tc1 pin. either the rising or falling edge of the input pulse is se lected as the count up edge in tc1cr page 85 TMP86FS49AIFG 8.3.4 window mode in the window mode, the up-counter counts up at the rising edge of the pulse that is logical anded product of the input pulse to the tc1 pin (window pulse) and the internal source clock. eith er the positive logic (count up during high-going pulse) or negative logic (count up during low-going pulse) can be selected. when a match between the up-counter and the tc1dra va lue is detected, an inttc1 interrupt is generated and the up-counter is cleared. define the window pulse to the frequency which is sufficiently lower than the internal source clock pro- grammed with tc1cr page 86 8. 16-bit timercounter 1 (tc1) 8.3 function TMP86FS49AIFG 8.3.5 pulse width measurement mode in the pulse width measurement mode, the up-counter starts counting by the input pulse triggering of the tc1 pin, and counts up at the edge of the internal clock. either the rising or falling edge of the internal clock is selected as the trigger edge in tc1cr< tc1s>. either the single- or double-e dge capture is selected as the trig- ger edge in tc1cr page 87 TMP86FS49AIFG example :duty measurem ent (resolution fc/2 7 [hz]) clr (inttc1sw). 0 ; inttc1 serv ice switch initial setting address set to convert inttc1sw at each inttc1 ld (tc1cr), 00000110b ; sets the tc1 mode and source clock di ; imf = ?0? set (eirl). 5 ; enables inttc1 ei ; imf = ?1? ld (tc1cr), 00100110b ; starts tc1 with an external trigger at mcap1 = 0 : pinttc1: cpl (inttc1sw). 0 ; inttc1 interrupt, inverts and tests inttc1 service switch jrs f, sinttc1 ld a, (tc1drbl) ; reads tc1drb (high-level pulse width) ld w,(tc1drbh) ld (hpulse), wa ; stores high-level pulse width in ram reti sinttc1: ld a, (tc1drbl) ; reads tc1drb (cycle) ld w,(tc1drbh) ld (width), wa ; stores cycle in ram : reti ; duty calculation : vinttc1: dw pinttc1 ; inttc1 interrupt vector width hpulse tc1 pin inttc1 interrupt request inttc1sw page 88 8. 16-bit timercounter 1 (tc1) 8.3 function TMP86FS49AIFG figure 8-6 pulse wi dth measurement mode tc1drb inttc1 interrupt request interrupt request tc1 pin input counter internal clock (mcap1 = "1") 23 n count start count start trigger (tc1s = "10") 1 3 2 1 4 0 n 0 capture n - 1 tc1drb inttc1 tc1 pin input counter internal clock (mcap1 = "0") 12 n count start count start (tc1s = "10") 3 2 1 4 0 n capture capture n + 1 m - 2 n + 3 n + 2 n + 1 m - 1 m0 m [application] high-or low-level pulse width measurement [application] (1) cycle/frequency measurement (2) duty measurement (a) single-edge capture (b) double-edge capture page 89 TMP86FS49AIFG 8.3.6 programmable pulse generate (ppg) output mode in the programmable pulse generation (ppg) mode, an arbitrary duty pulse is generated by counting per- formed in the internal clock. to start the timer, tc1c r page 90 8. 16-bit timercounter 1 (tc1) 8.3 function TMP86FS49AIFG figure 8-7 ppg output example :generating a pulse which is high-going for 800 s and low-going for 200 s (fc = 16 mhz) setting port ld (tc1cr), 10000111b ; sets the ppg mode, selects the source clock ldw (tc1dra), 007dh ; sets the cycle (1 ms 2 7 /fc ms = 007dh) ldw (tc1drb), 0019h ; sets the low-level pulse width (200 s 2 7 /fc = 0019h) ld (tc1cr), 10010111b ; starts the timer example :after stopping ppg, setting the ppg pin to a high-level to restart ppg (fc = 16 mhz) setting port ld (tc1cr), 10000111b ; sets the ppg mode, selects the source clock ldw (tc1dra), 007dh ; sets the cycle (1 ms 2 7 /fc s = 007dh) ldw (tc1drb), 0019h ; sets the low-level pulse width (200 s 2 7 /fc = 0019h) ld (tc1cr), 10010111b ; starts the timer :: ld (tc1cr), 10000111b ; stops the timer ld (tc1cr), 10000100b ; sets the timer mode ld (tc1cr), 00000111b ; sets the ppg mode, tff1 = 0 ld (tc1cr), 00010111b ; starts the timer q r d ppg pin function output port output enable i/o port output latch shared with ppg output data output toggle set clear q tc1cr page 91 TMP86FS49AIFG figure 8-8 pp g mode timing chart inttc1 tc1dra internal clock counter tc1drb tc1dra ppg pin output 0 inttc1 interrupt request interrupt request 12 m01 2 n m01 n 2 n n + 1 n + 1 m (a) continuous pulse generation (tc1s = 01) tc1drb trigger count start timer start counter internal clock tc1 pin input ppg pin output 0 1m n n n + 1 m 0 (b) one-shot pulse generation (tc1s = 10) match detect note: m > n note: m > n [application] one-shot pulse output page 92 8. 16-bit timercounter 1 (tc1) 8.3 function TMP86FS49AIFG page 93 TMP86FS49AIFG 9. 16-bit timer/counter2 (tc2) 9.1 configuration note: when control input/output is used, i/o port setting should be set correctly. for det ails, refer to the section "i/o ports" . figure 9-1 time r/counter2 (tc2) c d f tc2 control register tc2 pin tc2cr 16-bit up counter tc2dr clear tc2s tc2ck source clock timer/ event counter window tc2s 16-bit timer register 2 3 h a b e s b a s y inttc2 interrupt port (note) cmp tc2m fc fs match fc/2 23, fs/2 15 fc/2 8 fc/2 3 fc/2 13, fs/2 5 page 94 9. 16-bit timer/counter2 (tc2) 9.2 control TMP86FS49AIFG 9.2 control the timer/counter 2 is controlled by a timer/counter 2 control register (tc2cr) and a 16-bit timer register 2 (tc2dr). note 1: fc: high-frequency clock [hz], fs : low-frequency clock [hz], *: don't care note 2: when writing to the timer register 2 (tc2dr), always write to the lower side (tc2drl) and then the upper side (tc2drh) in that order. writing to only the lower side (tc2drl) or the upper side (tc2drh) has no effect. note 3: the timer register 2 (tc2dr) uses the value previously set in it for coinci dence detection until data is written to the upper side (tc2drh) after writing data to the lower side (tc2drl). note 4: set the mode and source clock when the tc2 stops (tc2s = 0). note 5: values to be loaded to the timer regi ster must satisfy the following condition. tc2dr > 1 (tc2dr 15 to tc2dr 11 > 1 at warm up) note 6: if a read instruction is executed for tc2cr, read data of bit 7, 6 and 1 are unstable. note 7: the high-frequency clock (fc) can be selected only when the time mode at slow2 mode is selected. note 8: on entering stop mode, the tc2 start control (tc2s) is cl eared to "0" automatically. so, the timer stops. once the stop mode has been released, to start using the timer counter, set tc2s again. tc2dr (0025h, 0024h) 1514131211109876543210 tc2drh (0025h) tc2drl (0024h) (initial value: 1111 1111 1111 1111) r/w tc2cr (0023h) 76543210 tc2s tc2ck tc2m (initial value: **00 00*0) tc2s tc2 start control 0:stop and counter clear 1:start r/w tc2ck tc2 source clock select unit : [hz] normal1/2, idle1/2 mode divider slow1/2 mode sleep1/2 mode r/w dv7ck = 0 dv7ck = 1 000 fc/2 23 fs/2 15 dv21 fs/2 15 fs/2 15 001 fc/2 13 fs/2 5 dv11 fs/2 5 fs/2 5 010 fc/2 8 fc/2 8 dv6 ? ? 011 fc/2 3 fc/2 3 dv1 ? ? 100 ? ? ? fc (note7) ? 101 fs fs ? ? ? 110 reserved external clock (tc2 pin input) 111 tc2m tc2 operating mode select 0:timer/event counter mode 1:window mode r/w page 95 TMP86FS49AIFG 9.3 function the timer/counter 2 has three operating modes: timer, event counter and window modes. and if fc or fs is selected as th e source clock in timer mode, when sw itching the timer mode from slow1 to normal2, the timer/counter2 can generate warm-up time until the oscillator is stable. 9.3.1 timer mode in this mode, the internal clock is used for counting up. the contents of tc2dr are compared with the con- tents of up counter. if a match is found, a timer/counter 2 interrupt (inttc2) is generated, and the counter is cleared. counting up is resumed after the counter is cleared. when fc is selected for source cl ock at slow2 mode, lower 11-bits of tc2dr are ignored and generated a interrupt by matching upper 5-bits only. though, in this situation, it is necessary to set tc2drh only. note:when fc is selected as the source clock in timer mo de, it is used at warm-up for switching from slow1 mode to normal2 mode. table 9-1 source clock (internal clock) for timer/counter2 (at fc = 16 mhz, dv7ck=0) tc2c k normal1/2, idle1/2 mode slow1/2 mode sleep1/2 mode dv7ck = 0 dv7ck = 1 resolution maximum time set- ting resolution maximum time set- ting resolu- tion maxi- mum time setting resolu- tion maxi- mum time setting 000 524.29 [ms] 9.54 [h] 1 [s] 18.2 [h] 1 [s] 18.2 [h] 1 [s] 18.2 [h] 001 512.0 [ms] 33.55 [s] 0.98 [ms] 1.07 [min] 0.98 [ms] 1.07 [min] 0.98 [ms] 1.07 [min] 010 16.0 [ms] 1.05 [s] 16.0 [ms] 1.05 [s] ? ? ? ? 011 0.5 [ms] 32.77 [ms] 0.5 [ms] 32.77 [ms] ? ? ? ? 100 ? ? ? ? 62.5 [ns] ? ? ? 101 30.52 [ms] 2 [s] 30.52 [ms] 2 [s] ? ? ? ? example :sets the timer m ode with source clock fc/2 3 [hz] and generates an interrupt every 25 ms (at fc = 16 mhz ) ldw (tc2dr), 061ah ; sets tc2dr (25 ms 2 8 /fc = 061ah) di ; imf= ?0? set (eire). 6 ; enables inttc2 interrupt ei ; imf= ?1? ld (tc2cr), 00001000b ; source clock / mode select ld (tc2cr), 00101000b ; starts timer page 96 9. 16-bit timer/counter2 (tc2) 9.3 function TMP86FS49AIFG figure 9-2 timer mode timing chart inttc2 interrupt source clock up-counter tc2dr match detect counter clear timer start 01234 n 0 123 :? page 97 TMP86FS49AIFG 9.3.2 event counter mode in this mode, events are counted on the rising edge of the tc2 pin input. the contents of tc2dr are com- pared with the contents of the up counter. if a match is found, an inttc2 interrupt is generated, and the counter is cleared. counting up is resumed every the rising edge of the tc2 pin input after the up counter is cleared. match detect is executed on the falling edge of the tc2 pin. therefore, an inttc2 interrupt is generated at the falling edge after the match of tc2dr and up counter. the minimum input pulse width of tc2 pin is shown in table 9-2. two or more machine cycles are required for both the ?h? and ?l? levels of the pulse width. figure 9-3 event c ounter mode timing chart 9.3.3 window mode in this mode, counting up performed on the rising edge of an internal clock during tc2 external pin input (window pulse) is ?h? level. the contents of tc2dr are co mpared with the contents of up counter. if a match found, an inttc2 interrupt is genera ted, and the up-counter is cleared. the maximum applied frequency (tc2 input) must be considerably slower than the selected internal clock by the tc2cr page 98 9. 16-bit timer/counter2 (tc2) 9.3 function TMP86FS49AIFG figure 9-4 window mode timing chart example :generates an interrupt , inputting ?h? level pulse width of 120 ms or more. (at fc = 16 mhz, tbtcr page 99 TMP86FS49AIFG 10. 8-bit timercounter (tc3, tc4) 10.1 configuration figure 10-1 8-bit timercouter 3, 4 8-bit up-counter decode en a y b s a b y c d e f g h s a y b s s a y b toggle q set clear 8-bit up-counter a b y c d e f g h s decode en toggle q set clear pwm mode pdo, ppg mode pdo mode pwm, ppg mode pwm mode pwm mode 16-bit mode 16-bit mode 16-bit mode 16-bit mode timer, event counter mode overflow overflow timer, event couter mode 16-bit mode clear clear fc/2 7 fc/2 5 fc/2 3 fc/2 fc fc/2 7 fc/2 5 fc/2 3 fc/2 fc pdo, pwm, ppg mode pdo, pwm mode 16-bit mode fc/2 11 or fs/2 3 fc/2 11 or fs/2 3 fs fs tc4cr tc3cr ttreg4 pwreg4 ttreg3 pwreg3 tc3 pin tc4 pin tc4s tc3s inttc3 interrupt request inttc4 interrupt request tff4 tff3 pdo 4/pwm 4/ ppg 4 pin pdo 3/pwm 3/ pin tc3ck tc4ck tc3m tc3s tff3 tc4m tc4s tff4 timer f/f4 timer f/f3 page 100 10. 8-bit timercounter (tc3, tc4) 10.1 configuration TMP86FS49AIFG 10.2 timercounter control the timercounter 3 is controlled by the timercounter 3 control register (tc3cr) and two 8-bit timer registers (ttreg3, pwreg3). note 1: do not change the timer register (t treg3) setting while the timer is running. note 2: do not change the timer register (pwreg3) setting in the operating mode except the 8-bit and 16-bit pwm modes while the timer is running. note 1: fc: high-frequency clock [hz] fs: low-frequency clock[hz] note 2: do not change the tc3m, tc3ck and tff3 settings while the timer is running. note 3: to stop the timer operation (tc3s= 1 0), do not change the tc3m, tc3ck and tff3 settings. to start the timer oper- ation (tc3s= 0 1), tc3m, tc3ck and tff3 can be programmed. note 4: to use the timercounter in the 16-bit mode, set th e operating mode by programming tc4cr page 101 TMP86FS49AIFG note 7: the timer register settings are limited depending on t he timer operating mode. for the detailed descriptions, see table 10- 3. note 8: the operating clock fc in t he slow or sleep mode can be used only as the high-frequency warm-up mode. page 102 10. 8-bit timercounter (tc3, tc4) 10.1 configuration TMP86FS49AIFG the timercounter 4 is controlled by the timercounter 4 control register (tc4cr) and two 8-bit timer registers (ttreg4 and pwreg4). note 1: do not change the timer register (t treg4) setting while the timer is running. note 2: do not change the timer register (pwreg4) setting in the operating mode except the 8-bit and 16-bit pwm modes while the timer is running. note 1: fc: high-frequency clock [hz] fs: low-frequency clock [hz] note 2: do not change the tc4m, tc4ck and tff4 settings while the timer is running. note 3: to stop the timer operation (tc4s= 1 0), do not change the tc4m, tc4ck and tff4 settings. to start the timer operation (tc4s= 0 1), tc4m, tc4ck and tff4 can be programmed. note 4: when tc4m= 1** (upper byte in the 16-bit mode), the sour ce clock becomes the tc4 over flow signal regardless of the tc3ck setting. note 5: to use the timercounter in the 16-bit mode, select the operating mode by programming tc4m, where tc3cr page 103 TMP86FS49AIFG note 6: to the timercounter in the 16-bit mode, select the so urce clock by programming tc3cr page 104 10. 8-bit timercounter (tc3, tc4) 10.1 configuration TMP86FS49AIFG note: n = 3 to 4 table 10-3 constraints on register values being compared operating mode register value 8-bit timer/event counter 1 (ttregn) 255 8-bit pdo 1 (ttregn) 255 8-bit pwm 2 (pwregn) 254 16-bit timer/event counter 1 (ttreg4, 3) 65535 warm-up counter 256 (ttreg4, 3) 65535 16-bit pwm 2 (pwreg4, 3) 65534 16-bit ppg 1 (pwreg4, 3) < (ttreg4, 3) 65535 and (pwreg4, 3) + 1 < (ttreg4, 3) page 105 TMP86FS49AIFG 10.3 function the timercounter 3 and 4 have the 8-bit timer, 8-bit ev ent counter, 8-bit programmable divider output (pdo), 8- bit pulse width modulation (pwm) output modes. the time rcounter 3 and 4 (tc3, 4) are cascadable to form a 16- bit timer. the 16-bit timer has the operat ing modes such as the 16-bit timer, 16-bit event counter, warm-up counter, 16-bit pulse width modulation (pwm) output and 16-bit programmable pulse generation (ppg) modes. 10.3.1 8-bit timer mode (tc3 and 4) in the timer mode, the up-counter counts up using the internal clock. when a match between the up-counter and the timer register j (ttregj) value is detected, an inttcj interrupt is generated and the up-counter is cleared. after being cl eared, the up-counter restarts counting. note 1: in the timer mode, fix tcjcr page 106 10. 8-bit timercounter (tc3, tc4) 10.1 configuration TMP86FS49AIFG figure 10-2 8-bit timer mode timing chart (tc4) 10.3.2 8-bit event counter mode (tc3, 4) in the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the tcj pin. when a match between the up-counter and the ttregj valu e is detected, an inttcj interrupt is generated and the up-counter is cleared. after being cleared, the up-counter restarts counti ng at the falling edge of the input pulse to the tcj pin. two machine cycles are required for the low- or high-level pulse input to the tcj pin. therefore, a maximum freque ncy to be supplied is fc/2 4 hz in the normal1/2 or idle1/2 mode, and fs/2 4 hz in the slow1/2 or sleep1/2 mode. note 1: in the event counter mode, fix tcjcr page 107 TMP86FS49AIFG note 1: in the programmable divider output mode, do not change the ttregj setting while the timer is running. since ttregj is not in the shift register configur ation in the programmable divider output mode, the new value programmed in ttregj is in effect immediatel y after programming. therefore, if ttregi is changed while the timer is running, an ex pected operation may not be obtained. note 2: when the timer is stopped during pdo output, the pdoj pin holds the output status when the timer is stopped. to change the output status, program tcjcr page 108 10. 8-bit timercounter (tc3, tc4) 10.1 configuration TMP86FS49AIFG figure 10-4 8-bi t pdo mode timing chart (tc4) 12 0 n 0 n 0 n 0 n 0 1 2 2 1 2 1 2 3 1 0 n ? internal source clock counter match detect match detect match detect match detect held at the level when the timer is stopped set f/f write of "1" tc4cr page 109 TMP86FS49AIFG 10.3.4 8-bit pulse width modulat ion (pwm) output mode (tc3, 4) this mode is used to generate a pulse-width modulated (pwm) signals with up to 8 bits of resolution. the up-counter counts up using the internal clock. when a match between the up-counter and the pwregj value is detected, the logic level output from the timer f/fj is switched to the opposite state. the counter continues counting. the logic level output from the timer f/fj is switched to the opposite state again by the up-co unter overflow, and the counter is cleared. the inttcj interrupt request is generated at this time. since the initial value can be set to the timer f/fj by tcjcr page 110 10. 8-bit timercounter (tc3, tc4) 10.1 configuration TMP86FS49AIFG figure 10-5 8-bit pwm mode timing chart (tc4) 1 0 n n+1 ff 0 n n+1 ff 0 1 m m+1 ff 0 1 1 p n ? internal source clock counter write to pwreg4 write to pwreg4 m p m p n ? shift registar shift shift shift shift match detect match detect one cycle period match detect match detect n m p n tc4cr page 111 TMP86FS49AIFG 10.3.5 16-bit time r mode (tc3 and 4) in the timer mode, the up-counter counts up using the internal clock. the timercounter 3 and 4 are cascad- able to form a 16-bit timer. when a match between the up-counter and the timer regi ster (ttreg3, ttreg4) valu e is detected after the timer is started by setting tc4cr page 112 10. 8-bit timercounter (tc3, tc4) 10.1 configuration TMP86FS49AIFG 10.3.6 16-bit event c ounter mode (tc3 and 4) 10.3.7 16-bit pulse wi dth modulation (pwm) ou tput mode (tc3 and 4) this mode is used to generate a pulse-width modulated (pwm) signals with up to 16 bits of resolution. the timercounter 3 and 4 are cascadable to form the 16-bit pwm signal generator. the counter counts up using the internal clock or external clock. when a match between the up-counter and the timer register (pwreg3, pwreg4) value is detected, the logic level output from the timer f/f4 is switched to the opposite state. the counter continues counting. the logic level output from the timer f/f4 is switched to the opposite state again by the counter overflow, and the counter is cleared. the inttc4 interrupt is generated at this time. two machine cycles are required for the high- or low-level pulse input to the tc3 pin. therefore, a maxi- mum frequency to be supplied is fc/2 4 hz in the normal1 or idle1 mode, and fs/2 4 to in the slow1/2 or sleep1/2 mode. since the initial value can be set to the timer f/f4 by tc4cr page 113 TMP86FS49AIFG clr (tc4cr).3: stops the timer. clr (tc4cr).7 : sets the pwm 4 pin to the high level. note 3: to enter the stop mode, stop the timer and then enter the stop mode. if the stop mode is entered with- out stopping of the timer when fc, fc/2 or fs is select ed as the source clock, a pulse is output from the pwm 4 pin during the warm-up period time after exiting the stop mode. table 10-7 16-bit pwm output mode source clock resolution repeated cycle normal1/2, idle1/2 mode slow1/2, sleep1/2 mode fc = 16 mhz fs = 32.768 khz fc = 16 mhz fs = 32.768 khz dv7ck = 0 dv7ck = 1 fc/2 11 fs/2 3 [hz] fs/2 3 [hz] 128 s244.14 s 8.39 s 16 s fc/2 7 fc/2 7 ?8 s ? 524.3 ms ? fc/2 5 fc/2 5 ?2 s ? 131.1 ms ? fc/2 3 fc/2 3 ? 500ns ? 32.8 ms ? fs fs fs 30.5 s30.5 s2 s 2 s fc/2 fc/2 ? 125 ns ? 8.2 ms ? fc fc ? 62.5 ns ? 4.1 ms ? example :generating a pulse with 1-ms high-level width and a period of 32.768 ms (fc = 16.0 mhz) setting ports ldw (pwreg3), 07d0h : sets the pulse width. ld (tc3cr), 33h : sets the operating clock to fc/2 3 , and 16-bit pwm output mode (lower byte). ld (tc4cr), 056h : sets tff4 to the initial value 0, and 16-bit pwm signal generation mode (upper byte). ld (tc4cr), 05eh : starts the timer. page 114 10. 8-bit timercounter (tc3, tc4) 10.1 configuration TMP86FS49AIFG figure 10-7 16-bit pwm mode timing chart (tc3 and tc4) 1 0 an an+1 ffff 0 an an+1 ffff 0 1 bm bm+1 ffff 0 bm cp b c 1 1 cp n a an ? ? ? internal source clock 16-bit shift register shift shift shift shift counter match detect match detect one cycle period match detect match detect an bm cp an m p tc4cr page 115 TMP86FS49AIFG 10.3.8 16-bit programmable pulse generate (ppg) ou tput mode (tc3 and 4) this mode is used to generate pulses with up to 16- bits of resolution. the timer counter 3 and 4 are cascad- able to enter the 16-bit ppg mode. the counter counts up using the inte rnal clock or external clock. when a match between the up-counter and the timer register (pwreg3, pwreg4 ) value is detected, the logic level output from the timer f/f4 is switched to the opposite state. the counter continues counting. the logic level output from the timer f/f4 is switched to the opposite state again when a match betw een the up-counter and th e timer register (ttreg3, ttreg4) value is detected, and the counter is cleared. the inttc4 interrupt is generated at this time. since the initial value can be set to the timer f/f4 by tc4cr page 116 10. 8-bit timercounter (tc3, tc4) 10.1 configuration TMP86FS49AIFG figure 10-8 16-bit ppg mode timing chart (tc3 and tc40) 1 0 mn mn+1 qr-1 mn qr-1 1 mn mn+1 mn+1 0 qr 0 qr 1 0 internal source clock counter write of "0" match detect match detect match detect mn mn mn match detect match detect ? n m ? ? r q ? held at the level when the timer stops f/f clear tc4cr page 117 TMP86FS49AIFG 10.3.9 warm-up counter mode in this mode, the warm-up period time is obtained to assure oscillation stability when the system clocking is switched between the high-frequency and low-frequency. the timer counter 3 and 4 are cascadable to form a 16-bit timercouter. the warm-up counter mode has two types of mode; switching from the high-frequency to low-frequency, and vice-versa. note 1: in the warm-up counter mode, fi x tcicr page 118 10. 8-bit timercounter (tc3, tc4) 10.1 configuration TMP86FS49AIFG 10.3.9.2 high-frequency warm-up counter mode (slow1 slow2 normal2 normal1) in this mode, the warm-up period time from a stop of the high-frequency clock fc to the oscillation sta- bility is obtained. before starting the timer, set sy scr2 page 119 TMP86FS49AIFG 11. 8-bit timercounter (tc5, tc6) 11.1 configuration figure 11-1 8-bit timercouter 5, 6 8-bit up-counter decode en a y b s a b y c d e f g h s a y b s s a y b toggle q set clear 8-bit up-counter a b y c d e f g h s decode en toggle q set clear pwm mode pdo, ppg mode pdo mode pwm, ppg mode pwm mode pwm mode 16-bit mode 16-bit mode 16-bit mode 16-bit mode timer, event counter mode overflow overflow timer, event couter mode 16-bit mode clear clear fc/2 7 fc/2 5 fc/2 3 fc/2 fc fc/2 7 fc/2 5 fc/2 3 fc/2 fc pdo, pwm, ppg mode pdo, pwm mode 16-bit mode fc/2 11 or fs/2 3 fc/2 11 or fs/2 3 fs fs tc6cr tc5cr ttreg6 pwreg6 ttreg5 pwreg5 tc5 pin tc6 pin tc6s tc5s inttc5 interrupt request inttc6 interrupt request tff6 tff5 pdo 6/pwm 6/ ppg 6 pin pdo 5/pwm 5/ pin tc5ck tc6ck tc5m tc5s tff5 tc6m tc6s tff6 timer f/f6 timer f/f5 page 120 11. 8-bit timercounter (tc5, tc6) 11.1 configuration TMP86FS49AIFG 11.2 timercounter control the timercounter 5 is controlled by the timercounter 5 control register (tc5cr) and two 8-bit timer registers (ttreg5, pwreg5). note 1: do not change the timer register (t treg5) setting while the timer is running. note 2: do not change the timer register (pwreg5) setting in the operating mode except the 8-bit and 16-bit pwm modes while the timer is running. note 1: fc: high-frequency clock [hz] fs: low-frequency clock[hz] note 2: do not change the tc5m, tc5ck and tff5 settings while the timer is running. note 3: to stop the timer operation (tc5s= 1 0), do not change the tc5m, tc5ck and tff5 settings. to start the timer oper- ation (tc5s= 0 1), tc5m, tc5ck and tff5 can be programmed. note 4: to use the timercounter in the 16-bit mode, set th e operating mode by programming tc6cr page 121 TMP86FS49AIFG note 7: the timer register settings are limited depending on the timer operating mode. for the detailed descriptions, see table 11- 3. note 8: the operating clock fc in t he slow or sleep mode can be used only as the high-frequency warm-up mode. page 122 11. 8-bit timercounter (tc5, tc6) 11.1 configuration TMP86FS49AIFG the timercounter 6 is controlled by the timercounter 6 control register (tc6cr) and two 8-bit timer registers (ttreg6 and pwreg6). note 1: do not change the timer register (t treg6) setting while the timer is running. note 2: do not change the timer register (pwreg6) setting in the operating mode except the 8-bit and 16-bit pwm modes while the timer is running. note 1: fc: high-frequency clock [hz] fs: low-frequency clock [hz] note 2: do not change the tc6m, tc6ck and tff6 settings while the timer is running. note 3: to stop the timer operation (tc6s= 1 0), do not change the tc6m, tc6ck and tff6 settings. to start the timer operation (tc6s= 0 1), tc6m, tc6ck and tff6 can be programmed. note 4: when tc6m= 1** (upper byte in the 16-bit mode), the sour ce clock becomes the tc6 over flow signal regardless of the tc5ck setting. note 5: to use the timercounter in the 16-bit mode, select the operating mode by programming tc6m, where tc5cr page 123 TMP86FS49AIFG note 6: to the timercounter in the 16-bit mode, select the so urce clock by programming tc5cr page 124 11. 8-bit timercounter (tc5, tc6) 11.1 configuration TMP86FS49AIFG note: n = 5 to 6 table 11-3 constraints on register values being compared operating mode register value 8-bit timer/event counter 1 (ttregn) 255 8-bit pdo 1 (ttregn) 255 8-bit pwm 2 (pwregn) 254 16-bit timer/event counter 1 (ttreg6, 5) 65535 warm-up counter 256 (ttreg6, 5) 65535 16-bit pwm 2 (pwreg6, 5) 65534 16-bit ppg 1 (pwreg6, 5) < (ttreg6, 5) 65535 and (pwreg6, 5) + 1 < (ttreg6, 5) page 125 TMP86FS49AIFG 11.3 function the timercounter 5 and 6 have the 8-bit timer, 8-bit ev ent counter, 8-bit programmable divider output (pdo), 8- bit pulse width modulation (pwm) output modes. the time rcounter 5 and 6 (tc5, 6) are cascadable to form a 16- bit timer. the 16-bit timer has the operat ing modes such as the 16-bit timer, 16-bit event counter, warm-up counter, 16-bit pulse width modulation (pwm) output and 16-bit programmable pulse generation (ppg) modes. 11.3.1 8-bit timer mode (tc5 and 6) in the timer mode, the up-counter counts up using the internal clock. when a match between the up-counter and the timer register j (ttregj) value is detected, an inttcj interrupt is generated and the up-counter is cleared. after being cl eared, the up-counter restarts counting. note 1: in the timer mode, fix tcjcr page 126 11. 8-bit timercounter (tc5, tc6) 11.1 configuration TMP86FS49AIFG figure 11-2 8-bit time r mode timing chart (tc6) 11.3.2 8-bit event counter mode (tc5, 6) in the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the tcj pin. when a match between the up-counter and the ttregj valu e is detected, an inttcj interrupt is generated and the up-counter is cleared. after being cleared, the up-counter restarts counti ng at the falling edge of the input pulse to the tcj pin. two machine cycles are required for the low- or high-level pulse input to the tcj pin. therefore, a maximum freque ncy to be supplied is fc/2 4 hz in the normal1/2 or idle1/2 mode, and fs/2 4 hz in the slow1/2 or sleep1/2 mode. note 1: in the event counter mode, fix tcjcr page 127 TMP86FS49AIFG note 1: in the programmable divider output mode, do not change the ttregj setting while the timer is running. since ttregj is not in the shift register configur ation in the programmable divider output mode, the new value programmed in ttregj is in effect immediatel y after programming. therefore, if ttregi is changed while the timer is running, an ex pected operation may not be obtained. note 2: when the timer is stopped during pdo output, the pdoj pin holds the output status when the timer is stopped. to change the output status, program tcjcr page 128 11. 8-bit timercounter (tc5, tc6) 11.1 configuration TMP86FS49AIFG figure 11-4 8-bit pdo mode timing chart (tc6) 12 0 n 0 n 0 n 0 n 0 1 2 2 1 2 1 2 3 1 0 n ? internal source clock counter match detect match detect match detect match detect held at the level when the timer is stopped set f/f write of "1" tc6cr page 129 TMP86FS49AIFG 11.3.4 8-bit pulse width modulat ion (pwm) output mode (tc5, 6) this mode is used to generate a pulse-width modulated (pwm) signals with up to 8 bits of resolution. the up-counter counts up using the internal clock. when a match between the up-counter and the pwregj value is detected, the logic level output from the timer f/fj is switched to the opposite state. the counter continues counting. the logic level output from the timer f/fj is switched to the opposite state again by the up-co unter overflow, and the counter is cleared. the inttcj interrupt request is generated at this time. since the initial value can be set to the timer f/fj by tcjcr page 130 11. 8-bit timercounter (tc5, tc6) 11.1 configuration TMP86FS49AIFG figure 11-5 8-bit pwm mode timing chart (tc6) 1 0 n n+1 ff 0 n n+1 ff 0 1 m m+1 ff 0 1 1 p n ? internal source clock counter write to pwreg4 write to pwreg4 m p m p n ? shift registar shift shift shift shift match detect match detect one cycle period match detect match detect n m p n tc6cr page 131 TMP86FS49AIFG 11.3.5 16-bit timer mode (tc5 and 6) in the timer mode, the up-counter counts up using the internal clock. the timercounter 5 and 6 are cascad- able to form a 16-bit timer. when a match between the up-counter and the timer regi ster (ttreg5, ttreg6) valu e is detected after the timer is started by setting tc6cr page 132 11. 8-bit timercounter (tc5, tc6) 11.1 configuration TMP86FS49AIFG 11.3.6 16-bit event c ounter mode (tc5 and 6) 11.3.7 16-bit pulse width modulatio n (pwm) output mode (tc5 and 6) this mode is used to generate a pulse-width modulated (pwm) signals with up to 16 bits of resolution. the timercounter 5 and 6 are cascadable to form the 16-bit pwm signal generator. the counter counts up using the internal clock or external clock. when a match between the up-counter and the timer register (pwreg5, pwreg6) value is detected, the logic level output from the timer f/f6 is switched to the opposite state. the counter continues counting. the logic level output from the timer f/f6 is switched to the opposite state again by the counter overflow, and the counter is cleared. the inttc6 interrupt is generated at this time. two machine cycles are required for the high- or low-level pulse input to the tc5 pin. therefore, a maxi- mum frequency to be supplied is fc/2 4 hz in the normal1 or idle1 mode, and fs/2 4 to in the slow1/2 or sleep1/2 mode. since the initial value can be set to the timer f/f6 by tc6cr page 133 TMP86FS49AIFG clr (tc6cr).3: stops the timer. clr (tc6cr).7 : sets the pwm 6 pin to the high level. note 3: to enter the stop mode, stop the timer and then enter the stop mode. if the stop mode is entered with- out stopping of the timer when fc, fc/2 or fs is select ed as the source clock, a pulse is output from the pwm 6 pin during the warm-up period time after exiting the stop mode. table 11-7 16-bit pwm output mode source clock resolution repeated cycle normal1/2, idle1/2 mode slow1/2, sleep1/2 mode fc = 16 mhz fs = 32.768 khz fc = 16 mhz fs = 32.768 khz dv7ck = 0 dv7ck = 1 fc/2 11 fs/2 3 [hz] fs/2 3 [hz] 128 s244.14 s 8.39 s 16 s fc/2 7 fc/2 7 ?8 s ? 524.3 ms ? fc/2 5 fc/2 5 ?2 s ? 131.1 ms ? fc/2 3 fc/2 3 ? 500ns ? 32.8 ms ? fs fs fs 30.5 s30.5 s2 s 2 s fc/2 fc/2 ? 125 ns ? 8.2 ms ? fc fc ? 62.5 ns ? 4.1 ms ? example :generating a pulse with 1-ms high-level width and a period of 32.768 ms (fc = 16.0 mhz) setting ports ldw (pwreg5), 07d0h : sets the pulse width. ld (tc5cr), 33h : sets the operating clock to fc/2 3 , and 16-bit pwm output mode (lower byte). ld (tc6cr), 056h : sets tff6 to the initial value 0, and 16-bit pwm signal generation mode (upper byte). ld (tc6cr), 05eh : starts the timer. page 134 11. 8-bit timercounter (tc5, tc6) 11.1 configuration TMP86FS49AIFG figure 11-7 16-bit pwm mode timing chart (tc5 and tc6) 1 0 an an+1 ffff 0 an an+1 ffff 0 1 bm bm+1 ffff 0 bm cp b c 1 1 cp n a an ? ? ? internal source clock 16-bit shift register shift shift shift shift counter match detect match detect one cycle period match detect match detect an bm cp an m p tc6cr page 135 TMP86FS49AIFG 11.3.8 16-bit programmable pulse generate (ppg) ou tput mode (tc5 and 6) this mode is used to generate pulses with up to 16- bits of resolution. the timer counter 5 and 6 are cascad- able to enter the 16-bit ppg mode. the counter counts up using the inte rnal clock or external clock. when a match between the up-counter and the timer register (pwreg5, pwreg6 ) value is detected, the logic level output from the timer f/f6 is switched to the opposite state. the counter continues counting. the logic level output from the timer f/f6 is switched to the opposite state again when a match betw een the up-counter and th e timer register (ttreg5, ttreg6) value is detected, and the counter is cleared. the inttc6 interrupt is generated at this time. since the initial value can be set to the timer f/f6 by tc6cr page 136 11. 8-bit timercounter (tc5, tc6) 11.1 configuration TMP86FS49AIFG figure 11-8 16-bit ppg mode timing chart (tc5 and tc60) 1 0 mn mn+1 qr-1 mn qr-1 1 mn mn+1 mn+1 0 qr 0 qr 1 0 internal source clock counter write of "0" match detect match detect match detect mn mn mn match detect match detect ? n m ? ? r q ? held at the level when the timer stops f/f clear tc6cr page 137 TMP86FS49AIFG 11.3.9 warm-up counter mode in this mode, the warm-up period time is obtained to assure oscillation stability when the system clocking is switched between the high-frequency and low-frequency. the timer counter 5 and 6 are cascadable to form a 16-bit timercouter. the warm-up counter mode has two types of mode; switching from the high-frequency to low-frequency, and vice-versa. note 1: in the warm-up counter mode, fi x tcicr page 138 11. 8-bit timercounter (tc5, tc6) 11.1 configuration TMP86FS49AIFG 11.3.9.2 high-frequency warm-up counter mode (slow1 slow2 normal2 normal1) in this mode, the warm-up period time from a stop of the high-frequency clock fc to the oscillation sta- bility is obtained. before starting the timer, set sy scr2 page 139 TMP86FS49AIFG 12. asynchronous serial interface (uart1 ) 12.1 configuration figure 12-1 uart1 (asynch ronous serial interface) counter y a b c s s a b c d y e f g h uart status register uart control register 2 uart control register 1 transmit data buffer receive data buffer fc/13 fc/26 fc/52 fc/104 fc/208 fc/416 fc/96 stop bit parity bit fc/2 6 fc/2 7 fc/2 8 baud rate generator transmit/receive clock 2 4 3 2 2 2 noise rejection circuit m p x transmit control circuit shift register shift register receive control circuit mpx: multiplexer uart1cr1 td1buf rd1buf inttxd1 intrxd1 uart1sr uart1cr2 rxd1 txd1 inttc3 page 140 12. asynchronous serial interface (uart1 ) 12.2 control TMP86FS49AIFG 12.2 control uart1 is controlled by the uart1 control registers (uart1cr1, uart1cr2). the operating status can be monitored using the uart status register (uart1sr). note 1: when operations are disabled by se tting txe and rxe bit to ?0?, the setting be comes valid when data transmit or receive complete. when the transmit data is stored in the transmit data buffer, the data are not transmitted. even if data transmit is enabled, until new data are written to the transmit data buffer, the current data are not transmitted. note 2: the transmit clock and the parity are common to transmit and receive. note 3: uart1cr1 page 141 TMP86FS49AIFG note: when an inttxd is generated, tbep flag is set to "1" automatically. uart1 status register uart1sr (0f95h) 76543210 perr ferr oerr rbfl tend tbep (initial value: 0000 11**) perr parity error flag 0: 1: no parity error parity error read only ferr framing error flag 0: 1: no framing error framing error oerr overrun error flag 0: 1: no overrun error overrun error rbfl receive data buffer full flag 0: 1: receive data buffer empty receive data buffer full tend transmit end flag 0: 1: on transmitting transmit end tbep transmit data buffer empty flag 0: 1: transmit data buffer full (transmit data writing is finished) transmit data buffer empty uart1 receive data buffer rd1buf (0f97h) 76543210read only (initial value: 0000 0000) uart1 transmit data buffer td1buf (0f97h) 76543210write only (initial value: 0000 0000) page 142 12. asynchronous serial interface (uart1 ) 12.3 transfer data format TMP86FS49AIFG 12.3 transfer data format in uart1, an one-bit start bit (low level), stop bit (b it length selectable at high level, by uart1cr1 page 143 TMP86FS49AIFG 12.4 transfer rate the baud rate of uart1 is set of uart1cr1 |