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features ? two different if receiving bandwidth versions are available (b if = 300 khz or 600 khz) frequency receiving range of f 0 = 868 mhz to 870 mhz or f 0 =902mhz to 928mhz 30 db image rejection receiving bandwidth b if = 600 khz for low cost 90-ppm crystals and b if = 300 khz for 55 ppm crystals fully integrated lc-vco and pll loop filter very high sensitivity with power matched lna high system iip3 (?16 dbm), system 1-db compression point (?25 dbm) high large-signal capability at gsm band (blocking ?30 dbm at +20 mhz, iip3 = ?12 dbm at +20 mhz) 5v to 20v automotive compatible data interface data clock available for manchest er- and bi-phase-coded signals programmable digital noise suppression low power consumption due to configurable polling temperature range ?40c to +105c esd protection 2 kv hbm, all pins communication to microcontroller possible via a single bi-directional data line low-cost solution due to high integratio n level with minimum external circuitry requirements 1. description the ATA5760/ata5761 is a multi-chip pll receiver device supplied in an so20 pack- age. it has been especially developed for the demands of rf low-cost data transmission systems with data rates from 1 kbaud to 10 kbaud in manchester or bi-phase code. the receiver is well suited to operate with the atmel?s pll rf trans- mitter t5750. its main applications are in the areas of telemetering, security technology and keyless-entry systems. it can be used in the frequency receiving range of f 0 = 868 mhz to 870 mhz or f 0 = 902 mhz to 928 mhz for ask or fsk data transmission. all the statements made below refer to 868.3 mhz and 915.0 mhz applications. figure 1-1. system block diagram demod. if amp lna vco pll xto control ATA5760/ ata5761 1...5 c power amp. xto vco pll t5750 antenna antenna uhf ask/fsk remote control transmitter uhf ask/fsk remote control receiver uhf ask/fsk receiver ATA5760 ata5761 4896c?rke?04/06
2 4896c?rke?04/06 ATA5760/ata5761 figure 1-2. block diagram sens cdem avcc agnd dgnd lnagnd lna_in data polling/_on data_clk dvcc xtal polling circuit and control logic rssi limiter out poly-lpf fg = 7 mhz lc-vco f :256 xto standby logic fe clk fsk/ask- demodulator and data filter rssi if amp. lna 4. order f0 = 950 khz/ dem_out sensitivity- reduction lpf fg = 2.2 mhz if amp. ic_active data - interface lnaref f :2 loop- filter 1 mhz
3 4896c?rke?04/06 ATA5760/ata5761 2. pin configuration figure 2-1. pinning so20 1 2 3 4 5 6 7 8 10 9 19 18 17 16 14 15 13 12 11 20 avcc test 1 agnd nc lnaref lna_in ic_active cdem data_clk test 4 xtal nc test 3 dgnd lnagnd test 2 data dvcc sens ATA5760/ ata5761 table 2-1. pin description pin symbol function 1 sens sensitivity-control resistor 2 ic_active ic condition indicator: low = sleep mode, high = active mode 3 cdem lower cut-off frequency data filter 4 avcc analog power supply 5 test 1 test pin, during operation at gnd 6 agnd analog ground 7 nc not connected, connect to gnd 8 lnaref high-frequency reference node lna and mixer 9 lna_in rf input 10 lnagnd dc ground lna and mixer 11 test 2 do not connect during operating 12 test 3 test pin, during operation at gnd 13 nc not connected, connect to gnd 14 xtal crystal oscillator xtal connection 15 dvcc digital power supply 16 test 4 test pin, during operation at dvcc 17 data_clk bit clock of data stream 18 dgnd digital ground 19 polling/_on selects polling or receiving mode; low: receiving mode, high: polling mode 20 data data output/configuration input
4 4896c?rke?04/06 ATA5760/ata5761 3. rf front end the rf front end of the receiver is a low-if heterodyne configuration that converts the input sig- nal into an about 1 mhz if signal with an image rejection of typical 30 db. according to figure 2-1 on page 3 the front end consists of an lna (low no ise amplifier), lo (local oscillator), i/q mixer, polyphase lowpass filter and an if amplifier. the pll generates the carrier frequency for the mixer via a full integrated synthesizer with inte- grated low noise lc-vco (volta ge controlled oscillator) and pll-loop filt er. the xto (crystal oscillator) generates t he reference frequency f xto . the integrated lc-vco generates two times the mixer drive frequency f vco . the i/q signals for the mixer are generated with a divide by two circuit (f lo =f vco /2). f vco is divided by a factor of 256 and feeds into a phase frequency detector and compared with f xto . the output of the phase frequency detector is fed into an integrated loop filter and thereby generates the control voltage for the vco. if f lo is determined, f xto can be calculated using the following formula: f xto = f lo /128 the xto is a one-pin oscillator that operates at the series resonance of the quartz crystal with high current but low voltage signal, so that there is only a small voltage at the crystal oscillator frequency at pin xtal. according to figure 3-1 , the crystal should be connected to gnd with a series capacitor c l . the value of that capacitor is recommended by the crystal supplier. due to a somewhat inductive impedance at steady state oscillation and some pcb parasitics a lower value of c l is normally necessary. the value of c l should be optimized for the individual bo ard layout to achieve the exact value of f xto (the best way is to use a crystal with known load resonance frequency to find the right value for this capacitor) and hereby of f lo . when designing the system in terms of receiving bandwidth and local oscillator accuracy, the accuracy of the crystal and the xto must be considered. if a crystal with 30 ppm adjustment tolerance at 25c, 50 ppm over temperature ?40c to +105c, 10 ppm of total aging and a cm (motional capacitance) of 7 ff is used, an additional xto pulling of 30 ppm has to be added. the resulting total lo tolerance of 120 ppm agr ees with the receiving bandwidth specification of the 600 khz version of ATA5760/ata5761 if the t5750 has also a total lo tolerance of 120 ppm. for the ATA5760n3 crystals with 55 ppm total tolerance are needed for receiver and transmit- ter to cope with the reduced if-bandwidth. figure 3-1. xto peripherals dvcc xtal test 3 test 2 nc v s c l
5 4896c?rke?04/06 ATA5760/ata5761 the nominal frequency f lo is determined by the rf input frequency f rf and the if frequency f if using the following formula (low side injection): f lo = f rf - f if to determine f lo , the construction of the if filter must be considered at this point. the nominal if frequency is f if = 950 khz. to achieve a good accuracy of the filter corner frequencies, the filter is tuned by the crystal frequency f xto . this means that there is a fixed relation between f if and f lo . f if =f lo /915 for b if = 600 khz f if =f lo /878 for b if = 300 khz the relation is designed to achieve the nominal if frequency of f if = 950 khz for the 868.3 mhz and b if = 600 khz version, f if = 989 khz for the 868.3 mhz and b if = 300 khz version and for the 915 mhz version an if frequency of f if = 1.0 mhz results. the rf input either from an antenna or from an rf generator must be transformed to the rf input pin lna_in. the input impedance of that pin is provided in the electrical parameters. the parasitic board inductances and capacitances influence the input matching. the rf receiver ATA5760/ata5761 exhibits its highest sensitivity if the lna is power matched. this makes the matching to an saw filter as well as to 50 ? or an antenna easier. figure 14-1 on page 30 shows a typical input matching network for f rf = 868.3 mhz to 50 ? . fig- ure 14-2 on page 30 illustrates an according input matchi ng for 868.3 mhz to an saw. the input matching network shown in figure 14-1 on page 30 is the reference network for the parameters given in the electrical characteristics.
6 4896c?rke?04/06 ATA5760/ata5761 4. analog signal processing 4.1 if filter the signals coming from the rf front-end are filtered by the fully integrated 4th-order if filter. the if center frequency is f if = 950 khz for the 868.3 mhz and b if = 600 khz version, f if = 989 khz for the 868.3 mhz and b if = 300 khz version and f if = 1 mhz for the 915 mhz version. the nominal bandwidth is b if = 600 khz for ATA5760/ata5761 and b if = 300 khz for ATA5760n3. 4.2 limiting rssi amplifier the subsequent rssi amplifier enhances the output signal of the if amplifier before it is fed into the demodulator. the dynamic range of this amplifier is ? r rssi = 60 db. if the rssi amplifier is operated within its linear range, the best s/n ratio is maintained in ask mode. if the dynamic range is exceeded by the transmitter signal, the s/ n ratio is defined by the ratio of the maximum rssi output voltage and the rssi output voltage due to a disturber. the dynamic range of the rssi amplifier is exceeded if the rf input signal is about 60 db higher compared to the rf input signal at full sensitivity. in fsk mode the s/n ratio is not affected by the dynamic range of the rssi amplifier, because only the hard limited signal from a high gain limiting amplifier is used by the demodulator. the output voltage of the rssi amplifier is internally compared to a threshold voltage v th_red . v th_red is determined by the value of the external resistor r sens . r sens is connected between pin sens and gnd or v s . the output of the comparator is fed into the digital control logic. by this means it is possible to operate the receiver at a lower sensitivity. if r sens is connected to gnd, the rece iver switches to full sensitivit y. it is also possible to con- nect the pin sens directly to gn d to get the maximum sensitivity. if r sens is connected to v s , the receiver operates at a lower sensitivity. the reduced sensitivity is defined by the value of r sens , the maximum sensitivity by the signal-to-noise ratio of the lna input. the reduced sensitivity depends on the signal strength at the output of the rssi amplifier. since different rf input networks may exhibit slig htly different values for the lna gain, the sen- sitivity values given in the electrical characte ristics refer to a specific input matching. this matching is illustrated in figure 14-1 on page 30 and exhibits the best possible sensitivity and at the same time power matching at rf_in. r sens can be connected to v s or gnd via a microcontroller. the receiver can be switched from full sensitivity to reduced sensitivity or vice vers a at any time. in polling mode, the receiver will not wake up if the rf input signal does not exceed the selected sensitivity. if the receiver is already active, t he data stream at pin data will disappear when the input si gnal is lower than defined by the reduced sensitivity. instead of the data stream, the pattern according to figure 4-1 is issued at pin data to indicate th at the receiver is still active (see figure 13-2 on page 28 ).
7 4896c?rke?04/06 ATA5760/ata5761 figure 4-1. steady l state limited data output pattern 4.3 fsk/ask demodulator and data filter the signal coming from the rssi amplifier is converted into th e raw data signal by the ask/fsk demodulator. the operating mode of the demodulator is set via the bit ask/_fsk in the opmode register. logic l sets the demodulator to fsk, applying h to ask mode. in ask mode an automatic threshold control circui t (atc) is employed to set the detection refer- ence voltage to a value where a good signal to noise ratio is achieved. this circuit also implies the effective suppression of any kind of in-band noise signals or competing transmitters. if the s/n (ratio to suppress in-band noise signals) exceeds about 10 db the data signal can be detected properly, but better values are found for many modulation schemes of the competing transmitter. the fsk demodulator is intended to be used for an fsk deviation of 10 khz ? f 100 khz. in fsk mode the data signal can be detected if the s/n (ratio to suppress in-band noise signals) exceeds about 2 db. this value is valid for all modulation schemes of a disturber signal. the output signal of the demodulator is filtered by t he data filter before it is fed into the digital signal processing circuit. the data filter impr oves the s/n ratio as its passband can be adopted to the characteristics of the data signal. the data filter consists of a 1 st- order high pass and a 2 nd -order lowpass filter. the highpass filter cut-off frequency is defined by an external capacitor connected to pin cdem. the cut-off frequency of the highpass filter is defined by the following formula: in self-polling mode, the data filter must settle very rapidly to achieve a low current consumption. therefore, cdem cannot be increased to very high values if self-polling is used. on the other hand cdem must be large enough to meet the data filter requirements according to the data sig- nal. recommended values for cdem are given in the electrical characteristics. the cut-off frequency of the lowpass filter is defined by the selected baud-rate range (br_range). the br_range is defined in the opmode register (refer to section ?configuration of the receiver? on page 23 ). the br_range must be set in accordance to the used baud-rate. the ATA5760/ata5761 is designed to operate with data coding where the dc level of the data signal is 50%. this is valid for manchester and bi-phase coding. if other modulation schemes are used, the dc level should always remain within the range of v dc_min = 33% and v dc_max = 66%. the sensitivity may be reduced by up to 2 db in that condition. each br_range is also defined by a minimum and a maximum edge-to-edge time (t ee_sig ). these limits are defined in the el ectrical characteristics. they should not be exceeded to main- tain full sensitivity of the receiver. data t data_l_max t data_min fcu_df 1 2 30 k ? cdem ------------------------------------------------------------- =
8 4896c?rke?04/06 ATA5760/ata5761 5. receiving characteristics the rf receiver ATA5760/ata5761 can be operated with and without a saw front-end filter. in a typical automotive application, a saw filter is used to achieve better selectivity and large sig- nal capability. the rece iving frequency resp onse without a saw front-end filter is illustrated in figure 5-1 and figure 5-2 on page 8 . this example relates to ask mode and the 600 khz ver- sion ATA5760n3. fsk mode exhibits a similar behavior. the plots are printed relatively to the maximum sensitivity. if a saw f ilter is used, an insertion loss of about 3 db must be considered, but the overall selectivity is much better. when designing the system in te rms of receiving bandwidth, the lo deviation must be consid- ered as it also determines the if center frequency. the total lo deviation is calculated, to be the sum of the deviation of the crystal and the xto deviation of the ATA5760/ata5761. low-cost crystals are specified to be within 90 ppm over tolerance, temperature and aging. the xto deviation of the ATA5760/ata5761 is an additional deviation due to the xto circuit. this devia- tion is specified to be 30 ppm worst case for a crystal with cm = 7 ff. if a crystal of 90 ppm is used, the total deviation is 120 ppm in that case. note that the receiving bandwidth and the if-filter bandwidth are equivalent in ask mode but not in fsk mode. figure 5-1. narrow band receiving frequency response (b if = 600 khz) figure 5-2. wide band receiving frequency response (b if = 600 khz) -60.0 -50.0 -40.0 -30.0 -20.0 -10.0 0.0 -4.0 -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 4.0 df (mhz) dp (db) -100.0 -90.0 -80.0 -70.0 -60.0 -50.0 -40.0 -30.0 -20.0 -10.0 0.0 -12.0 -9.0 -6.0 -3.0 0.0 3.0 6.0 9.0 12.0 df (mhz) dp (db)
9 4896c?rke?04/06 ATA5760/ata5761 6. polling circuit and control logic the receiver is designed to consume less than 1 ma while being sensitive to signals from a cor- responding transmitter. this is achieved via the polling circuit. this circuit enables the signal path periodically for a short time. during this time the bit-check logic verifies the presence of a valid transmitter signal. only if a valid signal is detected, the receiver remains active and trans- fers the data to the connected microcontroller. if there is no valid signal present, the receiver is in sleep mode most of the time resulting in low current consumption. this condition is called poll- ing mode. a connected microcontroller is disabled during that time. all relevant parameters of the polling logic can be configured by the connected microcontroller. this flexibility enables the user to meet the specifications in terms of current consumption, sys- tem response time, data rate etc. regarding the number of connection wires to the mi crocontroller, the receiver is very flexible. it can be either operated by a single bi-directional line to save ports to the connected microcontrol- ler or it can be operated by up to five uni-directional ports. 7. basic clock cycle of the digital circuitry the complete timing of the digital circuitry and t he analog filtering is derived from one clock. this clock cycle t clk is derived from the crystal oscillator (x to) in combination wit h a divide by 14 cir- cuit. according to section ?rf front end? on page 4 , the frequency of th e crystal oscillator (f xto ) is defined by the rf input signal (f rfin ) which also defines the operating frequency of the local oscillator (f lo ). the basic clock cycle is t clk = 14/f xto giving t clk = 2.066 s for f rf =868.3mhz and t clk = 1.961 s for f rf =915mhz. t clk controls the following applic ation-relevant parameters: timing of the polling circuit including bit check timing of the analog and digital signal processing timing of the register programming frequency of the reset marker if filter center frequency (f if0 ) most applications are dominated by two transmission frequencies: f transmit = 915 mhz is mainly used in usa, f transmit = 868.3 mhz in europe. in order to ease the usage of all t clk -dependent parameters on this electrical characteristic s display three conditions for each parameter. application usa (f xto = 7.14063 mhz, t clk = 1.961 s) application europe (f xto = 6.77617 mhz, t clk = 2.066 s) for b if = 600 khz (f xto = 6.77587 mhz, t clk = 2.066 s) for b if = 300 khz other applications the electrical charac teristic is given as a function of t clk . the clock cycle of some function blocks depends on the selected baud-rate range (br_range) which is defined in the opmode register. this clock cycle t xclk is defined by the following for- mulas for further reference: br_range = br_range0: t xclk = 8 t clk br_range1: t xclk = 4 t clk br_range2: t xclk = 2 t clk br_range3: t xclk = 1 t clk
10 4896c?rke?04/06 ATA5760/ata5761 8. polling mode according to figure 8-4 on page 13 , the receiver stays in polling mode in a continuous cycle of three different modes. in sleep mode the signal processing circuitry is disabled for the time period t sleep while consuming low current of i s =i soff . during the start-up period, t startup , all sig- nal processing circuits are enabled and settled. in the following bit-check mode, the incoming data stream is analyzed bit by bit contra a valid transmitter signal. if no valid signal is present, the receiver is set back to sleep mode after the period t bit-check . this period varies check by check as it is a statistical process. an average value for t bit-check is given in the electrical charac- teristics. during t startup and t bit-check the current consumption is i s =i son . the condition of the receiver is indicated on pin ic_active. the average current consumption in polling mode is dependent on the duty cycle of the active mode and can be calculated as: during t sleep and t startup the receiver is not sensitive to a transmitter signal. to guarantee the reception of a transmitted command the transmitter must start the telegram with an adequate preburst. the required length of the preburst depends on the polling parameters t sleep , t startup , t bit-check and the start-up time of a connected microcontroller (t start_microcontroller ). thus, t bit-check depends on the actual bit rate and the number of bits (n bit-check ) to be tested. the following formula indicates how to calculate the preburst length. t preburst t sleep + t startup + t bit-check + t start_microcontroller 8.1 sleep mode the length of period t sleep is defined by the 5-bit word sle ep of the opmode register, the exten- sion factor x sleep (according to table 11-8 on page 25 ), and the basic clock cycle t clk . it is calculated to be: t sleep =sleep x sleep 1024 t clk in us- and european applications, the maximum value of t sleep is about 60 ms if x sleep is set to 1. the time resolution is about 2 ms in that case. the sleep time can be extended to almost half a second by setting x sleep to 8. x sleep can be set to 8 by bit x sleepstd to?1?. according to table 11-7 on page 25 , the highest register value of sleep sets the receiver into a permanent sleep condition. the receiver remains in that condition until another value for sleep is programmed into the opmode register. this func tion is desirable where several devices share a single data line and may also be used for microcontroller polling ? via pin polling/_on, the receiver can be switched on and off. spoll i soff t sleep i son t startup t bit-check + ( ) + t sleep t startup t bit-check ++ --------------------------------------------------------------------------------------------------------------- - =
11 4896c?rke?04/06 ATA5760/ata5761 figure 8-1. polling mode flow chart figure 8-2. timing diagram for complete successful bit check sleep mode: all circuits for signal processing are disabled. only xto and polling logic is enabled. output level on pin ic_active => low i s = i soff t sleep = sleep x x sleep x 1024 x t clk start-up mode: the signal processing circuits are enabled. after the start-up time (t startup ) all circuits are in stable condition and ready to receive. output level on pin ic_active => high i s = i son t startup bit-check mode: the incomming data stream is analyzed. if the timing indicates a valid transmitter signal, the receiver is set to receiving mode. otherwise it is set to sleep mode. output level on pin ic_active => high i s = i son t bit-check receiving mode: the receiver is turned on permanently and passes the data stream to the connected microcontroller. it can be set to sleep mode through an off command via pin data or output level on pin ic_active => high i s = i son bit check ok ? off command sleep: 5-bit word defined by sleep0 to sleep4 in opmode register x sleep : extension factor defined by xsleepstd according to table 9 t clk : basic clock cycle defined by fxto and pin mode t startup : is defined by the selected baud rate range and tclk. the baud-rate range is defined by baud0 and baud1 in the opmode register. no yes polling/_on. t bit-check : depends on the result of the bit check if the bit check is ok, t bit-check depends on the number of bits to be checked (n bit-check ) and on the utilized data rate. if the bit check fails, the average time period for that check depends on the selected baud-rate range and on t clk . the baud-rate range is defined by baud0 and baud1 in the opmode register. bit check ic_active data_out (data) 1/2 bit start-up mode (number of checked bits: 3) bit check ok 1/2 bit 1/2 bit 1/2 bit 1/2 bit 1/2 bit receiving mode dem_out bit-check mode t start-up t bit-check
12 4896c?rke?04/06 ATA5760/ata5761 8.2 bit-check mode in bit-check mode the incoming data stream is examined to distinguish between a valid signal from a corresponding transmitter and signals due to noise. this is done by subsequent time frame checks where the distances between 2 signal edges are continuously compared to a pro- grammable time window. the maximum count of this edge-to-edge tests before the receiver switches to receiving mode is also programmable. 8.3 configuring the bit check assuming a modulation scheme that contains 2 edg es per bit, two time frame checks are verify- ing one bit. this is valid for manchester, bi-phase and most other modulation schemes. the maximum count of bits to be checked can be set to 0, 3, 6 or 9 bits via the variable n bit-check in the opmode register. this implies 0, 6, 12 and 18 edge-to-edge checks respectively. if n bit-check is set to a higher value, the receiv er is less likely to switch to re ceiving mode due to noise. in the presence of a valid transmitter signal, the bit check takes less time if n bit-check is set to a lower value. in polling mode, the bit-check time is not dependent on n bit-check . figure 8-2 on page 11 shows an example where 3 bits are tested successfully and the data signal is transferred to pin data. according to figure 8-3 , the time window for the bit check is defined by two separate time limits. if the edge-to-edge time t ee is in between the lower bit-check limit t lim_min and the upper bit-check limit t lim_max , the check will be continued. if t ee is smaller than t lim_min or t ee exceeds t lim_max , the bit check will be terminated and the receiver switc hes to sleep mode. figure 8-3. valid time window for bit check for best noise immunity it is recommended to use a low span between t lim_min and t lim_max . this is achieved using a fixed frequency at a 50% duty cycle for the transmitter preburst. a ?11111...? or a ?10101...? sequence in manchester or bi-phase is a good choice concerning that advice. a good compromise between receiver sensitivity and susceptibility to noise is a time win- dow of 30% regarding the expected edge-to-edge time t ee . using pre-burst patterns that contain various edge-to-edge time periods, the bi t-check limits must be programmed according to the required span. the bit-check limits are determined by means of the formula below. t lim_min = lim_min t xclk t lim_max = (lim_max ? 1) t xclk lim_min and lim_max are defined by a 5-bit word each within the limit register. dem_out t ee t lim_min t lim_max 1/f sig
13 4896c?rke?04/06 ATA5760/ata5761 using above formulas, lim_min and lim_max can be determined according to the required t lim_min , t lim_max and t xclk . the time resolution defining t lim_min and t lim_max is t xclk . the mini- mum edge-to-edge time t ee (t data_l_min , t data_h_min ) is defined according to the section ?receiving mode? on page 14 . the lower limit should be set to lim_min 10. the maximum value of the upper limit is lim_max = 63. if the calculated value for lim_min is < 19, it is recommended to check 6 or 9 bits (n bit-check ) to prevent switching to receiving mode due to noise. figure 8-7 on page 15 , figure 8-8 and figure 8-9 on page 15 illustrate the bit check for the bit-check limits lim_min = 14 and lim_max = 24. wh en the ic is enabled, the signal processing circuits are enabled during t startup . the output of the ask/fsk demodulator (dem_out) is unde- fined during that period. when the bit check bec omes active, the bit-check counter is clocked with the cycle t xclk . figure 8-7 on page 15 shows how the bit check proceeds if the bit-check counter value cv_lim is within the limits defined by lim_min and lim_max at the occurrence of a signal edge. in fig- ure 8-8 on page 15 the bit check fails as the value cv_lim is lower than the limit lim_min. the bit check also fails if cv_lim reac hes lim_max. this is illustrated in figure 8-9 on page 15 . figure 8-4. timing diagram during bit check figure 8-5. timing diagram for failed bit check (condition: cv_lim < lim_min) bit check ic_active dem_out bit-check- counter 0 2 345 6 245 1 7 8 1 36789111213 14 10 1/2 bit 15 16 17 18 1 234 56 (lim_min = 14, lim_max = 24) 7891011 12 13 14 15 1234 1/2 bit 1/2 bit bit check ok bit check ok t xclk start-up mode bit-check mode t start-up t bit-check bit check ic_active bit-check- counter 0 2345 6 245 1 1 367891112 10 1/2 bit start-up mode 0 (lim_min = 14, lim_max = 24) sleep mode bit check failed ( cv_lim < lim_min ) dem_out bit-check mode t start-up t bit-check t sleep
14 4896c?rke?04/06 ATA5760/ata5761 figure 8-6. timing diagram for failed bit check (condition: cv_lim lim_max) 8.4 duration of the bit check if no transmitter signal is present during the bit check, the output of the ask/fsk demodulator delivers random signals. the bit check is a statistical process and t bit-check varies for each check. therefore, an average value for t bit-check is given in the electrical characteristics. t bit-check depends on the selected baud-rate range and on t clk . a higher baud-rate range causes a lower value for t bit-check resulting in a lower curren t consumption in polling mode. in the presence of a valid transmitter signal, t bit-check is dependent on the frequency of that sig- nal, f sig , and the count of the checked bits, n bit-check . a higher value for n bit-check thereby results in a longer period for t bit-check requiring a higher value for the transmitter pre-burst t preburst . 8.5 receiving mode if the bit check was successful for all bits specified by n bit-check , the receiver swit ches to receiving mode. according to figure 8-2 on page 11 , the internal data signal is switched to pin data in that case and the data clock is available after the start bit has been detected (see figure 9-1 on page 19 ). a connected microcontroller can be woken up by the negative edge at pin data or by the data clock at pin data_clk. the receiver stays in that condition until it is switched back to polling mode explicitly. 8.6 digital signal processing the data from the ask/fsk demodulator (dem_out) is digitally processed in different ways and as a result converted into the output signal data. this processing depends on the selected baud-rate range (br_range). figure 8-7 illustrates how dem_out is synchronized by the extended clock cycle t xclk . this clock is also used for the bit-check counter. data can change its state only after t xclk has elapsed. the edge-to-edge time period t ee of the data signal as a result is always an integr al multiple of t xclk . the minimum time period between two edges of the data signal is limited to t ee t data_min . this implies an efficient suppression of spikes at the data output. at the same time it limits the max- imum frequency of edges at data. this eases the interrupt handling of a connected microcontroller. the maximum time period for data to stay low is limited to t data_l_max . this function is employed to ensure a finite response time in programming or switching off the receiver via pin data. t data_l_max is thereby longer than the maximum time period indicated by the transmitter data stream. figure 8-9 on page 15 gives an example where dem_out remains low after the receiver has switched to receiving mode. bit check ic_active bit-check- counter 0 23 45 6 245 1 7 36 7 8 9 11 12 10 1/2 bit start-up mode 20 (lim_min = 14, lim_max = 24) sleep mode bit check failed ( cv_lim lim_max ) 13 14 15 16 17 18 19 21 22 23 24 0 1 dem_out bit-check mode t start-up t bit-check t sleep
15 4896c?rke?04/06 ATA5760/ata5761 figure 8-7. synchronization of the demodulator output figure 8-8. debouncing of the demodulator output figure 8-9. steady l state limited data output pattern after transmission after the end of a data transmission, the receiver remains active. depending of the bit noise_disable in the opmode register, the output signal at pin data is high or random noise pulses appear at pin data (see section ?digital noise suppression? on page 21 ). the edge-to-edge time period t ee of the majority of these noise puls es is equal or slightly higher than t data_min . clock bit-check counter data_out (data) t xclk dem_out t ee data_out (data) dem_out t ee t ee t data_min t ee t data_min t data_min bit check ic_active data_out (data) start-up mode receiving mode t data_l_max t data_min bit-check mode dem_out
16 4896c?rke?04/06 ATA5760/ata5761 8.7 switching the receive r back to sleep mode the receiver can be set back to polling mode via pin data or via pin polling/_on. when using pin data, this pin must be pulled to low for the period t1 by the connected micro- controller. figure 8-10 on page 16 illustrates the timing of the off command (see figure 13-2 on page 28 ). the minimum value of t1 depends on br_range. the maximum value for t1 is not limited but it is recommended not to exceed the specified value to prevent erasing the reset marker. note also that an inte rnal reset for the opmode and the limit register will be gener- ated if t1 exceeds the specified values. this item is explained in more detail in the section ?configuration of the receiver? on page 23 . setting the receiver to sleep mode via data is achieved by programming bit 1 to be ?1? during the register configuration. only one sync pulse (t3) is issued. the duration of the off command is determined by the sum of t1, t2 and t10. after the off command the sleep time t sleep elapses. note that the capacitive load at pin data is limited (see section ?data interface? on page 29 ). figure 8-10. timing diagram of the off command via pin data figure 8-11. timing diagram of the off command via pin polling/_on data_out (data) serial bi-directional data line x bit 1 ("1") x t1 t2 t3 t4 t5 t7 (start bit) start-up mode off-command t sleep receiving mode t10 sleep mode t start-up ic_active out1 (microcontroller) polling/_on data_out (data) serial bi-directional data line receiving mode x sleep mode start-up mode bit-check mode receiving mode x bit check ok x x t on2 t on3 ic_active
17 4896c?rke?04/06 ATA5760/ata5761 figure 8-12. activating the receiving mode via pin polling/_on figure 8-11 on page 16 illustrates how to set the receiver back to polling mode via pin poll- ing/_on. the pin polling/_on must be held to low for the time period t on2 . after the positive edge on pin polling/_on and the delay t on3 , the polling mode is active and the sleep time t sleep elapses. this command is faster than using pin data at the cost of an additional connection to the microcontroller. figure 8-12 on page 17 illustrates how to set the receiv er to receiving mode via the pin polling/_on. the pin polling/_on must be held to low. after the delay t on1 , the receiver changes from sleep mode to start-up mode regardless the programmed values for t sleep and n bit-check . as long as polling/_on is he ld to low, the values for t sleep and n bit-check will be ignored, but not deleted (see section ?digital noise suppression? on page 21 ). if the receiver is polled excl usively by a microcontroller, t sleep must be programmed to 31 (per- manent sleep mode). in this case the receiver remains in sleep mode as long as polling/_on is held to high. polling/_on data_out (data) serial bi-directional data line sleep mode receiving mode x x t on1 start-up mode ic_active
18 4896c?rke?04/06 ATA5760/ata5761 9. data clock the pin data_clk makes a data shift clock available to sample the data stream into a shift reg- ister. using this data clock, a microcontroller can easily synchron ize the data stream. this clock can only be used for manchester and bi-phase coded signals. 9.1 generation of the data clock after a successful bit check, the receiver switc hes from polling mode to receiving mode and the data stream is available at pin data. in receiv ing mode, the data clock control logic (manches- ter/bi-phase demodulator) is active and examines the incoming data stream. this is done, like in the bit check, by subsequent time frame chec ks where the distance between two edges is con- tinuously compared to a programmable time windo w. as illustrated in figure 9-1 on page 19 , only two distances between two edges in manchester and bi-phase coded signals are valid (t and 2t). the limits for t are the same as used for the bit check. they can be programmed in the limit-register (lim_min and lim_max, see table 11-10 on page 26 and table 11-11 on page 26 ). the limits for 2t are calculated as follows: lower limit of 2t: lim_min_2t = (lim_min + lim_max) ? (lim_max ? lim_min)/2 upper limit of 2t: lim_max_2t= (lim_min + lim_max) + (lim_max ? lim_min)/2 (if the result for ?lim_min_2t? or ?lim_max_2t? is no t an integer value, it will be round up) the data clock is available, after the data clock control logic has detected the distance 2t (start bit) and is issued with the delay t delay after the edge on pin data (see figure 9-1 on page 19 ). if the data clock control logic detects a timing or logical error (manchester code violation), like illustrated in figure 9-2 on page 19 and figure 9-3 on page 19 , it stops the output of the data clock. the receiver remains in re ceiving mode and starts with the bit check. if the bit check was successful and the start bit has been detected, the data clock control logic starts again with the generation of the data clock (see figure 9-4 on page 20 ). it is recommended to use the function of the data clock only in conjunction with the bit check 3, 6 or 9. if the bit check is set to 0 or the receiver is set to receiving mode via the pin polling/_on, the data clock is available if the data clock control logic has detected the distance 2t (start bit). note that for bi-phase-coded signals, the da ta clock is issued at the end of the bit.
19 4896c?rke?04/06 ATA5760/ata5761 figure 9-1. timing diagram of the data clock figure 9-2. data clock disappears because of a timing error figure 9-3. data clock disappears because of a logical error dem_out data_out (data) data_clk '1' '1' '1' '1' '1' '0' '1' '1' '0' '1' '0' bit check ok preburst data t delay t p_data_clk t2t receiving mode, data clock control logic active bit-check mode start bit dem_out data_out (data) data_clk '1' '1' '1' '1' '1' '0' '1' '1' '0' '1' '0' data t ee receiving mode, bit check active receiving mode, data clock control logic active timing error t ee < t lim_min or t lim_max < t lim_min_2t or t ee > t lim_max_2t ) dem_out data_out (data) data_clk '1' '1' '1' '0' '1' '1' '?' '0' '0' '1' '0' logical error (manchester code violation) data receiving mode, bit check aktive receiving mode, data clock control logic active
20 4896c?rke?04/06 ATA5760/ata5761 figure 9-4. output of the data clock after a successful bit check the delay of the data clock is calculated as follows: t delay = t delay1 + t delay2 t delay1 is the delay between the internal signals data_out and data_in. for the rising edge, t delay1 depends on the capacitive load c l at pin data and the external pull-up resistor r pup . for the falling edge, t delay1 depends additionally on the external voltage v x (see figure 9-5 , figure 9-6 on page 21 and figure 13-2 on page 28 ). when the level of data_in is equal to the level of data_out, the data clock is issued after an additional delay t delay2 . note that the capacitive load at pin data is limited. if the maximum tolerated capacitive load at pin data is exceeded, the data clock disappears (see section ?data interface? on page 29 ). figure 9-5. timing characteristic of the da ta clock (rising edge on pin data) dem_out data_out (data) data_clk '1' '1' '1' '1' '1' '0' '1' '1' '0' '1' '0' bit check ok data receiving mode, bit check active receiving mode, data clock control logic active start bit v ih = 0.65 v s v x data_clk serial bi-directional data line t delay1 t p_data_clk data_out data_in t delay2 t delay v ii = 0.35 v s
21 4896c?rke?04/06 ATA5760/ata5761 figure 9-6. timing characteristic of the data clock (falling edge of the pin data) 10. digital noise suppression after a data transmission, digital noise appears on the data output (see figure 10-1 on page 21 ). preventing that digital noise keeps the connec ted microcontroller busy. it can be suppressed in two different ways. 10.1 automatic noise suppression if the bit noise_disable ( table 11-9 on page 25 ) in the opmode register is set to 1 (default), the receiver changes to bit-check mode at the end of a valid data stream. the digital noise is sup- pressed and the level at pin data is high in that case. the receiver changes back to receiving mode, if the bit check was successful. this way to suppress the noise is recommended if the data stream is manchester or bi-phase coded and is active after power on. figure 10-3 on page 22 illustrates the behavior of the data output at t he end of a data stream. note that if the last period of the data stream is a high period (rising edge to falling edge), a pulse occurs on pin data. the length of the pu lse depends on the selected baud-rate range. figure 10-1. output of digital noise at the end of the data stream data_clk serial bi-directional data line t delay1 t p_data_clk data_out data_in t delay2 t delay v ih = 0.65 v s v ii = 0.35 v s v x data_out (data) data_clk preburst data digital noise preburst data digital noise digital noise bit check ok bit-check mode bit check ok receiving mode, bit check aktive receiving mode, bit check aktive receiving mode, data clock control logic active receiving mode, data clock control logic active
22 4896c?rke?04/06 ATA5760/ata5761 figure 10-2. automatic noise suppression figure 10-3. occurrence of a pulse at the end of the data stream 10.2 controlled noise suppre ssion by the microcontroller if the bit noise_disable (see table 11-9 on page 25 ) in the opmode register is set to 0, digital noise appears at the end of a valid data stream. to suppress the noise, the pin polling/_on must be set to low. the receiver remains in receiving mode. then, the off command causes the change to the start-up mode. the programmed sleep time (see table 11-7 on page 25 ) will not be executed because the level at pin polling/_on is low, but the bit check is active in that case. the off command activates the bit check also if the pin polling/_on is held to low. the receiver changes back to receiving mode if the bit check was successful. to activate the polling mode at the end of the data transmission, the pin polling/_on must be set to high. this way of suppressing the noise is recommended if the data stream is not manchester or bi-phase coded. figure 10-4. controlled noise suppression data_out (data) data_clk preburst data preburst data bit check ok bit check ok bit-check mode bit-check mode bit-check mode receiving mode, data clock control logic active receiving mode, data clock control logic active dem_out data_out (data) data_clk '1' '1' '1' t ee bit-check mode receiving mode, data clock control logic active data stream digital noise t pulse timing error t ee < t lim_min or t lim_max < t ee < t lim_min_2t or t ee > t lim_max2t serial bi-directional data line (data_clk) preburst data digital noise preburst data digital noise bit check ok bit check ok receiving mode polling/_on off-command receiving mode start-up mode bit-check mode sleep mode bit-check mode
23 4896c?rke?04/06 ATA5760/ata5761 11. configuration of the receiver the t5760/t5761 receiver is configured via two 12-bit ram registers called opmode and limit. the registers can be programmed by means of the bidirectional data port. if the register contents have changed due to a voltage drop, this condition is indicated by a certain output pat- tern called reset marker (rm). the receiver must be reprogrammed in that case. after a power-on reset (por), the registers are set to default mode. if the receiver is operated in default mode, there is no need to program the registers. table 11-3 on page 23 shows the struc- ture of the registers. according to table 11-2 , bit 1 defines if the receiver is set back to polling mode via the off command (see section ?receiving mode? on page 14 ) or if it is programmed. bit 2 represents the register address. it selects the appropriate register to be programmed. to get a high programming reliability, bit 15 (stop bit), at the end of the programming operation, must be set to 0. table 11-1. effect of bit 1 and bit 2 on programming the registers bit 1 bit 2 action 1 x the receiver is set back to polling mode (off command) 0 1 the opmode register is programmed 0 0 the limit register is programmed table 11-2. effect of bit 15 on programming the register bit 15 action 0 the values will be written into the register (opmode or limit) 1 the values will not be written into the register table 11-3. effect of the configuration words within the registers bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 bit 15 off command 1? ? ? ? ? ? ? ? ? ? ? ? ? ? ? opmode register ? 01 br_range n bit-check modu-lat ion sleep x sleep noise suppression 0 baud1 baud0 bitchk1 bitchk0 ask/ _fsk sleep4 sleep3 sleep2 sleep1 sleep0 x sleepstd noise_ disable default values of bit 3...14 00 0 10001100 1 ? ? limit register ? 00 lim_min lim_max ? lim_ min5 lim_ min4 lim_ min3 lim_ min2 lim_ min1 lim_ min0 lim_ max5 lim_ max4 lim_ max3 lim_ max2 lim_ max1 lim_ max0 0 default values of bit 3...14 01 0 10110100 1 ?
24 4896c?rke?04/06 ATA5760/ata5761 the following tables illustrate the effect of the individual configuration words. the default config- uration is highlighted for each word. br_range sets the appropriate baud-rate range an d simultaneously defines xlim. xlim is used to define the bit-check limits t lim_min and t lim_max as shown in table 11-10 on page 26 and table 11-11 on page 26 . table 11-4. effect of the configuration word br_range br_range baud-rate range/extension factor for bit-check limits (xlim) baud1 baud0 00 br_range0 (application usa/europe: br_rang e0 = 1.0 kbaud to 1.8 kbaud) xlim = 8 (default) 01 br_range1 (application usa/europe: br_rang e1 = 1.8 kbaud to 3.2 kbaud) xlim = 4 10 br_range2 (application usa/europe: br_rang e2 = 3.2 kbaud to 5.6 kbaud) xlim = 2 11 br_range3 (application usa/europe: br_ra nge3 = 5.6 kbaud to 10 kbaud) xlim = 1 table 11-5. effect of the configuration word n bit-check n bit-check number of bits to be checked bitchk1 bitchk0 00 0 0 1 3 (default) 10 6 11 9 table 11-6. effect of the configuration bit modulation modulation selected modulation ask/_fsk ? 0 fsk (default) 1 ask
25 4896c?rke?04/06 ATA5760/ata5761 table 11-7. effect of the configuration word sleep sleep start value for sleep counter (t sleep = sleep x sleep 1024 t clk ) sleep4 sleep3 sleep2 sleep1 sleep0 00000 0 (receiver is continuously polling until a valid signal occurs) 00001 1 (t sleep 2.1 ms for x sleep = 1 and f rf = 868.3 ms, 2.0 ms for f rf = 915 mhz) 000102 000113 ... ... ... ... ... ... 00110 6 (t sleep = 12.695 ms for f rf = 868.3 mhz, 12.047 ms for f rf = 915 mhz) (default) ... ... ... ... ... ... 1110129 1111030 1 1 1 1 1 31 (permanent sleep mode) table 11-8. effect of the configuration bit xsleep x sleep extension factor for sleep time (t sleep = sleep x sleep 1024 t clk) x sleepstd 0 1 (default) 18 table 11-9. effect of the configuration bit noise suppression noise suppression suppression of the digi tal noise at pin data noise_disable 0 noise suppression is inactive 1 noise suppression is active (default)
26 4896c?rke?04/06 ATA5760/ata5761 note: 1. lim_min is also used to determine the margins of the data clock control logic (see section ?data clock? on page 18 ). note: 1. lim_max is also used to determine the marg ins of the data clock control logic (see section ?data clock? on page 18 ). table 11-10. effect of the configuration word lim_min lim_min (1) (lim_min < 10 is not applicable ) lower limit value for bit check lim_min5 lim_min4 lim_min3 li m_min2 lim_min1 lim_min0 (t lim_min = lim_min xlim t clk ) 001010 10 001011 11 001100 12 .. .. .. .. .. .. 010101 21 (default) (t lim_min = 347 s for f rf = 868.3 mhz and br_range0 t lim_min = 329 s for f rf = 915 mhz and br_range0) .. .. .. .. .. .. 111101 61 111110 62 111111 63 table 11-11. effect of the configuration word lim_max lim_max (1) (lim_max < 12 is not applicable ) upper limit value for bit check lim_max5 lim_max4 lim_max3 lim_max2 lim_ma x1 lim_max0 (tlim_max = (lim_max ? 1) xlim t clk ) 001100 12 001101 13 001110 14 .. .. .. .. .. .. 101001 41 (default) (tlim_max = 661 s for f rf = 868.3 mhz and br_range0, tlim_max = 627 s for f rf = 915 mhz and br_range0) .. .. .. .. .. .. 111101 61 111110 62 111111 63
27 4896c?rke?04/06 ATA5760/ata5761 12. conservation of the register information the ATA5760/ata5761 implies an integrated power-on reset and brown-out detection circuitry to provide a mechanism to preserve the ram register information. according to figure 12-1 , a power-on reset (por) is generated if the supply voltage v s drops below the threshold voltage v threset . the default parameters are programmed into the configura- tion registers in that condition. once v s exceeds v threset the por is canceled after the minimum reset period t rst . a por is also generated when the supply voltage of the receiver is turned on. to indicate that condition, the receiver displays a reset marker (rm) at pin data after a reset. the rm is represented by the fixed frequency f rm at a 50% duty-cycle. rm can be canceled via a low pulse t1 at pin data. the rm implies the following characteristics: f rm is lower than the lowest feasible frequency of a data signal. by this means, rm cannot be misinterpreted by the connected microcontroller. if the receiver is set back to polling mode via pin data, rm cannot be canc eled by accident if t1 is applied according to the proposal in the section ?programming the configuration register? on page 28 . by means of that mechanism the receiver cannot lose its register information without communi- cating that condition via the reset marker rm. figure 12-1. generation of the power-on reset v s por data_out (data) 1/f rm t rst v threset x
28 4896c?rke?04/06 ATA5760/ata5761 13. programming the configuration register figure 13-1. timing of the register programming figure 13-2. data interface the configuration registers are programmed seria lly via the bi-directional data line according to figure 13-1 and figure 13-2 . to start programming, the serial data line data is pulled to low for the time period t1 by the microcontroller. when data has been released, the receiver becomes the master device. when the programming delay period t2 has elapsed, it emits 15 subsequent synchronization pulses with the pulse length t3. after each of these pulses, a programming window occurs. the delay until the program window starts is determined by t4, the duration is defined by t5. within the pro- gramming window, the individual bits are set. if the microcontroller pulls down pin data for the time period t7 during t5, the according bit is set to ?0?. if no programmin g pulse t7 is issued, this bit is set to ?1?. all 15 bits are subsequently programmed this way. the time frame to program a bit is defined by t6. out1 (microcontroller) data_out (data) serial bi-directional data line x bit 1 ("0") bit 2 ("1") bit 14 ("0") bit 15 ("0") x t1 t2 t3 t4 t5 t6 t8 t7 programming frame (start bit) (register- select) (poll8) (stop bit) receiving mode start-up mode t9 ic_active t sleep t start-up sleep mode data_in data_out input - interface data 0 ... 20 v 0 v/5 v v x = 5 v to 20 v r pup c l v s = 4.5 v to 5.5 v i/o serial bi-directional data line ATA5760/ ata5761 microcontroller out1 (microcontroller ) i d
29 4896c?rke?04/06 ATA5760/ata5761 bit 15 is followed by the equivalent time window t9. during this window, the equivalence acknowledge pulse t8 (e_ack) occurs if the ju st programmed mode word is equivalent to the mode word that was already stored in that regi ster. e_ack should be used to verify that the mode word was correctly transferred to the register. the register must be programmed twice in that case. programming of a register is possible both in sleep-mode and in active-mode of the receiver. during programming, the lna, lo, lowpass filter if-amplifier and the fsk/ask manchester demodulator are disabled. the programming start pulse t1 initiates the programming of the configuration registers. if bit 1 is set to ?1?, it represents the off command to set the receiver back to polling mode at the same time. for the length of the programming start pulse t1, the following convention should be considered: t1(min) < t1 < 5632 t clk : t1(min) is the minimum specified value for the relevant br_range programming respectively off command is initiated if the receiver is not in reset mode. if the receiver is in reset mode, programming respectively off command is not initiated and the reset marker rm is still pr esent at pin data. this period is generally used to switch the rece iver to polling mode or to start the programming of a register. in reset condition, rm is not cancelled by accident. t1 > 7936 t clk programming respectively off command is initiated in any case. the registers opmode and limit are set to the default values. rm is cancelled if present. this period is used if the connected microcontroller detected rm. if the receiver operates in default mode, this time period for t1 can generally be used. note that the capacitive load at pin data is limited. 14. data interface the data interface (see figure 13-2 on page 28 ) is designed for automotive requirements. it can be connected via the pull-up resistor r pup up to 20v and is short-circuit-protected. the applicable pull-up resistor r pup depends on the load capacity c l at pin data and the selected br_range (see table 14-1 ). table 14-1. applicable r pup - br_range applicable r pup c l 1nf b0 1.6 k ? to 47 k ? b1 1.6 k ? to 22 k ? b2 1.6 k ? to 12 k ? b3 1.6 k ? to 5.6 k ? c l 100pf b0 1.6 k ? to 470 k ? b1 1.6 k ? to 220 k ? b2 1.6 k ? to 120 k ? b3 1.6 k ? to 56 k ?
30 4896c?rke?04/06 ATA5760/ata5761 figure 14-1. application circuit: f rf = 868.3 mhz without saw filter figure 14-2. application circuit: f rf = 868.3 mhz with saw filter c7 4.7u 10% vs r3 >= 1.6k data polling/_on r2 56k to 150k sens 1 ic_active 2 cdem 3 avcc 4 test1 5 agnd 6 n.c. 7 lnaref 8 lna_in 9 lnagnd 10 test2 11 test3 12 n.c. 13 xtal 14 dvcc 15 test4 16 data_clk 17 dgnd 18 polling/_on 19 data 20 c14 39n 5% gnd c13 10n 10% q1 6.77587 mhz for b = 300 khz c11 if 2% data_clk c16 18p 5% toko ll1608-fs4n7s c17 1.5p 0.1p rf_in np0 np0 sensitivity reduction ic_active c12 12p 10% ATA5760 v x = 5 v to 20 v 4.7nh, 0.3nh np0 6.77617 mhz for b = 600 khz if 10n c7 4.7 10% vs r3 1.6k data polling/_on r2 56k to 150k sens 1 ic_active 2 cdem 3 avcc 4 test1 5 agnd 6 nc 7 lnaref 8 lna_in 9 lnagnd 10 test2 11 test3 12 nc 13 xtal 14 dvcc 15 test4 16 data_clk 17 dgnd 18 polling/_on 19 data 20 c14 39n 5% gnd c13 10n 10% q1 c11 12p 2% data_clk np0 sensitivity reduction ic_active c12 10n 10% ATA5760 v x = 5 v to 20 v c16 18p 5% c17 5.6p 0.1p in 1 in_gnd 2 case_gnd 3 case_gnd 4 out 5 out_gnd 6 case_gnd 7 case_gnd 8 epcos b3570 rf_in c2 3.3p 0.1p np0 np0 np0 toko ll1608-fs4n7s 12 nh, 5% 4.7nh, 0.3nh toko ll1608-fs12nj 6.77587 mhz for b = 300 khz if 6.77617 mhz for b = 600 khz if
31 4896c?rke?04/06 ATA5760/ata5761 15. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rati ng conditions for extended periods may affect device reliability . parameters symbol min. max. unit supply voltage v s 6v power dissipation p tot 1000 mw junction temperature t j 150 c storage temperature t stg ?55 +125 c ambient temperature t amb ?40 +105 c maximum input level, input matched to 50 ? p in_max 10 dbm 16. thermal resistance parameters symbol value unit junction ambient r thja 100 k/w 17. electrical characteristics all parameters refer to gnd, t amb = ?40c to +105c, v s = 4.5v to 5.5v, f 0 = 868.3 mhz and f 0 = 915 mhz, unless otherwise specified. (for typical values: v s = 5v, t amb = 25c) parameter test conditions symbol f rf = 868.3 mhz f rf = 915 mhz variable oscillator unit min. typ. max. min. typ. max. min. typ. max. basic clock cycle of the digital circuitry basic clock cycle t clk 2.0662 2.0662 1.9607 1.9607 14/f xto 14/f xto s extended basic clock cycle br_range0 br_range1 br_range2 br_range3 t xclk 16.53 8.26 4.13 2.07 16.53 8.26 4.13 2.07 15.69 7.84 3.92 1.96 15.69 7.84 3.92 1.96 8 t clk 4 t clk 2 t clk 1 t clk 8 t clk 4 t clk 2 t clk 1 t clk s s s s polling mode sleep time (see figure 8-4 on page 13 , figure 9-1 on page 19 and figure 14-1 on page 30 ) sleep and xsleep are defined in the opmode register t sleep sleep x sleep 1024 2.0662 sleep x sleep 1024 2.0662 sleep x sleep 1024 1.9607 sleep x sleep 1024 1.9607 sleep x sleep 1024 t clk sleep x sleep 1024 t clk ms start-up time (see figure 8-4 on page 13 and figure 8-5 on page 13 ) br_range0 br_range1 br_range2 br_range3 t startup 1852 1059 1059 662 1852 1059 1059 662 1758 1049 1049 628 1758 1049 1049 628 896.5 512.5 512.5 320.5 t clk 896.5 512.5 512.5 320.5 t clk s s s s s
32 4896c?rke?04/06 ATA5760/ata5761 time for bit check (see figure 8-4 on page 13 ) average bit-check time while polling, no rf applied (see figure 8-8 on page 15 and figure 8-9 on page 15 ) br_range0 br_range1 br_range2 br_range3 t bit-check 0.45 0.24 0.14 0.08 0.45 0.24 0.14 0.08 ms ms ms ms time for bit check (see figure 8-4 on page 13 ) bit-check time for a valid input signal f sig (see figure 8-5 on page 13 ) n bit-check = 0 n bit-check = 3 n bit-check = 6 n bit-check = 9 t bit-check 3/f sig 6/f sig 9/f sig 3.5/f sig 6.5/f sig 9.5/f sig 3/f sig 6/f sig 9/f sig 3.5/f sig 6.5/f sig 9.5/f sig 1 t xclk 3/f sig 6/f sig 9/f sig 1 t clk 3.5/f sig 6.5/f sig 9.5/f sig ms ms ms ms receiving mode intermediate frequency f if 0.95 1.00 f rf /915 mhz baud-rate range br_range0 br_range1 br_range2 br_range3 br_range 1.0 1.8 3.2 5.6 1.8 3.2 5.6 10.0 1.054 1.89 3.38 5.9 1.89 3.38 5.9 10.5 br_range0 2 s/t clk br_range1 2 s/t clk br_range2 2 s/t clk br_range3 2 s/t clk kbaud kbaud kbaud kbaud minimum time period between edges at pin data (see figure 8-11 and figure 8-12 on page 17 ) (with the exception of parameter t pulse ) br_range = br_range0 br_range1 br_range2 br_range3 t data_min 165.3 82.6 41.3 20.7 165.3 82.6 41.3 20.7 156.8 78.4 39.2 19.6 156.8 78.4 39.2 19.6 10 t xclk 10 t xclk 10 t xclk 10 t xclk 10 t xclk 10 t xclk 10 t xclk 10 t xclk s s s s maximum low period at pin data (see figure 8-9 on page 15 ) br_range = br_range0 br_range1 br_range2 br_range3 t data_l_max 2149 1074 537 269 2149 1074 537 269 2139 1020 510 255 2139 1020 510 255 130 t xclk 130 t xclk 130 t xclk 130 t xclk 130 t xclk 130 t xclk 130 t xclk 130 t xclk s s s s delay to activate the start-up mode (see figure 9-3 on page 19 ) ton1 19.6 21.7 18.6 20.6 9.5 t clk 10.5 t clk s 17. electrical characteristics (continued) all parameters refer to gnd, t amb = ?40c to +105c, v s = 4.5v to 5.5v, f 0 = 868.3 mhz and f 0 = 915 mhz, unless otherwise specified. (for typical values: v s = 5v, t amb = 25c) parameter test conditions symbol f rf = 868.3 mhz f rf = 915 mhz variable oscillator unit min. typ. max. min. typ. max. min. typ. max.
33 4896c?rke?04/06 ATA5760/ata5761 off command at pin polling/_o n (see figure 9-2 on page 19 ) ton2 16.5 15.6 8 t clk s delay to activate the sleep mode (see figure 9-2 on page 19 ) ton3 17.6 19.6 16.6 18.6 8.5 t clk 9.5 t clk s pulse on pin data at the end of a data stream (see figure 12-1 on page 27 ) br_range = br_range0 br_range1 br_range2 br_range3 t pulse 16.5 8.3 4.1 2.1 16.5 8.3 4.1 2.1 15.69 7.84 3.92 1.96 15.69 7.84 3.92 1.96 8 t clk 4 t clk 2 t clk 1 t clk 8 t clk 4 t clk 2 t clk 1 t clk s s s s configuration of the receiver (see figure 8-10 on page 16 and figure 14-1 on page 30 ) frequency of the reset marker frequency is stable within 50 ms after por f rm 118.2 118.2 124.5 124.5 1/ (4096 t clk ) 1/ (4096 t clk ) hz programming start pulse br_range = br_range0 br_range1 br_range2 br_range3 after por t1 3355 2273 1731 1461 16397 11637 11637 11637 11637 3184 2168 1643 1386 15560 11043 11043 11043 11043 1624 t clk 1100 t clk 838 t clk 707 t clk 7936 t clk 5632 t clk 5632 t clk 5632 t clk 5632 t clk s s s s s programming delay period t2 795 797 754 756 384.5 t clk 385.5 t clk s synchroni-zat ion pulse t3 264 264 251 251 128 t clk 128 t clk s delay until of the program window starts t4 131 131 125 125 63.5 t clk 63.5 t clk s programming window t5 529 529 502 502 256 t clk 256 t clk s time frame of a bit t6 1058 1058 1004 1004 512 t clk 512 t clk s programming pulse t7 132 529 125 502 64 t clk 256 t clk s equivalent acknowledge pulse: e_ack t8 264 264 251 251 128 t clk 128 t clk s equivalent time window t9 533 533 506 506 258 t clk 258 t clk s off-bit programming window t10 929 929 881 881 449.5 t clk 449.5 t clk s 17. electrical characteristics (continued) all parameters refer to gnd, t amb = ?40c to +105c, v s = 4.5v to 5.5v, f 0 = 868.3 mhz and f 0 = 915 mhz, unless otherwise specified. (for typical values: v s = 5v, t amb = 25c) parameter test conditions symbol f rf = 868.3 mhz f rf = 915 mhz variable oscillator unit min. typ. max. min. typ. max. min. typ. max.
34 4896c?rke?04/06 ATA5760/ata5761 data clock (see figure 10-2 on page 22 and figure 10-3 on page 22 ) minimum delay time between edge at data and data_clk br_range = br_range0 br_range1 br_range2 br_range3 t delay2 0 0 0 0 16.5 8.3 4.1 2.1 0 0 0 0 16.7 7.8 3.9 1.96 0 0 0 0 1 t xclk 1 t xclk 1 t xclk 1 t xclk s s s s pulse width of negative pulse at pin data_clk br_range = br_range0 br_range1 br_range2 br_range3 t p_data_clk 66.1 33.0 16.5 8.3 66.1 33.0 16.5 8.3 63 31 15.7 7.8 63 31 15.7 7.8 4 t xclk 4 t xclk 4 t xclk 4 t xclk 4 t xclk 4 t xclk 4 t xclk 4 t xclk s s s s 17. electrical characteristics (continued) all parameters refer to gnd, t amb = ?40c to +105c, v s = 4.5v to 5.5v, f 0 = 868.3 mhz and f 0 = 915 mhz, unless otherwise specified. (for typical values: v s = 5v, t amb = 25c) parameter test conditions symbol f rf = 868.3 mhz f rf = 915 mhz variable oscillator unit min. typ. max. min. typ. max. min. typ. max. 18. electrical characteristics (continued) all parameters refer to gnd, t amb = ?40c to +105c, v s = 4.5v to 5.5v, f 0 = 868.3 mhz and f 0 = 915 mhz, unless otherwise specified. (for typical values: v s = 5v, t amb = 25c) parameters test conditions symbol min. typ. max. unit current consumption sleep mode (xto and polling logic active) is off 170 276 a ic active (start-up-, bit-check-, receiving mode) pin data = h fsk ask is on 7.8 7.4 9.9 9.6 ma ma lna, mixer, polyphase lowp ass and if amplifier (input matched according to figure 14-1 on page 30 referred to rfin) third-order intercept point lna/mixer/if amplifier iip3 ?16 dbm lo spurious emission required according to i-ets 300220 is lorf ?70 ?57 dbm system noise figure with power matching |s11| < ?10 db nf 5 db lna_in input impedance at 868.3 mhz at 915 mhz zi lna_in 200 || 3.2 200 || 3.2 ? || pf ? || pf 1 db compression point ip 1db ?25 dbm image rejection within the complete image band 20 30 db maximum input level ber 10 -3 , fsk mode ask mode p in_max ?10 ?10 dbm dbm
35 4896c?rke?04/06 ATA5760/ata5761 local oscillator operating frequency range vco t5760 t5761 f vco f vco 866 900 871 929 mhz mhz phase noise local oscillator f osc = 867.3 mhz at 10 mhz l (fm) ?140 ?130 dbc/hz spurious of the vco at f xto ?55 ?45 dbc xto pulling xto pulling, appropriate load capacitance must be connected to xtal, crystal c m = 7 ff f xto ?30ppm f xtal +30ppm mhz series resonance resistor of the crystal parameter of the supplied crystal r s 120 ? static capacitance at pin xtal to gnd parameter of the supplied crystal and board parasitics c 0 6.5 pf analog signal processing (input matched according to figure 14-1 on page 30 referred to rfin) input sensitivity ask ask (level of carrier) 300 khz if-filter ber 10 -3 , 100% mod f in = 868.3 mhz/915 mhz v s = 5v, t amb = 25c f if = 950 khz/1 mhz p ref_ask br_range0 ?111 ?113 ?115 dbm br_range1 ?109 ?111 ?113 dbm br_range2 ?108 ?110 ?112 dbm br_range3 ?106 ?108 ?110 dbm input sensitivity ask ask (level of carrier) 600 khz if-filter ber 10 -3 , 100% mod f in = 868.3 mhz/915 mhz v s = 5v, t amb = 25c f if = 950 khz/1 mhz p ref_ask br_range0 ?110 ?112 ?114 dbm br_range1 ?108.5 ?110.5 ?112.5 dbm br_range2 ?108 ?110 ?112 dbm br_range3 ?106 ?108 ?110 dbm sensitivity variation ask for the full operating range compared to t amb = 25c, v s =5v f in = 868.3 mhz/915 mhz f if = 950 khz/989 khz/1 mhz p ask = p ref_ask + ? p ref ? p ref +2.5 ?1.0 db 18. electrical characteristics (continued) all parameters refer to gnd, t amb = ?40c to +105c, v s = 4.5v to 5.5v, f 0 = 868.3 mhz and f 0 = 915 mhz, unless otherwise specified. (for typical values: v s = 5v, t amb = 25c) parameters test conditions symbol min. typ. max. unit
36 4896c?rke?04/06 ATA5760/ata5761 sensitivity variation ask for full operating range including if filter compared to t amb = 25c, v s = 5v 300 khz version f in = 868.3 mhz/915 mhz f if = 950 khz/989 khz/1 mhz f if ?110 khz to +110 khz f if ?140 khz to +140 khz p ask = p ref_ask + ? p ref ? p ref +5.5 +7.5 ?1.5 ?1.5 db db 600 khz version f in = 868.3 mhz/915 mhz f if = 950 khz/989 khz/1 mhz f if ?210 khz to +210 khz f if ?270 khz to +270 khz p ask = p ref_ask + ? p ref ? p ref +5.5 +7.5 ?1.5 ?1.5 db db input sensitivity fsk 300 khz and 600 khz version ber 10 -3 f in = 868.3 mhz/915 mhz v s = 5v, t amb = 25c f if = 950 khz/989 khz/1 mhz br_range0 df = 16 khz to 28 khz df = 10 khz to 100 khz p ref_fsk ?103 ?101 ?106 ?107.5 ?107.5 dbm dbm br_range1 df = 16 khz to 28 khz df = 10 khz to 100 khz p ref_fsk ?101 ?99 ?104 ?105.5 ?105.5 dbm dbm br_range2 df = 18 khz to 31 khz df = 13 khz to 100 khz p ref_fsk ?99.5 ?97.5 ?102.5 ?104 dbm dbm br_range3 df = 25 khz to 44 khz df = 20 khz to 100 khz p ref_fsk ?97.5 ?95.5 ?100.5 ?102 dbm dbm sensitivity variation fsk for the full operating range compared to t amb = 25c, v s = 5v f in = 868.3 mhz/915 mhz f if = 950 khz/989 khz/1 mhz p fsk = p ref_fsk + ? p ref ? p ref +3 ?1.5 db sensitivity variation fsk for the full operating range including if filter compared to t amb = 25c, v s = 5v 300 khz version f in = 868.3 mhz/915 mhz f if = 950 khz/989 khz/1 mhz f if ?110 khz to +110 khz f if ?140 khz to +140 khz f if ?180 khz to +180 khz p fsk = p ref_fsk + ? p ref ? p ref +6 +8 +11 ?2 ?2 ?2 db db db 600 khz version f in = 868.3 mhz/915 mhz f if = 950 khz/989 khz/1 mhz f if ?150 khz to +150 khz f if ?200 khz to +200 khz f if ?260 khz to +260 khz p fsk = p ref_fsk + ? p ref ? p ref +6 +8 +11 ?2 ?2 ?2 db db db s/n ratio to suppress inband noise signals. noise signals may have any modulation scheme ask mode fsk mode snr ask snr fsk 10 2 12 3 db db dynamic range rssi amplifier ? r rssi 60 db 18. electrical characteristics (continued) all parameters refer to gnd, t amb = ?40c to +105c, v s = 4.5v to 5.5v, f 0 = 868.3 mhz and f 0 = 915 mhz, unless otherwise specified. (for typical values: v s = 5v, t amb = 25c) parameters test conditions symbol min. typ. max. unit
37 4896c?rke?04/06 ATA5760/ata5761 lower cut-off frequency of the data filter cdem = 33 nf fcu_df 0.11 0.16 0.20 khz recommended cdem for best performance br_range0 (default) br_range1 br_range2 br_range3 cdem 39 22 12 8.2 nf nf nf nf edge-to-edge time period of the input data signal for full sensitivity br_range0 (default) br_range1 br_range2 br_range3 t ee_sig 270 156 89 50 1000 560 320 180 ms ms ms ms upper cut-off frequency data filter upper cut-off frequency programmable in 4 ranges via a serial mode word br_range0 (default) br_range1 br_range2 br_range3 fu 2.8 4.8 8.0 15.0 3.4 6.0 10.0 19.0 4.0 7.2 12.0 23.0 khz khz khz khz reduced sensitivity 300 khz if-filter r sense connected from pin sens to v s , input matched according to figure 14-1 on page 30 , f in = 868.3 mhz/915 mhz, v s = 5v, t amb = +25c dbm (peak level) r sense = 56 k ? p ref_red ?67 ?72 ?77 dbm r sense = 100 k ? p ref_red ?76 ?81 ?86 dbm 600 khz if-filter r sense connected from pin sens to v s , input matched according to figure 14-1 on page 30 , f in = 868.3 mhz/915 mhz, v s = 5v, t amb = +25c dbm (peak level) r sense = 56 k ? p ref_red ?63 ?68 ?73 dbm r sense = 100 k ? p ref_red ?72 ?77 ?82 dbm reduced sensitivity variation over full operating range r sense = 56 k ? r sense = 100 k ? p red = p ref_red + ? p red ? p red 5 5 0 0 0 0 db db reduced sensitivity variation for different values of r sense values relative to r sense = 56 k ? r sense = 56 k ? r sense = 68 k ? r sense = 82 k ? r sense = 100 k ? r sense = 120 k ? r sense = 150 k ? p red = p ref_red + ? p red ? p red 0 ?3.5 ?6.0 ?9.0 ?11.0 ?13.5 db db db db db db threshold voltage for reset v threset 1.95 2.8 3.75 v 18. electrical characteristics (continued) all parameters refer to gnd, t amb = ?40c to +105c, v s = 4.5v to 5.5v, f 0 = 868.3 mhz and f 0 = 915 mhz, unless otherwise specified. (for typical values: v s = 5v, t amb = 25c) parameters test conditions symbol min. typ. max. unit f cu_df 1 2 30 k ? cdem ------------------------------------------------------------- =
38 4896c?rke?04/06 ATA5760/ata5761 digital ports data output - saturation voltage low - max voltage at pin data - quiescent current - short-circuit current - ambient temp. in case of permanent short-circuit data input - input voltage low - input voltage high i ol 12 ma i ol = 2 ma v oh = 20v v ol = 0.8v to 20v v oh = 0v to 20v v ol v ol v oh i qu i ol_lim t amb_sc v il v ich 13 0.65 v s 0.35 0.08 30 0.8 0.3 20 20 45 85 0.35 v s v v v a ma c v v data_clk output - saturation voltage low - saturation voltage high idata_clk = 1ma idata_clk = ?1ma v ol v oh v s ? 0.4v 0.1 v s ? 0.15v 0.4 v v ic_active output - saturation voltage low - saturation voltage high iic_active = 1 ma iic_active = ?1 ma v ol v oh v s ? 0.4 v 0.1 v s ? 0.15 v 0.4 v v polling/_on input - low level input voltage - high level input voltage receiving mode polling mode v il v ih 0.8 v s 0.2 v s v v test 4 pin - high level input voltage test input must al ways be set to high v ih 0.8 v s v test 1 pin - low level input voltage test input must always be set to low v il 0.2 v s v 18. electrical characteristics (continued) all parameters refer to gnd, t amb = ?40c to +105c, v s = 4.5v to 5.5v, f 0 = 868.3 mhz and f 0 = 915 mhz, unless otherwise specified. (for typical values: v s = 5v, t amb = 25c) parameters test conditions symbol min. typ. max. unit
39 4896c?rke?04/06 ATA5760/ata5761 20. package information 19. ordering information extended type number package remarks ATA5760n-tgsy so20 tube, for 868 mhz ism band, pb-free, b if = 600 khz ATA5760n-tgqy so20 taped and reeled, for 868 mhz ism band, pb-free, b if = 600 khz ata5761n-tgsy so20 tube, for 915 mhz ism band, pb-free, b if = 600 khz ata5761n-tgqy so20 taped and reeled, for 915 mhz ism band, pb-free, b if = 600 khz ATA5760n3-tgqy so20 taped and reeled, for 868 mhz ism band, pb-free, b if = 300 khz technical drawings according to din specifications package so20 dimensions in mm 9.15 8.65 11.43 12.95 12.70 2.35 0.25 0.10 0.4 1.27 7.5 7.3 0.25 10.50 10.20 20 11 110
40 4896c?rke?04/06 ATA5760/ata5761 21. revision history please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. revision no. history 4896c-rke-04/06 ? page 4: first paragraph changed ? page 5: text changed ? page 4.1 if filter: text changed ? page 10: text changed ? page 30: figures 14-1 and 14-2 changed ? page 31: el.char. table: heading row changed ? page 35-36: test condition values changed 4896b-rke-02/06 ? page 1: pb-free logo deleted ? page 1: features changed ? page 4: rf front end - text changed ? page 5: if filter - text changed ? page 7: receiving characteristics - text changed ? page 7: fig.5-1 - title text changed ? page 8: fig.5-2 - title text changed ? pages 33 to 37: some lines changed ? page 38: ordering information table changed
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