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ordering number : enn7695 60304tn (ot) no. 7695-1/24 overview the LC78684NE integrates cd-rom signal-processing functions, mp3 signal-processing functions, and cd-da anti-shock signal-processing functions on a single chip. the LC78684NE achieves lower power consumption than other approaches by implementing these signal-processing functions with hardwired structures. a cd player that supports mpeg audio (mp3) playback from cd media as well as cd-da anti-shock (prevents audio skipping due to mechanical shock) playback can be implemented by combining this ic with cd dsp, dram, audio d/a converter, and other components. features 1. mp3 (mpeg audio standard (iso/iec 11172-3) layer 3) decoding function ? decodes mp3 data decoded from the cd-rom decoder to the original (digital) audio signal and outputs that signal. ? supports all bit rates including variable bit rate ? supports the following sampling rates mpeg1 (fs = 32k, 44.1k, 48k) mpeg2 (fs = 16k, 22.05k, 24k) mpeg2.5 (fs = 8k, 11.025k, 12k) ? can read out the mpeg header information and the ancillary information ? supports automatic muting when crc errors occur using an mp3 crc check function ? mpeg data external serial input function supports playback from memory cards 2. cd-rom decoding function ? supports cd-rom mode 1 and mode 2 (forms 1 and 2) ? cd-rom error correction function provides faithful and accurate decoding of data written to the cd- rom disc. ? header and sector management ? supports up to 4 -speed playback ? in addition to data buffering, also supports c2 error flag buffering ? external serial output of cd-rom decoded data 3. cd-da playback function (with anti-shock support) ? provides about 180 seconds of anti-shock play when a 64m dram is used (when data compression is used). ? supports both compressed and uncompressed, and also provides a data through output ? supports vcec (variable speed) playback up to 4 speed 4. audio signal processing ? audio signal output is provided as a serial output signal from the lrck, bck, and data pins (i 2 s format and pcm output data have a precision of 16 or 20 bits, and 16, 24, and 32 bit output modes are supported for data slot output.) ? digital bass boost (4 modes), attenuator, and muting (C , C12 db) functions ? base clock (384 fs) output pin for use with external digital filter or d/a converter circuits 5. dram interface ? supports edo dram (1 to 64 mb, 2 cas, 16-bit data path) or sdram (16 or 64 mb, 16-bit data path, cas latency: 2, burst length: full) as external memory ? supports allocation of a dram user area during cd-rom (mp3) playback 6. package and supply voltage specifications ? package (units: mm): sanyo qfp80 (14 14 mm) ? supply voltages: internal power supply: 1.8 v (typical) i/o power supply: 3.3 v (typical) analog system power supply: 3.3 v (typical) LC78684NE sanyo electric co.,ltd. semiconductor company tokyo office tokyo bldg., 1-10, 1 chome, ueno, taito-ku, tokyo, 110-8534 japan compact disc player mp3 decoder cmos ic any and all sanyo products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircrafts control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo representative nearest you before using any sanyo products described or contained herein in such applications. sanyo assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo products described or contained herein.
p ac ka g e dimensions unit: mm 3255-qfp80 no. 7695- 2 /24 LC78684NE 14.0 14.0 17.2 17.2 0.15 0.1 3.0max 0.25 0.65 (0.83) (2.7) 0.8 1 20 21 40 41 60 80 61 sanyo: qfp80 [LC78684NE]
block diagram no. 7695- 3 /24 LC78684NE anti-shock (compressed and uncompressed) cdrom decoder mp3 decoder mux audio i/f cpu-i/f intb cmdout cmdin ce cl mdata[15:0] madrs[12:0] rasb casub caslb oeb web ckin vprfr vcoc vpdo ckout lrsy datack datain c2fin sfsy pw sbsy sbck resb wok cntok ovf data-i/f dram-i/f vco + pll system clock-generator streq stck stdat crcf fsync adlrck adbck addata
pin assignment no. 7695- 4 /24 LC78684NE cmdout datack streq cntok dvdd5 datain cmdin fsync dvdd6 stdat resb stck crcf wok intb vss ovf vss ce cl 80 79 78 77 76 75 74 73 72 71 70 69 86 67 66 65 64 63 62 24 23 22 21 36 35 34 33 32 31 30 29 28 27 24 25 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 37 38 39 40 mdata13 mdata14 mdata15 mdata12 41 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LC78684NE 61 lrsy madrs0 addata madrs1 adbck madrs2 adlrck madrs3 c2fin madrs4 te st1 madrs5 ckin madrs6 vss madrs7 ckout vss dvdd4 test2 dvdd1 madrs8 pw madrs9 sbsy madrs10 sfsy madrs11 sbck madrs12 avdd oeb vprfr casub vcoc caslb vpdo web avss rasb top view dvdd2 mdata0 dvdd3 vss vss mdata5 mdata6 mdata7 mdata8 mdata4 mdata9 mdata10 mdata3 mdata1 mdata11 mdata2
no. 7695- 5 /24 LC78684NE parameter symbol conditions ratings unit maximum supply voltage v dd 1 max C0.3 to v ss + 4.0 v v dd 2 max C0.3 to v ss + 2.2 v input voltage vin C0.3 to v dd 1 + 0.3 v output voltage vout C0.3 to v dd 1 + 0.3 v allowable power dissipation pdmax 400 mw operating temperature topr C30 to +75 c storage temperature tstg C40 to +125 c specifications absolute maximum ratings at v ss = 0 v, av ss = 0 v parameter symbol pin name conditions ratings unit min typ max v dd 1 dv dd 1, dv dd 3, dv dd 4, dv dd 6, 3.0 3.3 3.6 v supply voltage av dd v dd 2 dv dd 2, dv dd 5 1.62 1.8 1.98 v mdata0 to 15, lrsy, datain, datack, c2fin, pw, sbsy, high-level input voltage vih sfsy, streq, stck, stdat, 0.8v dd 1 v dd 1 v wok, ckin, ce, cl, cmdin, resb mdata0 to 15, lrsy, datain, datack, c2fin, pw, sbsy, low-level input voltage vil sfsy, streq, stck, stdat, 0 0.2v dd 1 v wok, ckin, ce, cl, cmdin, resb, test1, test2 operating frequency range fop ckin 16.9344 mhz allowable operating ranges at ta = C30 to +75 c, v ss = 0 v, av ss = 0 v
no. 7695- 6 /24 LC78684NE parameter symbol pin name conditions ratings unit min typ max i dd (1) dv dd 1, dv dd 3, dv dd 4, dv dd 6, v dd 1 = 3.0 to 3.6 v 10.0 20.0 ma current drain av dd i dd (2) dv dd 2, dv dd 5 v dd 2 = 1.62 to 1.98 v 4.5 10.0 ma mdata0 to 15, lrsy, datain, datack, c2fin, pw, sbsy, high-level input current iih sfsy, streq, stck, stdat, vin = v dd 1 10 a wok, ckin, ce, cl, cmdin, resb mdata0 to 15, lrsy, datain, datack, c2fin, pw, sbsy, low-level input current iil sfsy, streq, stck, stdat, vin = 0 v C10 a wok, ckin, ce, cl, cmdin, resb, test1, tes2 mdata0 to 15, streq, stck, stdat, madrs0 to 12, rasb, voh (1) casub, caslb, oeb, web, ioh = C2 ma v dd 1 C 0.6 v sbck, addata, adlrck, high-level output voltage adbck, intb, fsync, crcf, cntok, ovf voh (2) ckout ioh = C4 ma v dd 1 C 0.6 v voh (3) vpdo ioh = C0.2 ma v dd 1 C 0.6 v mdata0 to 15, streq, stck, stdat, madrs0 to 12, rasb, vol (1) casub, caslb, oeb, web, iol = 2 ma 0.4 v sbck, addata, adlrck, low-level output voltage adbck, intb, fsync, crcf, cntok, ovf, cmdout vol (2) ckout iol = 4 ma 0.4 v vol (3) vpdo iol = 0.2 ma 0.4 v ioff (1) mdata0 to 15, streq, stck, vout = v dd 1 10 a output off leakage current stdat, cmdout ioff (2) mdata0 to 15, streq, stck, vout = 0 v C10 a stdat, cmdout electrical characteristics at ta = C30 to +75 c, v dd 1 = 3.0 v to 3.6 v, v dd 2 = 1.62 v to 1.98 v, v ss = 0 v, av ss = 0 v
microcontroller interface 1. microcontroller interface timing ? write cycle no. 7695- 7 /24 LC78684NE t1 t2 t3 t4 t5 t6 t7 ce cl cmdin t1 t2 t3 t4 t5 ce cl cmdout t9 t10 t8 ? read cycle symbol parameter ratings unit min typ max t1 ce/cl setup time 500 ns t2 ce/cl hold time 250 ns t3 command wait time 1000 ns t4 cl high-level pulse width 250 ns t5 cl low-level pulse width 250 ns t6 data/cl setup time 150 ns t7 data/cl hold time 150 ns t8 data-read access time * 1 0 240 ns t9 data-read turn-on time * 1 0 150 ns t10 data-read turn-off time * 1 0 240 ns * 1: pull-up register = 1 k , output load = 30 pf.
2. command input/data output interface commands (data write operations) from the microcontroller must be transferred lsb first in the following order: first the data and then the address. to perform a data output (data read) operation, first issue a read mode setup command and then perform the read access. ? data write no. 7695- 8 /24 LC78684NE lsb msb data address high (due to the external pull-up resistor) lsb msb ce cl cmdin cmdout ? data read to read the data at address 61h, first write the address and set up read mode by setting ce low temporarily. when ce is set high again and then a cl is issued, the contents of the set register address will be output serially (lsb first) from cmdout. if read mode is set up, a read access must be performed. read mode setup command register address read code (61h) lsb msb lsb msb ls b m s b read access high (due to the external pull-up resistor) cmdout cmdin cl ce
memory interface edo dram interface timing ? read cycle no. 7695- 9 /24 LC78684NE rasb casub/lb madrs [12:0] web oeb mdata [15:0] t1 t3 t2 t4 t10 read data t6 t7 t8 t9 t12 t11 read data read data ro w column column column t5 t13 t1 t3 t2 t4 t1 4 write data t6 t7 t8 t9 t15 t16 row column column t5 t18 t 1 9 t17 write data write data rasb casub/lb madrs [12:0] web oeb mdata [15:0] column ? write cycle
? refresh cycle (cas before ras) no. 7695- 10 /24 LC78684NE rasb casub/lb mdata [15:0] t24 t17 t22 t21 t20 t23 symbol parameter ratings unit min typ max t1 rasb width high 100 ns t2 rasb casb delay 80 ns t3 casb rasb delay 40 ns t4 casb width low 40 ns t5 casb width high 40 ns t6 row address setup time 15 ns t7 row address hold time 40 ns t8 column address setup time 15 ns t9 column address hold time 40 ns t10 oeb ready time 30 ns t11 oeb hold time 10 ns t12 read data setup time 30 ns t13 read data hold time 0 ns t14 web ready time 30 ns t15 web hold time 40 ns t16 write data turn on time 60 ns t17 write data turn off time 80 ns t18 write data setup time 15 ns t19 write data hold time 40 ns t20 refresh cycle 300 ns t21 rasb low width (refresh) 200 ns t22 rasb casb delay (refresh) 50 ns t23 casb setup time (refresh) 40 ns t24 casb hold time (refresh) 100 ns * : these values apply when the frequency of the clock input to the ckin pin is 16.9344 mhz.
sdram interface timing ? read cycle no. 7695- 11 /24 LC78684NE t7 t6 column read-data t12 t6 t7 t5 cs dqml t6 t5 t 6 sdcl k cke rasb casb web ma[13:0] row c o l u m n column all-pre md[15:0] r-data r-data read-data t1 t6 t7 t 5 t4 t8 t9 t6 t7 t 5 t10 t11 t7 cas-latency 2 t2 t3 t7 t5 row t12 t6 t7 dqmu cs sdclk cke rasb casb web ma[13:0] md[15:0] dqmu row column all-pre t3 t2 data latch timing (dram) t13 t14 write-data dqml ? write cycle
no. 7695- 12 /24 LC78684NE ? refresh cycle (auto refresh) ma[13:0] md[15:0] t16 t15 cs dclk cke web dqmu dqml rasb casb *: the correspondence between the signal names used in the above diagrams (read cycle, write cycle, and refresh cycle) and the actual LC78684NE pin names is shown in the table below. signal name in figure LC78684NE pin signal name in figure LC78684NE pin cs oeb ma [13] crcf sdclk caslb ma [12:0] madrs [12:0] cke streq md [15:0] mdat [15:0] rasb rasb dqmu stdat casb casub dqml stck web web symbol parameter ratings unit min typ max t1 sdram clock frequency 59 ns t2 active to active command period (t1) 6 ns t3 active to precharge command period (ras to cas delay) (t1) 4 ns t4 active to read or write delay (t1) 2 ns t5 command low-level width (cke, ras, cas, web) 40 ns t6 command setup time (cke, ras, cas, web, dqmu/l) 30 ns t7 command hold time (cke, ras, cas, web, dqmu/l) 2.5 ns t8 address setup time 30 ns t9 address hold time 2.5 ns t10 read data setup time (dram: read / lc78684: input) 30 ns t11 read data hold time (dram: read / lc78684: input) 0 ns t12 dqm low-level width (bite-access mode) 90 ns t13 write data setup time (dram: write / lc78684e: output) 80 ns t14 write data hold time (dram: write / l78684e output) 2.5 ns t15 precharge to refresh command period (t1) 2 ns t16 refresh to active command period (t1) 6 ns notes: 1. these values apply when the frequency of the clock input to the ckin pin is 16.9344 mhz. 2. the setup time and hold time values shown above are times relative to the rise of the sdclk signal. 3. the above times are common to all of the read, write and refresh operation modes.
cd dsp interface ? cd dsp interface timing no. 7695- 13 /24 LC78684NE t1h lrsy datack datain c2fin fbck t4 t5 t1l t2 t3 symbol parameter ratings unit min typ max fbck datack frequency 14.5 mhz t1h datack high-level pulse width 30 ns t1l datack low-level pulse width 30 ns t2 lrsy setup time 30 ns t3 lrsy hold time 30 ns t4 datain, c2fin setup time 30 ns t5 datain, c2fin hold time 25 ns *: the figure above shows the timings relative to the rise of the datack signal. when data is latched on the fall of the datack signal, the setup and hold times are the same as those shown in the table above.
? subcode interface timing no. 7695- 14 /24 LC78684NE sbs y sbc k p w sfs y subcode frame t3 sf97 sf0 sf1 sf2 sf3 fsbck p w sbc k tssd t2 t1h t1l symbol parameter ratings unit min typ max tssd sfsyCsbck delay time 235 7150 ns fsbck sbck frequency * 1.0584 mhz t1h sbck high-level pulse width 450 ns t1l sbck low-level pulse width 450 ns t2 pw setup time 50 ns t3 pw hold time 0 ns * : these values apply when the frequency of the clock input to the ckin pin is 16.9344 mhz.
no. 7695- 15 /24 LC78684NE audio output interface ? audio output interface timing t1 t2 t3 adlrck adbck addata ckout the figure above applies when the audio data output slot is a 48-bit slot. fck symbol parameter ratings unit min typ max t1 ckout ? adlrck delay time 0 35 ns t2 ckout ? adbck delay time 0 35 ns t3 ckout ? addata delay time 0 35 ns fck ckout frequency * 16.9344 mhz * : these values apply in mpeg1 (fs = 44.1 khz) playback mode when the pll is locked normally. these values depend on the playback sampling frequency (fs). (ckout frequency = fs 384) ? supplement: output timing in full through mode playback t5 lrsy datack datain ckout * : full through mode is the mode where the through bit (bit 6 in register 60h) is set to 1. t6 ckin adlrck adbck addata symbol parameter ratings unit min typ max t5 input ? output delay time 0 35 ns t6 ckin ? ckout delay time * 0 35 ns * : these values apply when the ckin pin input is directly output from the ckout pin.
no. 7695- 16 /24 LC78684NE data serial i/o interface ? dram data serial output timing * : when edo dram is used, a transfer data command from dram must be issued first to output data from dram. (this function cannot be used with sdram.) if this command has not been issued, the clock and data signals will not be outp ut from the stck and stdat pins even if streq is set high. t6 t5 t3 stdat stck t1 t2 fsck t4 streq stck stdat crcf t7 symbol parameter ratings unit min typ max fsck transfer clock frequency 4.2336 mhz t1 stdat/stck setup time 30 ns t2 stdat/stck hold time 30 ns t3 data (1 byte) transfer time 1.89 s t4 data transfer wait time 1.89 s t5 data transfer start time 1.89 15.2 s t6 data transfer stop time 0 15.2 s t7 enable flag turn off time 210 236.2 270 ns * 1: the typical values apply when the frequency of the clock signal input to the ckin pin is 16.9344 mhz. * 2: there are cases in data transfer operations where between a minimum of 0 bytes and a maximum of 4 bytes of data are output from the stdat pin after the streq pin goes low. the period t6 in the figure above stipulates this time. * 3: the t7 stipulation in the figure above applies when one or more bytes of data are output from the stdat pin after the streq pin goes low. the timing with which the crcf pin goes low when data output from the stdat does not occur is the same as the timing with which streq goes low. ? the fsck clock frequency can also be set to 2.1168 mhz (typical), 1.084 mhz (typical). in these cases, the values for t3 to t7 will be 2 times or 4 times the listed values. ? the wok, ovf, and cntok pins can be used in place of streq (input mode), stck, and stdat. the above timing specifications apply in this case as well.
no. 7695- 17 /24 LC78684NE ? mp3 data serial input timing * : for data serial input, if edo dram is used, a serial input command must have bee n issued. (this function cannot be used with sdram.) if this command has not been issued, the mp3 decoder will not operate, even if c lock and data signals are input to the stck and stdat pins. streq ( * output from the lc78684) stdat stck t 2 t3 t1h t1l fsck stck stdat symbol parameter ratings unit min typ max fsck transfer clock frequency * 9.216 mhz t1h stck high-level pulse width 45 ns t1l stck low-level pulse width 45 ns t2 stdat / stck setup time 30 ns t3 stdat / stck hold time 30 ns symbol parameter ratings unit min typ max fsck transfer clock frequency 3.072 mhz t1h stck high-level pulse width 150 ns t1l stck low-level pulse width 150 ns t2 stdat / stck setup time 125 ns t3 stdat / stck hold time 125 ns * : the maximum frequencies of the transfer clock signal during serial input are listed in the following table. determine the frequency of the transfer clock such that the frequency is below the maximum frequency listed above and the mp3 d ecoding processing is performed in time. note that the values in the table above apply when mp3dset (bit 0 in register 41h) is set to 1 (high-speed transfer mode). if mp3dset is set to 0 (low-speed transfer mode) the following timings apply. * 2: the LC78684NE can receive up to a maximum of 3 bytes of data even after the streq pin has gone low. mode fs (khz) maximum serial transfer clock frequency (mhz) 48 9.216 mpeg1 44.1 8.4672 32 6.144 mpeg2 24 (12) 4.608 (mpeg2.5) 22.05 (11.025) 4.2336 16 (8) 3.072
no. 7695- 18 /24 LC78684NE system clock input twl twh fck ckin pin input symbol parameter ratings unit min typ max fck ckin input frequency 16.9344 18.0 mhz twh ckin high-level pulse width 20 ns twl ckin low-level pulse width 20 ns system reset input trst resb pin input symbol parameter ratings unit min typ max trst system reset pulse width 1 s * : a system reset must be applied after power is first applied. the reset line must be designed so that noise does not occur on the reset signal.
no. 7695- 19 /24 LC78684NE pin functions block no. pin i/o supplement cd if 1 lrsy i cd left/right clock input 2 addata o audio data output audio interface 3 adbck o audio bit clock output 4 adlrck o audio left/right clock output cd if 5 c2fin i cd c2 error flag input test 6 test1 i test input 1 (this pin must be connected to ground.) clock 7 ckin i system clock (16.9344 mhz) input power supply 8 vss ground clock 9 ckout o external digital filter and d/a converter clock output (384 fs) test 10 test2 i test input 2 (this pin must be connected to ground.) power supply 11 dvdd1 digital system power supply (i/o) 12 pw i cd subcode data serial input subcode interface 13 sbsy i cd subcode block sync signal input 14 sfsy i cd subcode frame sync signal input 15 sbck o cd subcode transfer serial clock output power supply 16 avdd analog system power supply (pll) 17 vprfr vco oscillator range setting pll 18 vcoc i vco control voltage input 19 vpdo o vco charge pump output 20 avss analog system ground power supply 21 dvdd2 internal logic system power supply 22 vss ground 23 mdata0 i/o dram data bus0 24 mdata1 i/o dram data bus1 25 mdata2 i/o dram data bus2 memory interface 26 mdata3 i/o dram data bus3 27 mdata4 i/o dram data bus4 28 mdata5 i/o dram data bus5 29 mdata6 i/o dram data bus6 30 mdata7 i/o dram data bus7 power supply 31 dvdd3 digital system power supply (i/o) 32 vss ground 33 mdata8 i/o dram data bus8 34 mdata9 i/o dram data bus9 35 mdata10 i/o dram data bus10 36 mdata11 i/o dram data bus11 37 mdata12 i/o dram data bus12 38 mdata13 i/o dram data bus13 39 mdata14 i/o dram data bus14 40 mdata15 i/o dram data bus15 41 rasb o ras output for edo dram or sdram (active low) 42 web o we output for edo dram or sdram (active low) memory interface 43 caslb o when edo dram is used: cas output (lower byte, active low) when sdram is used: dram clock output 44 casub o when edo dram is used: cas output (upper byte, active low) when sdram is used: cas output (active low) 45 oeb o when edo dram is used: oe output (active low) when sdram is used: cs output (active low) 46 madrs12 o dram address output 12 47 madrs11 o dram address output 11 48 madrs10 o dram address output 10 49 madrs9 o dram address output 9 50 madrs8 o dram address output 8 power supply 51 dvdd4 digital system power supply (i/o) 52 vss ground continued on next page.
no. 7695- 20 /24 LC78684NE continued from preceding page. block no. pin i/o supplement 53 madrs7 o dram address output 7 54 madrs6 o dram address output 6 55 madrs5 o dram address output 5 memory interface 56 madrs4 o dram address output 4 57 madrs3 o dram address output 3 58 madrs2 o dram address output 2 59 madrs1 o dram address output 1 60 madrs0 o dram address output 0 power supply 61 dvdd5 internal logic system power supply 62 vss ground when edo dram is used: mp3 data request flag output (active high)/dram data request flag mp3 stream 63 streq i/o input (in cd rom mode: active high) when sdram is used: cke output (active low) 64 stck i/o when edo dram is used: mp3 data transfer clock input/dram data transfer clock output i/o when sdram is used: dqml output (active low) 65 stdat i/o when edo dram is used: mp3 data serial input/dram data serial output when sdram is used: dqmh output (active low) mp3 decoder 66 fsync o mp3 frame sync signal (active high) data continuity point detection complete flag (cd-da mode, active high) when edo dram is used: crc check (cd rom data/cd-da subcode data) result output (active cd monitor 67 crcf o high)/dram data output enable flag (active high) when sdram is used: adrs13 output power supply 68 dvdd6 digital system power supply (i/o) 69 vss ground 70 wok i dram write enable input (cd-da mode, active high) dram data request flag input (only when edo dram is used) data continuity point detection complete flag (cd-da mode, active high) anti-shock/mp3 i/o 71 cntok o sync error monitor flag (mp3 mode, active high) dram data serial output (only when edo dram is used:) dram write interrupted flag (cd-da mode, active high) 72 ovf o emphasis output flag (cd-da and mp3 modes, active high) dram data transfer clock output (only when edo dram is used) 73 cmdout o command serial data output (this is an n-channel open-drain output.) 74 cmdin i command serial data input microcontroller 75 cl i command serial clock input interface 76 ce i command enable input (active high) 77 intb o interrupt signal output (active low) dram write interrupted flag (cd-da mode, active high) 78 resb i system reset (active low) cd if 79 datain i cd serial data input 80 datack i cd bit clock input note: 1. notes on unused ports unused input pins must be connected to ground (0 v). unused output pins must be left open. do not connect anything to these pins. unused i/o pins must either be connected to ground (0 v) or be left open. 2. the same potential must be supplied to all of the dvdd1, dvdd3, dvdd4, dvdd6, and avdd pins. the same potential must also be su pplied to the dvdd2 and dvdd5 pins. (see the allowable operating ranges section for details on the voltage supplied.) 3. the input pins test1 and test2 must be connected to ground (0 v). 4. the i/o pins (mdata0 to mdata15, streq, stck, and stdat) are set to input mode by the initial system reset. 5. applications must apply a low level (of at least 1 s) to the resb after power is first applied. 6. a clock signal with a frequency of 16.9344 mhz must applied to the ckin pin from the cd dsp ic or other source. an oscillator circuit cannot be formed with just this ic and an oscillator element.
application circuit examples (1) using edo dram no. 7695- 21 /24 LC78684NE to the cd dsp * : the ckout, adlrck, adbck, and addata pins must be connected to a cd dsp that supports d/a converter external input. an external d/a converter is required if the cd dsp does not provide this support. 3.3v gnd 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 lrsy addata adbck a d l rck c2 fin v ss ckin v ss ckout v s s dv dd 1 pw sbsy sfsy sbck av dd vprfr vcoc vpdo av ss LC78684NE mdata15 mdata14 mdata13 mdata12 mdata11 mdata10 mdata9 mdata8 v ss dv dd 3 mdata7 mdata6 mdata5 mdata4 mdata3 mdata2 mdata1 mdata0 v ss dv dd 2 madrs0 dv dd 5 madrs1 madrs2 madrs3 madrs4 madrs5 madrs6 madrs7 v ss dv dd 4 madrs8 madrs9 madrs10 madrs11 madrs12 oeb casub caslb web rasb v ss streq stdat stdat fs ync crcf dv dd 6 v ss wo k cntok ovf cmdout cmdin cl ce intb r esb datain datack 1.8v to edo-dram to -com
no. 7695- 22 /24 LC78684NE (2) using sdram to the cd dsp * : the ckout, adlrck, adbck, and addata pins must be connected to a cd dsp that supports d/a converter external input. an external d/a converter is required if the cd dsp does not provide this support. caution: when using sdram, extreme care is required for the access timing, for example, approaches such as making the connections between the lc78684 and the sdram all have identical lengths or making the clock line lengths the shortest possible should be adopted. 3.3v gnd 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 LC78684NE madrs0 dv dd 5 madrs1 madrs2 madrs3 madrs4 madrs5 madrs6 madrs7 v ss dv dd 4 madrs8 madrs9 madrs10 madrs11 madrs12 oeb casub caslb web rasb v ss streq stdat stdat fsync crcf dv dd 6 v ss wok cntok ovf cmdout cmdin cl ce intb resb datain da t a ck 1.8v lrsy addata adbck adlrck c2fin v ss ckin v ss ckout v ss dv dd 1 pw sbsy sfsy sbck av dd vprfr vcoc vpdo av ss mdata15 mdata14 mdata13 mdata12 mdata11 mdata10 mdata9 mdata8 v ss dv dd 3 mdata7 mdata6 mdata5 mdata4 mdata3 mdata2 mdata1 mdata0 v ss dv dd 2 to sdram to -com
application design notes while it goes without saying that strictly observing the absolute maximum ratings and allowable operating ranges (recommended operating conditions) for this ic is necessary for application reliability, careful consideration must also be given to the ambient temperature, static discharge, and other environmental conditions as well as the mounting conditions. this section presents notes regarding application design and circuit board mounting for this ic. 1. handling unused pins if any unused input pins on this ic are left open, internal circuits may become unstable. the instructions on handling unused pins for specific pins given in the technical documentation must be followed. also note that unused output pins must not be shorted to power, ground, or other outputs. 2. latchup prevention (1) the voltages stipulated in the specifications must be applied to the power supply pins. if there are multiple power supply pins that are stipulated to have the same voltage, the identical potential must be applied to all those pins. (2) the voltage levels on i/o pins must not exceed the peripheral 3 v system block supply voltage, and must not go below the ground level. (3) design applications so that overvoltages and abnormal noise are not applied to this ic. (4) in general, latchup can be prevented by holding unused input pins fixed at either vdd or vss. however, the handling of each pin must follow an specific instruction in the pin functions documentation. (5) the outputs must not be shorted. 3. interface when connected to other devices, this ic may not operate correctly if the input vil/vih and output vol/voh levels do not match. when connecting this ic to other devices in dual power supply systems, level shifters must be inserted to prevent the device from being destroyed. 4. load capacitance and output current (1) when connected to high capacitance loads, lines may be melted since the effect of such loads is the same as the load being shorted for an extended period. also, large charge/discharge currents may result in noise that may degrade equipment performance and cause malfunctions. the recommended load capacitance ratings must be observed. (2) excessive output sink or source current can cause problems. observe the maximum allowable power dissipation ratings and use this ic within the recommended current value range. 5. notes on power application and power-on reset (1) there are cases where special care is required at power on, during a reset, and after a reset is cleared. refer to spec sheets and other documentation and design applications taking these concerns into account. (2) this ic's output pin states, i/o settings, and register values are not guaranteed when power is first applied. the operation of items that are defined by a reset operation or mode settings is only guaranteed after the corresponding reset or setting operation. a reset must be applied to this ic after power is first applied. the states immediately after power on of pins and registers that are not explicitly defined cannot be relied on: they may differ either due to long-term variations in a given device or due to design changes in later versions of the same product. 6. notes on thermal design the failure rate of semiconductor devices is accelerated greatly by increases in ambient temperature or power consumption. to assure high reliability, design the application heat dissipation systems to provide adequate margin for variations in ambient conditions. no. 7695- 23 /24 LC78684NE
ps no. 7695- 24 /24 LC78684NE 7. notes on pwb pattern design (1) ideally, there should be separate power supply and ground lines for each system to reduce the influence of shared impedances. (2) the power supply and ground lines should be as wide and as short as possible, and the impedance to high frequencies should be as small as possible. insert both decoupling capacitors (of about 0.01 to 1 f) and capacitors of about 100 to 200 f between each power supply/ground pair. however, note that if these capacitors are too large, latchup may occur. 8. other notes if there are any points that are unclear, or if you have any questions, contact your sanyo representative during the design phase. this ic is a special-purpose device designed for cd player applications, and has specifications that differ from those of general-purpose logic devices. end products must be designed to operate in a failsafe manner appropriate for the application, and application operation must be verified using test equipment. this catalog provides information as of june, 2004. specifications and information herein are subject to change without notice. specifications of any and all sanyo products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customers products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customers products or equipment. sanyo electric co., ltd. strives to supply high-quality high-reliability products. however, any and all semiconductor products fail with some probability. it is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of sanyo electric co., ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the delivery specification for the sanyo product that you intend to use. information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.

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