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vishay siliconix SI1922EDH document number: 67192 s10-2766-rev. a, 29-nov-10 www.vishay.com 1 dual n-channel 20 v (d-s) mosfet features ? halogen-free according to iec 61249-2-21 definition ? trenchfet ? power mosfet ? 100 % r g tested ? typical esd protection 2100 v hbm ? compliant to rohs directive 2002/95/ec applications ? load switch for portable applications product summary v ds (v) r ds(on) ( ? )i d (a) a q g (typ.) 20 0.198 at v gs = 4.5 v 1.3 a 0.9 nc 0.225 at v gs = 2.5 v 1.3 a 0.263 at v gs = 1.8 v 1.3 a marking code cg xx lot tracea b ility and date code part # code y y sot-363 sc-70 (6-leads) 6 4 1 2 3 5 to p v ie w s 1 g 1 d 2 d 1 g 2 s 2 orderin g information: SI1922EDH-t1-ge3 (lead (p b )-free and halogen-free) d 1 s 1 g 1 1 k d 2 s 2 g 2 1 k notes: a. package limited. b. surface mounted on 1" x 1" fr4 board. c. t = 5 s. d. maximum under steady stat e conditions is 220 c/w. absolute maximum ratings (t a = 25 c, unless otherwise noted) parameter symbol limit unit drain-source voltage v ds 20 v gate-source voltage v gs 8 continuous drain current (t j = 150 c) t c = 25 c i d 1.3 a a t c = 70 c 1.3 a t a = 25 c 1.3 a, b, c t a = 70 c 1.2 b, c pulsed drain current i dm 4 continuous source-drain diode current t c = 25 c i s 1.0 t a = 25 c 0.61 b, c maximum power dissipation t c = 25 c p d 1.25 w t c = 70 c 0.8 t a = 25 c 0.74 b, c t a = 70 c 0.47 b, c operating junction and storage temperature range t j , t stg - 55 to 150 c thermal resistance ratings parameter symbol typical maximum unit maximum junction-to-ambient b, d t ? 5 s r thja 130 170 c/w maximum junction-to-foot (drain) steady state r thjf 80 100
www.vishay.com 2 document number: 67192 s10-2766-rev. a, 29-nov-10 vishay siliconix SI1922EDH notes: a. pulse test; pulse width ? 300 s, duty cycle ? 2 %. b. guaranteed by design, not s ubject to production testing. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. specifications (t j = 25 c, unless otherwise noted) parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = 250 a 20 v v ds temperature coefficient ? v ds /t j i d = 250 a 20 mv/c v gs(th) temperature coefficient ? v gs(th) /t j - 2.3 gate-source threshold voltage v gs(th) v ds = v gs , i d = 250 a 0.4 1 v gate-source leakage i gss v ds = 0 v, v gs = 8 v 25 a v ds = 0 v, v gs = 4.5 v 1 zero gate voltage drain current i dss v ds = 20 v, v gs = 0 v 1 a v ds = 20 v, v gs = 0 v, t j = 55 c 10 on-state drain current a i d(on) v ds ?? 5 v, v gs = 4.5 v 4 a drain-source on-state resistance a r ds(on) v gs = 4.5 v, i d = 1 a 0.165 0.198 ? v gs = 2.5 v, i d = 1 a 0.187 0.225 v gs = 1.8 v, i d = 0.2 a 0.210 0.263 forward transconductance a g fs v ds = 4 v, i d = 1.5 a 4 s dynamic b total gate charge q g v ds = 10 v, v gs = 8 v, i d = 1.5 a 1.6 2.5 nc v ds = 10 v, v gs = 4.5 v, i d = 1.5 a 0.9 1.8 gate-source charge q gs 0.1 gate-drain charge q gd 0.2 gate resistance r g f = 1 mhz 0.4 1.9 3.8 k ? tu r n - o n d e l ay t i m e t d(on) v dd = 10 v, r l = 8.3 ? i d ? 1.2 a, v gen = 4.5 v, r g = 1 ? 43 65 ns rise time t r 80 120 turn-off delay time t d(off) 480 720 fall time t f 220 330 turn-on delay time t d(on) v dd = 10 v, r l = 8.3 ? i d ? 1.2 a, v gen = 8 v, r g = 1 ? 22 33 rise time tr 46 70 turn-off delay time t d(off) 645 968 fall time tr 215 323 drain-source body diode characteristics continuous source-drain diode current i s t c = 25 c 1 a pulse diode forward current i sm 4 body diode voltage v sd i s = 1.2 a, v gs = 0 v 0.8 1.2 v body diode reverse recovery time t rr i f = 1.2 a, di/dt = 100 a/s, t j = 25 c 918ns body diode reverse recovery charge q rr 24nc reverse recovery fall time t a 5 ns reverse recovery rise time t b 4
document number: 67192 s10-2766-rev. a, 29-nov-10 www.vishay.com 3 vishay siliconix SI1922EDH typical characteristics (25 c, unless otherwise noted) gate current vs. gate-to-source voltage output characteristics on-resistance vs. drain current v gs - gate-to-so u rce v oltage ( v ) i g - gate c u rrent (ma) 0 0.1 0.2 0.3 0.4 0.5 03691215 t j = 25 c 0 1 2 3 4 0.0 0.5 1.0 1.5 2.0 v gs =5vthru2v v gs =1.5v v gs =1v v ds - drain-to-source voltage (v) i d - drain current (a) 0.13 0.16 0.19 0.22 0.25 01234 v gs =1.8v v gs =2.5v v gs =4.5v r ds(on) - on-resistance ( ) i d - drain current (a) gate current vs. gate-to-source voltage transfer characteristics gate charge 10 -10 10 -9 10 - 8 10 -7 10 -6 10 -5 10 -4 10 -3 03691215 v gs - gate-to-so u rce v oltage ( v ) i g - gate c u rrent (a) t j = 150 c t j = 25 c 0.0 0.2 0.4 0.6 0.8 1.0 0.0 0.3 0.6 0.9 1.2 1.5 t c = 125 c t c = 25 c t c = - 55 c v gs - gate-to-source voltage (v) i d - drain current (a) 0 2 4 6 8 0.0 0.5 1.0 1.5 2.0 i d =1.5a v ds =10v v ds =16v v ds =5v q g - total gate charge (nc) v gs - gate-to-source voltage (v)
www.vishay.com 4 document number: 67192 s10-2766-rev. a, 29-nov-10 vishay siliconix SI1922EDH typical characteristics (25 c, unless otherwise noted) on-resistance vs. junction temperature on-resistance vs. gate-to-source voltage single pulse power, junction-to-ambient 0.7 0.9 1.1 1.3 1.5 1.7 - 50 - 25 0 25 50 75 100 125 150 i d =1a v gs =4.5v v gs =2.5v t j - junction temperature (c) (normalized) r ds(on) - on-resistance 0.0 0.1 0.2 0.3 0.4 12345 t j = 25 c t j = 125 c i d =1a r ds(on) - on-resistance ( ) v gs - gate-to-source voltage (v) 0 1 5 power (w) time (s) 3 4 0 0 6 110 0.1 0.01 2 100 source-drain diode forward voltage threshold voltage safe operating area, junction-to-ambient 0.0 0.3 0.6 0.9 1.2 1.5 10 1 100 t j = 25 c t j = 150 c i s - source current (a) v sd - source-to-drain voltage (v) 0.20 0.35 0.50 0.65 0.80 - 50 - 25 0 25 50 75 100 125 150 i d = 250 a v gs(th) (v) t j - temperature (c) 10 0.1 0.1 1 10 1 t a = 25 c single pulse 1ms 0.01 1s,10s dc 100 limited by r ds(on) * 10 ms 100 ms 100 s bvdss limited v ds - drain-to-source voltage (v) * v gs > minimum v gs at which r ds(on) is specied i d - drain current (a)
document number: 67192 s10-2766-rev. a, 29-nov-10 www.vishay.com 5 vishay siliconix SI1922EDH typical characteristics (25 c, unless otherwise noted) * the power dissipation p d is based on t j(max) = 150 c, using junction-to-case thermal resi stance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. it is used to determ ine the current rating, when this rating falls below the package limit. current derating* 0.0 0.6 1.2 1.8 2.4 0 255075100125150 package limited t c - case temperature (c) i d - drain current (a) power, junction-to-foot 0.0 0.3 0.6 0.9 1.2 1.5 0 25 50 75 100 125 150 t f - case temperature (c) power (w) power, junction-to-ambient 0.00 0.15 0.30 0.45 0.60 0.75 0 25 50 75 100 125 150 t a - ambient temperature (c) power (w)
www.vishay.com 6 document number: 67192 s10-2766-rev. a, 29-nov-10 vishay siliconix SI1922EDH typical characteristics (25 c, unless otherwise noted) vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?67192 . normalized thermal transient im pedance, junction-to-ambient 10 -3 10 -2 0 0 6 0 1 1 10 -1 10 -4 100 2 1 0.1 0.01 0.2 0.1 0.05 single pulse duty cycle = 0.5 square wave pulse duration (s) normalized effective transient thermal impedance 1. duty cycle, d = 2. per unit base = r thja = 170 c/w 3. t jm - t a = p dm z thja (t) t 1 t 2 t 1 t 2 notes: 4. surface mounted p dm 0.02 normalized thermal transient impedance, junction-to-foot 10 -3 10 -2 0 1 1 10 -1 10 -4 2 1 0.1 0.01 0.2 0.1 0.05 single p u lse d u ty cycle = 0.5 sq u are w a v e p u lse d u ration (s) n ormalized effecti v e transient thermal impedance 0.02
l c e e 1 e d e 1 a 2 a a 1 1 -a- b -b- 23 654 package information vishay siliconix document number: 71154 06-jul-01 www.vishay.com 1

dim min nom max min nom max a 0.90 ? 1.10 0.035 ? 0.043 a 1 ? ? 0.10 ? ? 0.004 a 2 0.80 ? 1.00 0.031 ? 0.039 b 0.15 ? 0.30 0.006 ? 0.012 c 0.10 ? 0.25 0.004 ? 0.010 d 1.80 2.00 2.20 0.071 0.079 0.087 e 1.80 2.10 2.40 0.071 0.083 0.094 e 1 1.15 1.25 1.35 0.045 0.049 0.053 e 0.65bsc 0.026bsc e 1 1.20 1.30 1.40 0.047 0.051 0.055 l 0.10 0.20 0.30 0.004 0.008 0.012 7 nom 7 nom ecn: s-03946?rev. b, 09-jul-01 dwg: 5550
an816 vishay siliconix document number: 71405 12-dec-03 www.vishay.com 1 dual-channel little foot 6-pin sc-70 mosfet copper leadframe version recommended pad pattern and thermal performance introduction the new dual 6-pin sc-70 package with a copper leadframe enables improved on-resistance values and enhanced thermal performance as compared to the existing 3-pin and 6-pin packages with alloy 42 leadframes. these devices are intended for small to medium load applications where a miniaturized package is required. devices in this package come in a range of on-resistance values, in n-channel and p-channel versions. this technical note discusses pin-outs, package outlines, pad patterns, evaluation board layout, and thermal performance for the dual-channel version. pin-out figure 1 shows the pin-out description and pin 1 identification for the dual-channel sc-70 device in the 6-pin configuration. both n-and p-channel devices are available in this package ? the drawing example below illustrates the p-channel device. figure 1. sot-363 sc-70 (6-leads) 6 4 1 2 3 5 top view s 1 g 1 d 2 d 1 g 2 s 2 for package dimensions see outline drawing sc-70 (6-leads) ( http://www.vishay.com/doc?71154 ) basic pad patterns see application note 826, recommended minimum pad patterns with outline drawing access for vishay siliconix mosfet s, ( http://www.vishay.com/doc?72286 ) for the sc-70 6-pin basic pad layout and dimensions. this pad pattern is sufficient for the low-power applications for which this package is intended. increasing the drain pad pattern (figure 2) yields a reduction in thermal resistance and is a preferred footprint. figure 2. sc-70 (6 leads) dual 48 (mil) 16 (mil) 654 3 2 1 61 (mil) 26 (mil) 8 (mil) 0.0 (mil) 23 (mil) 71 (mil) 96 (mil) 26 (mil) 87 (mil) evaluation board for the dual- channel sc70-6 the 6-pin sc-70 evaluation board (evb) shown in figure 3 measures 0.6 in. by 0.5 in. the copper pad traces are the same as described in the previous section, basic pad patterns . the board allows for examination from the outer pins to the 6-pin dip connections, permitting test sockets to be used in evaluation testing. the thermal performance of the dual 6-pin sc-70 has been measured on the evb, comparing both the copper and alloy 42 leadframes. this test was then repeated using the 1-inch 2 pcb with dual-side copper coating. a helpful way of displaying the thermal performance of the 6-pin sc-70 dual copper leadframe is to compare it to the traditional alloy 42 version.
an816 vishay siliconix www.vishay.com 2 document number: 71405 12-dec-03 figure 3. front of board sc70-6 back of board sc70-6 d1 g2 s2 s1 g1 d2 sc70 ? 6 dual vishay.com thermal performance junction-to-foot thermal resistance (the package performance) thermal performance for the dual sc-70 6-pin package is measured as junction-to-foot thermal resistance, in which the ?foot? is the drain lead of the device as it connects with the body. the junction-to -foot thermal resistance for this device is typically 80 c/w, with a maximum thermal resistance of approximately 100 c/w. this data compares favorably with another compact, dual-channel package ? the dual tsop-6 ? which features a typical thermal resistance of 75 c/w and a maximum of 90 c/w. power dissipation the typical r ja for the dual-channel 6-pin sc-70 with a copper leadframe is 224 c/w steady-state, compared to 413 c/w for the alloy 42 version. all figures are based on the 1-inch 2 fr4 test board. the following example shows how the thermal resistance impacts power dissipation for the dual 6-pin sc-70 package at varying ambient temperatures. alloy 42 leadframe alloy 42 leadframe room ambient 25 c elevated ambient 60 c p d t j(max) t a r ja p d 150 o c 25 o c 413 o c w p d 303 mw p d t j(max) t a r ja p d 150 o c 60 o c 413 o c w p d 218 mw cooper leadframe room ambient 25 c elevated ambient 60 c p d t j(max) t a r ja p d 150 o c 25 o c 224 o c w p d 558 mw p d t j(max) t a r ja p d 150 o c 60 o c 224 o c w p d 402 mw although they are intended for low-power applications, devices in the 6-pin sc-70 dual-channel configuration will handle power dissipation in excess of 0.5 w. testing to further aid the comparison of copper and alloy 42 leadframes, figures 4 and 5 illustrate the dual-channel 6-pin sc-70 thermal performance on two different board sizes and pad patterns. the measured steady-state values of r ja for the dual 6-pin sc-70 with varying leadframes are as follows: little foot 6-pin sc-70 alloy 42 copper 1) minimum recommended pad pattern on the evb board (see figure 3). 518 c/w 344 c/w 2) industry standard 1-inch 2 pcb with maximum copper both sides. 413 c/w 224 c/w the results indicate that designers can reduce thermal resistance ( ja) by 34% simply by using the copper leadframe device as opposed to the alloy 42 version. in this example, a 174 c/w reduction was achieved without an increase in board area. if an increase in board size is feasible, a further 120 c/w reduction can be obtained by utilizing a 1-inch 2 . pcb area. the dual copper leadframe versions have the following suf fix: dual: si19xxedh compl.: si15xxedh
an816 vishay siliconix document number: 71405 12-dec-03 www.vishay.com 3 time (secs) figure 4. dual sc70-6 thermal performance on evb thermal resistance (c/w) 0 1 500 100 200 100 1000 300 10 10 -1 10 -2 10 -3 10 -4 10 -5 alloy 42 400 time (secs) figure 5. dual sc70-6 comparison on 1-inch 2 pcb thermal resistance (c/w) 0 1 500 100 200 100 1000 300 10 10 -1 10 -2 10 -3 10 -4 10 -5 400 copper copper alloy 42
application note 826 vishay siliconix www.vishay.com document number: 72602 18 revision: 21-jan-08 application note recommended minimum pads for sc-70: 6-lead 0.096 (2.438) recommended mi nimum pads dimensions in inches/(mm) 0.067 (1.702) 0.026 (0.648) 0.045 (1.143) 0.016 (0.406) 0.026 (0.648) 0.010 (0.241) return to index return to index
document number: 91 000 www.vishay.com revision: 11-mar-11 1 disclaimer legal disclaimer notice vishay all product, product specifications and data ar e subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicab le law, vishay disc laims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, incl uding without limitation specia l, consequential or incidental dama ges, and (iii) any and all impl ied warranties, including warran ties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of pro ducts for certain types of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in gene ric applications. such statements are not binding statements about the suitability of products for a partic ular application. it is the customers responsibility to validate that a particu lar product with the properties described in th e product specification is su itable for use in a particul ar application. parameters provided in datasheets an d/or specifications may vary in different applications and perfo rmance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product co uld result in person al injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk and agr ee to fully indemnify and hold vishay and it s distributors harmless from and against an y and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that vis hay or its distributor was negligent regarding the design or manufact ure of the part. please contact authorized vishay personnel t o obtain written terms and conditions regarding products designed fo r such applications. no license, express or implied, by estoppel or otherwise, to any intelle ctual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners.

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