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STLC5412 2b1q u interface device enhanced with dect mode preliminary data general features single chip 2b1q line code transceiver suitable for isdn, pair gain and dect applications meets or exceeds etsi european standard single 5v supply dip28 and plcc44 package hcmos3a sgs-thomson advanced 1.2 m m double-metal cmos process round trip delay measurement extended temperature range (-40 c to +70 c) transmission features 160 kbit/s full duplex transceiver 2b1q line coding with scrambler/de- scrambler supports bridge taps, splices and mixed gauges >70db adaptive echo-cancellation on chip hybrid circuit decision feedback equalization on chip analog vco system direct connection to small line transformer system features activation/deactivation controller on chip crc calculation and verifi- cation including two programma- ble block error counters eoc channel and overhead-bits transmission with automatic mes- sage checking gci and m w/dsi module interfaces compatible digital loopbacks complete (2b+d) analog loopback in lt elastic data buffers and backplane clock de-jitterizer automode nt1 and repeater ou activation onlyo in nt1 identification code as per gci standard dect frame synchronization easily interfaceable with st5451 (hdlc & gci controller), stlc5464 / stlc5465 and any other gci, idl or tdm compatible devices this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. february 1999 ? plcc44 ordering number: STLC5412fn plastic dip28 ordering number: STLC5412p 1/74
index distinctive characteristics .......................................... page 1 general description .................................................. ..... 5 pin function .................................................. .............. 6 functional description ............................................. ....... 14 digital interfaces . . . . ..................................... ................ m w/dsi mode . . . . . . ....................................... .............. m w control interface . . . . .................................... .............. 14 14 14 write cycle . . . . . . . . . . . . . . . . . . . . ........................ .......... readcycle............................................. ............ 14 14 digital system interface . . .............................. ................... gci mode . . . . . . . .............. .................................. ..... 15 18 frame structure . . . . . . . . ................. .......................... physical links . . . . . . . . . ................ ............................ monitor channel . . . . . . . . . . . . . . ........... .......................... c/i channel. . . . ..................... .............................. 18 18 22 23 line coding and frame format . . . .......... ................................. transmit section. . . . . . . . ........... ......... ..................... ........ receivesection.................... ... ... .. . .. .. ................. ........ elasticbuffers............................................................ dectsynchronization....................................................... 23 24 24 25 25 maintenance functions. . . . . ................ ............................... 26 m channel. . ..................................................... eoc............................................................. m4channel................................................ ....... sparem5andm6bits............................................... crc calculation checking. . . . . . . . . . . . . . . . . . . ................. ..... . . loopbacks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 27 27 27 27 27 identification code. . .................. ............................. ...... generalpurposei/os...................................................... test functions. . . .............................................. ........... turningonandoffthedevice............................. ................... 34 34 35 35 power on initialization . . . . . . . ...................... ......... . ...... line signal detection . .......... . . ...... . .. .. . ... ................. power up control . . . . . ........ ....... ..................... ... . ... power down control . . . . . . . ....................... . ............... power up state . ............ .... ............ ......... .. .... ...... power down state . . . . . . . . . . . . . . ........ .............. ............. 35 35 35 36 36 36 activation deactivation sequencing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........... case of restricted activation. . . . . . . . . . . . ..... ................. ...... . . . .... reset of activation / deactivation state machine . ..................... ..... ....... hardwarereset........................................................... quietmode................................................... ........... automode........................ ... . . ............................. ..... 36 36 36 36 36 37 command/indication (c/i) codes. . ................... ........ ............... internal register description . . . . . . . . .............. . . .. .......... ............ 37 41 line interface circuit . . ........... .......................... .............. board layout . . ........... .............................................. 55 55 appendix a: state matrix ............................. ...................... 60 appendix b: electrical parameters ........................................ 62 STLC5412 2/74
pin connections (top view) dip28 microwire mode dip28 gci mode plcc44 microwire mode plcc44 gci mode STLC5412 3/74
figure 1: block diagram. STLC5412 4/74
general description STLC5412 is a complete monolithic transceiver for isdn basic access data transmission on twisted pair subscriber loops typical of public switched telephone networks. the device is fully compatible with etsi etro80 and cse (c32-11) french specifications. the equivalent of 160 kbit/s full-duplex transmis- sion on a single twisted pair is provided, accord- ing to the formats defined in the a.m. spec. frames include two b channels, each of 64 kbit/s, one d channel of 16 kbit/s plus an additional 4 kbit/s m channel for loop maintenance and other user functions. 12 kbit/s bandwidth is reserved for framing. 2b1q line coding is used, where pairs of bits are coded into one of 4 quantum levels. this technique results in a low frequency spectrum (160 kbit/s turn into 80 kbaud), thereby reducing both line attenuation and crosstalk and achieving long range with low bit error rates. STLC5412 is designed to operate with bit error rate near-end crosstalk (next) as specified in european etsi recommendation. to meet these very demanding specifications, the device includes two digital signal processors, one configured as an adaptive echo-canceller to cancel the near end echoes resulting from the transmit/receive hybrid interface, the other as an adaptive line equalizer. a digital phase-locked loop (dpll) timing recovery circuit is also in- cluded that provides in nt modes a 15.36 mhz synchronized clock to the system. scrambling and descrambling are performed as specified in the specifications. on the system side, STLC5412 can be linked to two bus configuration simply by pin mw bias. microwire( m w/dsi) mode (mwpin = 5v): 144 kbit/s 2b+d basic access data is transferred on a multiplex digital system interface with 4 different interface formats (see fig. 2 and 3) providing maximum flexibility with a limited pin count (bclk, bx, br, fsa, fsb). three pre-defined 2b+d formats plus an internal time slot assigner allows direct connection of the uid to the most common multiplexed digital interfaces (tdm/idl). bit and frame synchronisation signals are inputs or outputs depending on the configuration se- lected. data buffers allow any phase between the line and the digital interface. that permits building of slave-slave configurations e.g. in nt12 trunk- cards. it is possible to separate the d from the b chan- nels and to transfer it on a separate digital inter- face (dx, dr) using the same bit and frame clocks as for the b channels or in a continuous mode us- ing an internally generated 16 khz bit clock output (dclk). all the control, status and interrupt registers are handled via a control channel on a separate serial interface microwire compatible (ci, co, cs, cclk, int) supported by a number of microcon- troller including the mcu families from sgs- thomson gci mode (mwpin = 0v). control/maintenance channels are multiplexed with 2b+d basic access data in a gci compatible interface format (see fig. 4a) requiring only 4 pins (bclk, bx, br, fsa). on chip gci channel assignement allows to multiplex on the same bus up to 8 gci channels, each sup- porting data and controls of one device. bit and frame synchronisation signals can be inputs or ouputs depending on the configuration selected. data buffers, again, allow to have any phase be- tween the line interface and the digital interface. through the m channel and its protocol allowing to check both direction exchanges, internal regis- ters can be configured, the eoc channel and the overhead-bits can be monitored. associated to the m channel, there are a and e channels for enabling the exchanged messages and to check the flow control. the c/i channel allows the primi- tive exchanges following the standard protocol. in both mode ( m w and gci) crc is calculated and checked in both directions internally. in lt mode, the transmit superframe can be syn- chronized by an external signal (sfsx) or be self running. in nt mode, the sfsx is always output synchronized by the transmit superframe. line side or digital interface side loopbacks can be selected for each b1, b2 or d channel inde- pendently without restriction in transparent or in non-transparent mode. a transparent complete analog loopback allowing the test of the transmis- sion path is also selectable. activation and deactivation procedures, which are automatically processed by uid, require only the exchange of simple commands as activation re- quest, deactivation request, activation indica- tion. cold and warm start up procedures are op- erated automatically without any special instruction. four programmable i/os are provided in gci for external device control. STLC5412 5/74
pin functions (no specific microwire / gci mode) note: all pin number are referred to plastic dip28 package. pin name in/out description 1, 4 lo+, lo- out, out transmit 2b1q signal differential outputs to the line transformer. when used with an appropriate 1:1.5 step-up transformer and the proper line interface circuit the line signal conforms to the output specifications in ansi standard with a nominal pulse amplitude of 2.5 volts. 2, 3 li+, li- in, in receive 2b1q signal differential inputs from the line transformer. 5, 8 vcca, vccd in, in positive power supply input for the analog and digital sections, which must be +5 volts +/-5% and must be directly connected together. 24, 9 23 gnda,gndd1 gndd2 in, in in negative power supply pins, which must be connected together close to the device. all digital and analog signals are referred to these pins, which are normally at the system ground. 10 tsr out (lt configuration only) this pin is an open drain output normally in the high impedance state which pulls low when b1 and b2 time-slots are active. it can be used to enable the tristate control of a backplane line-driver. sclk out (nt configuration only) 15.36 mhz clock output which is frequency locked to the received line signal active as soon as uid is powered up except in nt1 auto configuration (active only if s line activation is requested) 20 xtal2 out the output of the crystal oscillator, which should be connected to one end of the crystal, if used. otherwise, this pin must be left not connected. 21 xtal1 in the master clock input, which requires either a parallel resonance crystal to be tied between this pin and xtal2, or a logic level clock input from a stable source. this clock does not need to be synchronized to the digital interface clocks (fsa, bclk).crystal specifications: 15.36 mhz +/-50ppm parallel resonant; rs 20 ohms; load with 33pf to gnd each side. 28 mw in microwire selection: when set high, microwire control interface is selected. when set low, gci interface is selected. pin functions (specific micro wire mode) pin name in/out description 6 fsa in out input or output depending of the cms bit in cr1 register, fsa is a 8 khz clock which indicates the start of the frame on bx when fsa is input, or bx and br when fsa is output. input or output, the location of fsa relative to the frame on bx or bx and br depends of ddm bit in cr1 register, also the selected format. 7 fsb in out input or output depending of the cms bit in cr1 register, fsb is a 8 khz clock which indicates the start of the frame on br when it is an input. when it is an output, fsb is a 8 khz pulse conforming with the selected format and always indicating the second 64kbit/sec channel of the frame on br. input or output, the location of fsb relative to the frame on br depends of ddm bit in cr1 register, also the selected format. 11 br out 2b+d datas tristate output. datas received from the line are shifted out on the rising edge (at the bclk frequency or the half bclk frequency if format 4 is selected) during the assigned time slot. br is in high impedance state outside the assigned time slot and during the assigned time slot of the channel if it is disabled. when d channel port is enabled, only b1 b2 are on br. STLC5412 6/74
pin functions (specific micro wire mode) pin name in/out description 12 bclk in out bit clock input or output depending of the cms bit in cmr register. when bclk is an input, its frequency may be any multiple of 8 khz from 256 khz to 4096 khz in formats 1, 2, 3; 512 khz to 6176 khz in format 4. when bclk is an output, its frequency is 256 khz, 512 khz, 1536 khz, 2048 khz or 2560 khz depending of the selection in cr1 register. in this case, bclk is locked to the recovered clock received from the line. input or output bclk is synchronous with fsa/fsb. datas are shifted in and out (on bx and br) at the bclk frequency in formats 1, 2, 3. in format 4 datas are shifted out at half the bclk frequency. 13 bx in 2b+d input. basic access data to transmit to the line is shifted in on the falling edges (at the bclk frequency or the half bclk frequency if format 4 is selected) during the assigned time-slots. when d channel port is enabled, only b1 & b2 sampled on bx. 14 dclk out d channel clock output when the d channel port is enabled in continuous mode. datas are shifted in and out (on dx and dr) at 16 khz on the falling and rising edges of dclk respectively. in master mode, dclk is synchronous with bclk. 15 dr out d channel data output when the d channel port is enabled. d channel data is shifted out from the uid on this pin in 2 selectable modes: in tdm mode data is shifted out at the bclk frequency (or half bclk frequency in format 4) on the ridsing edges when the assigned time slot is active. in continuous mode data is shifted in at the dclk frequency on the rising edge continuously. 16 dx in d channel data input when the d channel port is enabled. d channel data is shifted in from the uid on this pin in 2 selectable modes: in tdm mode data is shifted in at the bclk frequency (or half bclk frequency in format 4) on the falling edges when the assigned time slot is active. in continuous mode data is shifted in at the dclk frequency on the falling edge continuously. 17 cclk in clock input for the microwire control channel: data is shifted in and out on ci and co pins with cclk frequency following 2 modes. for each mode the cclk polarity is indifferent. cclk may be asynchronous with all the others uid clocks. 18 ci in microwire control channel serial input: two bytes data is shifted in the uid on this pin on the rising or the falling edge of cclk depending of the working mode. 19 co out microwire control channel serial output: two bytes data is shifted out the uid on this pin on the rising or the falling edge of cclk depending of the working mode. when not enabled by cs low, co is high impedance. 22 sfsx in out tx super frame synchronization. the rising edge of sfsx indicates the beginning of the transmit superframe on the line. in nt mode sfsx is always an output. in lt mode sfsx is an input or an output depending of the sfs bit in cr2 register. when sfsx is input, it must be synchronous of fsa. in dect mode this pin is always an input in lt configuration and is used to evaluate the round trip delay, in nt configuration is an output used to resynchronise the dect frame counter.( refer to page 25) 25 sfsr out rx super frame synchronization. the rising edge of sfsr indicates the beginning of the received superframe on the line. uid provides this output only when esfr bit in cr4 register is set to 1. lsd out line signal detect output (default configuration): this pin is an open drain output which is normally in the high impedance state but pulls low when the device previously in the power down state receives a wake-up by tone from the line. this signal is intended to be used to wake-up a micro-controller from a low power idle mode. the lsd output goes back in the high impedance state when the device is powered up. 26 int out interrupt output: latched open-drain output signal which is normally high impedance and goes low to request a read cycle. pending interrupt data is shifted out from co at the following read-write cycle. several pending interrupts may be queued internally and may provide several interrupt requests. int is freed upon receiving of cs low and can go low again when cs is freed. 27 cs in chip select input: when this pin is pulled low, data can be shifted in and out from the uid through ci & co pins. when high, this pin inhibits the microwire interface. for normal read or write operation, cs has to be pulled low for 16 cclk periods. STLC5412 7/74
pin functions (specific gci mode) pin name in/out description 6 fsa in out input or output depending of the configuration. fsa is a 8 khz clock which indicates the start of the frame on bx and br. 7 fsb out in nt/te non auto-mode configuration, fsb is a 8 khz pulse always indicating the second 64kbit/sec channel of the frame on br. s0 in when mo = 0 (lt/nt12 configuration): s0 associated with s1 and s2 selects a gci channel number on bx/br. test2 in input pin to select a transmission test in all auto mode configurations. test2 is associated with test1. 11 br out 2b+d and gci control channel open drain output. data is shifted out (at the half bclk frequency) on the first rising edge of bclk during the assigned channels slot. br is in high impedance state outside the assigned time slot and during the assigned time slot of a channel if it is disabled. 12 bclk in out bit clock input or output depending of the configuration. when bclk is an input, its frequency may be any multiple of 16 khz from 512 khz to 6176 khz.. when bclk is an output, its frequency is 512 khz in nt1 auto and ntrr auto configurations, 1536 khz in nt/te configuration; in this case, bclk is locked to the recovered clock received from the line. input or output bclk is synchronous with fsa. data are shifted in and out (on bx and br) at half the bclk frequency. 13 bx in 2b+d and gci control channel input. data is sampled by the uid on the second falling edge of bclk within the period of the bit, during the assigned channels time slot. 14 io4 in out general purpose programmable i/o configured by cr5 register in all non auto mode configurations. test1 in input pin to select a transmission test in all auto mode configurations. test1 is associated with test2. 15 io3 in out general purpose programmable i/o configured by cr5 register in all non auto mode configurations. ec out external control output pin in nt1 auto configuration. normaly high, this pin is pulled low when an eoc message ooperate 2b+d loopbacko is recognized from the line. lfs in local febe select: when tied to 1 the febe is locally looped back. see figure 10. 16 io2 in, out general purpose programmable i/o configured by cr5 register in all non auto mode configurations. ec out external control output pin in ltrr auto configuration. normaly high, this pin is pulled low when an arl command is received by the uid. es2 in external status input pin. in nt1 auto and ntrr auto configurations, this status is sent on the line through the ps2 bit. 17 s2 in when mo = 0 (lt/nt12 configuration): s2 associated with s0 and s1 selects a gci channel number on bx/br. conf2 in when mo = 1: configuration input pin. is used associated with conf1 to select configuration nt/te (non auto), nt1 auto, ltrr auto and ntrr auto. 18 io1 in out general purpose programmable i/o configured by cr5 register in all non auto mode configurations. es1 in external status input pin. in nt1 auto and ntrr auto configurations, this status is sent on the line through the ps1 bit. plld in pll1 can be disabled in ltrr configuration with this pin. 19 s1 in when mo = 0 (lt/nt12 configuration): s1 associated with s0 and s2 selects a gci channel number on bx/br. conf1 in when mo = 1: configuration input pin. is used associated with conf2 to select configuration nt/te (non auto), nt1 auto, ltrr auto and ntrr auto. STLC5412 8/74
pin functions (specific gci mode) pin name in/out description 22 rfs in remote febe select: when tied to 0 the remote febe is not transferred. when tied to 1 febe is transparently reported. see figure 10. sfsx in out tx super frame synchronization. in lt mode this pin is an input giving the tx super frame synchronization if sfs = 0 in cr2. it becomes an output if sfs = 1 with isw free running on the line. in nt mode this pin is always an output giving the tx super frame position. if dect mode is selected (dect = 1 in cr7) this pin provide the dect synchronization pulse at each validated reception of the dect eoc message. 25 ais in analog interface select for all auto mode configurations sfsr out rx super frame synchronization. the rising edge of sfsr indicates the beginning of the received superframe on the line. uid provides this output only when esfr bit in cr4 register is to 1 and lt/nt12 or nt/te configuration is done. lsd out line signal detect output (default configuration): this pin is an open drain output which is normally in the high impedance state but pulls low when the device previously in the power down state receives a wake-up by tone from the line. this signal is intended to be used to wake-up a micro-controller from a low power idle mode. the lsd output goes back in the high impedance state when the device is powered up. 26 res in reset input pin with internal pull-up resistor. when pulled low, all registers of the uid are reset to their default values. uid is configured according to configuration inputs bias excluding mw input which must be maintained at the 0 volt. minimum recommended pulse length is 200 m s. 27 m0 in configuration input pin. when pulled low, gci channel assigner is selected (channel number defined by inputs s0, s1, s2). when pulled high, uid is configured by pins conf1 and conf2. multiple function pin description pin 6: fsa function or in/out conditions function in/ou t mw(pin) = 1 cms(cr1) = 1 fsa out cms(cr1) = 0 fsa in mw(pin) = 0 mo(pin) = 1 conf2(pin) = 1 fsa out conf2(pin) = 0 conf1(pin) = 1 fsa in conf1(pin) = 0 fsa out mo(pin) = 0 fsa in STLC5412 9/74
multiple function pin description pin 7: s0/fsb/test2 function or in/out conditions function in/ou t mw(pin) = 1 cms(cr1) = 1 fsb out cms(cr1) = 0 fsb in mw(pin) = 0 mo(pin) = 1 conf2(pin) = 1 conf1(pin) = 1 test2 in conf1(pin) = 0 fsb out conf2(pin) = 0 test2 in mo(pin) = 0 s0 in pin 10: tsr/sclk/tclk function or in/out conditions function in/ou t mw(pin) = 1 nts(cr2) = 1 sclk out nts(cr2) = 0 tsr out od mw(pin) = 0 mo(pin) = 1 conf2(pin) = 1 sclk out conf2(pin) = 0 conf1(pin) = 1 tsr out od conf1(pin) = 0 sclk out mo(pin) = 0 nts(cr2) = 1 sclk out nts(cr2) = 0 tsr out od pin 12: bclk function or in/out conditions function in/ou t mw(pin) = 1 cms(cr1) = 1 bclk out cms(cr1) = 0 bclk in mw(pin) = 0 mo(pin) = 1 conf2(pin) = 1 bclk out conf2(pin) = 0 conf1(pin) = 1 bclk in conf1(pin) = 0 bclk out mo(pin) = 0 bclk in STLC5412 10/74
multiple function pin description pin 14: dclk/io4/test1 with pull up resistor function or in/out conditions function in/ou t mw(pin) = 1 den(cr2) = 1 dmo(cr2) = 1 dclk out dmo(cr2) = 0 reserved reserved den(cr2) = 0 reserved reserved mw(pin) = 0 mo(pin) = 1 conf2(pin) = 1 conf1(pin) = 1 test1 in conf1(pin) = 0 io4(cr5) = 1 i4 in io4(cr5) = 0 o4 out conf2(pin) = 0 test1 in mo(pin) = 0 io4(cr5) = 1 i4 in io4(cr5) = 0 o4 out pin 15: dr/io3/ec/lfs with pull up resistor function or in/out conditions function in/ou t mw(pin) = 1 den(cr2) = 1 dr out den(cr2) = 0 reserved reserved mw(pin) = 0 mo(pin) = 1 conf2(pin) = 1 conf1(pin) = 1 ec out conf1(pin) = 0 io3(cr5) = 1 i3 in io3(cr5) = 0 o3 out conf2(pin) = 0 lfs in mo(pin) = 0 io3(cr5) = 1 i3 in io3(cr5) = 0 o3 out pin 16: dx/io2/ec/es2 with pull up resistor function or in/out conditions function in/ou t mw(pin) = 1 den(cr2) = 1 dx in den(cr2) = 0 reserved reserved mw(pin) = 0 mo(pin) = 1 conf2(pin) = 1 conf1(pin) = 1 es2 in conf1(pin) = 0 io2(cr5) = 1 i2 in io2(cr5) = 0 o2 out conf2(pin) = 0 conf1(pin) = 1 ec out conf1(pin) = 0 es2 in mo(pin) = 0 io2(cr5) = 1 i2 in io2(cr5) = 0 o2 out STLC5412 11/74
multiple function pin description pin 17: cclk/s2/conf2 function or in/out conditions function in/ou t mw(pin) = 1 cclk in mw(pin) = 0 mo(pin) = 1 conf2 in mo(pin) = 0 s2 in pin 18: ci/io1/es1/plldwith pull up resistor function or in/out conditions function in/ou t mw(pin) = 1 ci in mw(pin) = 0 mo(pin) = 1 conf2(pin) = 1 conf1(pin) = 1 es1 in conf1(pin) = 0 io1(cr5) = 1 i1 in io1(cr5) = 0 o1 out conf2(pin) = 0 conf1(pin) = 1 plld in conf1(pin) = 0 es1 in mo(pin) = 0 io1(cr5) = 1 i1 in io1(cr5) = 0 o1 out pin 19: co/s1/conf1 function or in/out conditions function in/ou t mw(pin) = 1 co out mw(pin) = 0 mo(pin) = 1 conf1 in mo(pin) = 0 s2 in pin 22: sfsx/rfs with pull up resistor function or in/out conditions function in/ou t mw(pin) = 1 nts(cr2) = 1 sfsx out nts(cr2) = 0 sfs(cr2) = 1 sfsx out sfs(cr2) = 0 sfsx in mw(pin) = 0 mo(pin) = 1 conf2(pin) = 1 sfsx out conf2(pin) = 0 rfs in mo(pin) = 0 nts(cr2) = 1 sfsx out nts(cr2) = 0 sfs(cr2) = 1 sfsx out sfs(cr2) = 0 sfsx in STLC5412 12/74
multiple function pin description pin 25: lsd/sfsr/ais function or in/out conditions function in/ou t mw(pin) = 1 esfr(cr4) = 1 sfsr out od esfr(cr4) = 0 lsd out od mw(pin) = 0 mo(pin) = 1 conf2(pin) = 1 conf1(pin) = 1 ais in conf1(pin) = 0 esfr(cr4) = 1 sfsr out od esfr(cr4) = 0 lsd out od conf2(pin) = 0 ais in mo(pin) = 0 esfr(cr4) = 1 sfsr out od esfr(cr4) = 0 lsd out od pin 26: int/res with pull up resistor function or in/out conditions function in/ou t mw(pin) = 1 int out od mw(pin) = 0 res in pin 27: cs/mo function or in/out conditions function in/ou t mw(pin) = 1 cs in mw(pin) = 0 mo in notes : out od = open drain output STLC5412 13/74
functional description digital interfaces STLC5412 provides a choice between two types of digital interface for both control data and (2 b+d) basic access data. these are: a) general circuit interface: gci. b) microwire/digital system interface: m w/dsi the device will automatically switch to one of them by sensing the mw input pin at the power up. m w/dsi mode microwire control interface the microwire interface is enabled when pin mw equal one. internal registers can be written or read through that control interface. it is constituted of 5 pins: ci: co: cclk: cs: int: data input data output data clock input chip select input interrupt output transmission of data onto ci & co is enabled when cs input is low. a write cycle or a read cycle is always consti- tuted of two bytes. cclk must be pulsed 16 times while cs is low. transmission of data onto ci & co is enabled fol- lowing 2 modes. mode a: the first cclk edge after cs fall- ing edge (and fifteen others odd cclk edges) are used to shift in the ci data, the even edges being used to shift out the co data. mode b: the cclk first edge after cs falling edge (and the fifteen others odd cclk edges) are used to shift out the co data, the even edges being used to shift in the ci data. for each mode the first cclk edge after cs fall- ing edge can be positive or negative: the uid automaticaly detects the cclk polarity. mode a is the default value. to select the mode b, write mwps register. you can write in the uid on ci while the uid send back a register content to the microprocessor. if the uid has no message to send, it forces the co output to all zero's. if the uid is to be read (status change has oc- cured in the uid or a read-back cycle has been requested by the controller), it pulls the int out- put low until cs is provided. int high to low transition is not allowed when cs is low (the uid waits for cs high if a pending interrupt occurs while cs is low) . when cs is high, the co pin is in the high imped- ance state. write cycle the format to write a 8 bits message into the uid is: a7 a6 a5 a4 a3 a2 a1 a0 1st byte d7 d6 d5 d4 d3 d2 d1 d0 2nd byte a7-a1: a0: d7-d0: register address write/read back indicator register content after the first byte is shifted in, register address is decoded. a0 set low indicates a write cycle: the content of the following received byte has to be loaded into the addressed register. a0 set high indicates a read-back cycle request and the byte following is not significant. the uid will respond to the request with an interrupt cycle. it is then possible for the microprocessor to re- ceive the required register content after several other pending interrupts. to write a 12bits message, the difference is: limited address field: a7 - a4 extended data field (d11 - d8): a3 - a0. the write/read back indicator doesn't apply; to read and write a 12 bits register two addresses are necessary. read cycle when uid has a register content to send to the microprocessor, it pulls low the int output to re- quest cs and cclk signals. note that the data to send can be the content of a register previously requested by the microprocessor by means of a read-back request. the format of the 8 bits message sent by the uid is: a7 a6 a5 a4 a3 a2 a1 a0 1st byte d7 d6 d5 d4 d3 d2 d1 d0 2nd byte a7-a1: a0: d7-d0: register address forced to 1 if read back forced to 0 if spontaneous register content STLC5412 14/74
to read a 12 bits message, the difference is: limited address field: a7 - a4 extended data field (d11 - d8): a3 - a0. the write/read back indicator doesn`t exit. digital system interface two b channels, each at 64 kbit/s and one d chan- nel at 16 kbit/s form the basic access data. basic access data is transferred on the digital system in- terface with several different formats selectable by means of the configuration register cr1. the dsi is basically constituted of 5 wires (see fig.2 and 3): bclk bx br fsa fsb bit clock data input to transmit to the line data output received from the line transmit frame sync receive frame sync it is possible to separate the d channel from the b channels and to transfer it on a separate digital interface constituted of 2 pins: dx dr d channel data input d channel data ouput the tdm (time division multiplex) mode uses the same bit and frame clocks as for the b chan- nels. the continuous mode uses an internally generated 16 khz bit clock output: dclk d channel clock output for all formats when d channel port is enabled ocontinuous modeo is possible. when the d chan- nel port is enabled in tdm mode, d bits are as- signed according to the related format on dx and dr . STLC5412 provides a choice of four multiplexed formats for the b and d channels data as shown in fig.2 and 3. format 1: the 2b+d data transfer is assigned to the first 18 bits of the frame on br and bx i/0 pins. channels are assigned as follows: b1(8 bits), b2(8 bits), d(2 bits), with the remaining bits ig- nored until the next frame sync pulse. format 2: the 2b+d data transfer is assigned to the first 19 bits of the frame on br and bx i/o pins. channels are assigned as follows: b1(8 bits), d(1 bit), 1 bit ignored, b2(8 bits), d(1 bit), with the remaining bits ignored until the next frame sync pulse. format 3: b1 and b2 channels can be inde- pendently assigned to any 8 bits wide time slot among 64 (or less) on the bx and br pins. the transmit and receive directions are also inde- pendent. when tdm mode is selected, the d channel can be assigned to any 2 bits wide time slot among 256 on the bx and br pins or on the dx and dr pins (d port disabled or enabled in tdm mode respectively). format 4: is a gci like format excluding monitor channel and c/i channel. the 2b+d data transfer is assigned to the first 26 bits of the frame on br and bx i/o pins. channels are assigned as fol- lows. b1(8 bits) b2(8 bits), 8 bits ignored, d(2 bits), with remaining bits ignored up to the next frame sync pulse. when the digital interface clocks are selected as inputs, fsa must be a 8 khz clock input which in- dicates the start of the frame on the data input pin bx. when the digital interface clocks are selected as outputs, fsa is an 8 khz output pulse con- forming to the selected format which indicates the frame beginning for both tx and rx direc- tions. when the digital interface clocks are selected as inputs, fsb is a 8 khz clock input which defines the start of the frame on the data ouput pin br. when the digital interface clocks are selected as outputs, fsb is a 8 khz output pulse indicating the second 64kbit/s slot. two phase-relations between the rising edge of fsa/fsb and the first (or second for fsb as out- put) slot of the frame can be selected depending on format selected: delayed timing mode or non delayed timing mode. non delayed data mode is similar to long frame timing on the comboi/ii series of devices: the first bit of the frame begins nominally coincident with the rising edge of fsa/b. when output, fsa is coincident with the first 8 bits wide time-slot while fsb is coincident with the second 8 bits wide time-slot. non delayed mode is not available in format 2. delayed timing mode, which is similar to short frame sync timing on combo i/ii, in which the fsa/b input must be set high at least a half cycle of bclk earlier the frame beginning. when out- put, fsa 1bit wide pulse indicates the first 8 bits wide time-slot while fsb indicates the second. delayed mode is not available in format 4. 2b+d basic access data to transmit to the line can be shifted in at the bclk frequency on the falling edges during the assigned time-slots. when d channel port is enabled, only b1 & b2 data is shifted in during the assigned time slots. in format 4, data is shifted in at half the bclk fre- quency on the receive falling edges. 2b+ d basic access data received from the line can be shifted out from the br output at the bclk frequency on the rising edges during the assigned time-slots. elsewhere, br is in the high impedance state. when the d channel port is enabled, only b1 & b2 data is shifted out from br. in format 4, data is shifted out at half the bclk frequency on the transmit rising edges; there is 1.5 period delay between the rising transmit edge and the receive falling edge of bclk. STLC5412 15/74
bit clock bclk determines the data shift rate on the digital interface. depending on mode se- lected, bclk is an input which may be any multi- ple of 8 khz from 256 khz to 6176 khz or an out- put at a frequency depending on the format and the frequency selected. possible frequencies are: 256 khz, 512 khz, 1536 khz, 2048 khz, 2560 khz. in format 4 the use of 256khz is forbidden. bclk is synchronous with fsa/b frame sync sig- nal. when output, bclk is phased locked to the recovered clock received from the line. figure 2 : dsi interface formats: master mode. STLC5412 16/74
figure 3 : dsi interface formats: slave mode. STLC5412 17/74
gci mode the gci is a standard interface for the intercon- nection of dedicated isdn components in the dif- ferent equipments of the subscriber loop : in a terminal, gci interlinks the STLC5412, the isdn layer 2 (lapd) controller and the voice/data processing components as an audio-processor or a terminal adaptor module. in nt1-2, pabx subscriber line card, or central office line card (lt), gci interlinks the uid, the isdn layer 2 (lapd) controllers and eventually the backplane where the channels are multi- plexed. in nt1, gci interlinks sid-gci and STLC5412, via automode (nt1-auto). in regenerators, gci links both STLC5412 uid in automode (nt-rr- auto, lt-rr-auto). (see fig. 4a) frame structure 2b+d data and control interface is transferred in a time-division multiplexed mode based on 8 khz frame structure and assigned to four octets per frame and direction.(see fig.4b). the 64 kbit/s channels b1 and b2 are conveyed in the first two octets; the third octet (m: monitor) is used for transferring most of the control and status registers; the fourth octet (sc: signalling & control) contains the two d channel bits, the four c/i (command/lndicate) bits controlling the activa- tion/deactivation procedures, and the e & a bits which support the handling of the monitor chan- nel. these four octets per frame serving one isdn subscribers line form a gci channel. one gci channel calls for a bit rate of 256 kbit/s. in nt1-2s or subscriber line cards up to 8 gci channels may be carried in a frame of a gci mul- tiplex. the bit rate of a gci multiplex may be from 256 kbit/s and up to 3088 kbit/s. adjacent 4-octet slots from the frame start are numbered 0 to 7. the gci channel takes the number of the slot it occupies. spare bits in the frame beyond 256 bits from the frame start will be ignored by gci com- patible devices but may be used for other pur- poses if required (see fig.4c). gci channel num- ber is selected by biasing pins s0,s1,s2. physical links four physical links are used in the gci. transmitted data to the line: bx received data from the line: br data clock: bclk frame synchronization clock: fsa gci is always synchronized by frame and data clocks derived by any master clock source. a device used in nt mode can deliver clock sources able to synchronize gci, either directly, or via a local clock generator synchronized on the line by means of the sclk 15.36 mhz output clock. frame clock and data clock could be inde- pendent of the internal devices clocks. logical one on the br output is the high impedance state while logical zero is low voltage. for e and a bits, active state is voltage low while inactive state is high impedance state. lt nt-rr-auto lt-rr-auto nt1-auto sid-gci sid-gci terminal nt1 repetor nt line termination su u u figure 4a: gci configurations of the uid priva te terminal or nt1-2 figure 4a: gci configurations of the uid. STLC5412 18/74
figure 4b: gci interface format bx/br b1 b2 m d c/i a e 88 8242 b1 b2 m d c/i a e 88 8242 b1 b2 m d c/i a e 88 8242 gci channel 0 gci channel 1 gci channel 7 fsb fsa 8 khz bx/br b1 b2 m d c/i a e 8 8 8 242 gci channel 0 bclk fsa 8 khz slave mode bclk free master mode figure 4b: gci interface format. master mode (bclk = 1.536mhz) STLC5412 19/74
figure 4c: gci multiplex examples, (slave mode). STLC5412 20/74
data is transmitted in both directions at half the data clock rate. the information is clocked by the transmitter on the front edge of the data clock and can be accepted by the receiver after 1 to 1.5 pe- riod of the data clock. the data clock (bclk) is a square wave signal at twice the data transmission frequency on bx and br with a 1 to 1 duty cycle. the frequency can be choosen from 512 to 6176 khz with 16 khz modularity. data transmission rate depends only on the data clock rate. the frame clock fsa is a 8 khz signal for syn- chronization of data transmission. the front edge of this signal gives the time reference of the first bit in the first gci input and output channel, and reset the slot counter at the start of each frame. when some gci channels are not selected on devices connected to the same gci link, these time slots are free for alternative uses. gci configuration selection is done by biasing of input pins mw, m0, conf1, conf2 according to table 1. table 1: gci configuration selection. pin number pin name configuration plcc44 dip28 lt/nt12 (1) nt/te nt1-auto lt-rr-auto nt-rr-auto 4328mw00000 4227m001111 27 19 s1/conf1 s1 0 1 1 0 25 17 s2/conf2 s2 1 1 0 0 10 7 s0/fsb/test2 s0 fsb test2 test2 test2 26 18 io1/es1 (2) io1 io1 es1 pldd es1 24 16 io2/es2 (2) io2 io2 es2 ec es2 23 15 io3/ec (2) io3 io3 ec lfs lfs 22 14 io4/test1 (2) io4 io4 test1 test1 test1 35 22 sfsx/rfs (2) sfsx sfsx sfsx rfs rfs (1) differentation between lt and nt configuration done by bit nts in cr2 register; gci in slave mode. when nt1-auto or nt-rr-auto configuration is selected, bclk bit clock frequency of 512 khz is automatically selected when nt configuration is selected, bclk bit clock frequency of 1536 khz is automatically selected. (2) connected to v cc through internal pull-up resistors. STLC5412 21/74
monitor channel the monitor channel is used to write and read all STLC5412 internal registers. protocol on the monitor channel allows a bidirectional transfer of bytes between uid and a control unit with ac- knowledgement at each received byte. bytes are transmitted on the br output and received on the bx input in the monitor channel time slot. a write or read cycle is always constituted of two bytes.(see fig. 5). it is possible to operate several write or read cycles within a single monitor mes- sage. note: special format is used for eoc channel. write cycle the format to write a message into the uid is: a7 a6 a5 a4 a3 a2 a1 a0 1st byte d7 d6 d5 d4 d3 d2 d1 d0 2nd byte a7-a1: a0: d7-d0: register address write/read back indicator register content after the first byte is shifted in, register address is decoded. a0 set low indicates a write cycle: the content of the following received byte has to be loaded into the addressed register. a0 set high indicates a read-back cycle request. the second byte content is not significative. STLC5412 will respond to the request by sending back a message with the register content associ- ated with its own address. it is then possible for the microprocessor to receive the required regis- ter content after several other pending messages. to avoid any loss of data, it is recommended to operate only one read-back request at a time. note: special format is used for eoc channel. read cycle when uid has a register content to send to the controller, it send it on the monitor channel di- rectly. note that the data to send can be the con- tent of a register previously requested by the controller by means of a read-back request. the format of the message sent by the uid is: a7 a6 a5 a4 a3 a2 a1 a0 1st byte d7 d6 d5 d4 d3 d2 d1 d0 2nd byte a7-a1: a0: d7-d0: register address forced to 0 if spontaneous interrupt, forced to 1 if read- back register content exchange protocol STLC5412 validates a received byte if it is de- tected two consecutive times identical. (see fig. 5) the exchange protocol is identical for both direc- tions. the sender uses the e bit to indicate that it is sending a monitor byte while the receiver uses a bit to acknowledge the received byte.when no message is transferred, e bit and a bit are forced to inactive state. a transmission is started by the sender (transmit section of the monitor channel protocol handler) by putting the e bit from inactive to active state and by sending the first byte on monitor channel in the same frame. transmission of a message is allowed only if a bit sent from the receiver has been set inactive for at least two consecutive frames. when the receiver is ready, it validates the incoming byte when received identical in two consecutive frames. then, the receiver set a bit from the inactive to the active state (preacknowl- edgement) and maintain active at least in the fol- lowing frame (acknowledgement). if validation is not possible (two last bytes re- ceived are not identical) the receiver aborts the message by setting the a bit active for only a sin- gle frame.the second byte can be transmitted by the sender putting the e bit from the active to the inactive state and sending the second byte on the monitor channel in the same frame . the e bit is set inactive for only one frame. if it remains inac- tive more than one frame, it is an end of mes- sage. the second byte may be transmitted only after receiving of the pre-acknowledgement of the previous byte . each byte has to be transmitted at least in two consecutive frames. the receiver validates the current received byte as for the first one and then set the a bit in the next two frames first from the active state to the inactive state (pre-acknowledgement) and back to the active (acknowledgement). if the receiver can- not validates the received current byte (two bytes received not identical)it pre-acknowledges nor- mally but let the a bit in the inactive state in the next frame which indicates an abort request . if a message sent by the uid is aborted, the uid will send again the complete message until receiving of an acknowledgement . a message received by the uid can be acknowledged or aborted with flow control. the most significant bit (msb) of monitor byte is sent first on the monitor channel. e & a bits are active low and inactive state on br is 5 v. when no byte is transmitted, monitor channel time slot STLC5412 22/74
on br is in the high impedance state. a 24 ms timer is implemented in the uid. this timer (when enabled) starts each time the sender starts a byte sending and waits for a pre acknow- ledgement. c/i channel the c/i channel is used for txact and rxact registers write and read operation. however, it is possible to access to act registers by monitor channel: this access is controled by the cid bit in cr2 register. the four bits code (c1,c2,c3,c4) of txact reg- ister can be loaded in the uid by writing perma- nently this code in the c/i channel time-slot on bx input every gci frames. the uid takes into ac- count the received code when it has been re- ceived two consecutive times identical. when a status change occurs in the rxact register, the new (c1,c2,c3,c4) code is sent in the c/i chan- nel time-slot on br output every gci frames. this code is sent permanently by the uid until a new status change occurs in rxact register. c1 bit is sent first to the line. line coding and frame format 2b1q coding rule requires that binary data bits are grouped in pairs so called quats (see tab.2). each quat is transmitted as a symbol, the magni- tude of which may be 1 out 4 equally spaced volt- age levels (see fig. 6). +3 quat refers to the nominal pulse waveform specified in the ansi standard. other quats are deduced directly with respect of the ratio and keeping of the waveform. the frame format used in uid follows ansi speci- fication (see tab. 3 and 4). each complete frame consists of 120 quats, with a line baud rate of 80 kbaud, giving a frame duration of 1.5ms. a nine quats lenght sync-word defines the framing boundary. furthermore, a multiframe consisting of 8 frames is defined in order to provide sub-chan- nels within the spare bits m1 to m6. inversion of the syncword defines the multiframe boundary. in lt, the transmit multiframe starting time may be synchronized by means of a 12 ms period of time pulse on the sfsx pin selected as an input (bit sfs in cr2); if sfsx is selected as an output, sfsx provides a square wave signal with the ris- ing edge indicating the multiframe starting time. in nt, the transmit multiframe starting time is pro- figure 5: gci monitor channel messaging examples. two bytes message - normal transmission (m1) xm1 tx tx rx m1 m2 m2 xxx 1st byte pre-ack ack 2nd byte pre-ack ack 3rd byte?? pre-ack?? eom ready for ready for a message (m1) (m1) (m2) (m2) (m2) (x) (x) e & a bits timing two bytes message aborted on the second and retransmitted tx tx rx 1st byte pre-ack ack 2nd byte pre-ack abort eom 1st byte pre-ack 3rd byte?? ready for retransmission ready for a message (m1) (m1) (m1) (m2) (m2) (m2) (x) (or abort ack) (m1) (m1) xm1m1 m2 m2 x xx x m1 m1 m2 tx m tx e rx a tx m tx e rx a STLC5412 23/74
vided on sfsx output by the rising edge of a 12 ms period square wave signal. lt or nt, when pin 25 is selected as sfsr by mean of bit esfr in cr4, sfsr is a square wave open drain output in- dicating the received superframe on the line. (see figure 7). prior to transmisssion, all data, with the exception of the sync-word,is scrambled using a self-synchronizing scrambler to perform the speci- fied 23rd-order polynomial. descrambling is in- cluded in the receiver. polynomial is different de- pending on the direction lt to nt or vice versa. transmit section data transmitted to the line consists of the 2b+d channel data received from the digital interface through an elastic data buffer allowing any phase deviation with the line, the activation/deactivation bits (m4) from the on-chip activation sequencer, the crc code plus maintenance data (eoc chan- nels) and other spare bits in the overhead chan- nels (m4, m5, m6). data is multiplexed and scrambled prior to addition of the sync-word, which is generated within the device. a pulse waveform synthesizer then drives the transmit fil- ter, which in turn passes the line signal to the line driver. the differential line-driver outputs, lo+, lo- are designed to drive a transformer through an external termination circuit. a 1:1.5 trans- former designed as shown in the STLC5412 user guide, results in a signal amplitude of 2.5v pk nominal on the line for single quats of the +3 level. (see output pulse template fig.8). short-cir- cuit protection is included in the output stage; over-voltage protection must be provided exter- nally. in lt applications, the network reference clock given by the fsa 8khz clock input synchronizes the transmitted data to the line. the digital inter- face normally accepts bclk and fsa signals from the network, requiring the selection of slave mode in cr1. a digital phase-locked loop (dpll 1) on the uid allows the sclk frequency to be plesiochronous with respect to the network reference clock (8 khz fsa input). with a toler- ance on the xtal1 oscillator of 15.36 mhz +/- 100 ppm, the lock-in range of dpll1 allows the network clock frequency to deviate up to +/- 50ppm from nominal. in lt, if dsi is selected in master mode, (mi- crowire only, bit cms = 1 in cr1), bclk and fsa signals are outputs frequency synchronized to xtal1 input, dpll 1 is disabled. in nt applications, data is transmitted to the line with a phase deviation of half a frame relative to the received data as specified in the ansi stand- ard. receive section the receive input signal should be derived from the transformer by a coupling circuit as shown in the user guide. at the front end of the receive section is a continuous filter which limits the noise bandwidth to approximately 100khz. then, an analog pre-canceller provides a degree of echo cancellation in order to limit the dynamic range of the composite signal which noise bandwidth lim- ited by a 4th order butterworth switched capacitor low pass filter. after an automatic gain control, a 13bits a/d converter then samples the composite received signal before the echo cancellation from local transmitter by means of an adaptive digital transversal filter. the attenuation and distortion of the received signal from the far-end, caused by the line, is equalized by a second adaptive digital filter configured as a decision feedback equal- izer (dfe), that restores a flat channel response with maximum received eye opening over a wide spread of cable attenuation characteristics. a timing recovery circuit based on a dpll (digital phase-locked loop) recovers a very low-jitter clock for optimum sampling of the received sym- bols. the 15.36mhz crystal oscillator (or the logic level clock input) provides the reference clock for the dpll. in nt configuration, sclk output pro- vides a very low jitter 15.36mhz clock synchro- nized from the line. received data is then detected and flywheel syn- chronization circuit searches for and locks onto the frame and superframe syncwords. STLC5412 is frame-synchronized when two consecutive synchwords have been consecutively detected. frame lock will be maintained until six consecu- tive errored sync-words are detected, which will cause the flywheel to attempt to re-synchronize. if a loss of frame sync condition persists for 480ms the device will cease searching, cease transmit- ting and go automatically into the reset state, ready for a further cold start. when uid is frame- synchronized, it is superframe-locked upon the first superframe sync-word detection. no loss of superframe sync-word is provided. while the receiver is synchronized, data is de- scrambled using the specified polynomial, and in- dividual channels demultiplexed and passed to their respective processing circuits: user's 2b+d channel data is transmitted to the digital interface through an elastic data buffer allowing any phase deviation with the line; the activation/deactivation bits (m4) are transmitted to the on-chip activation sequencer; crc is transmitted to crc checking section while maintenance data (eoc) and other spare bits in the overhead channels (m4, m5, m6) are stored in their respective rx registers. in nt applications, if the digital interface is se- lected in master mode (see cr1) bclk and fsa clock outputs are phase-locked to the recovered clock. if it is selected in slave mode ie for nt1-2 application, the on-chip elastic buffers allow bclk and fsa to be input from an external source, which must be frequency locked to the re- ceived line signal ie using the sclk output but STLC5412 24/74
with arbitrary phase. elastic buffers the uid buffers the 2b+d data in elastic fifos which are 3 line-frames deep in each direction. when the digital interface is a timing slave, these fifos compensate for relative jitter and wander between the digital interface and the line. each buffer can absorb wander up to 18 m s at 80 khz max without oslipo. this is particulary convenient for nt1-2 or pabx application in case the local reference clock is jitterized and wandered relative to the incoming signal from the line. dect synchronization in a dect system the u interface is used for digi- tal transmission between the base station control- ler (lt) and the base station (nt). the u inter- face allows the transmission of 4 dect channels through b1, b2 using adpcm compression. be- side the d channel allows the exchange of signal- ling information between the base station control- ler (bsc) and the base station (bs). seamless handover (for switching the radio-com- munication from one base station to another) re- quires additional features in u interface circuit for base stations synchronisation. dect oriented features in u interface possibility to measure the round-trip delay be- tween bsc and bs. the different delay of each bsc-bs connec- tion can be compensated in each bs with a preset counter that is loaded with the delay value provided by the STLC5412 in the bsc and sent to the bs via the d channel. round trip delay (rtd) measurement allows to estimate the link delay (sfsrnt-sfsxlt = rtd/2+konst) with a total accuracy of +/- 200 nsec when STLC5412 is used both in bsc and bs. the total accuracy is the sum of two con- tributions. the process spread on internal propagation delays ( 166.5ns) and jitter on re- covered clock in lt ( 32.5ns). dect frames synchronisation. the bsc must synchronise all the bss con- nected to itself. a synchronisation pulse dec- sync is provided by the network to all the STLC5412 devices in the bsc (lt). the STLC5412 devices synchronise the 2b1q frames on the u link with decsync and send an eoc message to the corresponding bs (nt). the STLC5412 in the bs (nt) on recep- tion of the eoc message provides a pulse to preset the counter for dect frame generation. the jitter related to this pulse is the jitter of the recovered clock in nt. maximum jitter guaran- teed on all etsi loops is 130ns. these two features allow the bsc to generate synchronous dect frames (160ms) and multi- frames with maximum phase difference of 330ns. lt dect mode in lt dect mode the STLC5412 provides round trip delay estimation with a resolution of +/- 33 nsec. and automatic eoc dect message trans- fer for base stations synchronisation. the decsync pulse is applied to pin sfsx (cr2.7=0). the decsync period must be multi- ple of 12ms and in phase with fsa. the sfsx in- put pulse resets the line frame counter when the device is in power-up. after power-up, before ac- tivation, it is suggested to wait for the first avail- able decsync pulse. if not, the decsync pulse will generate a jump in the line synchronisa- tion, that can cause a line deactivation. round trip delay estimation procedure the round trip delay is the delay between transmit sync word (isw) and receive sync word on the line. it can be estimated from three parameters that can be read in internal registers: tdd: total digital delay delay between sfsx and sfsr in steps of 12.5 m sec. it is available in register dbaud0-4 edd: elastic digital delay value to add to tdd that takes into account the internal elastic memory state. it is available in register dbaud5-7 ced: clock elastic delay it provides the phase difference between trans- mit and receive clocks in steps of 65.1 nsec. it is available in register dtxrx. see application note for use. dect eoc message transfer if cr7.0 = 1 (dect mode) a synchronisation pulse on pin sfsx triggers the dect eoc message transfer. the message stored in decteoc register is transmitted 3 times in the eoc channel starting from the 1st avail- able superframe following the decsync pulse on the sfsx pin. see application note for use. nt dect mode in nt dect mode the STLC5412 after recogni- tion of dect eoc message stored in dect eoc register, generates a pulse on pin sfsx, synchro- nous with next sfsr edge. in this way the STLC5412 provides on pin sfsx a pulse used to resynchronise the dect frame counter in the base station. the lock bit in cr7 register can be used to enable the locking of fsa with sfsr after line is activated. in particular the fsa rising edge will occur 62.5us after the sfsr rising edge. STLC5412 25/74
if not programmed this bit is inactive. the relock will take place only after completion of present monitor transfer. (eom received). this locking will cause a phase jump of fsa and bclk signals. to avoid problems on the gci bus that is synchro- nized by fsa, a number of 5 gci frames after the phase jump will be ignored by the STLC5412. for proper system operation before writing the lock bit in cr7 register, the mob bit (mask overhead bits) in cr4 register should be set to 1 to avoid spontaneous monitor message genera- tion from STLC5412. following the relocking the mob bit should be set back to desired value after a minimum time to be defined (ex. 1msec). the suggested procedure is to program the lock bit in cr7 register after the ai indication from STLC5412. in this case the system controller knows when the phase jump takes place and can reset the transmission/receptionof the gci controller. notes: the dect eoc message reception generates an interrupt as a normal eoc message according to the rules stored in opr register. the dect sync message must be checked 3 times (reset value of opr register). if it is not detected 3 times iden- tical no pulse is generated. the dect pulse width on output pin sfsx is 6msec. maintenance functions m channel in each frame there are 6 ooverheado bits assigned to various control and maintenance functions. some programmable processing of these bits is provided on chip while interaction with an external controller provides the flexibility to take full advan- tage of the maintenance channels. see opr, txm4, txm56, txeoc, rxm4, rxm56, rxeoc tx eoc sfsx n*12ms (n=40 minimum) 6ms dect dect dect txeoc txeoc txeoc txeoc txeoc txeoc txeoc txeoc txeoc dect dect dect lt dect mode nt dect mode sfsx n*12ms rx eoc 12 ms sfsr rxeoc int rxeoc int rxeoc int rxeoc int 6ms dect dect dect rxeoc rxeoc rxeoc rxeoc rxeoc rxeoc rxeoc rxeoc rxeoc dect dect dect 36ms + line delay timing diagrams for dect STLC5412 26/74
registers description for details. new data written to any of the overhead bit transmit registers is resyn- chronized internally to the next available complete superframe or half superframe, as appropriate. embedded operation channel (eoc) the eoc channel consists of two complete 12 bits messages per superframe, distributed through the m1, m2 and m3 bits of each frame. each mes- sage is composed of 3 fields; a 3 bit address identifying the message destination/origin, a 1 bit indicator for the data mode i.e. encoded message or raw data, and an 8 bits information field. the control interface (microwire or monitor channel in gci) provides access to the complete 12 bits of every message in tx and rx eoc registers. when non-auto mode is selected, uid does not in- terpret the received eoc messages e.g. osend cor- rupted crco; therefore the appropriate command instruction must be written to the device e.g. oset to one bit ctc in register cr4o. it is possible to select a transparent transmission mode in which the eoc channel can be considered as a transparent 2 kbit/s channel. see opr register description for details. when auto-mode is selected in gci configuration, uid performs automatic recognition / acknow- ledgement of the eoc messages sent by the net- work according to processing defined in ansi standard and illustrated in figure 9. when uid rec- ognizes a message with the appropriate address and a known command, it performs automatically the relevant action inside the device and send a message at the digital interface as appropriate. ta- ble 5 gives the list of recognizedeoc messages and associated actions. when nt-rr-auto configuration is selected, eoc addressing is processed according to appen- dix e of t1e1.601 standard: if address of the eoc message received from lt is in the range of 2 to 6, uid decrements address and pass the message onto gci. if address of the eoc message received from gci is in the range of 1 to 5, uid increments address and pass the message onto the line toward lt. if data/msg indicator is set to 0, uid pass data on transparently with eoc address as de- scribed above. m4 channel m4 bit positions of every frame is a channel in which are transmitted data bits loaded from the txm4 transmit register and from the on-chip acti- vation sequencer each superframe. on the re- ceive side, m4 bits from one complete superframe are first validated and then stored in the rxm4 receive register or transmitted to on-chip activa- tion sequencer. see opr, txm4 and rxm4 reg- isters description for details. when nt1-auto or nt-rr-auto mode is se- lected, bits ps1 and ps2 in m4 channel are con- trolled directly by biasing input pins es1 and es2 respectively. e.g. ps1 is sent continuously to the line equal 0 when es1 input is forced at 0 volt. spare m5 and m6 bits the spare bit positions in the m5 and m6 field form a channel in which are transmitted data bits loaded from the txm56 transmit register. on the receive side, the spare bits in the m5 and m6 field are first validated and then stored in the rxm56 receive register. see opr, txm56 and rxm56 registers description for details. crc calculation/checking in transmit direction, an on-chip crc calculation circuit automatically generates a checksum of the 2b+d+m4 bits using the specified 12th order polynomial. once per superframe, the crc is transmitted in the m5 and m6 bit positions. in re- ceive direction, a checksum is again calculated on the same bits as they are received and, at the end of the superframe compared with the re- ceived crc. the result of this comparison gener- ates a ofar end block erroro bit (febe) which is transmitted back towards the other end of the line in the next but one superframe and an indi- cation of near end block error is sent to the sys- tem by means of register rxm56. if there is no er- ror in superframe, febe is set = 1, and if there is one or more errors, febe is set = 0. uid also includes two 8 bits block error counters associated with the febe bits transmitted and re- ceived. it is then possible to select one error counter per direction or to select only one counter for both by means of bit c2e in opr register. block error counting is always enabled but it is possible to disabled the threshold interrupt and/or to en- able/disable the interrupt issued at each received or transmitted block error detection. see opr register for details. loopbacks six transparent or non transparent channel loop- backs are provided by uid. it is therefore possible to operate any loopback on b1, b2 and d channels line to line or dsi/gci to dsi/gci. command are groupedin cr3 register. in addition to the channel loopbacks in lt modes, a complete transparent loopback operated at the transmission side of uid allows the device to acti- vate through an appropriate sequence with the complete data stream looped-back to the re- ceiver. therefore, most of analog/digital clock and data recovery circuits are tested. after activation completed, an ai status indication is reported. complete loopback is enabled with arl command in txact register. STLC5412 27/74
table 3: network-to-nt 2b1q superframe technique and overhead bit assignments. framing 2b+d overhead bits (m 1 - m 6 ) quat positions 1-9 10-117 118s 118m 119s 119m 120s 120m bit positions 1-18 19-234 235 236 237 238 239 240 super basic frame frame # # sync word 2b+d m 1 m 2 m 3 m 4 m 5 m 6 a 1 isw 2b+d eoc a1 eoc a2 eoc a3 act 1 1 2 sw 2b+d eoc dm eoc i1 eoc i2 dea 1 febe 3 sw 2b+d eoc i3 eoc i4 eoc i5 1crc 1 crc 2 4 sw 2b+d eoc i6 eoc i7 eoc i8 1crc 3 crc 4 5 sw 2b+d eoc a1 eoc a2 eoc a3 1crc 5 crc 6 6 sw 2b+d eoc dm eoc i1 eoc i2 1crc 7 crc 8 7 sw 2b+d eoc i3 eoc i4 eoc i5 uoa crc 9 crc 10 8 sw 2b+d eoc i6 eoc i7 eoc i8 aib crc 11 crc 12 b,c,... nt-to-network superframe delay offset from network-to-nt superframe by 60 2 quats (about 0.75 ms). all bits than the sync word are scrambled. symbols & abbreviations: o1o reserve = reserved bit for future standard; set = 1 act activation bit eoc embedded operations channel a = address bit dm = data/message indicator i = information (data/message) crc cyclic redundancy check: covers 2b+d & m4 1 = most significant bit 2 = next most significant bit etc sw synchronization word febe far end block error bit (set = 0 for errored superframe) isw inverted synchronization word dea deactivation bit (set = 0 to announce deactivation) s sign bit (first) in quat uoa u only activation bit (set = 1 to activate s/t) m magnitude bit (second) in quat aib alarm indication bit (set = 0 to indicate interruption) table 2: 2b1q encoding of 2b+ d fields. data time b i b g d bit pair b 11 b 12 b 13 b 14 b 15 b 16 b 17 b 18 b 21 b 22 b 23 b 24 b 25 b 26 b 27 b 28 d 1 d 2 quat # (relative) q 1 q 2 q 3 q 4 q5 q 6 q 7 q 8 q 9 # bits 8 8 2 # quats 4 4 1 where: b 11 = first bit of b 1 octet as received at the s/t interface b 18 = last bit of b i octet as received at the s/t interface b 21 = first bit of b 2 octet as received at the s/t interface b 28 = last bit of b 2 octet as received at the s/t interface d 1 d 2 = consecutive d-channel bits (d 1 is first bit of pair as received at the s/t interface) q i = ith quat relative to start of given 18-bit 2b+d data field. note : there are 12 2b+d 18-bit fields per 1.5 msec basic frame. STLC5412 28/74
table 4: nt-to-network 2b1q superframe technique and overhead bit assignments. framing 2b+d overhead bits (m 1- m 6 ) quat positions 1-9 10-117 118s 118m 119s 119m 120s 120m bit positions 1-18 19-234 235 236 237 238 239 240 super basic frame frame # # sync word 2b+d m 1 m 2 m 3 m 4 m 5 m 6 1 1 isw 2b+d eoc a1 eoc a2 eoc a3 act 1 1 2 sw 2b+d eoc dm eoc i1 eoc i2 ps 1 1 febe 3 sw 2b+d eoc i3 eoc i4 eoc i5 ps 2 crc 1 crc 2 4 sw 2b+d eoc i6 eoc i7 eoc i8 ntm crc 3 crc 4 5 sw 2b+d eoc a1 eoc a2 eoc a3 cso crc 5 crc 6 6 sw 2b+d eoc dm eoc i1 eoc i2 1 crc 7 crc 8 7 sw 2b+d eoc i3 eoc i4 eoc i5 sai crc 9 crc 10 8 sw 2b+d eoc i6 eoc i7 eoc i8 1 crc 11 crc 12 2,3,... nt-to-network superframe delay offset from network-to-nt superframe by 60 2 quats (about 0.75 ms). all bits than the sync word are scrambled. symbols & abbreviations: o1o reserve = reserved bit for future standard; set = 1 ps 1 , ps 2 power status bits (set = 0 to indicate power problems) eoc embedded operations channel a = address bit dm = data/message indicator i = information (data/message) ntm nt in test mode bit (set = 0 to indicate test mode sw synchronization word cso cold-start-only bit (set = 1 to indicate cold-start-only isw inverted synchronization word crc cyclic redundancy check: covers 2b+d & m4 1 = most significant bit 2 = next most significant bit etc s sign bit (first) in quat febe far end block error bit (set = 0 for errored superframe) m magnitude bit (second) in quat sai s/t interface activation indication bit. act activation bit figure 6 : example of 2b1q quaternary symbols. STLC5412 29/74
figure 7: superframe i/o pin sfs STLC5412 30/74
figure 8: normalized output pulse form STLC5412 31/74
figure 9 : eoc message processing mode. STLC5412 32/74
figure 10: crc errors processing (auto-mode) STLC5412 33/74
identification code (gci) the identification register is implemented at the two addresses 80 h and 90 h. all accesses at ad- dresses 8x h will generate a read back interrupt containing the addresses 80 h. accesses at 9x h performs exactly the same thing that the 8x regis- ter except the interrupt will be at address 90 h. response will be according to the rule herebelow: identification request: 1 0 0 y x x x x x x x x x x x x identificationresponse: 100ycccc ttdddddd with: - c = circuit revision -t=devicetype(u=00) - d = device level identifying the manufacturer (001000 for sgs-thomson microelectronics) -y = don't care in particular for 1.0 version the identification re- sponse is: 100y0000 00001000 for 1.1 version the identification response is: 100y0101 00001000 general purpose i/os (gci) when gci non-auto mode is selected, (nt or lt), four programmable i/os (io1, io2, io3, io4) are provided and associated with cr5 register. each i/o is internaliy pulled-up with a 250k w resistor. input or output can be selected for each pin inde- pendently from the others by means of bits io1, io2, io3, io4 in cr5. d1, d2, d3, d4 bits give the logical value of the i/o pins respectively. when a status change occurs on one of the input pins, cr5 is sent on the monitor channel of the gci interface. when gci auto-mode is selected, two inputs (es1, es2) and one output (ec) are provided in nt1-auto and nt-rrauto configurations only. es1 and es2 inputs drive the logical values of ps1 and ps2 bits in the m4 channel on the line while ec ouput normally high is driven low using the eoc message ooperate 2b+d loopback. this intends to provide power supply testing command occuring simultaneously with the loopback com- mand. table 5: eoc message processing: local actions. nt1-auto: (eoc address 000 or 111) message code local action operate 2b+d loopback 0101 0000 send arl code on c/i channel to operate loopback 2 in sid-gci. forces ec output low operate b1channel loopback 0101 0001 performs transparent loopback on b1 channel identical to lb1 command in cr3 operate b2 channel loopback 0101 0010 performs transparent loopback on b2 channel identical to lb2 command in cr3 request corrupted crc 0101 0011 performs corruption of the transmit crc identical to ctc command in cr4. notify of corrupted crc 0101 0100 no action taken. send back to the network unable to comply message. return to normal 1111 1111 all outstanding eoc operations are reset. hold state 0000 0000 all outstanding eoc operations maintained in their present state unable to comply 1010 1010 sent by uid to indicate that the message is not in its menu nt-rr-auto: (eoc address 001 or 111) message code local action operate 2b+d loopback 0101 0000 send arl code on c/i channel to operate loopback 1a in uid configured in lt-rr-auto. forces ec output low. operate b1channel loopback 0101 0001 performs transparent loopback on b1 channel identical to lb1 command in cr3 operate b2 channel loopback 0101 0010 performs transparent loopback on b2 channel identical to lb2 command in cr3 request corrupted crc 0101 0011 performs corruption of the transmit crc identical to ctc command in cr4. notify of corrupted crc 0101 0100 no action taken. send back to the network unable to comply message. return to normal 1111 1111 all outstanding eoc operations are reset. hold state 0000 0000 all outstanding eoc operations maintained in their present state unable to comply 1010 1010 sent by uid to indicate that the message is not in its menu STLC5412 34/74
test functions various test functions are provided for transmitted pulse waveform checking, power spectral density measurement and transmitter linearity. three commands in txact register are provided. the associated test function is enabled as long as the command is not disabled by any other com- mand. sp1: (0010) send single pulses+1, -1: +1, -1, pulses are transmitted consecutively onto the line, one pulse per frame. sp3: (1011) send single pulses+3, -3: +3, -3, pulses are transmitted consecutively onto the line, one pulse per frame. rdt: (0011) random data transmitted: random data can be transmitted onto the line continuously. b1, b2 and d channel transparency between the digital interface and the line is en- abled. when auto-mode is selected, two test inputs (test1, test2) are provided allowing the same test functions as described above but without the need of a microcontroller. see table 6 for test pins biasing. table 6: test pins test1 test2 functions 1 1 normal operation 1 0 send single pulse 1 0 1 random data transmitted 0 0 send single pulse 3 turning on and off the device STLC5412 contains an automatic sequencer for the complete control of the start-up activation se- quences. interactions with an external control unit requires only activate request and deactivate request commands, with the option of inserting break-points in the sequence for additional exter- nal control allowing for instance easy building of a repetor application. automatic control of act, uoa/sai and dea bits in the m4 bit positions is pro- vided, along with the specified 40 ms, 480 ms and 15 s timers used during the sequencing. except the power up and power down control that is slightly different, the activation/deactiva- tion procedures are identical in gci and mi- crowire/dsi modes. same command codes or in- dication codes are used. in microwire and gci mode, activation control is done by writing in the activation control register txact and by read- ing the activation indication register rxact. for txact and rxact access, microwire port is used in microwire mode and c/i channel (or monitor channel depending of cid bit in cr2 register) is used in gci mode. in microwire mode, a primitive indication gen- erates first an interrupt requesting an action from the microprocessor, in gci mode the primitive in- dication is directly transmitted via c/i (or moni- tor channel). power on initialization following the initial application of power, STLC5412 enters the power down deactivated state in microwire mode or in gci mode de- pending on the polarization of the mw input. all the internal circuits including the master oscil- lator are inactive and in a low power state except for the 10 khz tone signal detector. the line out- puts lo+/lo- are low impedance and all digital outputs are high impedance. all programmable registers and the activation controller are reset to their default value. gci configuration is defined by means of the con- figuration pins m0, conf1 and conf2 when power supply is turned on. for lt and nt1-2 equipments, gci configuration should be completed by means of control regis- ter programming. see table 1 for configuration pins bias. line signal detection when uid is in the power down state and a 10khz tone tn or tl is detected from the line lsd and int (microwire/dsi only) open drain outputs are forced to zero. in nt configuration , code lsd (0000) is loaded in the activation indication register rxact. in lt configuration, code ap (1000) is loaded in the activation indication register rxact. in microwire/dsi these indications are sent onto co at the following access even if the uid is still in power down mode. in gci these indications are sent onto the c/i channel as soon as gci clocks are available. lsd open drain output is set back in the high im- pedance state as soon as the uid is powered up. int open drain output is set back in the high im- pedance state when cs input is detected at zero. depending of the actaut and pupaut bits in cr6 register, uid can powered up itself, also automatically to start the activation. for all auto mode configurations, on 10khz tone reception, power up and activation procedure are full automatic, but in nt1 auto, uid waits the uoa bit from the line before to provide (or not) the cloks and primitives to the s device. power up control microwire/dsi: control instruction pup in act STLC5412 35/74
register is required to power up the uid. gci: when gci ont master of the clocksoconfigura- tion is selected, uid provides the gci clocks needed for control channel transfer; pup control in- struction is provided to the uid by pulling low the bx data input; STLC5412 then reacts sending gci clocks. it is possible to operate an automatic power up of the uid when a wake up tone is detected from the line by connecting the lsd output directly to the bx input. gci: when nt1-2 or lt configuration is selected (m0 = 0), the uid is powered up after configura- tion setting by the pup code (0000) on c/i chan- nel. power down control a control instruction pdn in act register is re- quired to power down the device after a period of activity. pdn forces directly the device to the low power state without sequencing through any of the de-activation states. it should therefore only be used after the uid has been put in the line de- activated state. pdn has no influence on the con- tent of the internal registers, but immediately stops the output clocks when uid is in master mode and in m w/dsi mode. in gci mode, uid send first two times code di(1111) on c/i channel before powering down at the end of the assigned gci channel. the di code purpose is similar to pdn code but power down state is entered only when the line is entirely deactivated (state h1 or j1). the di com- mand is recommended. power up state power up transition enables all analog and digital circuitry, starts the crystal oscillator and internal clocks. the lsd output is in the high impedance state even if a tone is detected from the line. as for pdn, pup has no influence on the content of the internal registers power down state following a period of activity in the power up state, the power down state may be re-entered as described above. configuration registers remain in their current state. pdn and di have no influence on the content of the internal registers: it is then possible, for instance, after a normal deactivation procedure followed by a power down command, to power up again the device in order to operate di- rectly a warm start procedure. activation/deactivation sequencing activation/deactivation signals onto the line are in accordance with the activation/deactivation state matrix given in appendix a. case of restricted activation the standard specifies a mode where the u inter- face can be turned on without the need to activate the s/t interface provided this function is supported at both ends of the loop. in this condition mainte- nance channel is available, typically for setting loop-backs in the nt for error rate testing and other diagnostics. when this mode is enabled, bit m47 on the line in lt to nt direction becomes the uoa bit. setting uar activation command in the lt chip will set uoa bit equal zero on the line. detection of uoa bit equal zero by the nt will inhibit activation of the s/t interface. this results in sn3 signal in the nt to lt direction, which causes generation of uai indication by the lt u device when superframe synchronized. if during restricted activation operation, a te starts to try activate the s/t interface by sending info 1, the nt can pass this request to the lt via m47 bit, the sai bit. this bit is set equal one by writing ar command to the activation control register. sai bit received equal one causes gen- eration of an ap indication by the lt u device. reset of activation/deactivation state machine when the device is either powered-up or down, a control instruction res resets the activation con- troller ready for a cold start. that feature can be used if the far-end equipment fails to warm start, for example if the line card or nt has been re- placed or if in a regenerator, the loss of synchro- nisation of the second section imply the reset of the first section for a further cold start. the con- figuration registers remain in their selected value. hardware reset when gci configuration is selected, pin res acts as a logical hardware reset. the device is en- tirely reset including activation/deactivation state machine and configuration registers. configura- tion pins bias excluding mw define the eventual new configuration. pin mw must be maintained at the 0 volt for gci configuration setting. it is possible to operate a similar ocomplete reseto of uid by setting high bit rst in the rxoh com- mand register. in this last case the control inter- face remains enabled. refer to user guide for software reset procedure. quiet mode it is possible to force the device in a quiet mode in which uid does not react to any line wake-up tone and lsd pin remains high. there are two STLC5412 36/74
ways to enter quiet mode: qm bit in cr6 register and qm primitive command to write in txact register; in this last case, any further primitive will clear quiet mode. automode for all auto mode configurations, ais pin allows a choice of line interface: 27 or 15mh for the trans- former and resistors line or device side. in nt1, the activation/deactivation state machine and the automatic power-up / power-down capa- bilities of the uid provide for a direct connection through gci between uid and sid-gci (st 5421) without the need of an extra microcontroller (see figure 13b). lsd- pin of sid-gci must be con- nected together to the bx input pin of uid to ensure autonomous power-up/down control. activation/de- activation commands and indications are trans- ferred from one device to the other by means of the c/i channel. maintenance functions are automat- ically processed in uid. therefore, there is no transfer of messages on the monitor channel be- tween uid and sid-gci. please note that the 2b+d loop-back request at the s interface is pro- vided using the c/i channel code arl and that there is not automatic processing of s and q mes- sages in sid-gci. in repetor, the same advantages are provided by a direct connection through gci between both uid without the need of an extra microcontroller (see figure 13c). as for nt1, c/i channel transfers activation/deactivation commands and indica- tions. maintenance functions are automatically processed in uids, needing the transfer of eoc messages, overhead bits and crc fault detec- tions. this is performed autonomously on the monitor channel by sending when required mes- sages in a regular format as already described. eoc messages are transmitted according to table 5; overhead bits in the m4 channel excluding act, dea, uoa and sai, are transferred transparently; spare overhead bits in m5 or m6 bit positions are also transferred transparently; febe and nebe bits are transmitted according to figure10. command indication (c/i) codes activation, deactivation and some special test functions can be initiated by the system by writ- ing in txact register. any status change of the on-chip state machine is indicated to the system by the uid by setting a new code in the rxact register. when gci is selected, txact and rxact registers are normally associated with the c/i channel (it is possible to associate them with the monitor channel thank to the cid bit in cr2 register). all commands and indications are coded on four bits: c1, c2, c3, c4. codes are listed in table 7. for each mode, a list of recog- nized commands and generated indications is given. hereafter, you have a detailed description of the codes depending on mode selected. nt mode: command 0000 (pup): power up when in the power down state, pup command powers up the device ready for a cold or a warm start. when gci is selected with clocks as out- puts, pup command is replaced by pulling low bx input pin. 0001 (res): reset res command resets uid ready for a cold start. configuration registers are not changed. res can be operated when the device is either powered up or down. if res command is applied when the line is not fully deactivated, uid properly ends the activation before to come back in h1 state; in this case dp or eiu indication is returned (auto mode configu- ration or not respectively). 0010 (sp1): send single pulse +1 and -1 sp1 test command forces uid to send +1, -1, pulses to the line, one pulse per frame. 0011 (rdt): random data transmitted rdt test command forces uid to send data with random equiprobable levels at 80 kbaud. 0100 (eis): error indicate s interface eis command reports on the u line, a default on the s interface. 0101 (pdn): power down pdn command forces uid to power down state. it should normally be used after uid has been set in a known deactivated state, e.g. in an nt after a di status indication has been reported. in gci, c/i indication (di) is sent twice on br output before uid powers down. 0110 (uai): u interface activation indicate uai command is significant only when rr bit is set equal one in cr2 register or if nt-rr-auto auto-mode is selected. after the receiver has been super-frame synchronized, uai command allows uid to send sn3 signal to the line. 0111 (qm): quiet mode in this mode, uid does not react to any line status change. uid can be powered up or down and ready for a cold start or a warm start. all configu- ration registers and coefficients remain un- changed. quiet mode is disabled by any other command. note: inside uid, an logical or is implemented with this qm primitive and the qm bit in cr6 reg- ister. 1000 (ar): activation request beeing in the power up and deactivated state STLC5412 37/74
table 7a: rxact (indication) and txact (command) codes codes nt (gci or mw, non auto-mode) lt (gci or mw, non auto-mode) c4 c3 c2 c1 rxact (indications) txact (commands) rxact (indications) txact (commands) 0 0 0 0 0 dp/lsd pup (1) pup/dr 1 0 0 0 1 eiu res eiu res 2 0 0 1 0 sp1 sp1 3 0 0 1 1 rdt rdt 40100eieieifa0 5 0 1 0 1 pdn pdn 6 0 1 1 0 uai uar 7 0 1 1 1 qm qm 81000aparapar 91001 a1010arl b 1 0 1 1 sp3 sp3 c1100aiaiaiai d1101 e 1 1 1 0 ail f1111 di di di di note: (1) only in slave mode. in gci master mode, set bx pin to o0o to do a pup.. codes ntrr (gci or mw, non auto-mode) ltrr (gci or mw, non auto-mode) c4 c3 c2 c1 rxact (indications) txact (commands) rxact (indications) txact (commands) 0 0 0 0 0 dp/lsd pup (1) pup/dr 1 0 0 0 1 eiu res eiu res 2 0 0 1 0 sp1 sp1 3 0 0 1 1 rdt rdt 40100eieieifa0 5 0 1 0 1 pdn pdn 6 0 1 1 0 uap uai uai uar 7 0 1 1 1 qm qm 81000aparapar 91001 a1010arl b 1 0 1 1 sp3 sp3 c1100aiaiaiai d1101 e1110 f1111 di di di di (1) only in slave mode. STLC5412 38/74
table 7b: rxact (indication) and txact (command) codes. codes nt1 (gci only, auto-mode) c4 c3 c2 c1 rxact (indications) txact (commands) 0 0 0 0 0 dp/lsd (1) 1 0001 res 2 0010 sp1 3 0011 rdt 4 0100 ei ei 5 0101 pdn 6 0110 7 0111 qm 8 1000 ap ar 9 1001 a 1 0 1 0 arl b 1011 sp3 c 1100 ai ai d 1101 e 1110 ail f 1111 di di (1) must be set bx pin to `0` to force a pup. codes ntrr (gci only, auto-mode) ltrr (gci only, auto-mode) c4 c3 c2 c1 rxact (indications) txact (commands) rxact (indications) txact (commands) 0 0 0 0 0 dp/lsd (1) pup/dr 1 0 0 0 1 eiu res eiu res 20010 30011 40100eieieifa0 50101 6 0 1 1 0 uap uai uai uar 70111 81000aparapar 91001 a 1 0 1 0 arl arl b1011 c1100aiaiaiai d1101 e1110 f1111 di di di di (1) must be set bx pin to `0` to force a pup. STLC5412 39/74
(h1), ar instruction forces uid through the ap- propriate sequence to activate the line by sending tn followed by sn1. beeing in the u-only-active state (h8a), ar command forces the sai bit equal 1 to the line. it is intended to transfer to the net- work an activation attempt at the s/t interface. 1011 (sp3): send single pulse +3 and -3 sp3 test command forces uid to send +3, -3 pulses to the line, one pulse per frame. 1100 (ai): activation indicate ai command forces act bit equal one in sn3 sig- nal transmitted to the line. it reflects an activated state at the s/t interface. 1110 (ail): activation indicate loopback identical to ai command. ensure direct compati- bility with status indications of sid-gci. 1111 (di): deactivation indicate the di command allows the uid to automatically enter the power down state if the line is deacti- vated. di command has no effect as long as the line is not deactivated (di status indication re- ported). nt mode: status indication 0000 (dp/lsd): deactivation pending / line sig- nal detected when in the deactivated state (h1) either pow- ered up or down, lsd status indication is re- ported if tn wake-up tone is detected except if nt1 auto is selected; in this configuration, uid must check uoa bit before to send (or not) lsd. when in the superframe-synchronized states, dp status indication reports that the dea bit has been received equal zero from the line. uid enters in the receive reset state. when nt1-auto mode is selected, dp status indication is reported also when a transmission error has been detected on the loop. this is intended to ensure immediate deactivation of the s/t interface. 0001 (eiu): error indication user eiu status indication is reported in following cases: a. to acknowledge res command. uid is deacti- vated, ready for a cold start. b. to report a loss of signal for more than 480ms on the line. c. to report a loss of synchronization for more than 480ms on the line. d. to report that an expire of 15s timer interrupt has reset uid ready for a cold start. when nt1-auto is selected, eiu is replaced by dp. 0100 (ei): error indication ei status indication reports that act bit has been detected equal zero. 0110 (uap): u interface activation pending is significant only when rr bit in cr2 has been set equal one or if nt-rr-auto mode is se- lected. uap reports that the receiver is super- frame synchronized with uoa bit received equal zero. 1000 (ap): activation pending ap reports that the receiver is superframe syn- chronized with uoa bit received equal one . 1010 (arl): activation request loopback is significant only when nt1-auto or nt-rr- auto mode is selected. arl reports that an eoc message has been received requiring to operate a local 2b+d loopback. when connected to sid- gci in a nt1 or to uid in lt-rr-auto mode in a regenerator, 2b+d loopback command is there- fore automatically provided. 1100 (ai): activation indication ai reports that uid is superframe synchronized with act and uoa bits received equal one. 1111 (di): deactivation indication di reports that uid has entered the deactivated state (h1). lt mode: command 0000 (pup/dr): power up / deactivation re- quest when in the power down state, pup com- mand powers up the device ready for a cold or a warm start. when in one of the superframe syn- chronized states, dr command forces dea bit on the line equal zero for four consecutive superfra- mes before ceasing transmission. 0001 (res): reset res command resets uid ready for a cold start. configuration registers are not changed. res can be operated when the device is either powered up or down. if res command is applied when the line is not fully deactivated, uid returns eiu indi- cation and goes in j1 state (receive reset). if res command is applied when the line is not fully deactivated, uid properly ends the activation before to come back in j1 state; in this case eiu indication is returned. 0010 (sp1): send single pulse +1 and-1 sp1 test command forces uid to send +1, -1, pulses to the line, one pulse per frame. 0011 (rdt): random data transmitted rdt test command forces uid to send data with random equiprobable levels at 80 kbaud. 0100 (fa0): force act bit to 0 fa0 command forces the act bit to 0 in the sl3 signal transmitted to the line. it is intended to re- flect a transmission failure detected on the net- work side of the loop relative to uid. 0101 (pdn): power down pdn command forces uid to power down state. it should normally be used after uid has been set STLC5412 40/74
in a known deactivated state, e.g. in an lt after a di status indication has been reported. in gci, c/i indication di is sent twice on br output before uid powers down. 0110 (uar): u-interface-only activation request being in power up and deactivated , uar com- mand forces uid through the appropriate se- quence to activate the loop without activating the s/t interface. sl2/sl3 signal is sent with uoa bit set to zero. with the line already active, uar command forces bit uoa equal zero: this is in- tended to deactivate the s/t interface. 0111 (qm): quiet mode this command has the same effect as in nt mode. 1000 (ar): activation request being power up and deactivated, ar instruction forces uid through the appropriate sequence to activate the line by sending tl followed by sl1. sl2/sl3 signal is sent with uoa bit equal one. beeing in the u-only-active states, ar command forces the uoa bit equal 1 to the line. ar is in- tended to activate the s/t interface. 1010 (arl): activation request with loopback arl test command forces uid through the appro- priate sequence to activate with the complete transmit data stream looped-back to the receiver. when this loop-back is disabled by dr command, uid is ready to operate a warm start if a new arl command is issued. 1011 (sp3): send single pulse +3, -3 sp3 test command forces uid to send +3, -3 pulses to the line, one pulse per frame. 1100 (ai): activation indicate ai is an optional command recognized only when bp2 bit in cr2 register is set equal one or lt- rr-auto mode is selected. being in the super- frame-synchronized state with act bit received from the line equal one, ai command allows uid to send act bit equal one to the line. 1111 (di): deactivation indicate the di command allows the uid to automatically enter the power down state if the line is deacti- vated. di command has no effect as long as the line is not deactivated (di status indication re- ported). lt mode: status indication 0001 (eiu): error indication interface u it can be a oloss of signalo, a oloss of sync.o or an expiry of 15s timer. eiu is also the answer to the res comand. after sending eiu, the uid is always ready for a cold start. 0100 (ei): error indication ei status indication reports that act bit has been detected equal zero. 0110 (uai): u interface activation indication uai reports that the line is superframe synchro- nized. 1000 (ap): activation pending being in one of the deactivated states, ap reports that a wake up tone has been detected from the line. beeing in the u-only-activated state, ap re- ports that sai bit has been detected equal one from the line. it is intended to reflect an activation attempt at the s/t interface. 1100 (ai): activation indication ai reports that uid is superframe synchronized with act bit received equal one. te side of the loop relative to the uid is active 1111 (di): deactivation indication di reports that uid has entered the deactivated state (j1). b1, b2 and d channels transparency uid is able to control automatically transparency of b1, b2 and d channels. nevertheless, when etc bit in cr2 register is set equal 1, transparency is forced as soon as the line is synchronized. it is also possible to control each data channel b1, b2, d enabling at the dsi/gci interface inde- pendently by means of bits eb1, eb2 and ed in cr4 register. set to 1, b1, b2 or d channel on the dsi/gci interface are enabled. in this case, out of the transparency state (s), ones are forced on the relevant time slot of the dsi/gci, and ones or zeros are transmitted on the line conforming recommen- dations. set equal 0, relevant time slot on dsi/gci is always in high impedance state and ones or ze- ros are transmitted on the line. in this last case, as soon as transparency is enabled, ones are trans- mitted to the line. when rdt test command is applied, transpar- ency on 2b+d is forced. this intend to permit the user, if required, to send a random sequence of bits to the line. please note that the on-chip scrambler normally ensures transmission of equiprobable levels to the line, even if logical one only is provided to the dsi/gci system interface. internal registers description. here following a detailed description of STLC5412 internal registers. internal registers can be accessed: a) in gci mode, according to the monitor channel exchange rules. for rxact and txact also through c/i channel. b) in m w/dsi mode, using the microwire inter- face according to the rules described in section o m w control interfaceo. tables 8 and 10 gives the list of all STLC5412 in- ternal registers. registers are grouped by types and address ar- eas: STLC5412 41/74
area 00/0fh: nop operations. area 10/1fh: test registers: reserved. area 20/2fh: the configuration registers. opr cr1 cr2 cr3 cr4 cr5 cr6 cr7 read write access. cr5 only usefull in gci mode area 30/3fh: the b1 b2 d time slot registers. txb1 txb2 rxb1 rxb2 txd rxd status read write access except status: read only. usefull only in m w mode except status: m w & gci modes. area 40/4fh: the transmit and receive registers (except eoc). txm4 rxm4 txm56 rxm56 txact rxact bec1 bec2 ect1 ect2 rxoh read write access for the transmit registers: txm4 txm56 txact read access only for the receive registers: rxm4 rxm56 rxact read write access for the control registers: ect1 ect2 read access only for the error registers: bec1 bec2 write access only for the command registers: rxoh area 5x to bx: 5x: 6x: 7x: 8x & 9x: ax: bx: area c0/c3h: areac4htoex: area fx: for 12 bits registers. to write txeoc register, to read rxeoc register. to read txeoc register. reserved to read idr register. to write decteoc register to read decteoc register to read round trip delay registers reserved reserved except ff address: special register mwps. overhead bits programmable register (opr) after reset: 1eh cie eie fie ob1 ob0 oc1 oc0 c2e cie near-end crc interrupt enable: cie = 1: the rxm56 register is queued in the interrupt register stack with nebe bit set to zero each time the crc result is not identical to the corresponding crc received from the line. cie = 0: no interrupt is issued but the error detection remains active for instance for on chip error counting. eie error counting interrupt enable: eie = 1: an interrupt is provided for the counter when the threshold (ect1 or ect2) is reached. eie= 0: no interrupt is issued. it is feasible to read the counters even if no relevant interrupt has been provided. fie febe lnterrupt enable: fie = 1: the rxm56 register is queued into the interrupt register stack each time the febe bit is received at zero in a superframe. fie = 0: no interrupt is issued but the receive febe bit remains active for on chip error counting. ob1, ob0 overhead bit processing: select how each spare overhead bit received from the line is validated and transmitted to the sys- tem. rxm4 and rxm56 registers are inde- pendently provided onto the system interface as for the eoc channel. each spare overhead bit is validated independentlyfrom the others. ob1 ob0 0 0 each super frame, an interrupt is generated for the rxm4 or the rxm56 register. spare bits are transparently transmited to the system. 0 1 an interrupt is set at each new spare overhead bit(s) received. 1 0 an interrupt is set at each new spare overhead bit(s) received and confirmed once. ( two times identical). 1 1 an interrupt is set at each new spare overhead bit(s) received and confirmed twice. (three times identical). if new bits are received at the same time in m4 STLC5412 42/74
and m56, both registers rxm4 and rxm56 are queued in the interrupt register stack. bits act, dea, uoa, sai are dedicated to the activa- tion procedure. validation is always done in ac- cordance with the ansi rule: validation at each new activation bit received and confirmed twice independently from the above rules. these bits are taken into account directly by the activation decoder. an interrupt is not generated for the rxm4 register when one of these bits changes, but they are provided for test to the rxm4 regis- ter. oc1, oc0 eoc channel processing: select how a received eoc message is validated and transmitted to the system. oc1 oc0 0 0 every half a super frame, an interrupt is generated for the rxeoc register. eoc channel is transparently transmitted to the system. 0 1 an interrupt is set at each new eoc message received. 1 0 an interrupt is set at each new eoc message received and confirmed once. (two times identical) 1 1 an interrupt is set at each new eoc message received and confirmed twice. (three times identical). c2e counter 2 enable: c2e = 0: only counter bec1 is used for both febe and nebe counting. c2e = 1: counter bec1 is used for nebe. counter bec2 is used for febe. configuration register 1 (cr1) after reset: m w mode 00h gci: mo = 0 (lt/nt12) = c0h gci: mo = 1 (nt/te) = d2h ff1 ff0 ck2 ck1 ck0 ddm cms bex ff1, ff0 frame format selection: ( m w/dsi only) refer to fig. 2 and 3. ff1 ff2 0 0 format 1 0 1 format 2 1 0 format 3 1 1 format 4 gci like ck0-ck2 digital interface clock select: ( m w/dsi only) ck0-ck2 bits select the bclk output frequency when dsi clocks are outputs. ck2 ck1 ck0 bclk frequency: 0 0 0 256khz 0 0 1 512khz 0 1 0 1536khz 0 1 1 2048khz 1 0 0 2560khz ddm delayed data mode select:( m w/dsi only) two different phase-relations may be established between the frame sync signals and the first bit of the frame on the digital interface: ddm = 0: non delayed data mode the first bit of the frame begins nominally coincident with the rising edge of fsa/b. ddm = 1: delayed data mode: fsa/b input must be set high at least a half cycle of bclk earlier the frame beginning. cms clocks master select:( m w/dsi only) cms = 0: bclk, fsa and fsb are inputs; bclk can have in format 1, 2 and 3 value between 256khz to 4096khz, value in format 4: 512khz to 6176khz. cms = 1: bclk, fsa and fsb are outputs. fsa is a 8 khz clock pulse indicating the frame beginning. fsb is a 8 khz clock pulse indicating the second 8 bits wide time-slot. bclk is a bit clock signal whose frequency is fixed bits ck2-ck0. bex b channels exchange: bex = 0: b1 and b2 tx/rx channels are associated with txb1/rxb1 and txb2/rxb2 registers respectively. bex = 1: b1 and b2 channels are exchanged. configuration register 2 (cr2) after reset: m w mode 00h gci: mo = 0 (lt/nt12) = 00h gci: mo = 1 (nt/te) = 80h m w (lt,nt): sfs nts dmo den etc bp1 eif bp2 bfh9d rr gci (lt,nt): sfs nts t24d cid etc bp1 eif bp2 bfh9d rr sfs super frame synchronization select: significant in lt mode only. STLC5412 43/74
sfs = 0: sfsx is an input that synchronizes the transmit superframe. sfs = 1: sfsx is an output indicating the transmit superframe. in nt mode sfsx is always an output. nts lt / nt mode select. nts = 0: lt mode selected nts = 1: nt mode selected dmo d channel transfer mode select.( m w/dsi only) significant only when den=1. dmo = 1: d channel data is shifted in and out on dx and dr pins in continuous mode at 16 kbit/s on the falling and rising edges of dclk respectively. dmo = 0: d channel data is shifted in and out on dx and dr pins in a tdm mode at the bclk frequency on the falling and rising edges of bclk respectively when the assigned time-slots are active. t24d: 24ms timer disable (gci only). t24d = 1: the timer watches at the exchange on monitor channel every time the uid sends new byte. if it expires before pre-acknoledgement, an abort message is generated; in this last case, the aborted message is lost. t24d = 0: the timer is desable. this means for instance that uid may wait an pre- acknoledgement for ever. den d channel port enable. ( m w/dsi only) den = 0: d channel port disabled. d bits are transferred on br and bx; multiplexed mode is selected automatically. den = 1: d channel port (dx, dr, and dclk when dmo bit equal 1) is selected. d bits are transferred on dr and dx in a mode depending on dmo bit setting. cid : c/i channel disable (gci only). cid = 0: txact and rxact registers only accessible via the c/i channel. others registers only accessible via monitor channel. cid = 1: all registers only accessible via the monitor channel. etc 2b+d data extended transparency channel. etc = 1: 2b+d channel transparency is enabled as soon as the line is superframe synchronized. etc = 0: 2b+d channel transparency is under control of the on-chip state machine: act bit equal one both directions. bp1 break point 1 during activation(significative only when nts = 0: lt mode) . bp1 = 1: during an activation attempt from the loop, (before sl2 sending) uid waits for an ar command to pursue activation. it is recommended to set bp1 equal 1 for repetor application. bp1 = 0: the activation procedure is automatically processed without the need of an ar command. eif error indication filter. significant in nt mode only eif = 0: act bit is set to zero in the transmit superframe in case of ei command, even if ei is sent sporadically. eif = 1: act bit may be not set to zero in the transmit superframe in case of ei command with a duration of less than 36ms. bp2 break point 2 during activation. significant only when nts=0 (lt selected) bp2 = 1: during a full activation procedure, uid receiving act bit set to one in the received sn3 signal, uid waits for an ai command to send act bit equal one in sl3 signal. it is recommended to set bp2 equal 1 for repetor application. bp2 = 0: the activation procedure described above is automatically processed without the need of an ai command. bfh9d : back from h9 disabled. (significant in nt mode only) bfh9d = 0: uid is in h9 state (pending deactivation) after reception of dea bit = 0. it is waiting a loss of signal to return in h1 state via h12. bfh9d = 1: uid is h9 state (pending deactivation) after reception of dea bit = 0. it is waiting a loss of signal to return in h1 state via h12, or dea bit = 1; in this last case uid returns in the previous state. rr repetor mode. rr = 0: uid activation/deactivation complies with the standard requirements for nt1 or lt equipment depending on nts bit select. see state matrix for the detailed behaviour of uid. STLC5412 44/74
rr = 1: uid activation/deactivation complies with the requirements for repetor equipment. olto or onto behaviour is selected by means of bit nts. bp1 and bp2 break-points should be set equal one too. see state matrix for the detailed behaviour of uid in this mode of operation. configuration register 3 (cr3) after reset: 00h lb1 lb2 lbd db1 db2 dbd tlb t15d lb1, lb2, lbd line side loopback select. when set high they turn each individual b1, b2, or d channel from the line receive input to the line transmit output. they may be set separately or together. the loopback is operated close to bx and br (or dx and dr if the d port is selected). these loop backs ensures channels integrity. db1, db2, dbd digital side channel loopback select. when set high they turn each individual b1, b2, or d channel from the digital interface receive in- put to the digital interface transmit output. they may be set separately or together. the loopback is operated close to bx and br (or dx and dr if d port selected). these loop backs ensures chan- nels integrity whatever the selected format or as- signed channels time slot. tlb transparent loopback select tlb = 0: digital loopbacks are non transparent. when line side loopback is set, data transmitted onto the digital interface is forced to one. when digital side loopback is set, data transmitted onto the line is forced to 1 in nt mode and to 0 in lt mode. tlb = 1: 2b+d is transparently transferred through the uid. t15d timer 15 second disabled t15d = 0: on-chip 15 second timer (timer 4 or 5 of ansi standard) is enabled and ensure full reset of the activation procedure in case of non synchronization of the line within 15 second. t15d = 1: on-chip 15 second timer is disabled. this means for instance that uid may attempt to synchronize for ever. configuration register 4 (cr4) after reset: e0h eb1 eb2 ed ffit esfr ctlio mob ctc eb1 b1 channel enabling eb1 = 1: selected b1 channel time-slot on the dsi/gci interface is enabled. note that transparency of b1 channel remains under control of the activation state machine and the etc bit in cr2. eb1 = 0: selected b1 channel time-slot on the dsi/gci interface is disabled: br output remains in high impedance state and data on bx input is ignored. ones (nt) or zeroes (lt) are transmitted on the line. eb2 b2 channel enabling identical to eb1 bit but for b2 channel. ed d channel enabling identical to eb1 but for d channel on bx/br pin or dx/dr pin depending on den bit in cr2 register. ffit fifos interrupt. ffit = 1: overflow or underflow of the txfifo and rxfifo are reported in status register. an interrupt is generated in m w mode, a monitor message is automatically sent in gci mode. ffit = 0: no interrupt or message is generated when fifos overflow or underflow. esfr enable sfsr on pin 25 (40) esfr = 0: lsd output is selected on pin 25 (40). esfr = 1: sfsr output is selected on pin 25 (40). ctlio control io (significant in gci mode only) ctlio = 1: the input pins configurated via cr5 register generate a message on every change even if the uid is powered down in master mode; that is to say uid is able to wake up itself, to provide the clocks, to sends the message. after that uid is automatically powered down except if a pup command is sent to it. ctlio = 0: in master mode and powered down, the uid does not react to an input pin change. mob mask overhead bits. mob = 0: no mask on overhead bit interrupts. STLC5412 45/74
mob = 1: all interrupts issued from rxm4, rxm56 rxeoc and cr5 are masked. it is still possible to read these registers via rxoh. ctc corrupted transmit crc control ctc = 0: allows the normal calculation of the crc for the transmitted data to the line. ctc = 1: the crc result transmitted to the line in the next superframe is inverted. this ensure transmission of corrupted crc as long as ctc equal 1. configuration register 5 (cr5) significant in gci only. after reset: ffh io4 io3 io2 io1 d4 d3 d2 d1 io4, io3, io2, io1 input/outputselect for i/o pins (14, 15, 16, 18) ioi = 1: ioi pin is selected as an input. an on- chip pull up resistor ensures a stable logical 1 at power-on reset or if ioi pin is not connected to stable source. ioi = 0: ioi pin is selected as an output. each i/o pin can be selected independently from the others. d4, d3, d2, d1 i/o pin logical level com- mand/status. d4, d3, d2, d1 bits are associated with io4, io3, io2, io1 pins respectively. when ioi pin is selected as an output, the associated di bit can be written to control the logical level of the output; di equals 1 commands a high level on ioi. when ioi pin is se- lected as an input, the associated di bit indicates the status of the input; di equals one indicates a high level on ioi. cr5 register is buffered in the in- terrupt stack each time a status change is detected on an input. it is also possible to read-back at any time cr5. configuration register 6 (cr6) after reset: 0fh t15e acta ut pupaut qm ais tfb0 rfs lfs t15e timer 15 seconds extension t15e = 0: the on chip t4 or t6 timer is done for the ansi standard: 15 seconds. t15e = 1: the on chip t4 or t5 timer is extended to 20 seconds. note: the t15d bit in cr3 register enables or dis- ables the t4/t5 timer independently of thet15e bit. actaut: activation automatic actaut = 1: if uid is powered up, a 10khz tone from the line starts the activation without need of extra commands (like ar), except when qm (quiet mode) is enterred. actaut = 0 a detection of a 10khz tone from the line does not start the activation: uid waits a primitive command (normaly ar). pupaut pup automatic pupaut = 1: a 10khz tone from the line allows an automatic power up of the uid. notes if actaut is also set to 1, from a power down state a 10khz tone automatically starts the activation. pupaut = 0: a detection of a 10khz tone from the line does not power up the device: uid waits a pup primitive command. qm quiet mode. qm = 1: has the same effect of the qm primitive command enterred in txact register. an or logic is done with the qm bit and the qm primitive. the goal of this bit is to allow a quiet mode for an uid in power down state in some applications. qm = 0: no effect. ais analog interface select. ais = 1: selects an analog interface using 27mh transformer. ais = 0: selects an analog interface using 15mh transformer tfb0 transmit febe equal 0 tfb0 = 0: a permanent febe bit = 0 is sent on the line as long as tfb0 = 0 tfb0 = 1: the febe bit sent on the line is normaly computed. rfs remote febe select. please report to the figure 10. rfs is useful in repetor application to transfert or not the anoma- lies from the second line section to the first line section and viceversa. STLC5412 46/74
rfs = 1: transfer anomalies from second section to first section and viceversa allowed. rfs = 0: transfer anomalies from second section to first section and viceversa not allowed. lfs local febe select. please report to the figure 10. lfs is useful in repetor application to transfert or not the crc anomalies (nebe) of a line section to the febe bit of the same line section. rfs = 0: the computed febe takes in to account the local nebe. rfs = 1: the computed febe does not take in to account the local nebe. configuration register 7 cr7 after reset: 02h ----- lock pl2en dect dect dect = 0: normal mode dect = 1: dect mode pl2en pl2en = 0: pll2 remains frozen pl2en = 1: pll2 tracks the phase of the receive signal. lock lock = 0: no phase relation betweensfsr and fsa lock = 1: the phase of sfsr and fsa rising edges is fixed configuration register txb1 significant only when format 3 selected. ( m w/dsi only) after reset: 00h time slot 0 selected. - - b1x5 b1x4 b1x3 b1x2 b1x1 b1x0 b1x5-b1x0 transmit b1 time slot assignment those bits define the binary number of the trans- mit b1 channel time-slot on bx input. time slot are numbered from 0 to 63. the register content is taken into account at each frame beginning. configuration register rxb1 significant only when format 3 selected. ( m w/dsi only) after reset: 00h time slot 0 selected. b1r5 b2r4 b2r3 b2r2 b2r1 b2r0 b1r5-b1r0 receive b1 time slot assignment b1r5-b1r0 bits define the binary number of the receive b1 channel time-slot on br output. time slot are numbered from 0 to 63. the register con- tent is taken into account at each frame begin- ning. configuration register txb2 significant only when format 3 selected. ( m w/dsi only) after reset: 01h time slot 1 selected. - - b2x5 b2x4 b2x3 b2x2 b2x1 b2x0 b2x5-b2x0 transmit b2 time slot assignment those bits define the binary number of the trans- mit b2 channel time-slot on bx input. time slots are numbered from 0 to 63. the register content is taken into account at each frame beginning. configuration register rxb2 significant only when format 3 selected. ( m w/dsi only) after reset: 01h time slot 1 selected. - - b2r5 b2r4 b2r3 b2r2 b2r1 b2r0 b2r5-b2r0 receive b2 time slot assignment those bits define the binary number of the receive b2 channel time-slot on br output. time slot are numbered from 0 to 63. the register content is taken into account at each frame beginning. configuration register txd significant only when format 3 is selected with the d channel selected in the multiplexed mode. after reset: m w mode 08h (sub time slot 0, time slot 2 se- lected) dx5 dx4 dx3 dx2 dx1 dx0 sx1 sx0 dx5-sx0 transmit d channel time slot assign- ment dx5-dx0 and sx1-sx0 bits define the binary number of the transmit d channel time-slot. dx5- dx0 bits define the binary number of the 8 bits wide timeslot. time slot are numbered from 0 to 63. within this selected time slot, sx1,sx0 bits define the binary number of the 2 bits wide time- slot. sub time-slots are numbered 0 to 3. the reg- ister content is taken into account at each frame beginning. configuration register rxd significant only when format 3 is selected with the d channel selected in multiplexed mode. after reset: m w mode 08h (sub time slot 0, time slot 2 se- lected) dr5 dr4 dr3 dr3 dr2 dr1 sr1 sr0 STLC5412 47/74
dr5-sr0 receive d channel time slot assign- ment dr5-dr0 and sr1-sr0 bits define the binary number of the receive d channel time-slot. dr5- dr0 bits define the binary number of the 8 bits wide timeslot. time slot are numbered from 0 to 63. within this selected time slot., sr1,sr0 bits define the binary number of the 2 bits wide time- slot. sub time-slots are numbered 0 to 3. the reg- ister content is taken into account at each frame beginning. status register (status) (read only) after reset: 85h pwdn x x x rxffu rxffo txffu txffo pwdn power down pwdn = 1: uid is in power down state pwdn = 0: uid is in power up state rxffu rx fifo underflow rxffu = 1:the bits rate on br pin is higher than the bits rate side line. rxffu = 0:the bits rate on br is in accordance with the bits rate side line rxffo: rx fifo overflow rxffo = 1:the bits rate on br pin is lower than the bits rate side line. rxffo = 0:the bits rate on br pin is in accordance with the bits rate side line. txffu tx fifo underflow txffu = 1: the bits rate on bx pin is lower than the bits rate side line. txffu = 0: the bits rate on bx pin is in accordance with the bits rate side line. txffo tx fifo overflow txffo = 1: the bits rate on bx pin is higher than the bits rate side line. txffo = 0: the bits rate on bx pin is in accordance with the bits rate side line. when one of these four bits is set to 1, tx fifo and/or rx fifo is re-adjusted and data is lost. an interrupt or message is generated if ffit bit in cr4 register is set to 1. it is always possible to read this register by writting status bit = 1 in rxoh register. transmit m4 channel register (txm4) after reset: 7dh -m42 x m43 x m44 x m45 x m46 x - m48 x when transmitting sl2/sl3 or sn3, the uid shall continuously send in the m4 channel field the reg- ister content to the line once per superframe. register content is transmitted to the line at each superframe. m41 x , m42 x in lt, m47 x are activation bits. these bits are controlled directly by the on chip activation encoder-decoder. the corresponding bits in the txm4 register are not significant. m45 x in nt mode is cs0 bit: this is normally 0 (uid performing warm start). nevertheless, user can force cso to 1 by setting m45 x to 1. when a read back is operated on txm4, m41x, m42x in lt, m47x are indicating the current value of act, dea in lt and uoa/sai bits transmitted to the line. receive spare m4 overhead bits register (rxm4) (read only) after reset: 75h m41r m42r m43r m44r m45r m46r m47r m48r rxm4 register is constituted of 8 bits. when the line is fully activated (super frame synchronized), STLC5412 extracts the m4 channel bits. m41 is the act bit; m42 in nt mode is the dea bit; in nt m47 is the uoa bit; in lt m47 is the sai bit. these bits are under the control of the activation se- quencer. no interrupt cycle is provided for the rxm4 register when a change on one of the acti- vation bits is detected; never the less, they are available in rxm4. when one of the remaining received spare bits is validated following the criteria selected in the configuration register opr, the rxm4 register content is queued in the interrupt register stack, if no mask overhead bits is set (see mob bit in cr4 register). it is always possible to read this register by writting rxm4 bit = 1 in rxoh register. transmit m5 and m6 channels register (txm56) after reset: 1fh - - - m51 x m61 x m52 x febx febx m51 x , m61 x , m52 x spare over-head bits are nor- mally equal to 1. default value can be changed by setting the respective bits. these bits are trans- mitted to the line in sl2/sl3 or sn3 signal. febx transmit febe bit control the febe can be forced to 0 by writing 0 in one of febx if rfs bit in cr6 register is set to 1. the febe bit set to zero is sent once to the line in the following available superframe. after febe transmission, febx STLC5412 48/74
bit returns to 1; the two bits positions are identical and allow direct compatibility between uids set in auto-mode (repeter). note: the febx bits in txm56 register are not the only way to force febe = 0 to the line. first, the febx action is controlled by rfs bit in cr6 register. second, the nebe = 0 (local crc cmputing result) forces also febe = 0 to the line and this action is controlled by lfs bit in cr6 register. third, tfb0 = 0 in cr6 register forces permanen- tely febe = 0 to the line. receive m5 and m6 overhead bits register (rxm56) (read only) after reset: 1fh - - - m51r m61r m52r febr nebr when the line is fully activated (super frame syn- chronized), STLC5412 extracts the overhead bits. when one of the received spare bits m51, m61, m52 is validated following the criterias selected in the configuration register opr. the rxm56 reg- ister content is queued in the interrupt register stack, if no mask overhead bits is set (see mob bit in cr4 register). if the fie bit in opr register is set high, the rxm56 register content is queued in the interrupt register stack each time the febe bit is received equal zero with bit feb equal 0. the crc received from the far-end is compared at the end of the superframe with the crc calcu- lated by the uid during that superframe. if an er- ror is detected, the febe bit in the transmit direc- tion is forced equal zero in the next superframe. if the cie bit in the opr register is set high, the rxm56 register is queued in the interrupt register stack at each crc error detected with bit neb equal zero. it is always possible to read this regis- ter by writing rxm56 bit = 1 in rxoh register. activation control register (txact) after reset: 0fh ----c4c3c2c1 this register is constituted of four bits: (c1, c2, c3, c4). in gci mode, this register is normaly ad- dressed by means of the c/i channel, but it is possible to address it by means of the monitor channel (see cid bit in cr2 register). activation indication register (rxact) (read only) after reset: 0fh - - - - c4r c3r c2r c1r this register is constituted of four bits: (c1r, c2r, c3r, c4r). at each activation status change, rxact is queued in the interrupt register stack. in gci mode, the c1-c4 bits are directly sent on the c/i channel or monitor channel depending on the cid bit in cr2 register. activation indication instructions are coded on 4 bits according to acti- vation control description. it is always possible to read this register by writting rxact bit = 1 in rxoh register. block error counter 1 (bec1) (read only) after reset: 00h ec7 ec6 ec5 ec4 ec3 ec2 ec1 ec0 this register indicates the binary value of the block error up-counter 1. error are counted ac- cording to c2e bit setting in register opr (nebe + febe or nebe only). when counter one reachs the threshold ect1, bec1 register is queued in the interrupt stack. bec1 is reset to zero when it is read. block error counter 2 (bec2) (read only) after reset: 00h ec7 ec6 ec5 ec4 ec3 ec2 ec1 ec0 this register indicates the binary value of the block error up-counter 2. febe errors are always counted. according to c2e bit setting in register opr, when counter one reachs the threshold ect2, bec2 register is queued in the interrupt stack. bec2 is reset to zero when it is read. threshold block error counter 1 register (ect1) after reset: ffh ect17 ect16 ect15 ect14 ect13 ect12 ect11 it is possible to load in this register the binary value of a threshold for the block error counter 1.when block error counter reachs this value, an interrupt relative to bec1 register is loaded in the interrupt stack. this can be used as an early alarm in case of degraded transmission. threshold block error counter 2 register (ect2) after reset: ffh ect27 ect26 ect25 ect24 ect23 ect22 ect21 it is possible to load in this register the binary value of a threshold for the block error counter 2. STLC5412 49/74
when block error counter reachs this value, an interrupt relative to bec2 register is loaded in the interrupt stack. this can be used as an early alarm in case of degraded transmission. receive status register - read command (rxoh) (write only) eoc m4 m56 act 0 status 0 rst reset to zero of all the rxoh bits is automatic. eoc receive eoc status register read. when eoc bit is set to one, uid automatically loads the current value of rxeoc register in the interrupt stack independently of any status change. m4 receive m4 overhead bits status register read. when m4 bit is set to one, uid automatically loads the current value of rxm4 register in the in- terrupt stack independently of any status change. m56 receive m5 and m6 overhead bits status register read. when m56 bit is set to one, uid automatically loads the current value of rxm56 register in the interrupt stack independently of any status change. act activation indication status. when act bit is set to one, uid automatically loads the current value of rxact register in the interrupt stack independently of any status change. in gci mode, the rxact read back always uses the monitor channel. status when status bit is set to one, uid automat- ically loads the current value of status register in the interrupt stack independently of any status change. rst reset (microwire/dsi configuration only). when rst bit is set to one, uid is fully reset in- cluding configuration registers, state machine and all coefficients and reset to their default value. uid enters in the power-down state. transmit eoc register (txeoc) after reset: fffh xeoc1 xeoc2 xeoc3 xeoc4 xeoc5 xeoc6 xeoc7 xeoc8 txeoc register is constituted of 12 bits, 3 bits address (efg), 1 bit data/message flag (h), 8 bits information (xeoc1 - xeoc8). when trans- mitting sl2/sl3 or sn3 signal. STLC5412 shall continuously send into the eoc channel field the eoc bits twice per superframe. txeoc register is loaded in the transmit register at each half a su- perframe. the address of this register is composed only of 4 bits. read-back can be performed by means of a read-back command 6100h. dect mode eoc register (decteoc) after reset: fffh deoc1 deoc2 deoc3 deoc4 deoc5 deoc6 deoc7 deoc8 12 bits register to store the dect eoc message, 3 bits address (efg), 1 bit data/message flag (h), 8 bits information (deoc1 - deoc8) this register is significant only in dect mode. in lt dect mode the byte is transmitted 3 times in the eoc channel starting from the superframe identi- fied by the decsync pulse on the sfsx pin. once the decteoc byte has been transmitted 3 times, the content of the eoc channel returns to the previous existing value. in nt dect mode if the received eoc message field is detected 3 times identical to the decteoc register, the de- vice generates a pulse on the pin sfsx synchro- nous with the sfsr pulse. read back can be per- formed by means of command b100h. receive eoc register (rxeoc) (read only) after reset: fffh reoc1 reoc2 reoc3 reoc4 reoc5 reoc6 reoc7 reoc8 the rx eoc register is constituted of 12 bits. when the line is fully activated (super frame syn- chronized) and when a new eoc message is re- ceived and validated in accordance with the crite- ria selected in the configuration register opr, the rx eoc register is queued in the interrupt register stack. the address of this register is com- posed only of 4 bits. it is always possible to read this register by writ- ing eoc = 1 in rxoh register identification register (idr) fixed value: cccc 00001000 (read only 12 bit register) when a read-back operation of idr register is en- tered, uid loads the identification register in the interrupt stack. this register provides a reserved identification code agreed by gci standard: cccc 00001000 idr register is accessible via two addresses (see page 34). STLC5412 50/74
mwps micro wire port select register (signifi- cant in microwire mode only). (write only) default value: mode a (5410 compatible) writting ffh value select the mode b to ex- change data onto ci & co writing 00h value select the mode a (see mi- crowire control interface paragraph for more details mode a, mode b). note: soft reset has no effect on the select mode. baud delay register (dbaud) after reset: 00h dbaud7 dbaud6 dbaud5 dbaud4 dbaud3 dbaud2 dbaud1 dbaud0 8 bits read-only register that provides the round trip bauds delay (12.5usec step). it is significant in lt mode only. the register is split in two sections: dbaud4..dbaud0: 5 bits counter of bauds delay between sfsx and sfsr rising edges ( total digi- tal delay: tdd ). dbaud7..dbaud5: 3 bits to store the internal elastic memory (fifo) state. the table a shows the coding of the 3-stages elastic memory ( elas- tic digital delay: edd ). table a. fifo state baud delay (edd) 000 -1 010 -2 110 0 -2: 2 bauds have to be subtracted from bauds counter value (dbaud4..dbaud0) -1: 1 baud has to be subtracted to bauds counter value (dbaud4..dbaud0) 0: no correction all other fifo states are used during activation procedure. once pll2 is frozen you can be only in one of the 3 states in table a. tx rx clocks different register (dtxrx) after reset: 00h 76543210 8bits read-only register that provides the phase difference between transmit clock and receive re- covered clock by pll2 in steps of 65.1 nsec. ( clock elastic delay: ced ). the register is signifi- cant in lt mode only. STLC5412 51/74
table 8: register access messages function byte 1 byte 2 ad7/4 ad3/1 ad0 7 6 5 4 3 2 1 0 nop 0000 000 0 0 0 0 0 0 0 0 0 reserved 0001 xxx x 0 0 0 0 0 0 0 0 opr w 0010 000 0 cie eie fie ob1 ob0 0c1 0c0 c2e opr r 0010 000 1 0 0 0 0 0 0 0 0 cr1 w 0010 001 0 ff1 ff0 ck2 ck1 ck0 ddm cms bex cr1 r 0010 001 1 0 0 0 0 0 0 0 0 cr2 w 0010 010 0 sfs nts dmo den etc bp1 bp2 rr cr2 r 0010 010 1 0 0 0 0 0 0 0 0 cr3 w 0010 011 0 lb1 lb2 lbd db1 db2 dbd tlb t15d cr3 r 0010 011 1 0 0 0 0 0 0 0 0 cr4 w 0010 100 0 eb1 eb2 ed ffit esfr ctlio mob ctc cr4 r 0010 100 1 0 0 0 0 0 0 0 0 cr5 w 0010 101 0 io4 io3 io2 io1 d4 d3 d2 d1 cr5 r 0010 101 1 0 0 0 0 0 0 0 0 cr6 w 0010 110 0 t15e actaut pupaut qm ais tfb0 rfs lfs cr6 r 0010 110 1 0 0 0 0 0 0 0 0 cr7 w 0010 111 0 0 0 0 0 0 lock pl2en dect cr7 r 0010 111 1 0 0 0 0 0 0 0 0 txb1 w 0011 000 0 0 0 b1x5 b1x4 b1x3 b1x2 b1x1 b1x0 txb1 r 0011 000 1 0 0 0 0 0 0 0 0 txb2 w 0011 001 0 0 0 b2x5 b2x4 b2x3 b2x2 b2x1 b2x0 txb2 r 0011 001 1 0 0 0 0 0 0 0 0 rxb1 w 0011 010 0 0 0 b1r5 b1r4 b1r3 b1r2 b1r1 b1r0 rxb1 r 0011 010 1 0 0 0 0 0 0 0 0 rxb2 w 0011 011 0 0 0 b2r5 b2r4 b2r3 b2r2 b2r1 b2r0 rxb2 r 0011 011 1 0 0 0 0 0 0 0 0 txd w 0011 100 0 dx5 dx4 dx3 dx2 dx1 dx0 sx1 sx0 txd r 0011 100 1 0 0 0 0 0 0 0 0 rxd w 0011 101 0 dr5 dr4 dr3 dr2 dr1 dr0 sr1 sr0 rxd r 0011 101 1 0 0 0 0 0 0 0 0 reserved 0011 11x x 0 0 0 0 0 0 0 0 notes: 1. bit 7 of byte 1 is the first bit clocked into the uid. 2. all configuration registers can be read-back by setting bit 7 of byte 1 equal 1 3. rxoh is a write only register to force rxeoc, rxm4, rxm56, rxact status register sending. rst reset the device 4. it is recommended not to access all reserved adresses. x means 1 or 0 w refers to a write operation. r refers to a request for read-back. STLC5412 52/74
table 8: register access messages (continued) function byte 1 byte 2 ad7/4 ad3/1 ad0 7 6 5 4 3 2 1 0 txm4 w 0100 000 0 0 m42x m43x m44x m45x m46x 0 m48x txm4 r 0100 000 1 0 0 0 0 0 0 0 0 txm56 w 0100 001 0 0 0 0 m51x m61x m52x febx febx txm56 r 0100 001 1 0 0 0 0 0 0 0 0 txact w 0100 010 0 0 0 0 0 c4x c3x c2x c1x txact r 0100 010 1 0 0 0 0 0 0 0 0 bec1 r 0100 011 1 0 0 0 0 0 0 0 0 bec2 r 0100 100 1 0 0 0 0 0 0 0 0 ect1 w 0100 101 0 ect17 ect16 ect15 ect14 ect13 ect12 ect11 ect10 ect1 r 0100 101 1 0 0 0 0 0 0 0 0 ect2 w 0100 110 0 ect27 ect26 ect25 ect24 ect23 ect22 ect21 ect20 ect2 r 0100 110 1 0 0 0 0 0 0 0 0 rxoh w 0100 111 0 eoc m4 m56 act 0 status 0rst reserved 0100 111 1 0 0 0 0 0 0 0 0 txeoc w 0101 efg h xeoc1 xeoc2 xeoc3 xeoc4 xeoc5 xeoc6 xeoc7 xeoc8 txeoc r 0110 000 1 0 0 0 0 0 0 0 0 reserved 0111 xxx x 0 0 0 0 0 0 0 0 idr r 100x 000 0 0 0 0 0 0 0 0 0 decteoc w 1010 efg h deoc1 deoc2 deoc3 deoc4 deoc5 deoc6 deoc7 deoc8 decteoc r 1011 000 1 0 0 0 0 0 0 0 0 reserved 1100 xxx 0 0 0 0 0 0 0 0 0 dbaud r 1100 000 1 0 0 0 0 0 0 0 0 dtxrx r 1100 001 1 0 0 0 0 0 0 0 0 reserved 1100 x1x x 0 0 0 0 0 0 0 0 free 1101 xxx x 0 0 0 0 0 0 0 0 free 1110 xxx x 0 0 0 0 0 0 0 0 mwps w 1111 111 0 ff = mode b 00 = mode a notes: 1. all transmit registers can be read-back by setting bit 7 of byte 1 equal 1 except for txeoc and d ect eoc registers. to read-back txeoc, use the command 61-00 h, to read back dect eoc use command b1-00h.. 2. bec1, bec2 and idr are read-only registers. 3. free adresses are ignored by the device. 4. in the txeoc and decteoc registers: e = ea1, the msb of the eoc destination address f=ea2 g = ea3 h = dm, the eoc data/message mode indicator 5. m42x is significant in nt mode only STLC5412 53/74
table 9: read back messages function byte 1 byte 2 ad7/4 ad3/1 ad0 7 6 5 4 3 2 1 0 opr 0010 000 1 cie eie fie ob1 ob0 0c1 0c0 c2e cr1 0010 001 1 ff1 ff0 ck2 ck1 ck0 ddm cms bex cr2 0010 010 1 sfs nts dmo den etc bp1 bp2 rr cr3 0010 011 1 lb1 lb2 lbd db1 db2 dbd tlb t15d cr4 0010 100 1 eb1 eb2 ed ffit esfr ctlio mob ctc cr5 0010 101 1 i04 i03 i02 i01 d4 d3 d2 d1 cr6 0010 110 1 t1se actuat pupaut qm ais tfb0 rfs lfs cr7 0010 111 1 0 0 0 0 0 lock pl2en dect txb1 0011 000 1 0 0 b1x5 b1x4 b1x3 b1x2 b1x1 b1x0 txb2 0011 001 1 0 0 b2x5 b2x4 b2x3 b2x2 b2x1 b2x0 rxb1 0011 010 1 0 0 b1r5 b1r4 b1r3 b1r2 b1r1 b1r0 rxb2 0011 011 1 0 0 b2r5 b2r4 b2r3 b2r2 b2r1 b2r0 txd 0011 100 1 dx5 dx4 dx3 dx2 dx1 dx0 sx1 sx0 rxd 0011 101 1 dr5 dr4 dr3 dr2 dr1 dr0 sr1 sr0 txm4 0100 000 1 0 m42x m43x m44x m45x m46x 0 m48x txm56 0100 001 1 0 0 0 m51x m61x m52x febx febx txact 0100 010 1 0 0 0 0 c4x c3x c2x c1x bec1 0100 011 1 c7 c6 c5 c4 c3 c2 c1 c0 bec2 0100 100 1 c7 c6 c5 c4 c3 c2 c1 c0 ect1 0100 101 1 ect17 ect16 ect15 ect14 ect13 ect12 ect11 ect10 ect2 0100 110 1 ect27 ect26 ect25 ect24 ect23 ect22 ect21 ect20 txeoc 0110 efg h xeoc1 xeoc2 xeoc3 xeoc4 xeoc5 xeoc6 xeoc7 xeoc8 idr 1000 ccc c 0 0 0 0 1 0 0 0 decteoc 1011 efg h deoc1 deoc2 deoc3 deoc4 deoc5 deoc6 deoc7 deoc8 dbaud 1100 000 1 dbaud7 dbaud6 dbaud5 dbaud4 dbaud3 dbaud2 dbaud1 dbaud0 dtxrx 1100 001 1 dtxrx7 dtxrx6 dtxrx5 dtxrx4 dtxrx3 dtxrx2 dtxrx1 dtxrx0 notes: 1. for all these registers with the exception of txeoc, bit 0 of byte 1 is set to 1 to indicate read-ba ck message. 2. cr5 configuration/status register is listed with status registers. 3. bit 7 of byte 1 is the first clocked out from the uid. 4. m42x is significant in nt mode only table 10: spontaneous or driven messages function byte 1 byte 2 ad7/4 ad3/1 ad0 7 6 5 4 3 2 1 0 cr5 0010 101 0 io4 io3 io2 io1 d4 d3 d2 d1 status 0011 111 0 pwdn 0 0 0 rxffu rxffo txffu txffo rxm4 0100 000 0 m41r m42r m43r m44r m45r m46r m47r m48r rxm56 0100 001 0 0 0 0 m51r m61r m52r febr nebr rxact 0100 010 0 0 0 0 0 c4r c3r c2r c1r bec1 0100 011 0 c7 c6 c5 c4 c3 c2 c1 c0 bec2 0100 100 0 c7 c6 c5 c4 c3 c2 c1 c0 rxeoc 0101 efg h reoc1 reoc2 reoc3 reoc4 reoc5 reoc6 reoc7 reoc8 notes: 1. all status registers can be read by setting first the appropriate command. at any status change, an interrupt cycle is issued. 2. in the rxeoc register: e = ea1 f=ea2 g = ea3 h = d=0/m = 1 3. for all these registers with the exception of rxeoc, bit 0 of byte 1 is set to 0 to indicate a s tatus register. STLC5412 54/74
line interface circuit it is very important, comply with ansi, etsi and french standards, that the recommended line in- terface circuit should be strictly adhered to. the channel response and dynamic range of this cir- cuit have been carefully designed as an integral part of the overall signal processing system to ensure that the performance require- ments are met under all the specified loop conditions. deviations from this design are likely to result in sub-optimal performance or even total failure of the system on some types of loops. turns ratio: np:ns = 1:1.5. secondary inductance: lp 27mh. max leakage inductance: 100 m h winding resistances: 30 ohms (2.25rp + rs) > 10 ohms. return loss, at 40 khz and load of 135 ohms: 26 db. saturation characteristics: thd 70db when tested with 50ma d.c. through the secondary and a 40khz sine-wave injected into the primary at a level which generates, at the secondary, 5v p-p (r load = 135ohms). list of suppliers: shott pulse engineering table 11. winding number of turns wire gauge 1-2 98 single #34 awg 6-5, 8-7 120+120 bifilar #36 awg 3-4 62 single #34 awg winding inductance resistance 1-2 + 3-4 12 mh less than 5 w 5-6 + 7-8 27 mh less than 10 w board layout while the pins of the uid are well protected against electrical misuse, it is recommended that the stand- ard cmos practise, of applying gnd to the device before any other connections are made, should al- ways be followed. in applications where the printed circuit card may be plugged into a hot socket with power and clocks already present, an extra long ground pin on the connector should be used. great care must be taken in the layout of the printed cir- cuit board in order to preserve the high transmis- sion performance of the STLC5412. to maximize performance, do not use the philosophy of separat- ing analog and digital grounds for chip. all gnd pins should be connected together as close as pos- sible to the pins, and the vcc pins should be strapped together. all ground connections to each device should meet at a common point as close as possible to the gnd pins to prevent the interaction of ground return currents flowing through a com- mon bus impedance. two decoupling capacitors of 10 m f and 0.1 m f should be connected from this common point to vcc pins as close as possible to the chip. taking care with the board layout in the following ways will also help prevent noise injection into the receiver frontend and maximize the trans- mission performances. keep the crystal oscillator components away from the receiver inputs and use a shielded ground plane around these components. keep the device, the components connected to li+/li- and the transformer as close possible. sym- metrical layout for the line interface is suggested. .. .. 1 98t 2 6 120t 5 8 120t 7 3 62t 4 1.5:1 device side line side figure 11: transformer design. (secondary) (primary) STLC5412 55/74
figure 12: recommended connections. STLC5412 56/74
figure 13a: lt application. STLC5412 33pf 33pf STLC5412 57/74
figure 13b: lt application. STLC5412 58/74
figure 13c: rr application. STLC5412 STLC5412 STLC5412 59/74
appendix a - state matrix STLC5412 60/74
STLC5412 61/74
appendix b - electrical parameters absolute maximum ratings symbol parameter value unit v cc supply voltage 0.3 to 7.0 v v in input voltage 0.3 to 7.0 v t a operating temperature range -40 to 85 (3) c t stg storage temperature range 55 to 150 c transmission electrical parameters parameter min. typ. max. unit line interface features power up output differential impedance (020khz) between lo+/lo- 1 5 w power down output differential impedance (020khz) between lo+/lo- 8 12 16 w power consumption i cc in power down 48ma i cc in power up transmitting (2) 70 80 ma transmission performances transmit pulse amplitude on lo+, lo- (1) 3.27 3.61 v transmit pulse linearity (1:3 ratio accuracy) 36 50 db (1) this specification garanties the ansi specification, concerning the pulse amplitude using the line interface recommended schematics, of 2,5 5% volts peak amplitude for 2b1q pulse. (2) test condition: v cc = 5v, 2b1q random signal transmitted with recommended 27mh line interface (fig 12) terminated with 135 w . (3) test condition: etsi loop2 ( average loop ) and etsi loop 3r ( long loop) static characteristics symbol parameter test condition min. typ. max. unit v cc dc supply voltage 4.75 5.25 v v il input low voltage all dig inputs except xtal1 0.7 v v ih input high voltage all dig inputs except xtal1 2.2 v v ilx input low voltage xtal1 input 0.5 v v ihx input high voltage xtal1 input v cc 0.5 v v ol output low voltage br, i o = +7ma all other digital outputs, i ol = +1ma 0.4 0.4 v v v oh output high voltage br, i o = 7ma all other digital outputs i o = 1ma all outputs (3), i o = 100 m a 2.4 2.4 v cc 0.5 v v v i lh input current any digital v in =v dd 01 m a i ll input current input pin numbers: 6,7,12,13 17,19,25,27,28 vin = gnd (1) 1 0 m a i llr input current with internal pull up resistor input pin numbers: 14,15,16, 22,26,18, v in = gnd (1) 50 0 m a i llx input current on xtal1 gnd < v in STLC5412 62/74
timing characteristics symbol parameter test condition min. typ. max. unit master clock fmclk frequency of mclk tolerance including temperature, aging, etc... 100 15.36 +100 mhz ppm mclk/xtal input clock jitter external clock source 50 ns pk-pk twmh clock pulse width, mclk high level v ih =v cc 0.5v v il = 0.5v 20 ns twml clock pulse width, mclk low level 20 ns trm tfm rise time of mclk fall time of mclk used as a logic input 10 10 ns ns digital interface fbclk frequency of bclk formats 1, 2 and 3 format 4 and gci mode 256 512 4095 6144 khz khz twbh clock pulse width, bclk high level measured from v ih to v ih 30 ns twbl clock pulse width, bclk low level measured from v il to v il 30 ns trb risae time of bclk measured from v il to v ih 15 ns tfb fall time of bclk measured from v ih to v il 15 ns tsfb setup time, fs high or low to bclk low dsi or gci slave mode only 30 ns thbf hold time, bclk low to fs high or low dsi or gci slave mode only 20 ns tdbf delay time, bclk high to fs high or low dsi or gci master mode only 20 20 ns tdbd delay time, bclk high to data valid load = 150pf + 2 lsttlloads 80 ns tdbdz delay time, bclk high to data hz 50 ns tdfd delay time, fs high to data valid load = 150pf + 2 lsttlloads 80 ns tsdb setup time, data valid to bclk low 0 ns thbd hold time, bclk to data invalid 20 ns tdbt delay time, bclk high to tsr low load = 100pf + 2 lsttlloads 80 ns tdbtz delay time, bclk low to tsr hz 50 ns tdft delay tie, fs high to tsr low load = 100pf + 2 lsttlloads 80 ns d port in continuous mode: 16kbits/sec tsdd setup time, dclk low to dx high or low 50 ns thdd hold time, dclk low to dx high or low 50 ns tddd delay time,dclk high to dr high or low load = 50pf + 2 lsttl loads 80 ns microwire control interface fcclk frequency of cclk 5 mhz twch clock pulse width, cclk high level measured from v ih to v ih 85 ns twcl clock pulse width, cclk low level measured from v il to v il 85 ns trc rise time of cclk measured from v il to v ih 15 ns tfc fall time of cclk measured from v ih to v il 15 ns tssc setup time, csb low to cclk high 60 ns thcs hold time, cclk low to csb high 10 ns twsh duration of csb high 200 ns tsic setup time, ci valid to cclk high 25 ns thci hold time, cclk high to ci invalid 25 ns tdso delay time, csb low to co valid out first bit on co 50 ns tdco delay time cclk low to co valid load = 50 pf + 2lsttl loads 50 ns tdcoz delay time, cclk low to co hz 50 ns tdci delay time,cclk low to intb low or hz load = 80pf + 2lsttl loads 150 ns STLC5412 63/74
figure 14: bclk, fsa, fsb, slave mode, delayed mode, formats 1 2 3 ( m w only). figure 15: bclk, fsa, fsb, slave mode, non delayed mode, formats 1 2 3 ( m w only). STLC5412 64/74
figure 16: bclk, fsa, fsb, slave mode, format 4 always non delayed mode, ( m w and gci mode). bclk output t dbf t dbf t dbf t dbf note 1 note 1 note 1 t dbf t dbf t dbf t dbf last bit of the frame first bit of the frame second bit of the frame eight bit of the frame seventh bit of the frame fsa output fsb output bx input d96tl253 t rb t fb note 1: in accordance to the selected frequency. high level duration - low level duration or br output figure 17: bclk, fsa, fsb, master mode, delayed mode, formats 1 2 3 ( m w only). STLC5412 65/74
figure 18: bclk, fsa, fsb, master mode, non delayed mode, formats 1 3 ( m w only). figure 19: bclk, fsa, fsb, master mode, format 4 always non delayed mode, ( m w and gci mode). STLC5412 66/74
figure 20: bx, dx, br, dr, slave & master, delayed & non delayed, formats 1 2 3 ( m w only) m w 22 figure 21: bx, dx, br, dr, slave & master, format 4 always non delayed, ( m w & gci mode) STLC5412 67/74
figure 22: special case br, dr, only first bit of the frame, in slave and non de- layed modes formats 1 3 (mw mode), format 4 ( m w & gci mode) 24 figure 23: tsrb, slave & master, delayed & non delayed, formats 123( m w only) STLC5412 68/74
25 figure 24: tsrb, slave & master, format 4 always non delayed mode ( m w & gci) figure 25: special case tsrb, b1 or b2 first channel of the frame, in slave & non delayed mode, formats 1 3 (mw mode), format 4 ( m w & gci mode) STLC5412 69/74
figure 26: dclk, dx, dr in continuous mode slave & master, delayed & non delayed modes all formats in m w mode only figure 27: mclk all modes figure 28: m w port mode a STLC5412 70/74
figure 29: m w port mode b STLC5412 71/74
plcc44 dim. mm inch min. typ. max. min. typ. max. a 17.4 17.65 0.685 0.695 b 16.51 16.65 0.650 0.656 c 3.65 3.7 0.144 0.146 d 4.2 4.57 0.165 0.180 d1 2.59 2.74 0.102 0.108 d2 0.68 0.027 e 14.99 16 0.590 0.630 e 1.27 0.050 e3 12.7 0.500 f 0.46 0.018 f1 0.71 0.028 g 0.101 0.004 m 1.16 0.046 m1 1.14 0.045 outline and mechanical data STLC5412 72/74
dim. mm inch min. typ. max. min. typ. max. a1 0.63 0.025 b 0.45 0.018 b1 0.23 0.31 0.009 0.012 b2 1.27 0.050 d 37.34 1.470 e 15.2 16.68 0.598 0.657 e 2.54 0.100 e3 33.02 1.300 f 14.1 0.555 i 4.445 0.175 l 3.3 0.130 dip28 outline and mechanical data STLC5412 73/74
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 1999 stmicroelectronics printed in italy all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. http://www.st.com esd - the sgs-thomson internal quality standards set a target of 2 kv that each pin of the devic e should withstand in a series of tests based on the human body model (mil-std 883 method 3015): with c = 100pf; r = 1500 w and performing 3 pulses for each pin versus v cc and gnd. device characterization showed that, in front of the sgs-thomson internaly quality standards, all pins of STLC5412 withstand at least 2000v. the above points are not expected to represent a pratical limit for the correct device utilization nor for its reliability in the field. nonetheless they must be mentionned in connection with the applicability of the different sure 6 requirements to STLC5412. STLC5412 74/74

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