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ar c hive inf o rmati o n archive information 1 motorola semiconductor application information prepared by; paul sofianos motorola, inc., wssg rf/if applications engineering introduction this application note describes a full?duplex, wireless data communication link targeted for rs?232 applications. an encoding technique has been designed which addresses many of the problems incurred when attempting to implement the rs?232 (eia?232) standard, including but not limited to: hardware flow control, the dc component of the transmitted signal, automatic synchronization from host to slave and error detection. the design emulates a rs?232 null modem cable for computer?to?computer communications. the actual design was realized with standard ssi logic from the high speed cmos family (mc74hcxxx), an hc05 based mcu, and motorola?s ism band rf chipset. the targeted data rate was 57,600 baud, although both higher and lower data rates are easily attainable. it is expected that most applications would embed the logic functions (and possibly the mcu functions) into a fpga, cpld, asic, or other lsi logic building block. throughout this application note, it is assumed the user is familiar with standard ttl?compatible cmos devices and the ism band rf chipset. please refer to dl110/d and dl129/d for additional details on individual device specifications. the wireless link the actual implementation of the wireless link transceiver was accomplished with the motorola?s ism band rf chipset. this consists of a mc13145 rf receiver, mc13146 rf transmitter and mc33411 baseband. figure 1 depicts the block diagram of the rf transceiver. figures 2, 3, and 4 are the actual schematics for the receiver, transmitter, and baseband, respectively. the transceiver was designed to operate in the unlicensed (i.e. fcc part 15) 902?928 mhz industrial, scientific and medical (ism) band with low?power transmission. since direct?conversion fsk modulation is used in conjunction with a pll synthesized carrier, the digital modulation source must meet certain requirements: 1. the dc component should be as close to zero as possible. this maintains the best noise immunity at the receiver. 2. a minimum frequency component must be maintained at all times. if this condition is not met, the transmitter?s pll and receiver?s coilless demodulator will tend to ?track?out? the modulating signal. 3. the maximum frequency component should be known. this will help define the modulation index and total bandwidth required for the transceiver. 4. the system should be able to tolerate reasonable bit?errors. the mc33411 baseband controls all of the synthesizer functions via a mcu spi compatible interface. none of the audio processing capabilities of the device are used. table 1 lists various mc33411 register values for both baseset and handset for the 5 channels used for the prototype. figure 1. rf transceiver block diagram order this document by AN1687/d semiconductor application note ? motorola, inc. 1999 rev 1 archived by freescale semiconductor, inc. 2005
ar c hive inf o rmati o n archive information 2 motorola semiconductor application information figure 2. rf receiver default units: ohms, microfarads and microhenries cf1,cf2 toko type cfsk series sk107mx?ae?xxx, 330 khz bw cf3,cf4 handset: tdk cf6118702 baseset: tdk cf6118902 d1 mmbv809lt1 t1 toko a638an?a099ywn archived by freescale semiconductor, inc. 2005
ar c hive inf o rmati o n archive information 3 motorola semiconductor application information figure 3. rf transmitter default units: ohms, microfarads and microhenries cf5 handset: tdk cf 6118902 baseset: tdk cf 6118702 d2,d3 mmbv809lt1 archived by freescale semiconductor, inc. 2005
ar c hive inf o rmati o n archive information 4 motorola semiconductor application information figure 4. baseband default units: ohms, microfarads and microhenries archived by freescale semiconductor, inc. 2005
ar c hive inf o rmati o n archive information 5 motorola semiconductor application information digital encoding description as mentioned above, it is necessary to encode the raw rs?232 data prior to rf transmission since the incoming data stream can, and usually will, contain a dc component and has no pre?defined minimum frequency component. figure 5 is a block diagram of the digital encoder/decoder section, and figure 6 shows a possible implementation of the encoder. figure 5. encoder/decoder block diagram (baseset shown) 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13 archived by freescale semiconductor, inc. 2005
ar c hive inf o rmati o n archive information 6 motorola semiconductor application information figure 6. encoder figure 7 illustrates the encoding scheme which was developed for this purpose. four additional bits surround a data byte: the i bit, i bit, d/c bit and d /c bit. the function of these bits are: i (invert) bit: a logic low on this bit indicates that the data byte and d/c bit are in true form. a logic high on this bit indicates that the data byte and d/c bit are complemented from their original form. i (invert bar) bit: just the complement of the i bit. d/c (data/control ) bit: a logic low on this bit indicates that the data byte should be interpreted as a control word. a logic high on this bit indicates that the data byte contains real data. d /c (data /control): just the complement of the d/c bit. figure 7. archived by freescale semiconductor, inc. 2005
ar c hive inf o rmati o n archive information 7 motorola semiconductor application information this encoding scheme allows for the representation of 256 unique data words and 256 unique control words. the control byte $h00 is reserved and referred to as the idle byte. when the parallel?input/serial?output (piso) register is ready to transmit a data byte (txr asserted), a check is made to see if real data has been transferred into the serial communications interface (sci) data register of the mcu. if data has been received, the data byte will be read, and the initial state of d/c will be set to 1. if data has not been received, the data byte will be set to $h00 (the idle byte) and the initial state of d/c will be set to 0. next, the data byte is examined for a dc component. each 0 bit of the data byte represents ?1 and each 1 bit of the data byte represents +1. all of these values are summed together: a negative result indicates a low dc component, zero indicates no dc component, and a positive (non?zero) result indicates a high dc component. this component is compared to a cumulative sum (which may be negative, zero, or positive) and the following actions are taken: if the current dc component sum is negative, and the cumulative sum is positive or zero or if the current dc component sum is positive or zero and the cumulative sum is negative then clear the i bit (i=0). the new cumulative sum is equal to the old cumulative sum plus the current sum. otherwise set the i bit (i=1). the new cumulative sum is equal to the old cumulative sum minus the current sum. if the i bit is set, the contents of the data byte and d/c bit are complemented. the updated value of the i bit, data byte, and d/c bit are placed on the piso, and a transmission acknowledge signal (ntxa) is asserted. please note, the net effect of the dc component contributed by the i and i bits and d/c and d /c bits will always equal zero. an analysis of this encoding scheme brings to light a few interesting observations: 1. the average dc component over time will approach zero. 2. the minimum frequency component which will be observed in the data stream will equal 1/(2 x transmitted bit period x 10). 3. the maximum (fundamental) frequency component which will be observed in the data stream will equal 1/(2 x transmitted bit period). 4. a sequence of ten consecutive zeros or ones indicates the presence of an idle byte. item 4 is perhaps the most interesting observation, since it will allow the receiver to synchronize the incoming data and align the serial stream on a byte?wide basis. transmitting frequency for encoded data for rs?232 communications which take the form of one start bit, eight data bits, no parity, and one stop bit, the sci will receive 10 bits of data to represent one actual data byte. for our encoding scheme, 12 bits must be transmitted for each data or control byte received. if the transmit pipeline is set to a frequency of at least 1.2 times the sci receive pipeline, the receive bandwidth will not have to be reduced (i.e. no stop or hold conditions would be required). in actual practice, the transmit pipeline was set to a frequency 25% greater than the receive pipeline. as a result, at a minimum, there will be at least one idle byte transmitted for every 24 real data bytes. this useful feature allows the receiver to re?synchronize from time to time. additional features as mentioned above, the opportunity presents itself to transmit a control word (the idle byte just being a special case of a control word) from time to time. with 255 control words remaining, various special features can be built into the link, all transparent to the actual rs?232 data communications. one of the more obvious features which can be implemented is hardware (rts/cts) flow control. the rts signal (for the baseset) and cts signal (for the handset) can be monitored and transmitted/received and interpreted by the link. the latency will mostly be a function of the overhead bandwidth. other features which can be implemented include, but are not limited to: remote channel changing adaptive channel selection acknowledgments dcd/dsr, etc. commands crc or other error checking half duplex handshaking power conservation modes archived by freescale semiconductor, inc. 2005
ar c hive inf o rmati o n archive information 8 motorola semiconductor application information figure 8. decoder

archived by freescale semiconductor, inc. 2005
ar c hive inf o rmati o n archive information 9 motorola semiconductor application information figure 8 illustrates a possible implementation of the digital decoder section of the design. received data is ?squared up? by the data slicer of the mc33411 baseband ic. the transmitted data is generally frequency limited in order to preserve bandwidth (i.e. low?pass filtered). because of this limiting, as well as noise components and hysteresis in the data slicer, the duty cycle of the received data stream can vary substantially from that of the transmitted data. for this reason, a data and clock recovery block is utilized which oversamples the incoming data (digital noise filtering) and captures the embedded clock. once the clock and data have been recovered, they are presented to the serial?input/parallel?output (sipo) register. data is transferred into the register every 12 bits, this representing the i , i, data byte, d/c and d /c bits. another circuit analyzes the serial data stream looking for ten consecutive bits without a transition. if this condition is observed, it indicates an idle byte has been received, and the sipo register clock can be synchronized. when the sipo register indicates that a byte has been received (rxr asserted), the mcu asserts an acknowledgement (nrxa), loads the data byte, the i bit and d/c bit from the bus. at this time, a comparison is made which verifies that the i bit is the complement of the i bit and the d/c bit is the complement of the d /c bit. if either of these conditions is not met, a framing error has occurred and the received data is simply ignored. if a valid byte has been received, the mcu checks the status of the i bit. if the i bit is set, the byte, as well as the d/c bit, is complemented. next, the mcu checks the value of the updated d/c bit; a logic zero indicates a control word, and the mcu can take appropriate action. if the d/c bit indicates real data has been received, the data is placed on an internal first?in/first?out (fifo) memory stack. the sci transmitter is checked: if empty, the next data byte is placed into the sci transmitter and if full, the data will be transferred at a later time. as can be seen, the decoding of the data is a relatively simple task. if desired, the mcu can consider the lack of an idle byte, within a given period of time or reception of some number of bytes, an indication that the rf link has failed. again, this condition can be used to re?initialize the rf link, or other courses of action can be taken. summary this application note has described a robust, full featured rs?232 wireless interface which can be implemented with an inexpensive mcu. for slower data rates, it is possible to eliminate all of the external ?glue logic? shown in this note. a plethora of additional features can be added by the use of embedded control words which are transparent to the actual data transceiver. motorola?s inexpensive and easy to use ism band rf chipset is easily capable of accomplishing the wireless portion of the task as long as the digital information presented to the transmitter and receiver have been properly preconditioned prior to modulation and demodulation. archived by freescale semiconductor, inc. 2005
ar c hive inf o rmati o n archive information 10 motorola semiconductor application information table 1. baseband register address handset value transmit frequency (mhz) receive frequency (mhz) baseset value transmit frequency (mhz) receive frequency (mhz) channel number $h01 $h004822 925.0 ? $h004686 903.0 ? 0 $h02 $h004c27 ? 903.0 $h004e03 ? 925.0 0 $h01 $h004827 925.5 ? $h00468b 903.5 ? 1 $h02 $h004c2c ? 903.5 $h004e08 ? 925.5 1 $h01 $h00482c 926.0 ? $h004690 904.0 ? 2 $h02 $h004c31 ? 904.0 $h004e0d ? 926.0 2 $h01 $h004831 926.5 ? $h004695 904.5 ? 3 $h02 $h004c36 ? 904.5 $h004e12 ? 926.5 3 $h01 $h004836 927.0 ? $h00469a 905.0 ? 4 $h02 $h004c3b ? 905.0 $h004e17 ? 927.0 4 $h03 $h0e0276 ? ? $h0e0276 ? ? x $h04 $h160070 ? ? $h160070 ? ? x $h05 $h000010 ? ? $h000010 ? ? x $h06 $h0000ff ? ? $h0000ff ? ? x $h07 $h01c000 ? ? $h01c000 ? ? x archived by freescale semiconductor, inc. 2005
ar c hive inf o rmati o n archive information 11 motorola semiconductor application information notes archived by freescale semiconductor, inc. 2005
ar c hive inf o rmati o n archive information 12 motorola semiconductor application information motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, represe ntation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the applicati on or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operatin g parameters, including ?t ypicals? must be validated for each customer application by customer?s technical experts. motorola does not convey any license under it s patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical imp lant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a s ituation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expens es, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motoro la, inc. motorola, inc. is an equal opportunity/affirmative action employer. mfax is a trademark of motorola, inc. how to reach us: usa/europe/locations not listed : motorola literature distribution; japan : motorola japan ltd.; spd, strategic planning office, 141, p.o. box 5405, denver, colorado 80217. 1?303?675?2140 or 1 ?800?441?2447 4?32?1 nishi?gotanda, shinagawa?ku, tokyo, japan. 81?3? 5487?8488 customer focus center: 1?800?521?6274 mfax ? : rmfax0@email.sps.mot.com ? to uchtone 1?602?244?6609 asia/pacific : motorola semiconductors h.k. ltd.; silicon harbour centre, motorola fax back system ? us & canada only 1?800?774?1848 2, dai king street, tai po industrial estate, tai po, n.t., hong kong. ? http://sps.motorola.com/mfax/ 852?26668334 home page : http://motorola.com/sps/ AN1687/d ? archived by freescale semiconductor, inc. 2005

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