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em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 1 www.emmicroelectronic.com ultra low power microcontroller with adc and eeprom features ? low power - 3.2 a active mode, adc off - 9.0 a active mode, adc on - 0.6 a standby mode - 0.1a sleep mode @ 3.0v, 32khz, 25c ? voltage range logic incl. eeprom 2.0 to 5.5 v ? system operating clock : 32 or 128khz (metal option) ? voltage range for the adc is 2.6 to 5.5 v ? 2 clocks per instruction cycle ? 72 basic instructions ? rom 3k 16 bit ? ram 128 4 bit ? e 2 prom 64 8 bit ? voltage level detector, 3 levels software selectable :2.2, 2.5, 3.0 v ? 2 channel adc, successive approximation method; conversion time at 32 khz : 305s ? max. 12 inputs (3 ports); port a, port b, port c ? max. 8 outputs (2 ports); port b, port c ? serial write buffer, 256 bit wide , 4 bit rates ? oscillation supervisor and timer watchdog ? universal 10-bit counter, pwm, event counter ? 8 internal interrupt sources (2 timer , 2 prescaler, adc, vld, fifo, eeprom) ? 4 external interrupt sources (input port a ) ? frequency output; 32khz, 2khz, 1khz, pwm description the em6617 is an advanced single chip cmos 4-bit microcontroller. it contains rom, ram, power on reset, watchdog timer, oscillation detection circuit, combined timer , event counter, prescaler, e 2 prom, 2 channel adc, serial write buffer, voltage level detector and several clock functions. the low voltage feature and low power consumption make it the most suitable controller for battery, stand alone and mobile equipment. the em6617 is manufactured using em microelectronic?s advanced low power (alp) cmos process. typical applications ? sensor & detector interface ? heat meter interface ? security systems ? household equipment controls ? automotive controls ? measurement equipment ? r/f and ir. control ? voltage control figure 1. architecture figure 2. pin configuration em microelectronic - marin sa
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 2 www.emmicroelectronic.com em6617 at a glance power supply - low voltage low power architecture including internal voltage regulator - 2.0 ... 5.5 v battery voltage for all logic functions - 2.6 ... 5.5 v battery voltage for the adc (0.2lsb) - 3.2 a in active mode, adc off - 9.0 a active mode, adc on - 0.6a in standby mode - 0.1a in sleep mode - 32 khz crystal oscillator ram - 64 x 4 bit, direct addressable - 64 x 4 bit, indirect addressable rom - 3072 x 16 bit metal mask programmable e 2 prom - 64 x 8 bit, indirect addressable - interrupt request at the end of a write operation cpu - 4 bit risc architecture - 2 clock cycles per instruction - 72 basic instructions main operating modes and resets - active mode (cpu is running) - standby mode (cpu in halt) - sleep mode (no clock, reset state) - initial reset on power on (por) - watchdog resets (logic and oscillation watchdogs) - reset terminal - reset with input combination on port a register selectable, and or or type by metal mask 4-bit input port a - direct input read on the port terminals - debouncer function available on all inputs - interrupt request on positive or negative edge - pull-up or pull-down or none selectable by register - test variables (software) for conditional jumps - pa[0] and pa[3] are inputs for the event counter - reset with input combination (register selectable) serial write buffer (output) - max 256 bits long bit rates of 16khz,8khz,2khz,1khz - automatic or interactive send mode - interrupt request when buffer is empty 2 channel 8-bit adc - conversion time is 305 s @32khz - 2 operating modes (continuous, single) - interrupt request at the end of conversion prescaler - 15 stage system clock divider down to 1 hz - 2 interrupt requests; 1 hz, 32 hz or 8 hz - prescaler reset (4 khz to 1hz) 4-bit bi-directional port b - all different functions bit-wise selectable - direct input read on the port terminals - data output latches - cmos or nch. open drain outputs - pull-down or pull-up selectable - weak pull-up in nch. open drain mode - selectable pwm, 1khz, 32khz and 2khz output 4bit bi-directional port c - input or output mode as whole port - direct input read on port terminal - data output latches - cmos or nch. open drain outputs - pull-down or pull-up selectable - weak pull-up in nch. open drain mode voltage level detector - 3 levels software selectable (2.0, 2.5, 3.0 v) - busy flag during measure - interrupt request at end of measure 10-bit universal counter - 10, 8, 6 or 4bit up/down counting - parallel load - 8 different input clocks - event counting (pa[0] or pa[3] ) - full 10 bit or limited (8, 6, 4 bit) compare function - 2 interrupt requests (on compare and on 0) - hi-frequency input on pa[3] and pa[0] - pulse-width modulation ( pwm ) output interrupt controller - 4 external and 8 internal interrupt request sources - each interrupt can individually be maskable - each interrupt can individually be reset - automatic reset of each interrupt request after read - general interrupt request to cpu can be disabled - automatic enabling of general interrupt request flag when going into halt mode
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 3 www.emmicroelectronic.com table of contents f eatures 1 d escription ________________________________ 1 typical applications _______________________ 1 em6617 at a glance _________________________ 2 1. pin description for em6617 _________________ 4 2. typical configurations _____________________ 5 3. operating modes _________________________ 6 3.1 active mode _________________________ 6 3.2 standby mode________________________ 6 3.3 sleep mode__________________________ 6 4. power supply ____________________________ 7 5. reset __________________________________ 8 5.1 oscillation detection circuit _____________ 9 5.2 reset terminal _______________________ 9 5.3 input port a reset function _____________ 9 5.3.1 and-type reset function ___________ 9 5.3.2 or -type reset function ___________ 10 5.4 digital watchdog timer reset __________ 10 5.5 cpu state after reset ________________ 11 6. oscillator and prescaler___________________ 12 6.1 oscillator___________________________ 12 6.2 prescaler___________________________ 12 7. input and output ports ____________________ 13 7.1 ports overview ______________________ 13 7.2 port a _____________________________ 14 7.2.1 irq on port a ___________________ 14 7.2.2 pull-up or pull-down ______________ 15 7.2.3 software test variables ___________ 15 7.2.4 port a for 10-bit counter ___________ 15 7.3 port a registers ______________________ 15 7.4 port b _____________________________ 17 7.4.1 input / output mode_______________ 17 7.4.2 pull-up or pull-down ______________ 18 7.4.3 cmos or nch. output _____________ 18 7.4.4 pwm and frequency output________ 19 7.5 port b registers ______________________ 19 7.6 port c _____________________________ 19 7.6.1 pull-up or pull-down ______________ 20 7.6.2 cmos or nch. output _____________ 21 7.7 port c registers _____________________ 21 8. 10-bit counter __________________________ 23 8.1 full and limited bit counting ___________ 23 8.2 frequency select and up/down counting _ 24 8.3 event counting ______________________ 25 8.4 compare function ___________________ 25 8.5 pulse width modulation (pwm) _________ 25 8.5.1 how the pwm generator works._____ 26 8.5.2 pwm characteristics______________ 26 8.6 counter setup_______________________ 27 8.7 10-bit counter registers_______________ 27 9. serial (output) write buffer - swb __________ 29 9.1 swb automatic send mode ____________29 9.2 swb interactive send mode ____________31 9.3 swb registers _______________________32 10. 2-channel adc (8-bit digital converter) _____33 10.1 continuous mode ____________________34 10.2 single mode ________________________34 10.3 2-channel adc registers ______________35 11. eeprom ( 64 8 bit ) __________________36 11.1 eeprom registers ___________________37 12. supply voltage level detector ____________38 12.1 svld register_______________________38 13. interrupt controller _____________________39 13.1 interrupt control registers ______________40 14. ram ________________________________41 15. strobe output _________________________42 15.1 strobe register_______________________42 16. peripheral memory map ____________43 17. option register memory map _____________46 18. active supply current test _______________47 19. mask options _________________________48 19.1 input / output ports ___________________48 19.1.1 port a metal options ______________48 19.1.2 port b metal options ______________49 19.1.3 port c metal options ______________50 19.1.4 swb high impedance state _________51 19.1.5 debouncer frequency option _______51 19.1.6 system frequency ________________51 19.1.7 additional mask options ____________51 20. temp. and voltage behavior _____________52 20.1 i(vdd) current ______________________52 20.2 iol, ioh ___________________________53 20.3 pull-up, pull-down ____________________54 20.4 vreg, eeprom ______________________54 20.5 adc8______________________________55 21. electrical specification __________________57 21.1 absolute maximum ratings ____________57 21.2 handling procedures__________________57 21.3 standard operating conditions __________57 21.4 dc characteristics - power supply _______58 21.5 oscillator ___________________________58 21.6 dc characteristics - i/o pins ____________59 21.7 supply voltage level detector __________60 21.8 adc 8 bit___________________________60 21.9 eeprom___________________________60 22. pad location diagram __________________61 23. package & ordering information___________62 23.1 ordering information __________________65 23.2 package marking ____________________65 23.3 customer marking____________________65 em microelectronic-marin sa cannot assume responsibility for use of any circuitry described other than circuitry entirely embodied in an em microelectronic-marin sa product. em microelectronic-marin sa reserves the right to change the circuitry and specifications without notice at any time. you are strongly urged to ensure that the information given has not been superseded by a more up-to-date version.
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 4 www.emmicroelectronic.com 1. pin description for em6617 pdip24 so24 pdip28 so28 tssop28 signal name function remarks 17 20 v bat= v dd positive power supply main power pin mfp programming connection 21 24 v ss negative power supply reference terminal, substrate mfp programming connection 18 21 vreg internal voltage regulator connect to minimum 100nf mfp programming connection 15 18 test input test terminal, internal pull-down 15k for em tests only, ground 0 ! except for mfp programming 14 17 reset reset terminal internal pull-down 15k 16 19 strobe strobe / reset status c reset state + port b write 19 22 qin crystal terminal 1 32khz crystal mfp programming connection 20 23 qout crystal terminal 2 32khz crystal mfp programming connection 10 13 pb[0] input or output, cmos or nch. open drain; port b terminal 0 ck[12] output (2 khz) 11 14 pb[1] input or output, cmos or nch. open drain; port b terminal 1 ck[16] output (32 khz) 12 15 pb[2] input or output, cmos or nch. open drain; port b terminal 2 ck[11] output (1 khz) 13 16 pb[3] input or output, cmos or nch. open drain; port b terminal 3 pwm output 6 7 pa[0] input port a terminal 0 testvar 1, event counter 7 8 pa[1] input port a terminal 1 testvar 2 5 6 pa[2] input port a terminal 2 8 9 pa[3] input port a terminal 3 event counter 4 5 pc[0] input or output, cmos or nch. open drain; port c terminal 0 9 10 pc[1] input or output, cmos or nch. open drain; port c terminal 1 - 4 pc[2] input or output, cmos or nch. open drain; port c terminal 2 bonded only in 28 pin package - 12 pc[3] input or output, cmos or nch. open drain; port c terminal 3 bonded only in 28 pin package 22 25 ain channel a for a/d converter 23 26 bin channel b for a/d converter 24 27 vref external voltage reference input for the a/d converter only used for external vref i.e. vref not equal to v dd 1 28 vgnd virtual analogue ground for a/d converter virtual ground, usually v dd /2 2 2 data serial write buffer data out 3 3 clk serial write buffer clock out gray shaded area : mfp programming connections (v dd , vreg, qin , qout, test, vss).
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 5 www.emmicroelectronic.com 2. typical configurations full range adc : vref = v dd , vgnd = v dd /2. for power saving one might connect the vgnd resistor divider chain onto a port b output. this output should be driving v dd during the conversion and driving v ss or high impedance in the adc off state. limited range adc : v dd > vref > vgnd, vgnd=v dd /2. for power saving one might connect the vgnd and the vref resistor divider chain onto a port b output to v ss . this output should be driving v dd during the conversion and driving vss or high impedance in the adc off state. other possibility: vref = vreglogic, vgnd = vreglogic/2 for power saving one might connect the vgnd resistor divider chain from vreglogic onto a port b output. this output should be driving v ss during the conversion and driving ?high impedance? in the adc off state. figure 3. typical application, full range main power vreg v ss vss r1 r1 vss ain bin port c port b strobe reset port a vref vgnd v dd v dd , or port driven v dd 32 khz >1.3v v dd vss vgnd + - full range a dc figure 4. typical application, limited range main power vreg vss vss or vgnd >1.3v vdd or port b driven r1 c1 r1 vss ain bin vref vgnd v dd 32 khz limited range a dc vref vref vgnd + - vdd vss +| vref - vgnd | -| vref - vgnd | port c port b strobe reset port a
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 6 www.emmicroelectronic.com 3. operating modes the em6617 has two low power dissipation modes, standby and sleep. figure 5 is a transition diagram for these modes. 3.1 active mode the active mode is the actual cpu running mode. instructions are read from the internal rom and executed by the cpu. leaving active mode via the halt instruction to go into standby mode, the sleep bit write to go into sleep mode or a reset from port a to go into reset mode. 3.2 standby mode executing a halt instruction puts the em6617 into standby mode. the voltage regulator, oscillator, watchdog timer, adc, interrupts, swb, timers and counters are operating. however, the cpu stops since the clock related to instruction execution stops. registers, ram and i/o pins retain their states prior to standby mode. a reset or an interrupt request if enabled cancels standby. 3.3 sleep mode writing to the sleep bit in the regsyscntl1 register puts the em6617 in sleep mode. the oscillator stops and most functions of the em6617 are inactive. to be able to write to the sleep bit, the sleepen bit in regsyscntl2 must first be set to "1". in sleep mode only the voltage regulator and the reset input are active. the ram data integrity is maintained. sleep mode may be canceled only by a high level of min 10s at the reset terminal or by the selected port a input reset combination, if option inpressleep in register optfselpb is turned on. due to the cold-start characteristics of the oscillator, waking up from sleep mode may take some time to guarantee stable oscillation. during sleep mode and the following start up the em6617 is in reset state. waking up from sleep clears the sleep flag but not the sleepen bit. inspecting the sleepen allows to determine if the em6617 was powered up ( sleepen = "0") or woken up from sleep ( sleepen = "1"). table 3.3.1. internal state in standby and sleep mode function standby sleep oscillator active stopped oscillator watchdog active stopped instruction execution stopped stopped interrupt functions active stopped registers and flags retained reset ram data retained retained option registers retained retained timer & counter active reset logic watchdog active reset i/o port b and serial port active high impedance, pull?s as defined in option register input port a active no pull-downs and inputs deactivated except if inpressleep = "1" lcd active stopped (display off) strobe output active active buzzer output active high impedance voltage level detector finishes ongoing measure, then stop stopped reset pin active active figure 5. mode transition diagram active halt instruction sleep bit write irq standby sleep reset=1 reset=0 reset=1 reset=1 reset
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 7 www.emmicroelectronic.com 4. power supply the em6617 is supplied by a single external power supply between v dd (vbat) and v ss (ground). a built-in voltage regulator generates vreg providing regulated voltage for the oscillator and the internal logic. the output drivers and the adc are supplied directly from the external supply vdd. a typical power connection configuration and the internal power connection is shown below. figure 6. typical power connection port b v dd port c vreg test vss qout qin + c min 100nf port a crystal em6617-1 reset strobe ain bin vref vgnd data clk figure 7. internal power connection ref. logic terminal vreg terminal vbat all pad input & output buffers, adc, svld, eeprom core logic, oscillator 1kohm
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 8 www.emmicroelectronic.com 5. reset figure 8. illustrates the reset structure of the em6617-1. there are six possible reset sources : (1) internal initial reset from the power on reset (por) circuitry. --> por (2) external reset from the reset terminal. --> system reset, reset cpu (3) external reset by simultaneous high/low inputs to port a. --> system reset, reset cpu (combinations are defined in the registers optinprsel1 and optinprsel2) (4) internal reset from the digital watchdog. --> system reset, reset cpu (5) internal reset from the oscillation detection circuit. --> system reset, reset cpu (6) internal reset when sleep mode is activated. --> system reset, reset cpu all reset sources activate the system reset and the reset cpu . the ?system reset delay? ensures that the system reset remains active long enough for all system functions to be reset (active for n system clock cycles). the ?cpu reset delay? ensures that the reset cpu remains active until the oscillator is in stable oscillation. as well as activating the system reset and the reset cpu, the por also resets all option registers and the sleep enable ( sleepen) latch. system reset and reset cpu do not reset the option registers nor the sleepen latch. reset state can be shown on strobe terminal by selecting strobeoutsel1,0 = 0 in optcandstr register. figure 8. reset structure system reset delay cpu reset delay enable a ctivate digital w atchdog o scillation detection r eset from p ort a input com bination reset pad sleep optinprsleep reset cpu inhibit oscillation detection inhibit digital w atchdog por po r to o ption registers & sleepen latch debounce sleep latch sleepen latch por internal d ata b us write reset read status write active read status ck[10] ck [ 1 ] ck[8] ck[1] ck[15] por analogue f ilte r
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 9 www.emmicroelectronic.com 5.1 oscillation detection circuit at power on, the voltage regulator starts to follow the supply voltage and triggers the power on reset circuitry, and thus the system reset. the cpu of the em6617 remains in the reset state for the ?cpu reset delay?, to allow the oscillator to stabilize after power up. the oscillator is disabled during sleep mode. so when waking up from sleep mode, the cpu of the em6617 remains in the reset state for the cpu reset delay, to allow the oscillator to stabilize. during this time, the oscillation detection circuit is inhibited. in active or standby modes, the oscillator detection circuit monitors the oscillator. if it stops for any reason, a system reset is generated. after clock restart the cpu waits for the cpu reset delay before executing the first instructions. the oscillation detection circuitry can be inhibited with bit nooscwd = 1 in register regsyscntl3. at power up, and after any system reset, the function is activated. the ?cpu reset delay? is 32768 system clocks ( ck[16] ) long. 5.2 reset terminal during active or standby modes the reset terminal has a debouncer to reject noise. reset must therefore be active for at least 16 ms (system clock = 32 khz). when canceling sleep mode, the debouncer is not active (no clock), however, reset passes through an analogue filter with a time constant of typical. 5s. in this case reset pin must be high for at least 10 s to generate a system reset. 5.3 input port a reset function by writing the optinprsel1 and optinprsel2 registers it is possible to choose any combination of port a input values to execute a system reset. the reset condition must be valid for at least 16ms (system clock = 32khz) in active and standby mode. optinprsleep selects the input port a reset function in sleep mode. if set to "1" the occurrence of the selected combination for input port a reset will immediately trigger a system reset (no debouncer) . reset combination selection ( inpreset) is done with registers optinprsel1 and optinprsel2. either an ?and? or an ?or? type port a combination can be chosen to generate the reset. 5.3.1 and-type reset function default setting(metal option). one or a combination of port a inputs will trigger a reset. following formula is applicable : inprespa = inprespa[0] inprespa[1] inprespa[2] inprespa[3] inpres1pa[n] inpres2pa[n] inprespa[n] 00v ss 0 1 pa[n] 1 0 not pa[n] 11v dd n = 0 to 3 i.e. ; - no reset if inprespa[n] = v ss . - don't care function on a single bit with its inprespa[n] = v dd . - always reset if inprespa[3:0] = 'b1111 figure 9. input port a reset structure 0 1 mux 2 3 1 0 v ss pa[3] pa[3] v dd bit [0] bit [1] bit [2] bit [3] inprespa inprespa[3] inpres2pa[3] inpres1pa[3] input port a reset bit[2] selection input port a reset bit[1] selection input port a reset bit[0] selection input port a reset bit[3] selection input reset from port a
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 10 www.emmicroelectronic.com 5.3.2 or -type reset function if wanted, needs to be chosen with the metal 1 option settings. any one of the port a inputs can trigger a reset. following formula is applicable : inprespa = inprespa[0] + inprespa[1] + inprespa[2] + inprespa[3] inpres1pa[n] inpres2pa[n] inprespa[n] 00v ss 0 1 pa[n] 1 0 not pa[n] 11v dd n = 0 to 3 i.e. ; - no reset if all inprespa[n] = v ss . - don't care function on a single bit with its inprespa[n] = vss. - always reset if any inprespa[3:0] = v dd 5.4 digital watchdog timer reset the digital watchdog is a simple, non-programmable, 2-bit timer, that counts on each rising edge of ck[1]. it will generate a system reset if it is not periodically cleared. the watchdog timer function can be inhibited by activating an inhibit digital watchdog bit ( nologicwd ) located in regsyscntl3 . at power up, and after any system reset, the watchdog timer is activated. if for any reason the cpu stops, then the watchdog timer can detect this situation and activate the system reset signal. this function can be used to detect program overrun, endless loops, etc. for normal operation, the watchdog timer must be reset periodically by software at least every 2.5 seconds (system clock = 32 khz), or a system reset signal is generated. the watchdog timer is reset by writing a ?1? to the wdreset bit in the timer. this resets the timer to zero and timer operation restarts immediately. when a ?0? is written to wdreset there is no effect. the watchdog timer operates also in the standby mode and thus, to avoid a system reset, one should not remain in standby mode for more than 2.5 seconds. from a system reset state, the watchdog timer will become active after 3.5 seconds. however, if the watchdog timer is influenced from other sources (i.e. prescaler reset), then it could become active after just 2.5 seconds. it is therefore recommended to use the prescaler irqhz1 interrupt to periodically reset the watchdog every second. it is possible to read the current status of the watchdog timer in regsyscntl2 . after watchdog reset, the counting sequence is (on each rising edge of ck[1]) : ?00?, ?01?, ?10?, ?11? { wdval1 wdval0 }. when going into the ?11? state, the watchdog reset will be active within ? second. the watchdog reset activates the system reset which in turn resets the watchdog. if the watchdog is inhibited it?s timer is reset and therefore always reads ?0?. figure 10. input port a reset structure 0 1 mux 2 3 1 0 v ss pa[3] pa[3] v dd bit [0] bit [1] bit [2] bit [3] inprespa inprespa[3] inpres2pa[3] inpres1pa[3] input port a reset bit[2] selection input port a reset bit[1] selection input port a reset bit[0] selection input port a reset bit[3] selection input reset from port a
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 11 www.emmicroelectronic.com table 5.4.1 watchdog timer register regsyscntl2 bit name reset r/w description 3 wdreset 0 r/w reset the watchdog 1 -> resets the logic watchdog 0 -> no action the read value is always '0' 2 sleepen 0 r/w see operating modes (sleep) 1 wdval1 0 r watchdog timer data ck[1] divided by 4 0 wdval0 0 r watchdog timer data ck[1] divided by 2 table 5.4.2 watchdog control register regsyscntl3 bit name reset r/w description 3 vref1/2sel 0 r/w reference selection for the adc 2 -- 0 r/w always reads 0 1 nooscwd 0 r/w no oscillation supervisor 0 nologicwd 0 r/w no logic watchdog 5.5 cpu state after reset reset initializes the cpu as shown in table 5.5.1 below. table 5.5.1 initial cpu value after reset. name bits symbol initial value program counter 0 12 pc0 hex 000 (as a result of jump 0) program counter 1 12 pc1 undefined program counter 2 12 pc2 undefined stack pointer 2 sp psp[0] selected index register 7 ix undefined carry flag 1 cy undefined zero flag 1 z undefined halt 1 halt 0 instruction register 16 ir jump 0 periphery registers 4 reg. see peripheral memory map
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 12 www.emmicroelectronic.com 6. oscillator and prescaler 6.1 oscillator a built-in crystal oscillator generates the system operating clock for the cpu and peripheral blocks, from an externally connected crystal (typically 32.768khz or 128khz depending of the metal opt. on table 19.1.6). the oscillator circuit is supplied by the regulated voltage, vreg. in sleep mode the oscillator is stopped. em?s special design techniques guarantee the low current consumption of this oscillator. the external impedance between the oscillator pads must be greater than 10mohm. connection of any other components to the two oscillator pads must be confirmed by em microelectronic-marin sa. 6.2 prescaler the prescaler consists of fifteen elements divider chain which delivers clock signals for the peripheral circuits such as timer/counter, buzzer, lcd voltage multiplier, debouncer and edge detectors, as well as generating prescaler interrupts. the input to the prescaler is the system clock signal. power on initializes to hex(0001). table 6.2.1 prescaler clock name definition function name 32 khz xtal function name 32 khz xtal system clock ck[16] 32768 hz system clock / 256 ck[8] 128 hz system clock / 2 ck[15] 16384 hz system clock / 512 ck[7] 64 hz system clock / 4 ck[14] 8192 hz system clock / 1024 ck[6] 32 hz system clock / 8 ck[13] 4096 hz system clock / 2048 ck[5] 16 hz system clock/ 16 ck[12] 2048 hz system clock / 4096 ck[4] 8 hz system clock / 32 ck[11] 1024 hz system clock / 8192 ck[3] 4 hz system clock / 64 ck[10] 512 hz system clock / 16384 ck[2] 2 hz system clock / 128 ck [9] 256 hz system clock / 32768 ck[1] 1 hz table 6.2.2 control of prescaler register regpresc bit name reset r/w description 3 pwmon 0 r/w see 10 bit counter 2 respresc 0 r/w write reset prescaler 1 -> resets the divider chain from ck[14] down to ck[2], sets ck[1]. 0 -> no action. the read value is always '0' 1 printsel 0 r/w interrupt select. 0 -> interrupt from ck[4] 1 -> interrupt from ck[6] 0 debsel 0 r/w debouncer clock select. 0 -> debouncer with ck[8] 1 -> debouncer with ck[11] or ck[14] with debsel = 1 one may choose either the ck[11] or ck[14] debouncer frequency by selecting the corresponding metal mask option. relative to 32khz the corresponding max. debouncer times are then 2 ms or 0.25 ms. for the metal mask selection refer to chapter 19.1.4. switching the printsel may generate an interrupt request. avoid it with maskirq32/8 = 0 selection during the switching operation. the prescaler contains 2 interrupt sources: - irq32/8 ; this is ck[6] or ck[4] positive edge interrupt, the selection is depending on bit printsel. - irqhz1 ; this is ck[1] positive edge interrupt there is no interrupt generation on reset. the first irqhz1 interrupt occurs 1 sec (32khz) after reset. figure 11. prescaler frequency timing system clock ck[16] ck[15] ck[14] horizontal scale change ck[2] ck[1] first positive edge of 1 hz clock is 1s after the falling reset edge prescaler reset
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 13 www.emmicroelectronic.com 7. input and output ports the em6617 has one input port and two bi-directional ports. 7.1 ports overview table 7.1.1 input and output ports overview port mode mask(m:) or register(r:) option function bit-wise multifunction on ports pa [3:0] input m: pull-up m: pull-down (default) r: pull enabling r: debouncer or direct input for irq requests and counter r: + or - for irq-edge and counter r: input reset combination -input -bit-wise interrupt request -software test variable conditional jump -pa[3],pa[0] input for the event counter -port a reset inputs pa[3] 10 bit event counter clock - pa[2] - - pa[1] - testvar2 pa[0] 10 bit event counter clock testvar1 pb [3:0] individual input or output r: cmos or nch. open drain output r: pull-down on input r: pull-up on input m: pull-up m: pull-down -input or output -pb[3] for the pwm output -pb[2:0] for the ck[11,16,12] output -tristate output pb[3] pwm output pb[2] ck[11] output pb[1] ck[16] output pb[0] ck[12] output pc [3:0] port-wise input / output r: cmos or nch. open drain output r: pull-down on input r: pull-up on input m: pull-up m: pull-down -input or output -tristate output pc[3] only in 28 pin package pc[2] only in 28 pin package pc[1] pc[0]
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 14 www.emmicroelectronic.com 7.2 port a the em6617 has one four bit general purpose cmos input port. the port a input can be read at any time, internal pull-up or pull-down resistors can be chosen. all selections concerning port a are bit-wise executable. i.e. pull-up on pa[2], pull-down on pa[0], positive irq edge on pa[0] but negative on pa[1], etc. in sleep mode the port a pull-up or pull-down resistors are turned off, and the inputs are deactivated except if the inpressleep bit in the option register optfselpb is set to 1. in this case the port a inputs are continuously monitored to match the input reset condition which will immediately wake the em6617 from sleep mode (all pull resistors remain). figure 12. input port a configuration intedgpa[n]=0 nodebintpa[n]=1 mask opt mpapu[n] irqpa[3:0] pa[n]terminal pa0, pa3 for 10-bit counter mask opt mpapd[n] debouncer p testvar ck[8] ck[11] or ck[14] db[3:0] nopullpa[n] vbat (v dd ) v ss input reset allowed when in sleep sleep 7.2.1 irq on port a for interrupt request generation (irq) one can choose direct or debouncer input and positive or negative edge irq triggering. with the debouncer selected ( optdebintpa ) the input must be stable for two rising edges of the selected debouncer clock ( regpresc ). this means a worst case of 16 ms (default) or 2 ms (0.25 ms by metal mask) with a system clock of 32 khz. either a positive or a negative edge on the port a inputs - after debouncer or not - can generate an interrupt request. this selection is done in the option register optintedgpa. all four bits of port a can provide an irq, each pin with its own interrupt mask bit in the regirqmask1 register. when an irq occurs, inspection of the regirq1 , regirq2 and regirq3 registers allows the interrupt to be identified and treated. at power on or after any reset the regirqmask1 is set to 0, thus disabling any input interrupt. a new interrupt is only stored with the next active edge after the corresponding interrupt mask is cleared. see also the interrupt chapter 13. it is recommended to mask the port a irq?s while one changes the selected irq edge. else one may generate a irq (software irq). i.e. pa[0] on ?0? then changing from positive to negative edge selection on pa[0] will immediately trigger an irqpa[0] if the irq was not masked.
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 15 www.emmicroelectronic.com 7.2.2 pull-up or pull-down each of the input port terminals pa[3:0] has a resistor integrated which can be used either as pull-up or pull- down resistor, depending on the selected metal mask options. see the port a metal mask chapter for details. the pull resistor can be inhibited using the nopullpa[n] bits in the register optnopullpa. table 7.2.1. pull-up or pull-down resistor on port a inputs option mask pull-up mpapu[n] option mask pull-down mpapd[n] nopullpa[n] value action no no x no pull-up, no pull-down no yes 0 no pull-up, pull-down no yes 1 no pull-up, no pull-down yes no 0 pull-up, no pull-down yes no 1 no pull-up , no pull-down yes yes x not allowed* * only pull-up or pull-down may be chosen on any port a terminal (one choice is excluding the other) 7.2.3 software test variables the port a terminals pa[2:0] are also used as input conditions for conditional software branches. independent of the optdebintpa and the optintedgpa. these cpu inputs always have a debouncer. - debounced pa[0] is connected to cpu testvar1. - debounced pa[1] is connected to cpu testvar2. - swb signal swbempty is connected to cpu testvar3 7.2.4 port a for 10-bit counter the pa[0] and pa[3] inputs can be used as the clock input terminal for the 10 bit counter in "event count" mode. as for the irq generation one can choose debouncer or direct input with the register optdebintpa and non- inverted or inverted input with the register optintedgpa . debouncer input is always recommended. 7.3 port a registers table 7.3.1 register regpa bit name reset r/w description 3 padata[3] - r* pa[3] input status 2 padata[2] - r* pa[2] input status 1 padata[1] - r* pa[1] input status 0 padata[0] - r* pa[0] input status *direct read on port a terminal table 7.3.2 register regirqmask1 bit name reset r/w description 3 maskirqpa[3] 0 r/w interrupt mask for pa[3] input 2 maskirqpa[2] 0 r/w interrupt mask for pa[2] input 1 maskirqpa[1] 0 r/w interrupt mask for pa[1] input 0 maskirqpa[0] 0 r/w interrupt mask for pa[0] input default "0" is: interrupt request masked, no new request stored with n=0?3
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 16 www.emmicroelectronic.com table 7.3.3 register regirq1 bit name reset r/w description 3 irqpa[3] 0 r/w* interrupt request on pa[3] 2 irqpa[2] 0 r/w* interrupt request on pa[2] 1 irqpa[1] 0 r/w* interrupt request on pa[1] 0 irqpa[0] 0 r/w* interrupt request on pa[0] w*; write "1" clears the bit, write "0" has no action, default "0" is: no interrupt request table 7.3.4 register optintedgpa bit name power on value r/w description 3 intedgpa[3] 0 r/w interrupt edge select for pa[3] 2 intedgpa[2] 0 r/w interrupt edge select for pa[2] 1 intedgpa[1] 0 r/w interrupt edge select for pa[1] 0 intedgpa[0] 0 r/w interrupt edge select for pa[0] default "0" is: positive edge selection table 7.3.5 register optdebintpa bit name power on value r/w description 3 nodebintpa[3] 0 r/w interrupt debounced for pa[3] 2 nodebintpa[2] 0 r/w interrupt debounced for pa[2] 1 nodebintpa[1] 0 r/w interrupt debounced for pa[1] 0 nodebintpa[0] 0 r/w interrupt debounced for pa[0] default "0" is: debounced inputs for interrupt generation table 7.3.6 register optnopullpa bit name power on value r/w description 3 nopull[3] 0 r/w pull-up/down selection on pa[3] 2 nopull[2] 0 r/w pull-up/down selection on pa[2] 1 nopull[1] 0 r/w pull-up/down selection on pa[1] 0 nopull[0] 0 r/w pull-up/down selection on pa[0] default "0" is: depending on mask selection
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 17 www.emmicroelectronic.com 7.4 port b the em6617 has one four bit general purpose i/o port. each bit can be configured individually by software for input/output, pull-up, pull-down and cmos or nch. open drain output type. the port outputs either data, frequency or pwm signals. 7.4.1 input / output mode each port b terminal is bit-wise bi-directional. the input or output mode on each port b terminal is set by writing the corresponding bit in the regpbcntl control register. to set for input (default), 0 is written to the corresponding bit of the regpbcntl register which results in a high impedance state for the output driver. the output mode is set by writing 1 in the control register, and consequently the output terminal follows the status of the bits in the regpbdata register. the port b terminal status can be read on address regpbdata even in output mode. be aware that the data read on port b is not necessary of the same value as the data stored on regpbdata register. see also figure 13 for details. figure 13. port b architecture open drain option register port b direction register port b data register internal data bus mux active pull-down i / o terminal pb[n] pbiocntl[n] pbdata[n] db[n] read read for pb[3:0] multiplexed output multiplexed output active multiplexed outputs are: pwm, ck[11], ck[16], ck[12] port b control active pull-up in nch. open drain mode read nopdpb[n] pull-down option register nchopdpb[n] mask option mpbpd[n] mask option mpbpd[n] 4
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 18 www.emmicroelectronic.com 7.4.2 pull-up or pull-down on each terminal of pb[3:0] an internal input pull-up (metal mask mpbpu[n]) or pull-down (metal mask mpbpd[n]) resistor can be connected per metal mask option. per default the two resistors are in place. in this case one can chose per software to have either a pull-up, a pull-down or no resistor. see below. for metal mask selection and available resistor values refer to 19.1.2. pull-down on : mpbpd[n] must be in place , and bit nopdpb [n] must be ?0? . pull-down off : mpbpd[n] is not in place, or if mpbpd[n] is in place nopdpb [n] = ?1? cuts off the pull-down. or selecting nchopdpb [n] = ?1? cuts off the pull-down. pull-up on : mpbpu[n] must be in place, and bit nchopdpb [n] must be ?1? , and (bit pbiocntl[n] = ?0? (input mode) or if pbiocntl[n] = ?1? while pbdata [n] = 1. ) pull-up off : mpbpu[n] is not in place, or if mpbpu[n] is in place nchopdpb [n] = ?0? cuts off the pull-up, or if mpbpu[n] is in place and if nchopdpb [n] = ?1? then pbdata [n] = 0 cuts the pull-up. never pull-up and pull-down can be active at the same time. for power saving one can switch off the port b pull resistors between two read phases. no cross current flows in the input amplifier while the port b is not read. the recommended order is : ? switch on the pull resistor. ? allow sufficient time - rc constant - for the pull resistor to drive the line to either v ss or v dd . ? read the port b ? switch off the pull resistor minimum time with current on the pull resistor is 4 system clock periods, if the rc time constant is lower than 1 system clock period. adding a nop instruction before reading moves the number of periods with current in the pull resistor to 6 and the maximum rc delay to 3 clock periods. 7.4.3 cmos or nch. output the port b outputs can be configured as either cmos or nch. open drain outputs. in cmos both logic ?1? and ?0? are driven out on the terminal. in nch. open drain only the logic ?0? is driven on the terminal, the logic ?1? value is defined by the internal pull-up resistor (if implemented), or high impedance. figure 14. cmos or nch. open drain outputs i / o term inal pb[n] mux active pull-up for high state pbdata[n] frequency outputs tri-state output buffer : high im pedance for data = 1 i / o term inal pb[n] mux pbdata[n] frequency outputs tri-state output buffer : closed data 1 cmos output nch. open drain output
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 19 www.emmicroelectronic.com 7.4.4 pwm and frequency output pb[3] can also be used to output the pwm (pulse width modulation) signal from the 10-bit counter, the ck[11], ck[16] as well as the ck[12] prescaler frequencies. -selecting pwm output on pb[3] with bit pwmon in register regpresc and running the counter. -selecting ck[11] output on pb[2] with bit pb1khzout in register optfselpb -selecting ck[16] output on pb[1] with bit pb32khzout in register optfselpb -selecting ck[12 ] output on pb[0] with bit pb2khzout in register optfselpb 7.5 port b registers table 7.5.1 register regpbdata bit name reset r/w description 3 pbdata[3] - r/w* pb[3] input and output 2 pbdata[2] - r/w* pb[2] input and output 1 pbdata[1] - r/w* pb[1] input and output 0 pbdata[0] - r/w* pb[0] input and output r* : direct read on pin (not the internal register read). table 7.5.2 register regpbcntl bit name reset r/w description 3 pbiocntl[3] 0 r/w i/o control for pb[3] 2 pbiocntl[2] 0 r/w i/o control for pb[2] 1 pbiocntl[1] 0 r/w i/o control for pb[1] 0 pbiocntl[0] 0 r/w i/o control for pb[0] default "0" is: port b in input mode table 7.5.3 register optfselpb bit name power on value r/w description 3 pb1khzout 0 r/w ck[11] output on pb[2] 2 pb32khzout 0 r/w ck[16] output on pb[1] 1 pb2khzout 0 r/w ck[12] output on pb[0] 0 inpressleep 0 r/w reset from sleep with port a default "0" is: no frequency output, port a input reset can not reset the sleep mode. table 7.5.4 option register optnopdpb bit name power on value r/w description 3 nopdpb[3] 0 r/w no pull-down on pb[3] 2 nopdpb[2] 0 r/w no pull-down on pb[2] 1 nopdpb[1] 0 r/w no pull-down on pb[1] 0 nopdpb[0] 0 r/w no pull-down on pb[0] default "0" is: pull-down on table 7.5.5 option register optnchopdpb bit name power on value r/w description 3 nchopdpb[3] 0 r/w n-channel open drain on pb[3] 2 nchopdpb[2] 0 r/w n-channel open drain on pb[2] 1 nchopdpb[1] 0 r/w n-channel open drain on pb[1] 0 nchopdpb[0] 0 r/w n-channel open drain on pb[0] default "0" is: cmos on pb[3..0] 7.6 port c
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 20 www.emmicroelectronic.com the em6617 has one globally configurable input / output port which is 4 bit wide (only two bits are available for 24 pin packages). input or output mode can be set by writing the bit pciocntl in regpccntl register. ?0? = input mode (default), ?1? = output mode. the regpcdata register is used to write output data on port c. input data is read directly on the input terminal and put onto the internal data bus. it is not stored in the regpcdata register. the port c terminal status can be read on address regpcdata even in output mode. be aware that the data read on port c is not necessary of the same value as the data stored on regpcdata register. at any reset, the regpccntl register is cleared, thus setting the port in input mode. during sleep mode, pc[3:0] are in high impedance state. the port c is globally configurable to act as cmos or nch. open drain port , selectable in optpcandstr register ( nchopdpc bit). 7.6.1 pull-up or pull-down on each terminal of pc[3:0] an internal input pull-up (metal mask mpcpu[n]) or pull-down (metal mask mpcpd[n]) resistor can be connected per metal mask option. per default the two resistors are in place. in this case one can chose per software to have either a pull-up, a pull-down or no resistor. figure 15. port c architecture open drain option register port c direction register port c data register internal data bus active pull-down i / o terminal pc[n] pciocntl pcdata[n] db[n] read read for pc[3:0] port c control active pull-up in nch. open drain mode read nopdpc pull-down option register nchopdpc mask option mpcpd[n] mask option mpcpd[n] 4
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 21 www.emmicroelectronic.com for metal mask selection and available resistor values refer to chapter 19.1.3. pull-down on : mpcpd[n] must be in place , and bit nopdpc [n] must be ?0? . pull-down off : mpcpd[n] is not in place, or if mpcpd[n] is in place nopdpc [n] = ?1? cuts off the pull-down. or selecting nchopdpc [n] = ?1? cuts off the pull-down. pull-up on : mpcpu[n] must be in place, and bit nchopdpc [n] must be ?1? , and (bit pciocntl = ?0? (input mode) or if pbiocntl = ?1? while pcdata [n] = 1. ) pull-up off : mpcpu[n] is not in place, or if mpcpu[n] is in place nchopdpc [n] = ?0? cuts off the pull-up, or if mpcpu[n] is in place and if nchopdpc [n] = ?1? then pcdata [n] = 0 cuts the pull-up. never pull-up and pull-down can be active at the same time. for power saving one can switch off the port c pull resistors between two read phases. no cross current flows in the input amplifier while the port c is not read. the recommended order is : ? switch on the pull resistor. ? allow sufficient time - rc constant - for the pull resistor to drive the line to either v ss or v dd . ? read the port c ? switch off the pull resistor minimum time with current on the pull resistor is 4 system clock periods, if the rc time constant is lower than 1 system clock period. adding a nop instruction before reading moves the number of periods with current in the pull resistor to 6 and the maximum rc delay to 3 clock periods. 7.6.2 cmos or nch. output the port c outputs can be configured as either cmos or nch. open drain outputs. in cmos both logic ?1? and ?0? are driven out on the terminal. in nch. open drain only the logic ?0? is driven on the terminal, the logic ?1? value is defined by the internal pull-up resistor (if implemented), or high impedance. in cmos output mode the pad can be driven high or low. pull-ups and pull-downs are not active. in cmos input mode, if the corresponding metal option is in place (default), one can choose to have an internal pull-down resistor by setting to ?1? the bit nopdpc in optpcandstr register (default pull-down). in n-channel open drain mode, if the corresponding metal option is in place (default), one always has the pull- up resistor active except if the port is in output mode and drives a "0" (regpccntl= "1", regpbdata[n]= "0") the pull-down resistor is always off in nch. open drain mode. pull-downs in cmos input mode and weak pull-ups in nch. open drain mode are port-wise configurable with the register settings. the metal mask options to selectively connect or disconnect pull-up or pull-down resistors can be different for each port c terminal. 7.7 port c registers table 7.7.1 register regpcdata figure 16. cmos or nch. open drain outputs i / o term inal pc[n] mux active pull-up for high state pc data[n] tri-state output buffer : high im pedance for data = 1 i / o term inal pc[n] pcdata[n] tri-state output buffer : closed 1 cmos output nch. open drain output
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 22 www.emmicroelectronic.com bit name reset r/w description 3 pcdata[3] - r/w* pc[3] input and output 2 pcdata[2] - r/w* pc[2] input and output 1 pcdata[1] - r/w* pc[1] input and output 0 pcdata[0] - r/w* pc[0] input and output r* : direct read on port c terminal (not the internal register read). table 7.7.2 register regpccntl bit name reset r/w description 3 -- 0 r always reads 0 2 -- 0 r always reads 0 1 -- 0 r always reads 0 0 pciocntl 0 r/w i/o control for port c default "0" is : port c in input mode table 7.7.3 option register optpcandstr bit name power on value r/w description 3 nopdpc 0 r/w no pull-down on port c 2 nchopdpc 0 r/w n-channel open drain port c 1 strobeoutsel1 0 r/w strobe output selection 0 strobeoutsel0 0 r/w strobe output selection default "0" is : pull-down on, cmos on pc[3:0]
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 23 www.emmicroelectronic.com 8. 10-bit counter the em6617 has a built-in universal cyclic counter. it can be configured as 10, 8, 6 or 4-bit counter. if 10-bits are selected we call that full bit counting, if 8, 6 or 4-bits are selected we call that limited bit counting. the counter works in up- or down count mode. eight clocks can be used as the input clock source, six of them are derived prescaler frequencies and two are coming from the input pads pa[0] and pa[3]. in this case the counter can be used as an event counter. the counter generates an interrupt request irqcount0 every time it reaches 0 in down count mode or 3ff in up count mode. another interrupt request irqcntcomp is generated in compare mode whenever the counter value matches the compare data register value. each of this interrupt requests can be masked (default). see section 13 for more information about the interrupt handling. a 10-bit data register creg[9:0] is used to initialize the counter at a specific value (load into count[9:0] ). this data register ( creg[9:0] ) is also used to compare its value against count[9:0] for equivalence. a pulse-width-modulation signal (pwm) can be generated and output on port b terminal pb[3]. 8.1 full and limited bit counting in full bit counting mode the counter uses its maximum of 10-bits length (default ). with the bitsel[1,0] bits in register regcdatah one can lower the counter length, for irq generation, to 8, 6 or 4 bits. this means that actually the counter always uses all the 10-bits, but irqcount0 generation is only performed on the number of selected bits. the unused counter bits may or may not be taken into account for the irqcomp generation depending on bit selintfull . refer to chapter 8.4. figure 17. 10-bit counter block diagram en comparator ck up/down up/down counter en evcount counter read register regcdatal, m, h (count[9:0]) regcdatal, m, h (creg[9:0]) load irqcntcomp pwm irqcount0 data register db[3:0] pa[0] ck[15] ck[12] ck[10] ck[8] ck[4] ck[1] pa[3] ck mux regccntl1, 2 countfsel2...0 up/down start evcount load encomp table 7.7.1. counter length selection bitsel[1] bitsel[0 ] counter length 0 0 10-bit 018-bit 106-bit 114-bit
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 24 www.emmicroelectronic.com 8.2 frequency select and up/down counting 8 different input clocks can be selected to drive the counter. the selection is done with bits countfsel2?0 in register regccntl1 . 6 of this input clocks are coming from the prescaler. the maximum prescaler clock frequency for the counter is half the system clock and the lowest is 1hz. therefore a complete counter roll over can take as much as 17.07 minutes (1hz clock, 10 bit length) or as little as 977 s (ck[15], 4 bit length). the irqcount0 , generated at each roll over, can be used for time bases, measurements length definitions, input polling, wake up from halt mode, etc. the irqcount0 and irqcomp are generated with the system clock ck[16] rising edge. irqcount0 condition in up count mode is : reaching 3ff if 10-bit counter length (or ff, 3f, f in 8, 6, 4-bit counter length). in down count mode the condition is reaching ?0?. the non-selected bits are ?don?t care?. for irqcomp refer to section 8.4. note: the prescaler and the microprocessor clock?s are usually non-synchronous, therefore time bases generated are max. n, min. n-1 clock cycles long (n being the selected counter start value in count down mode). however the prescaler clock can be synchronized with p commands using for instance the prescaler reset function. the two remaining clock sources are coming from the pa[0] or pa[3] terminals. refer to the figure 12 on page 14 for details. both sources can be either debounced (ck[11] or ck[8]) or direct inputs, the input polarity can also be chosen. the output after the debouncer polarity selector is named pa3 , pa0 respectively. for the debouncer and input polarity selection refer to chapter 7.2.4. in the case of port a input clock without debouncer, the counting clock frequency will be half the input clock on port a. the counter advances on every odd numbered port a negative edge ( divided clock is high level ). irqcount0 and irqcomp will be generated on the rising pa3 or pa0 input clock edge. in this condition the em6617 is able to count with a higher clock rate as the internal system clock (hi-frequency input). maximum port a input frequency is limited to 200khz. if higher frequencies are needed, please contact em-marin. in both, up or down count (default) mode, the counter is cyclic. the counting direction is chosen in register regccntl1 bit up/down (default ?0? is down count). the counter increases or decreases its value with each positive clock edge of the selected input clock source. start up synchronization is necessary because one can not always know the clock status when enabling the counter. with evcount=0, the counter will only start on the next positive clock edge after a previously latched negative edge, while the start bit was already set to ?1?. this synchronization is done differently if event count mode (bit evcount ) is chosen. refer also to figure 19. internal clock synchronization. figure 18. counter clock timing prescaler frequencies or debounced port a clocks non-debounced port a clocks (system clock independent) system clock prescaler clock counting counter irq?s divided clock system clock port a clock counting c ounter ir q ?s
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 25 www.emmicroelectronic.com 8.3 event counting the counter can be used in a special event count mode where a certain number of events (clocks) on the pa[0] or pa[3] input are counted. in this mode the counting will start directly on the next active clock edge on the selected port a input. the event count mode is switched on by setting bit evcount in the register regccntl2 to ?1?.pa[3] and pa[0] inputs can be inverted depending on register optintedgpa and should be debounced. the debouncer is switched on in register optdebintpa bits nodebintpa[3,0]=0. its frequency depends on the bit debsel from register regpresc setting. the inversion of the internal clock signal derived from pa[3] or pa[0] is active with intedgpa[3] respectively intedgpa[0] equal to 1. refer also to figure 12 for internal clock signal generation. 8.4 compare function a previously loaded register value ( creg[9:0] ) can be compared against the actual counter value ( count[9:0] ) . if the two are matching (equality) then an interrupt ( irqcomp ) is generated. the compare function is switched on with the bit encomp in the register regccntl2 . with encomp = 0 no irqcomp is generated. starting the counter with the same value as the compare register is possible, no irq is generated on start. full or limited bit compare are possible, defined by bit selintfull in register regsyscntl1 . encomp must be written after a load operation ( load = 1). every load operation resets the bit encomp. full bit compare function. bit selintfull is set to ?1?. the function behaves as described above independent of the selected counter length. limited bit counting together with full bit compare can be used to generate a certain amount of irqcount0 interrupts until the counter generates the irqcomp interrupt. with pwmon =?1? the counter would have automatically stopped after the irqcomp, with pwmon =?0? it will continue until the software stops it. encomp must be cleared before setting selintfull and before starting the counter again. be careful, pwmon also redefines the port b pb[3] output data.(refer to section 8.5). limited bit compare with the bit selintfull set to ?0? (default) the compare function will only take as many bits into account as defined by the counter length selection bitsel[1:0] (see chapter 8.1). 8.5 pulse width modulation (pwm) the pwm generator uses the behavior of the compare function (see above) so encomp must be set to activate the pwm function.. at each roll over or compare match the pwm state - which is output on port b pb[3] - will toggle. the start value on pb[3] is forced while encomp is 0 the value is depending on the up or down count mode. every counter value load operation resets the bit encomp and therefore the pwm start value is reinstalled. setting pwmon to ?1? in register regpresc routes the counter pwm output to port b terminal pb[3]. insure that pb[3] is set to output mode . refer to section 7.4 for the port b setup. the pwm signal generation is independent of the limited or full bit compare selection bit selintfull. however if selintfull = 1 (full) and the counter compare function is limited to lower than 10 bits one can generate a predefined number of output pulses. in this case, the number of output pulses is defined by the value of the unused counter bits. it will count from the start value until the irqcomp match. one must not use a compare value of hex 0 in up count mode nor a value of hex 3ff (or ff,3f, f if limited bit compare) in down count mode. figure 19. internal clock synchronization ck start count[9:0 ] + / - 1 + / - 1 evcount = 0 ck start evcount = 0 ck start evcount = 1 ck start evcount = 1 count[9:0 ] + / - 1 count[9:0 ] count[9:0 ]
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 26 www.emmicroelectronic.com for instance, loading the counter in up count mode with hex 000 and the comparator with hex c52 which will be identified as : - bits[11:10] are limiting the counter to limits to 4 bits length, =03 (bitsel[1,0]) - bits [9:4] are the unused counter bits = hex 05 (bin 000101), (number of pwm pulses) - bits [3:0] (comparator value = 2). (length of pwm pulse) thus after 5 pwm-pulses of 2 clocks cycles length the counter generates an irqcomp and stops. the same example with selintfull=0 (limited bit compare) will produce an unlimited number of pwm at a length of 2 clock cycles. 8.5.1 how the pwm generator works. for up count mode ; setting the counter in up count and pwm mode the pb[3] pwm output is defined to be 0 ( encomp =0 forces the pwm output to 0 in upcount mode, 1 in downcount). each roll over will set the output to ?1? and each compare match will set it back to ?0?. the compare match for pwm always only works on the defined counter length. this, independent of the selintfull setting which is valid only for the irq generation. refer also to the compare setup in chapter 8.4. in above example the pwm starts counting up on hex 0, 2 cycles later compare match -> pwm to ?0?, 14 cycles later roll over -> pwm to ?1? 2 cycles later compare match -> pwm to ?0? , etc. until the completion of the 5 pulses. the normal irq generation remains on during pwm output. if no irq?s are wanted, the corresponding masks need to be set. in down count mode everything is inverted. the pwm output starts with the ?1? value. each roll over will set the output to ?0? and each compare match will set it back to ?1?. for limited pulse generation one must load the complementary pulse number value. i.e. for 5 pulses counting on 4 bits load bits[9 :4] with hex 3a (bin 111010). 8.5.2 pwm characteristics pwm resolution is : 10bits (1024 steps), 8bits (256 steps), 6bits (64 steps) or 4 bits (16 steps) the minimal signal period is : 16 (4-bit) x fmax* -> 16 x 1/ck[15] -> 977 s (32 khz) the maximum signal period is : 1024 x fmin* -> 1024 x 1/ck[1] -> 1024 s (32 khz) the minimal pulse width is : 1 bit -> 1 x 1/ck[15] -> 61 s (32 khz) * this values are for fmax or fmin derived from the internal system clock (32khz). much shorter (and longer) pwm pulses can be achieved by using the port a as frequency input. one must not use a compare value of hex 0 in up count mode nor a value of hex 3ff (or ff,3f, f if limited bit compare) in downcount mode. figure 20. pwm output in up count mode data+2 data+1 data-1 data ... 001 000 03f 03e pwm output irqcomp irqcount0 compare roll-over count[9 :0] clock figure 21. pwm output in down count mode data-2 data-1 data+1 data ... 3f e 3ff 000 001 pwm output irqcomp irqcount0 compare roll-over count[9 :0] clock
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 27 www.emmicroelectronic.com 8.6 counter setup regcdatal[3:0], regcdatam[3:0], regcdatah[1:0] are used to store the initial count value called creg[9:0] which is written into the count register bits count[9:0] when writing the bit load to ?1? in regccntl2 . this bit is automatically reset thereafter. the counter value count[9:0] can be read out at any time, except when using non-debounced high frequency port a input clock. to maintain data integrity the lower nibble count[3:0] must always be read first. the shcount[9:4] values are shadow registers to the counter. to keep the data integrity during a counter read operation (3 reads), the counter values [9:4] are copied into these registers with the read of the count[3:0] register. if using non-debounced high frequency port a input the counter must be stopped while reading the count[3:0] value to maintain the data integrity. in down count mode an interrupt request irqcount0 is generated when the counter reaches 0. in up count mode, an interrupt request is generated when the counter reaches 3ff (or ff,3f,f if limited bit counting). never an interrupt request is generated by loading a value into the counter register. when the counter is programmed from up into down mode or vice versa, the counter value count[9:0] gets inverted. as a consequence, the initial value of the counter must be programmed after the up/down selection. loading the counter with hex 000 is equivalent to writing stop mode, the start bit is reset, no interrupt request is generated. how to use the counter; if pwm output is required one has to put the port b[3] in output mode and set pwmon=1 in step 5. 1st, set the counter into stop mode ( start =0). 2nd, select the frequency and up- or down count mode in regccntl1. 3rd, write the data registers regcdatal, regcdatam, regcdatah (counter start value and length) 4th, load the counter, load =1, and choose the mode. ( evcount , encomp =0) 5th, select bits pwmon in regpresc and selintfull in regsyscntl1 6th, if compare mode desired , then write regcdatal, regcdatam, regcdatah (compare value) 7th, set bit start and select encomp in regccntl2 8.7 10-bit counter registers table 8.7.1 register regccntl1 bit name reset r/w description 3 up/down 0 r/w up or down counting 2 countfsel2 0 r/w input clock selection 1 countfsel1 0 r/w input clock selection 0 countfsel0 0 r/w input clock selection default : pa0 ,selected as input clock, down counting table 8.7.2 counter input frequency selection with countfsel[2..0] countfsel2 countfsel1 countfsel0 clock source selection 0 0 0 port a pa[0] 0 0 1 prescaler ck[15] 0 1 0 prescaler ck[12] 0 1 1 prescaler ck[10] 1 0 0 prescaler ck[8] 1 0 1 prescaler ck[4] 1 1 0 prescaler ck[1] 1 1 1 port a pa[3]
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 28 www.emmicroelectronic.com table 8.7.3 register regccntl2 bit name reset r/w description 3 start 0 r/w start/stop control 2 evcount 0 r/w event counter enable 1 encomp 0 r/w enable comparator 0 load 0 r/w write: load counter register; read: always 0 default : stop, no event count, no comparator, no load table 8.7.4 register regsyscntl1 bit name reset r/w description 3 inten 0 r/w general interrupt enable 2 sleep 0 r/w sleep mode 1 selintfull 0 r/w compare interrupt select 0 chtmdis 0 r/w for em test only default : interrupt on limited bit compare table 8.7.5 register regcdatal, counter/compare low data nibble bit name reset r/w description 3 creg[3] 0 w counter data bit 3 2 creg[2] 0 w counter data bit 2 1 creg[1] 0 w counter data bit 1 0 creg[0] 0 w counter data bit 0 3 count[3] 0 r data register bit 3 2 count[2] 0 r data register bit 2 1 count[1] 0 r data register bit 1 0 count[0] 0 r data register bit 0 table 8.7.6 register regcdatam, counter/compare middle data nibble bit name reset r/w description 3 creg[7] 0 w counter data bit 7 2 creg[6] 0 w counter data bit 6 1 creg[5] 0 w counter data bit 5 0 creg[4] 0 w counter data bit 4 3 shcount[7] 0 r data register bit 7 2 shcount[6] 0 r data register bit 6 1 shcount[5] 0 r data register bit 5 0 shcount[4] 0 r data register bit 4 table 8.7.7 register regcdatah, counter/compare high data nibble bit name reset r/w description 3 bitsel[1] 0 r/w bit select for limited bit count/compare 2 bitsel[0] 0 r/w bit select for limited bit count/compare 1 creg[9] 0 w counter data bit 9 0 creg[8] 0 w counter data bit 8 1 shcount[9] 0 r data register bit 9 0 shcount[8] 0 r data register bit 8 table 8.7.8 counter length selection bitsel[1] bitsel[0 ] counter length 0 0 10-bit 018-bit 106-bit 114-bit
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 29 www.emmicroelectronic.com 9. serial (output) write buffer - swb the em6617 has simple serial write buffer which outputs serial data and serial clock. serial write buffer clock frequency is selected by bits swbfsel0 and swbfsel1 in regswbcntl register. the possible values are 1khz (default), 2khz, 8khz or 16khz. the signal testvar[3], which is used by the processor to make conditional jumps, indicates "transmission finished" in automatic send mode or "swbbuffer empty" in interactive send mode. in interactive mode, testvar[3] is equivalent to the interrupt request flags stored in regirq[i] registers : it permits to recognize the interrupt source. (see also the interrupt handling section 13 for further information). to serve the "swbbuffer empty " interrupt request, one only has to make a conditional jump on testvar[3]. the swb data is output on the rising edge of the clock. consequently, on the receiver side the serial data can be evaluated on falling edge of the serial clock edge. normally the clock and the data output terminals are always driven to ?0? outside a swb data transfer. with a metal option one can put the data output, the clock output or both into a high impedance state outside of a swb transfer. refer to 19.1.4 for the mask settings. the timing going into high impedance state into swb transfer and back into high impedance is depending on the selected mode, interactive or automatic. figure 22. serial write buffer architecture size[5:0] a ddr. counter ram swb buffe r swbauto swbstart swbfsel0,1 control lo g ic shift re g iste r db [ 3:0 ] clk mux swb clock swb data testvar3 swb buffer re g iste r irq ( onl y in interactive swb has two operational modes, automatic mode and interactive mode. 9.1 swb automatic send mode automatic mode enables a buffer on a predefined length to be sent at high transmission speeds up to ck[15] (16khz). in this mode user prepares all the data to be sent (minimum 8 bits, maximum 256 bits) in the ram. the user then selects the clock speed, sets the number of data nibbles to be sent, selects automatic transmission mode ( swbauto bit set to 1) and enters standby mode by executing a halt instruction. once the halt instruction is activated the swb peripheral module sends the data in register regswbuff followed by the data in the ram starting at address 00 up to the address specified by the bits size[5:0] located in the regswbsizel, regswbsizeh registers.
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 30 www.emmicroelectronic.com during automatic transmission the general inten bit is disabled automatically to prevent other interrupts to reset the standby mode. at the end of automatic transmission em6617 leaves standby mode ( inten is automatically enabled) and sets testvar[3] high. testvar[3] = 1 is signaling swb transmission is terminated. as soon as swbauto is high, the general inten flag is disabled until the swbauto goes back low. after automatic swb transmission inten bit becomes high. although set to 1 via the halt instruction the bit inten is disabled throughout the whole swb automatic transmission. it resumes to 1 at the end of transmission . the data to be sent must be prepared in the following order: first nibble to be sent must be written in the regswbuff register . the other nibbles must be loaded in the ram from address 00 (second nibble at adr.00, third at adr.01,...) up to the address with last nibble of data to be send = " size " address. max. address space for swb is 3e (" size " 3e hex) what gives together with regswbuff up to 64 nibbles (256 bits) of data to be sent. the minimum amount of data bits one can send in automatic swb mode is 8 . in this case the last ram address to be sent is 00 ("size" = 00). once data are written into the ram and into the regswbuff, the user has to load the " size " (adr. of the last nibble to be send - bits size[5 :0]) into the regswbsizel and regswbsizeh register, later register together with swbauto =1 bit. now everything is ready for automatic serial transmission. to start the transmission one has to put the em6617 in standby mode with the halt instruction. when transmission is finished testvar[3] (can be used for conditional jumps) becomes active high, the bit swbauto is cleared , the processor is leaving the standby mode and inten is switched on. the processor now starts to execute the first instruction placed after the halt instruction (for instance write of regswbuff register to clear testvar[3]), except if there was a irq during the serial transmission. in this case the cpu will go directly in the interrupt routine. testvar[3] stays high until regswbuff is rewritten. before starting a second swb action this bit must be cleared by performing a dummy write on regswbuff address. figure 23. automatic serial write buffer transmission because the data in the ram are still present one can start transmitting the same data once again only by recharging the regswbuff , regswbsizel and regswbsizeh register together with swbauto bit and putting the em6617 in halt mode. this will start a new transmission. using the swb high impedance mask option in automatic mode. as soon as one goes into halt mode the swb outputs go to ?0? and swb transfer starts. at the end of the transfer the swb outputs go immediately back into high impedance state.
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 31 www.emmicroelectronic.com 9.2 swb interactive send mode in interactive swb mode the reloading of the data transmission register regswbuff is performed by the application program. this means that it is possible to have an unlimited length transmission data stream. however, since the application program is responsible for reloading the data a continuous data stream can only be achieved at ck[11] or ck[12] (1 khz or 2 khz) transmission speeds. for the higher transmission speeds a series of writes must be programmed and the serial output clock will not be continuous. serial transmission using the interactive mode is detailed in figure 24. programming of the swb in interactive is achieved in the following manner: select the transmission clock speed using the bits swbfsel1 and swbfsel0 in the regswbcntl register. load the first nibble of data into the swb data register regswbuff start serial transmission by selecting the bit swbstart in the register regswbsizeh register. once the data has been transferred into the serial transmission register a non maskable interrupt (swbempty) is generated and testvar[3] goes high. the cpu goes in the interrupt routine, with the jpv3 as first instruction in the routine one can immediately jump to the swb update routine to load the next nibble to be transmitted into the regswbuff register. if this reload is performed before all the serial data is shifted out then the next nibble is automatically transmitted. this is only possible at the transmission speeds of ck[11] or ck[12] due to the number of instructions required to reload the register. at the higher transmission speeds of ck[14] or ck[15] (8 khz or 16 khz) the application must restart the serial transmission by writing the swbstart in the regswbsizeh register after writing the next nibble to the regswbuff register. each time the regswbuff register is written the "swbbuffer empty interrupt" and testvar[3 ] are cleared to "0". for proper operation the regswbuff register must be written before the serial clock drops to low during sending the last bit (msb) of the previous data. figure 24 interactive serial write buffer transmission after loading the last nibble in the regswbuff register a new interrupt is generated when this data is transferred to an intermediate shift register. precaution must be made in this case because the swb will give repetitive interrupts until the last data is sent out completely and the swbstart bit goes low automatically. one possibility to overcome this is to check in the interrupt subroutine that the swbstart bit went low before exiting interrupt. be careful because if swbstar t bit is cleared by software, transmission is stopped immediately. using the swb high impedance mask option in interactive mode. as soon as one sets the start bit the swb outputs go to ?0? and swb transfer starts. at the end of the transfer the swb outputs go immediately back into high impedance state.
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 32 www.emmicroelectronic.com 9.3 swb registers table 9.3.1 swb clock selection register regswbcntl bit name reset r/w description 3-- 2-- 1 swbfsel1 0 r/w swb clock selection 0 swbfsel0 0 r/w swb clock selection table 9.3.2 serial write buffer clock selection swb clock output swbfsel1 swbfsel0 1024 hz 0 0 2048 hz 0 1 8192 hz 1 0 16384 hz 1 1 table 9.3.3 swb buffer register regswbuff bit name reset r/w description 3 buff[3] 1 r/w swb buffer bit 3 2 buff[2] 1 r/w swb buffer bit 2 1 buff[1] 1 r/w swb buffer bit 1 0 buff[0] 1 r/w swb buffer bit 0 table 9.3.4 swb low size register regswbsizel bit name reset r/w description 3 size[3] 0 r/w auto mode buffer size bit3 2 size[2] 0 r/w auto mode buffer size bit2 1 size[1] 0 r/w auto mode buffer size bit1 0 size[0] 0 r/w auto mode buffer size bit0 table 9.3.5 swb high size register regswbsizeh bit name reset r/w description 3 swbauto 0 r/w swb automatic mode select 2 swbstart 0 r/w swb start interactive mode 1 size[5] 0 r/w auto mode buffer size bit5 0 size[4] 0 r/w auto mode buffer size bit4
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 33 www.emmicroelectronic.com 10. 2-channel adc (8-bit digital converter) the em6617 contains one 8-bit adc with 2 independent input channels. in addition one can choose also vref and vgnd as adc input. the control logic uses an internal analogue multiplexor to select the channel to be converted. when data conversion is complete, indicated by a data valid signal, the control logic saves the converted value in the regadcdatah and the shadow low registers. regadcdatal registers is updated when reading the regadcdatah register. at the end of conversion an interrupt irqadc is sent to the p. the architecture of the adc is illustrated in figure 25. the adc 8 bit contains an inherent sample and hold function : the input voltage is sampled during acquisition phase (2 clock cycles) and is held until the end of conversion. total conversion time is 10 clock cycles. figure 25. adc 8 bit architecture 8-bit charge redistribution adc core 4-bit internal data bus rdhigh irq rdlow regadcdatal rdlow shadow low regadcdatah rdhigh 4 svref1/2sel start convert channel select vgnd vrefint vref1 vref2 vref vin convert data[7 :1] data valid ain bin 0 3 1 2 8 2 vdd vgnd v dd v ss irqadc ck[16] control logic external figure 26. adc 8 bit timing start convert adc clock 1 9 8 7 6 5 4 3 2 10 data valid re-sampling 8 clocks conversion sample&hold irqadc
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 34 www.emmicroelectronic.com the adc is of bipolar type : positive or negative input signal referred to the virtual ground point vgnd are converted. the virtual ground point vgnd is ideally on (vss + vbat)/2 voltage level and must be supplied from external circuitry. the positive reference voltage vref referred to the virtual ground point vgnd defines the input voltage range without overflow (full scale conversion : +/- vref referred to vgnd) data format is the following : msb adcdata[7] is a sign bit indicating if input signal vin is higher than virtual ground (adcdata[7] = ?1?) or lower (adcdata[7] = ?0?). for negative input signal the lsb?s are coded in 1? complement. for instance : vin = +vref -> adcdata[7:0] = ?1 1111111? +127 vin = +vref/ 2 -> adcdata[7:0] = ?1 0111111? +63 vin = vgnd -> adcdata[7:0] = ?1 0000000? +0 vin = -vref/ 2 -> adcdata[7:0] = ?0 1000000? -63 vin = -vref -> adcdata[7:0] = ?0 0000000? -127 the input channel to be converted is selected by channelsela and channelselb bits in regadccntl register. the default channel selection is vref as adc input. setting to ?1? the vref1/2sel bit in regsyscntl 3 selects the internal v dd (vref2 input) as the reference voltage. by default, vref is defined by the external vref pad (vref1 input). the adc has two working modes (continuous or single mode) selected by the single bit (single = ?0? --> continuous mode ; single = ?1? --> single mode). 10.1 continuous mode the conversion process is activated by setting to ?1? the startconvert bit. the selected channel is cyclically (3.2khz) converted and the result is stored in regadcdatal and regadcdatah registers. when the startconvert bit is set to ?0?, the process runs until completion of the current 10 clock cycles and then stops. after each completion, an interrupt request irqadc is generated. this interrupt request can be masked (default) ( maskirqadc bit). see also the interrupt handling section 13 for further information. one always needs to read regadcdatah first , this read updates the regadcdatal value (shadow register). 10.2 single mode setting to ?1? the startconvert bit activates 1 conversion of the selected channel. at the end of the conversion, the startconvert bit is automatically cleared and irqadc is generated. data are available in regadcdatal and regadcdatah registers. one always needs to read regadcdatah first , this read updates the regadcdatal value (shadow register).
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 35 www.emmicroelectronic.com 10.3 2-channel adc registers table 10.3.1 adc control register regadccntl bit name reset r/w description 3 startconvert 0 w start conversion 3 adcbusy r adc busy flag 2 single 0 r/w single mode 1 channelselb 0 r/w input channel selection 0 channelsela 0 r/w input channel selection default : continuous mode, vref pad as input channel table 10.3.2 input channel selection channelsela channelselb input channel 0 0 vref pad 01 bin 10 ain 1 1 vgnd table 10.3.3 adc data low register regadcdatal bit name reset r/w description 3 adcdata[3] 0 r/w adc data bit 3 2 adcdata[2] 0 r/w adc data bit 2 1 adcdata[1] 0 r/w adc data bit 1 0 adcdata[0] 0 r/w adc data bit 0 table 10.3.4 adc data high register regadcdatah bit name reset r/w description 3 adcdata[7] 0 r/w adc data bit 7 2 adcdata[6] 0 r/w adc data bit 6 1 adcdata[5] 0 r/w adc data bit 5 0 adcdata[4] 0 r/w adc data bit 4 table 10.3.5 control register regsyscntl3 bit name reset r/w description 3 vref1/2sel 0 reference voltage selection for adc 2-- 1 nooscwd 0 r/w no oscillator watchdog 0 nologicwd 0 r/w no logic watchdog default : external vref for the voltage reference
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 36 www.emmicroelectronic.com 11. eeprom ( 64 8 bit ) the eeprom addressing is indirect using 6 bits (64 addresses) defined in regeepadr and regeepcntl registers. the eeprom consist of 2 pages 32x8bit each, address eepadr[4 :0] . the page is selected in the regeepcntl register bit eepage . so the user can address the eeprom as it would be one block of 64x8 bit. any access to the eeprom is done in two phases. 1 st , one needs to define the address location. 2 nd , one needs to start the desired action, read or write. refer to the examples below.. how to read data from eeprom : 1 st inst. : write eeprom address (4 low bits) in regeepaddr register. 2 nd inst. : write the high address bit, page and select reading operation in regeepcntl. ( eepadr[4] , eepage , eeprdwr =0) 3 rd inst. : nop instruction in case of 128khz operation (metal option setting). 4 th inst. : read eeprom low data in regeepdatal register. 5 th inst. : read eeprom high data in regeepdatah register. the two last instructions can be executed in the reverse order. how to write data in eeprom : 1 st inst. : write eeprom address (4 low bits) in regeepadr register. 2 nd inst. : write eeprom low data in regeepdatal register. 3 rd inst.: write eeprom high data in regeepdatah register. 4 th inst. : write the high address bit, page and select writing operation in regeepcntl . ( eepadr[4] , eepage , eeprdwr =1) 5 th . : irqeep is generated at the end of write. the three first instructions can be executed in any order. writing regeepcntl register starts automatically eeprom reading or writing operation according to the bit eeprdwr . eeprom access time is max. 20s : data is available in regeepdatal and regeepdatah registers at the instruction following the read access on 32khz system clock the read signal is 1.5 system clock wide. the cpu reads at end of phase 3. with the 128khz metal option the eeread signal is 3.5 system clock cycles wide. using this option the user must use a nop instruction before actually reading the regeepdatal,h values. eeprom writing operation lasts 24ms (erase followed by write). the flag eepbusy in regeepcntl register stays high until the writing operation is finished. an interrupt request irqeep is generated at the end of each writing operation. while eepbusy is high the eeprom must not be used at all. the eeprom interrupt request can be masked (default) ( maskirqeep bit). see also the interrupt handling section 13 for further information . note : any reset or sleep mode will immediately cancel the eeprom write operation. the data to be stored at this time may be corrupted. figure 27. read timing 32khz operation max. 20 s ee read ee stable data sys. clock cpu phase 4 3 2 1 4 3 1 2
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 37 www.emmicroelectronic.com 11.1 eeprom registers table 11.1.1 eeprom control register regeepcntl bit name reset r/w description 3 eepage 0 r/w eeprom page select 2 eepbusy 0 r eeprom writing operation busy flag 1 eeprdwr 0 r/w eeprom operation read=0 / write=1 0 eepadr[4] 0 r/w eeprom`address bit 4 writing this register starts automatically eeprom reading or writing operation table 11.1.2 eeprom address register regeepadr bit name reset r/w description 3 eepadr[3] 0 r/w eeprom address bit 3 2 eepadr[2] 0 r/w eeprom address bit 2 1 eepadr[1] 0 r/w eeprom address bit 1 0 eepadr[0] 0 r/w eeprom address bit 0 table 11.1.3 eeprom data low register regeepdatal bit name reset r/w description 3 eepdata[3] 0 r/w eeprom data bit 3 2 eepdata[2] 0 r/w eeprom data bit 2 1 eepdata[1] 0 r/w eeprom data bit 1 0 eepdata[0] 0 r/w eeprom data bit 0 table 11.1.4 eeprom data high register regeepdatah bit name reset r/w description 3 eepdata[7] 0 r/w eeprom data bit 7 2 eepdata[6] 0 r/w eeprom data bit 6 1 eepdata[5] 0 r/w eeprom data bit 5 0 eepdata[4] 0 r/w eeprom data bit 4
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 38 www.emmicroelectronic.com 12. supply voltage level detector the em6617 has a built-in supply voltage level detector (svld) circuitry, such that the cpu can compare the supply voltage against a pre-selected value. during sleep mode this function is inhibited. the cpu activates the supply voltage level detector by writing vldstart = 1 in the register regvldcntl . the actual measurement starts on the next ck[9] rising edge and lasts during the ck[9] high period (2 ms at 32 khz). the busy flag vldbusy stays high from vldstart set until the measurement is finished. the worst case time until the result is available is 1.5 ck[9] prescaler clock periods (32 khz -> 6 ms). the detection level must be defined in register regvldlevel before the vldstart bit is set. during the actual measurement (2 ms) the device will draw an additional 5 a of i vdd current. after the end of the measure the result is available by inspection of the bit vldresult . an interrupt irqvld is send to indicate the end of measure. if the result is read 0, then the power supply voltage was greater than the detection level value. if read 1, the power supply voltage was lower than the detection level value. during each read while busy=1 the vldresult is not guaranteed. the interrupt request can be masked (default) ( maskirqvld bit). 12.1 svld register table 12.1.1 register regvldcntl bit name reset r/w description 3 vldresult 0 r* vld result flag 2 vldstart 0 w vld start 2 vldbusy 0 r vld busy flag 1 vldlevel1 0 r/w vld level selection 0 vldlevel0 0 r/w vld level selection r*; vldresult is not guaranteed while vldbusy=1 table 12.1.2 voltage level detector value selecting level vldlevel1 vldlevel0 typical voltage level level1 0 0 2.2 level2 0 1 2.5 level3 1 0 3.0 level3 1 1 3.0 figure 28. svld timing diagram vbat =v dd compare level ck[9] ( 256 hz ) cpu starts measure busy flag measure 1 0 result read result svld > vbat svld < vbat cpu starts measure
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 39 www.emmicroelectronic.com 13. interrupt controller the em6617 has 12 different interrupt request sources each of which is maskable. 4 of them are coming from extarnal sources and 8 from internal. external(4) - port a, pa[3] .. pa[0] inputs internal(8) - prescaler ck[1], 32 hz / 8 hz - 10-bit counter count to 0, count equal to compare - eeprom end of writing operation - adc end of conversion - vld end of measure - swb (non-maskable) swb empty in interactive mode note : the interrupt request from serial output buffer (swbempty) in interactive mode can not be masked in opposition to the others and goes directly to the cpu. for interrupt requests except swbempty interrupt : to be able to send an interrupt to the cpu, at least one of the interrupt request flags must ?1? ( irqxx ) and the general interrupt enable bit inten located in the register regsyscntl1 must be set to 1. the interrupt request flags can only be set high by a positive edge on the irqxx data flip-flop while the corresponding mask register bit ( maskirqxx ) is set to 1. at power on or after any reset all interrupt request mask registers are cleared and therefore do not allow any interrupt request to be stored. also the general interrupt enable inten is set to 0 (no irq to cpu) by reset. after each read operation on the interrupt request registers regirq1 , regirq2 or regirq3 the contents of the addressed register are reset. therefore one has to make a copy of the interrupt request register if there was more than one irq to treat. each interrupt request flag may also be reset individually by writing 1 into it . interrupt handling priority must be resolved through software by deciding which register and which flag inside the register need to be serviced first. since the cpu has only one interrupt subroutine and the irqxx registers are cleared after reading, the cpu does not miss any interrupt request which comes during the interrupt service routine. if any occurs during this time a new interrupt will be generated as soon as the software comes out of the current interrupt subroutine. figure 29. interrupt controller block diagram interrupt request ca p ture re g ister 12 input-or read clrintbit reset general int en irq to p one of these blocks for each irq db db[n] irqxx swbempty write mask write halt swbauto
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 40 www.emmicroelectronic.com any interrupt request sent by a periphery cell while the corresponding mask is not set will not be stored in the interrupt request register. all interrupt requests are stored in their irqxx registers depending only on their mask setting and not on the general interrupt enable status. whenever the em6617 goes into halt mode the inten bit is automatically set to 1, thus allowing to resume from halt mode with an interrupt. this behavior is blocked if swbauto is set high. in this case the peripheral interrupts are disabled until the swbauto bit is reset low. please refer also to the swb chapter 9. 13.1 interrupt control registers table 13.1.1 register regirq1 bit name reset r/w description 3 irqpa[3] 0 r/w* port a pa[3] interrupt request 2 irqpa[2] 0 r/w* port a pa[2] interrupt request 1 irqpa[1] 0 r/w* port a pa[1] interrupt request 0 irqpa[0] 0 r/w* port a pa[0] interrupt request w*; writing of 1 clears the corresponding bit. table 13.1.2 register regirq2 bit name reset r/w description 3 irqhz1 0 r/w* prescaler interrupt request 2 irqhz32/8 0 r/w* prescaler interrupt request 1 irqeep 0 r/w* eeprom interrupt request 0 irqadc 0 r/w* adc interrupt request w*; writing of 1 clears the corresponding bit. table 13.1.3 register regirq3 bit name reset r/w description 3-- 2 irqvld 0 r/w* vld interrupt request 1 irqcount0 0 r/w* counter interrupt request 0 irqcntcomp 0 r/w* counter interrupt request w*; writing of 1 clears the corresponding bit. table 13.1.4 register regirqmask1 bit name reset r/w description 3 maskirqpa[3] 0 r/w port a pa[3] interrupt mask 2 maskirqpa[2] 0 r/w port a pa[2] interrupt mask 1 maskirqpa[1] 0 r/w port a pa[1] interrupt mask 0 maskirqpa[0] 0 r/w port a pa[0] interrupt mask interrupt is not stored if the mask bit is 0. table 13.1.5 register regirqmask2 bit name reset r/w description 3 maskirqhz1 0 r/w prescaler interrupt mask 2 maskirqhz32/8 0 r/w prescaler interrupt mask 1 maskirqeep 0 r/w eeprom interrupt mask 0 maskirqadc 0 r/w adc interrupt mask interrupt is not stored if the mask bit is 0. table 13.1.6 register regirqmask3 bit name reset r/w description 3-- 2 maskirqvld 0 r/w vld interrupt mask 1 maskirqcount0 0 r/w counter interrupt mask 0 maskirqcntcomp 0 r/w counter interrupt mask interrupt is not stored if the mask bit is 0
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 41 www.emmicroelectronic.com 14. ram the em6617 has two 64x4 bit ram?s built-in. the main ram (ram1) is direct addressable on addresses decimal(0 to 63). a second ram (ram2) is indirect addressable on addresses 64,65, 66 and 67 together with the index from regindexadr. the ram2 addressing is indirect using the regindexadr value as an offset to the directly addressed base ram2_0 , ram2_1 , ram2_2 or ram2_3 registers. to write or read the ram2 the user has first to set the offset value in the regindexadr register. the actual access then is made on the ram2 base addresses ram2_0 , ram2_1, ram2_2 or ram2_3. refer to figure 30. ram architecture, for the address mapping. i.e. writing hex(5) to ram2 add location 30: first write hex(e) to regindexadr, then write hex(5) to ram2_1 ram extension : unused r/w registers can often be used as possible ram extension. be careful not to use register which start, stop, or reset some functions. figure 30. ram architecture ram1_63 ram1_62 ram1_61 ram1_60 4 bit r/w regindexadr[f] regindexadr[e] 4 bit r/w ... ... regindexadr[1] 4 bit r/w 4 bit r/w regindexadr[0] ram1_0 4 bit r/w 4 bit r/w 4 bit r/w 4 bit r/w 4 bit r/w . . . . . . ram1_3 ram1_2 ram1_1 ram2_3 ram2_2 ram2_1 4 bit r/w ram2_0 4 bit r/w 4 bit r/w 4 bit r/w regindexadr[f] regindexadr[e] 4 bit r/w ... ... regindexadr[1] 4 bit r/w 4 bit r/w regindexadr[0] 4 bit r/w regindexadr[f] regindexadr[e] 4 bit r/w ... ... regindexadr[1] 4 bit r/w 4 bit r/w regindexadr[0] 4 bit r/w regindexadr[f] regindexadr[e] 4 bit r/w ... ... regindexadr[1] 4 bit r/w 4 bit r/w regindexadr[0] 64 x 4 indexed addressable ram2 64 x 4 direct addressable ram1
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 42 www.emmicroelectronic.com 15. strobe output the strobe output is used to indicate either the em6617 reset condition, a write operation on port b (writepb) or the sleep mode. the selection is done in register reglcdcntl1 . per default, the reset condition is output on the strobe terminal. for a port b write operation the strobe signal goes high for half a system clock period. data can be latched on the falling edge of the strobe signal. this function is used to indicate when data on port b output terminals is changing. the reset signal on the strobe output is a copy of the internal cpu reset signal. the strobe pin remains active high as long as the cpu gets the reset. both the reset condition and the port b write operation can be output simultaneously on the strobe pin. the strobe output select latches are reset by initial power on reset only. table 13.1.1. strobe output selection strobeoutsel1 strobeoutsel0 strobe terminal output 00system reset 01 system reset and writepb 10writepb 1 1 sleep 15.1 strobe register table 15.1.1 register optpcandstr bit name power on value r/w description 3 nopdpc 0 r/w no pull-down on portc 2 nchopdpc 0 r/w n-channel open drain on portc 1 strobeoutsel1 0 r/w strobe output selection 0 strobeoutsel0 0 r/w strobe output selection default : system reset on strobe output figure 31 . strobe output reset, writepb strobeoutsel1 strobeoutsel0 sleep writepb reset 3 01 2 1 0 terminal strobe
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 43 www.emmicroelectronic.com 16. peripheral memory map reset values are valid after power up or after every system reset. register name add hex add dec reset value read bits write bits remarks b'3210 read/write_bits ram1_0 00 0 xxxx 0: data0 1: data1 2: data2 3: data3 direct addressable ram 64x4 bit ... ... ... ... ... ... ram1_63 3f 63 xxxx 0: data0 1: data1 2: data2 3: data3 direct addressable ram 64x4 bit ram2_0 40 64 xxxx 0: data0 1: data1 2: data2 3: data3 16 nibbles addressable over index register on add 'h70 ... ... ... ... ... ... ram2_3 43 67 xxxx 0: data0 1: data1 2: data2 3: data3 16 nibbles addressable over index register on add 'h70 --- 44 68 reserved, not implemented ... ... ... ... --- 4f 79 reserved, not implemented regpa 50 80 xxxx 0: padata[0] 1: padata[1] 2: padata[2] 3: padata[3] ---- read port a directly regpbcntl 51 81 0000 0: pbiocntl[0] 1: pbiocntl[1] 2: pbiocntl[2] 3: pbiocntl[3] port b control default: input mode regpbdata 52 82 0000 0: pb[0] 1: pb[1] 2: pb[2] 3: pb[3] 0: pbdata[0] 1: pbdata[1] 2: pbdata[2] 3: pbdata[3] port b data output pin port b read default : 0 regpccntl 53 83 0000 0: pciocntl 1: '0' 2: '0' 3: '0' 0: pciocntl 1: -- 2: -- 3: -- port c control default: input mode regpcdata 54 84 0000 0: pc[0] 1: pc[1] 2: pc[2] 3: pc[3] 0: pcdata[0] 1: pcdata[1] 2: pcdata[2] 3: pcdata[3] port c data output pin port c read default : 0 regswbcntl 55 85 0000 0: swbfsel0 1: swbfsel1 2: '0' 3: '0' 0: swbfsel0 1: swbfsel1 2: -- 3: -- swb control : clock selection regswbuff 56 86 1111 0: buff[0] 1: buff[1] 2: buff[2] 3: buff[3] swb buffer register
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 44 www.emmicroelectronic.com register name add hex add dec reset value read bits write bits remarks b'3210 read/write_bits regswbsizel 57 87 0000 0: size[0] 1: size[1] 2: size[2] 3: size[3] swb size low bits regswbsizeh 58 88 0000 0: size[4] 1: size(5] 2: swbstart 3: swbauto swb size high bits automatic/interactive mode regeepcntl 59 89 0000 0: eepadr[4] 1: eeprdwr 2: eepbusy 3: eepage 0: eepadr[4] 1: eeprdwr 2: -- 3: eepage eeprom control : address high bit, read/write and busy flag regeepadr 5a 90 0000 0: eepadr[0] 1: eepadr[1] 2: eepadr[2] 3: eepadr[3] eeprom address low bits regeepdatal 5b 91 0000 0: eepdata[0] 1: eepdata[1] 2: eepdata[2] 3: eepdata[3] eeprom data low bits regeepdatah 5c 92 0000 0: eepdata[4] 1: eepdata[5] 2: eepdata[6] 3: eepdata[7] eeprom data high bits regccntl1 5d 93 0000 0: countfsel0 1: countfsel1 2: countfsel2 3: up/down 10 bit counter control 1 : frequency and up/down regccntl2 5e 94 0000 0: '0' 1: encomp 2: evcount 3: start 0 : load 1: encomp 2: evcount 3: start 10 bit counter control 2 : load, compare, event counter and start regcdatal 5f 95 1111 0: count[0] 1: count[1] 2: count[2] 3: count[3] 0: creg[0] 1: creg[1] 2: creg[2] 3: creg[3] 10 bit counter data low nibble regcdatam 60 96 1111 0: count[4] 1: count[5] 2: count[6] 3: count[7] 0: creg[4] 1: creg[5] 2: creg[6] 3: creg[7] 10 bit counter data middle nibble regcdatah 61 97 0011 0: count[8] 1: count[9] 2: bitsel[0] 3: bitsel[1] 0: creg[8] 1: creg[9] 2: bitsel[0] 3: bitsel[1] 10 bit counter data high nibble regadccntl 62 98 0000 0: channelsela 1: channelselb 2: single 3: adcbusy 0: channelsela 1: channelselb 2: single 3: startconvert adc control : channel, mode selection start and busy flag regadcdatal 63 99 0000 0: adcdata[0] 1: adcdata[1] 2: adcdata[2] 3: adcdata[3] adc data low nibble regadcdatah 64 100 0000 0: adcdata[4] 1: adcdata[5] 2: adcdata[6] 3: adcdata[7] adc data high nibble
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 45 www.emmicroelectronic.com register name add hex add dec reset value read bits write bits remarks b'3210 read/write bits regirqmask1 65 101 0000 0: maskirqpa[0] 1: maskirqpa[1] 2: maskirqpa[2] 3: maskirqpa[3] port a interrupt mask masking active low regirqmask2 66 102 0000 0: maskirqadc 1: maskirqeep 2: maskirqhz32/8 3: maskirqhz1 prescaler, eeprom, adc interrupt mask masking active low regirqmask3 67 103 0000 0: maskirqcntcomp 1: maskirqcount0 2: maskirqvld 3 : '0' 0: maskirqcntcomp 1: maskirqcount0 2: maskirqvld 3: -- 10 bit counter, vld interrupt mask masking active low regirq1 68 104 0000 0: irqpa[0] 1: irqpa[1] 2: irqpa[2] 3: irqpa[3] 0: rirqpa[0] 1: rirqpa[1] 2: rirqpa[2] 3: rirqpa[3] read: port a irq write: reset irq if data bit = 1. regirq2 69 105 0000 0: irqadc 1: irqeep 2: irqhz32/8 3: irqhz1 0: rirqadc 1: rirqeep 2: rirqhz32/8 3: rirqhz1 read: prescaler, eeprom, adc irq ; write: reset irq if data bit = 1 regirq3 6a 106 0000 0:irqcntcomp 1: irqcount0 2: irqvld 3: '0' 0: rirqcntcomp 1: rirqcount0 2: rirqvld 3: -- read: 10 bit counter, vld irq write: reset irq if data bit =1. regsyscntl1 6b 107 00x0 0: chtmdis 1: selintfull 2: '0' 3: inten 0: chtmdis 1: selintfull 2: sleep 3: inten system control 1 : chtmdis only usable only for em test modes with test=1 regsyscntl2 6c 108 0000 0: wdval0 1: wdval1 2: sleepen 3: '0' 0: -- 1: -- 2: sleepen 3: wdreset system control 2 : watchdog value and periodical reset, enable sleep mode regsyscntl3 6d 109 0000 0: nologicwd 1: nooscwd 2: '0' 3: vref1/2sel 0: nologicwd 1: nooscwd 2: -- 3: vref1/2sel system control 3 : watchdogs control, reference voltage for adc ixlow 6e 110 xxxx 0: ixlow[0] 1: ixlow[1] 2: ixlow[2] 3: ixlow[3] internal p index register low nibble ixhigh 6f 111 xxxx 0: ixhigh[4] 1: ixhigh[5] 2: ixhigh[6] 3: '0' 0: ixhigh[4] 1: ixhigh[5] 2: ixhigh[6] 3: -- internal p index register high nibble regindexadr 70 112 0000 0: indexadr[0] 1: indexadr[1] 2: indexadr[2] 3: indexadr[3] index addressing register for4x16 nibble of ram2 regpresc 71 113 0000 0: debsel 1: printsel 2: '0' 3: pwmon 0: debsel 1: printsel 2: respresc 3: pwmon prescaler control : debouncer and prescaler interrupt selection regvldcntl 72 114 0000 0: vldlevel0 1: vldlevel1 2: vldbusy 3: vldresult 0: vldlevel0 1: vldlevel1 2: vldstart 3: -- vld control : level detection start (busy flag) and result
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 46 www.emmicroelectronic.com 17. option register memory map the values of the option registers are set by initial reset on power up and through write operations only. other resets as reset from watchdog, reset from input port a do not change the options register value. register name add hex add dec power up value read bits write bits remarks b'3210 read/write bits optdebintpa opt[3:0] 75 117 0000 0: nodebintpa[0] 1: nodebintpa[1] 2: nodebintpa[2] 3: nodebintpa[3] option register : debouncer on port a for interrupt gen. default: debouncer on optintedgpa opt[7:4] 76 118 0000 0: intedgpa[0] 1: intedgpa[1] 2: intedgpa[2] 3: intedgpa[3] option register : interrupt edge select on port a default: pos edge optnopullpa opt[11:8] 77 119 0000 0: nopullpa[0] 1: nopullpa[1] 2: nopullpa[2] 3: nopullpa[3] option register : pull-down selection on port a default: pull-down optnopdpb opt[15:12] 78 120 0000 0: nopdpb[0] 1: nopdpb[1] 2: nopdpb[2] 3: nopdpb[3] option register : pull-down selection on port b default: pull-down optnchopdpb opt[19:16] 79 121 0000 0: nchopdpb[0] 1: nchopdpb[1] 2: nchopdpb[2] 3: nchopdpb[3] option register : nch. open drain output on port b default: cmos output optpcandstr opt[23:20] 7a 122 0000 0: strobeoutsel0 1: strobeoutsel1 2: nchopdpc 3: nopdpc strobe output selection nch. open drain output pull-down selection on port c optselpb opt[31:28] 7b 123 0000 0: inpressleep 1: pb2khzout 2: pb32khzout 3: pb1khzout port a input reset option option register : frequency output on port b optinprsel1 7c 124 0000 0: inpres1pa[0] 1: inpres1pa[1] 2: inpres1pa[2] 3: inpres1pa[3] option register : reset through port a inputs selection, refer to reset part optinprsel2 7d 125 0000 0: inpres2pa[0] 1: inpres2pa[1] 2: inpres2pa[2] 3: inpres2pa[3] option register; reset through port a inputs selection, refer to reset part regtestem 7f 127 ---- ---- accu for em test only; write accu on port b test = 1
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 47 www.emmicroelectronic.com 18. active supply current test for this purpose, five instructions at the end of the rom will be added. testloop: sti 00h, 0ah ldr 1bh nxorx jpz testloop jmp 00h to stay in the testloop, these values must be written in the corresponding addresses before jumping in the loop: 1bh: 0101b 32h: 1010b 6eh: 0010b 6fh: 0011b free space after last instruction: jmp 00h (0000) remark: empty space within the program are filled with nop (foff).
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 48 www.emmicroelectronic.com 19. mask options most options which in many controllers are realized as metal mask options are directly user selectable with the option registers, therefore allowing a maximum freedom of choice . the following options can be selected at the time of programming the metal mask rom. 19.1 input / output ports 19.1.1 port a metal options pull-up or no pull-up can be selected for each port a input. a pull-up selection is excluding a pull-down on the same input. pull-down (default) or no pull-down can be selected for each port a input. a pull-down selection is excluding a pull-up on the same input. the total pull value (pull-up or pull- down) is a series resistance out of the resistance r1 and the switching transistor. as a switching transistor the user can choose between a high impedance (weak) or a low impedance (strong) switch. weak, strong or none must be chosen. the default is strong. the default resistor r1 value is 100 kohm. the user may choose a different value from 150 kohm down to 0 ohm. however the value must first be checked and agreed by em microelectronic marin sa. to select an option put an x in column 1,2 and 4 and reconfirm the r1 value in column 3. the default value is : strong pull- down with r1=100 kohm to select an option put an x in column 1,2 and 4 and reconfirm the r1 value in column 3. the default value is : no pull-up figure 32. port a pull options resistor r1 mpapdweak[n] weak pull-down mpapdstrong[n] strong pull-down mpapuweak[n] weak pull-up mpapustrong[n] strong pull-up pull-up control pa[n] terminal 100 kohm no pull-up no pull-down pull-down control or input circuitry option name strong pull- down w pull- down r1 value typ.100 k no pull- down 1 2 3 4 mpapd[3] pa3 input pull-down mpapd[2] pa2 input pull-down mpapd[1] pa1 input pull-down mpapd[0] pa0 input pull-down option name strong pull-up weak pull-up r1 value typ.100k no pull-up 1 2 3 4 mpapu[3] pa3 input pull-up mpapu[2] pa2 input pull-up mpapu[1] pa1 input pull-up mpapu[0] pa0 input pull-up
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 49 www.emmicroelectronic.com 19.1.2 port b metal options pull-up or no pull-up can be selected for each port b input. the pull-up is only active in nch. open drain mode. pull-down or no pull-down can be selected for each port b input. the total pull value (pull-up or pull- down) is a series resistance out of the resistance r1 and the switching transistor. as a switching transistor the user can choose between a high impedance (weak) or a low impedance (strong) switch. weak , strong or none must be chosen. the default is strong. the default resistor r1 value is 100 kohm. the user may choose a different value from 150 kohm down to 0 ohm. however the value must first be checked and agreed by em microelectronic marin sa to select an option put an x in column 1,2 and 4 and reconfirm the r1 value in column 3. the default value is : strong pull- down with r1=100 kohm to select an option put an x in column 1,2 and 4 and reconfirm the r1 value in column 3. the default value is : strong pull-up with r1=100 kohm figure 33. port b pull options resistor r1 mpbpdweak[n] weak pull-down mpbpdstrong[n] strong pull-down mpbpuweak[n] weak pull-up mpbpustrong[n] strong pull-up pull-u p control pb[n] terminal 100 kohm pull-down control or block no pull-up no pull-down input circuitry option name strong pull- down weak pull- down r1 value typ.100k no pull- down 1 2 3 4 mpbpd[3] pb3 input pull-down mpbpd[2] pb2 input pull-down mpbpd[1] pb1 input pull-down mpbpd[0] pb0 input pull-down option name strong pull-up weak pull-up r1 value typ. 100k no pull-up 1 2 3 4 mpbpu[3] pb3 input pull-up mpbpu[2] pb2 input pull-up mpbpu[1] pb1 input pull-up mpbpu[0] pb0 input pull-up
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 50 www.emmicroelectronic.com 19.1.3 port c metal options pull-up or no pull-up can be selected for each port c input. the pull-up is only active in nch. open drain mode. pull-down or no pull-down can be selected for each port c input. the total pull value (pull-up or pull- down) is a series resistance out of the resistance r1 and the switching transistor. as a switching transistor the user can choose between a high impedance (weak) or a low impedance (strong) switch. weak , strong or none must be chosen. the default is strong. the default resistor r1 value is 100 kohm. the user may choose a different value from 150 kohm down to 0 ohm. however the value must first be checked and agreed by em microelectronic marin sa. refer also to chapter to select an option put an x in column 1,2 and 4 and reconfirm the r1 value in column 3. the default value is : strong pull- down with r1=100 kohm to select an option put an x in column 1,2 and 4 and reconfirm the r1 value in column 3. the default value is : strong pull-up with r1=100 kohm figure 34. port c pull options resistor r1 mpcdweak[n] weak pull-down mpcdstrong[n] strong pull-down mpcuweak[n] weak pull-up mpcustrong[n] strong pull-up pull-up control pc[n] terminal 100 kohm pull-down control or block no pull-up no pull-down input circuitry option name strong pull- down weak pull- down r1 value typ.100k no pull- down 1 2 3 4 mpcd[3] pc3 input pull-down mpcd[2] pc2 input pull-down mpcd[1] pc1 input pull-down mpcd[0] pc0 input pull-down option name strong pull-up weak pull-up r1 value typ. 100k no pull-up 1 2 3 4 mpcu[3] pc3 input pull-up mpcu[2] pc2 input pull-up mpcu[1] pc1 input pull-up mpcu[0] pc0 input pull-up
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 51 www.emmicroelectronic.com 19.1.4 swb high impedance state by default the swb clock output is driven to logic ?0? outside a transmission. the user may choose high impedance state on clock output instead of logic?0?. by default the swb data output is driven to logic ?0? outside a transmission. the user may choose high impedance state on data output instead of logic?0?. 19.1.5 debouncer frequency option by default the debouncer frequency is ck[11]. the user may choose ck[14] instead of ck[11]. ck[14 ]corresponds to maximum 0.25ms debouncer time in case of a 32khz oscillator. 19.1.6 system frequency by default the system frequency is defined as being 32khz. higher frequencies are possible. a second setting guarantees typical write times for the eprom at a system frequency of 128 khz. 19.1.7 additional mask options other functions and parameters may also be changed using the metal 1 mask (i.e svld levels). please contact em marin if you have a special request. the customer should specify the required options at the time of ordering. a copy of the pages 48 to 51 as well as the ? software rom characteristic file ? generated by the assembler (*.sta) should be attached to the order. also the customer package marking should be defined at that time. option name no yes a b mswbz_clk swb clock high impedance state. option name no yes a b mswbz_dat swb data high impedance state. option name ck[11] ck[14] a b mdeb debouncer freq. option name 32khz 128khz a b mfreq system frequency = xtal frequency
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 52 www.emmicroelectronic.com 20. temp. and voltage behavior 20.1 i(v dd ) current i(v dd ) current over temperature for run mode, halt mode, sleep mode, adc and eeprom running modes. i(vdd) cpu in active mode, vdd=3.0v 2.0 2.5 3.0 3.5 4.0 -40-20 0 20406080 [c] [ua] i(vdd) sleep mode, vdd = 3.0v 0 50 100 150 200 -40-20 0 20406080 [c] [na] i(vdd) cpu in halt mode, vdd = 3.0v 400 500 600 700 800 -40-20 0 20406080 [c] [na] i(vdd) adc on + i(vdd) run, vdd = 3.0v 0.0 5.0 10.0 15.0 20.0 -40-20 0 20406080 [c] [ua] i(vdd) eeprom r ead + i(vdd) run, vdd = 3.0v 100 125 150 175 200 -40-20 0 20406080 [c] [ua] i(vdd) eeprom write + i(vdd) run, vdd = 3.0v 0.0 20.0 40.0 60.0 80.0 -40-20 0 20406080 [c] [ua] i(vdd) cpu in active mode, vdd=5.0v 2.0 2.5 3.0 3.5 4.0 -40-20 0 20406080 [c] [ua] i(vdd) sleep mode, vdd = 5.0v 0 50 100 150 200 -40-20 0 20406080 [c] [na] i(vdd) cpu in halt mode, vdd = 5.0v 400 500 600 700 800 -40-20 0 20406080 [c] [na] i(vdd) adc on + i(vdd) run, vdd =5.0v 0.0 5.0 10.0 15.0 20.0 -40-20 0 20406080 [c] [ua] i(vdd) eeprom r ead + i(vdd) run, vdd = 5.0v 100 125 150 175 200 -40-20 0 20406080 [c] [ua] i(vdd) eeprom write + i(vdd) run, vdd = 5.0v 0.0 20.0 40.0 60.0 80.0 -40-20 0 20406080 [c] [ua]
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 53 www.emmicroelectronic.com 20.2 iol, ioh iol and ioh temperature dependencies on different vds voltages for port b, port c, strobe, clk, data. ioh data,clock,strobe ; vdd=5.0v; vds=0.15/0.3/0.5/1.0v 0.15 0.3 0.5 1.0 -15.00 -12.00 -9.00 -6.00 -3.00 0.00 -40-20 0 20406080 [c] [ma] iol data,clock,strobe ; vdd=5.0v; vds=0.15/0.3/0.5/1.0v 0.15 0.3 0.5 1.0 0.00 5.00 10.00 15.00 20.00 -40-20 0 20406080 [c] [ma] iol portb,c; vdd=5.0v; vds=0.15/0.3/0.5/1.0v 0.15 0.3 0.5 1.0 0.00 10.00 20.00 30.00 40.00 50.00 -40-200 20406080 [c] [ma] ioh portb.c; vdd=5.0v; vds=0.15/0.3/0.5/1.0v 0.15 0.3 0.5 1.0 -20.00 -15.00 -10.00 -5.00 0.00 -40-20 0 20406080 [c] [ma] ioh data,clock,strobe ; vdd=3.0v; vds=0.15/0.3/0.5/1.0v 0.15 0.3 0.5 1.0 -15.00 -12.00 -9.00 -6.00 -3.00 0.00 -40-20 0 20406080 [c] [ma] iol data,clock,strobe ; vdd=3.0v; vds=0.15/0.3/0.5/1.0v 0.15 0.3 0.5 1.0 0.00 5.00 10.00 15.00 20.00 -40-20 0 20406080 [c] [ma] iol portb,c; vdd=3.0v; vds=0.15/0.3/0.5/1.0v 0.15 0.3 0.5 1.0 0.00 10.00 20.00 30.00 40.00 50.00 -40-20 0 20406080 [c] [ma] ioh portb,c; vdd=3.0v; vds=0.15/0.3/0.5/1.0v 0.15 0.3 0.5 1.0 -20.00 -15.00 -10.00 -5.00 0.00 -40-200 20406080 [c] [m a]
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 54 www.emmicroelectronic.com 20.3 pull-up, pull-down pull-up and pull-down temperature and voltage dependencies for port a, port b, port c. 20.4 vreg, eeprom vreg voltage, temperature and load behavior. eeprom minimal vdd characteristic over temperature. pull-down strong, 25deg 80 90 100 110 120 1.5 2.5 3.5 4.5 5.5 [v] [kohm] pull-down strong vdd=3.0v 50 100 150 200 -40-200 20406080 [c] [kohm] pull-up, 25deg 80 90 100 110 120 1.5 2.5 3.5 4.5 5.5 [v] [kohm] pull-up vdd=3.0v 50 100 150 200 -40-20 0 20406080 [c] [kohm] vreg load dependency 25c -40c 85c 1 1.25 1.5 1.75 2 2.25 0 100 200 300 400 500 ua [v] vddmin eeprom write 1.0 1.3 1.5 1.8 2.0 -40-200 20406080 [c] [v] vreg vdd=3.0v 1.6 1.8 2.0 2.2 2.4 -40-200 20406080 [c] [v] vreg temp = 25c 1.6 1.8 2.0 2.2 2.4 1.5 2.5 3.5 4.5 5.5 vdd [v]
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 55 www.emmicroelectronic.com 20.5 adc8 differential, integral non-linearity, gain, offset and total unadjusted errors dnl @ 3.0v 0.0 0.1 0.2 0.3 0.4 0.5 -40 -10 20 50 80 [c] inl @ 3.0v 0.0 0.1 0.2 0.3 0.4 0.5 -40 -10 20 50 80 [c] gain error @ 3.0v -0.5 -0.4 -0.3 -0.2 -0.1 0.0 -40 -10 20 50 80 [c] offset error @ 3.0v 0.0 0.2 0.4 0.6 0.8 1.0 -40 -10 20 50 80 [c] dnl @ 5.0v 0.0 0.1 0.2 0.3 0.4 0.5 -40 -10 20 50 80 [c] inl @ 5.0v 0.0 0.1 0.2 0.3 0.4 0.5 -40 -10 20 50 80 [c] gain error @ 5.0v -0.5 -0.4 -0.3 -0.2 -0.1 0.0 -40 -10 20 50 80 [c] offset error @ 5.0v 0.0 0.2 0.4 0.6 0.8 1.0 -40 -10 20 50 80 [c] total unadjusted error @ 3.0v 0.0 0.2 0.4 0.6 0.8 1.0 -40 -10 20 50 80 [c] total unadjusted error @ 5.0v 0.0 0.2 0.4 0.6 0.8 1.0 -40 -10 20 50 80 [c]
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 56 www.emmicroelectronic.com dnl voltage dependency @ 25c 0.0 0.1 0.2 0.3 0.4 0.5 2.5 3 3.5 4 4.5 5 5.5 6 [v] inl voltage dependency @ 25c 0.0 0.1 0.2 0.3 0.4 0.5 2.533.544.555.56 [v] gain error voltage dependency @ 25c -0.5 -0.4 -0.3 -0.2 -0.1 0.0 2.5 3 3.5 4 4.5 5 5.5 6 [v] offset error voltage dependency @ 25c 0.0 0.2 0.4 0.6 0.8 1.0 2.533.544.555.56 [v] total unadjusted error dependency @ 25c 0.0 0.2 0.4 0.6 0.8 1.0 2.5 3 3.5 4 4.5 5 5.5 6 [v] differential non-linearity performance -0.2 -0.1 0 0.1 0.2 0 32 64 96 128 160 192 224 256 codes s integral non-linearity performance -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0 32 64 96 128 160 192 224 256 codes
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 57 www.emmicroelectronic.com 21. electrical specification 21.1 absolute maximum ratings min. max. units power supply v dd -v ss - 0.2 + 6.5 v input voltage v ss - 0,2 v dd +0,2 v storage temperature - 40 + 125 c electrostatic discharge to mil-std-883c method 3015.7 with ref. to v ss -2000 +2000 v maximum soldering conditions 10s x 250 c stresses above these listed maximum ratings may cause permanent damage to the device. exposure beyond specified electrical characteristics may affect device reliability or cause malfunction. 21.2 handling procedures this device has built-in protection against high static voltages or electric fields; however, anti-static precautions should be taken as for any other cmos component. unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the supply voltage range. 21.3 standard operating conditions parameter min typ max unit description temperature -40 25 85 c v dd _range 1 (note 1) 2.0 3.0 5.5 v with internal voltage regulator v ss 0 v reference terminal, die substrate c v dd ca (note 2) 100 nf regulated voltage capacitor fq 32768 hz nominal frequency rqs 35 kohm typical quartz serial resistance cl 8.2 pf typical quartz load capacitance df/f +/- 30 ppm quartz frequency tolerance note 1: the minimum v dd of 2.0v allows proper system functionality for the core logic and the eeprom, however the adc minimum voltage is > 2.6v for full range conversion and 0.2 lsb error. note 2: this capacitor filters switching noise from v dd to keep it away from the internal logic cells. in noisy systems the capacitor should be chosen bigger than minimum value.
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 58 www.emmicroelectronic.com 21.4 dc characteristics - power supply conditions: v dd =3.0v, t=25c, 32khz parameter conditions symbol min. typ. max. unit active supply current iv dda1 9.0 12.0 a (in active mode , adc on) -40 ... 85c iv dda1 14.0 a active supply current iv dda2 3.2 3.8 a (in active mode , adc off) -40 ... 85c iv dda2 4.5 a eeprom write current iv dda3 38 48 a during write pulse (20ms) -40 ... 85c iv dda3 70 a eeprom read current iv dda4 90 120 a during read pulse (30s) -40 ... 85c iv dda4 150 a standby supply current iv ddh1 0.55 0.8 a (in halt mode, adc off) -40 ... 85c iv ddh1 1.0 a sleep supply current iv dds1 0.1 0.3 a (in sleep mode) -40 ... 85c iv dds1 0.4 a por static level v por1 1.4 1.6 1.8 v ram data retention v rd1 1.4 v regulated voltage v dd > 2.2 v vreg 2.05 21.5 oscillator conditions: t=25 c , vdd=3.0v (unless otherwise specified) parameter conditions symbol min. typ. max. unit temperature stability +15 ... +35 c df/f x dt 0,3 ppm /c voltage stability v dd =2.2 - 5.5 v df/f x du 5 ppm /v input capacitor ref. on v ss cin 5,5 7 8,5 pf output capacitor ref. on v ss cout 11,0 14 17.0 pf transconductance 50mvpp,v dd min gm 2.5 15.0 a /v oscillator start voltage tstart < 10 s ustart v dd min v oscillator start time v dd > v dd min tdosc 0.5 3 s system start time (oscillator + cold-start + reset) tdsys 1.5 4 s oscillation detector frequency v dd > v dd min t detfreq 12 khz
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 59 www.emmicroelectronic.com 21.6 dc characteristics - i/o pins conditions: t= -40 ... 85 c (unless otherwise specified) parameter conditions symb. min. typ. max. unit input low voltage (static) ports a,b,c test vdd = 3.0 v v il vss 0.3*v dd v qin with regulator vdd = 3.0 v v il vss 0.1*vreg v qout (note 7) input high voltage (static) ports a,b,c test v ih 0.7*v dd v dd v qin with regulator v ih 0.9*vreg vreg v qout (note 7) output low current v dd =3.0v , vol=0.15v i ol 4.8 ma portb. portc v dd =3.0v , vol=0.30v i ol 9.5 ma v dd =3.0v , vol=0.50v i ol 15.0 ma v dd =3.0v , vol=1.0v i ol 16.0 29.0 ma output low current v dd =3.0v , vol=0.15v i ol 1.8 ma data, clock, strobe v dd =3.0v , vol=0.30v i ol 3.6 ma v dd =3.0v , vol=0.50v i ol 5.8 ma v dd =3.0v , vol=1.0v i ol 6.0 10.0 ma output high current v dd =3.0v, voh= v dd -0.15v i oh -1.6 ma portb, portc v dd =3.0v, voh= v dd -0.30v i oh -3.2 ma v dd =3.0v, voh= v dd -0.50v i oh -5.4 ma v dd =3.0v, voh= v dd -1.0 v i oh -10 -6.0 ma output high current v dd =3.0v, voh= v dd -0.15v i oh -1.3 ma data, clock, strobe v dd =3.0v, voh= v dd -0.30v i oh -2.5 ma v dd =3.0v, voh= v dd -0.50v i oh -4.1 ma v dd =3.0v, voh= v dd -1.0 v i oh -7.5 -4 ma input pull-down v dd =3.0v, pin at 3.0v, 25 c r pd 12k ohm test, reset input pull-down v dd =3.0v, pin at 3.0v, 25 c r pd 150k ohm port a,b,c ( note 8 ) weak input pull-up v dd =3.0v, pin at 0.0v, 25 c r pu 400k ohm port a,b,c ( note 8 ) weak input pull-down v dd =3.0v, pin at 3.0v, 25 c r pd 63k 94k 142k ohm port a,b,c ( note 8 ) strong input pull-up v dd =3.0v, pin at 0.0v, 25 c r pu 62k 98k 146k ohm port a,b,c ( note 8 ) strong note 7 ; qout (osc2) is used only with quartz. note 8 : weak or strong are standing for weak pull or strong pull transistor. values are for r1=100kohm
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 60 www.emmicroelectronic.com 21.7 supply voltage level detector parameter conditions symbol min. typ. max. unit svld voltage level1 -10 ... 60 c v svld1 2.02 2.20 2.38 v -40 ... 85 c 1.98 2.20 2.42 svld voltage level2 -10 ... 60 c v svld2 2.30 2.50 2.70 v -40 ... 85 c 2.25 2.50 2.75 svld voltage level3 -10 ... 60 c v svld3 2.78 3.02 3.26 v -40 ... 85 c 2.72 3.02 3.32 temperature coefficient 0 ... 50 c < +/- 0.2 mv/ c 21.8 adc 8 bit conditions: t=25 c , vdd=3.0v, system clock=32 khz , ramp input parameter conditions symb. min. typ. max. unit differential nonlinearity vgnd = vdd/2 vref = vdd dnl +/-0.2 +/-0.5 lsb integral nonlinearity vgnd = vdd/2 vref = vdd inl +/-0.2 +/-0.5 lsb gain error vgnd = vdd/2 vref = vdd ge +/- 0.5 lsb offest error vgnd = vdd/2 vref = vdd oe +/- 0.5 lsb total unadjusted error vgnd = vdd/2 vref = vdd tue +/- 1 lsb battery voltages for full range conversion error dnl 0.2 lsb vrange 2.6 5.5 v missing codes no missing codes the total unadjusted error is a combination of the offset, gain and inl errors. 21.9 eeprom parameter conditions symb. min. typ. max. unit read time (note 9) -40 ... 85c eeprd 45 us write time (note 9) -40 ... 85c eepwr 24 ms vdd during write and read operation -40 ... 85c v eep 2.0 5.5 v note 9 : the typical values are guaranteed by design for a) 32khz operation or b) 128khz operation with the corresponding metal mask set. using different frequencies one must assure not to fall below min value.
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 61 www.emmicroelectronic.com 22. pad location diagram the pad test is twice on the circuit, it can be bound either on top or on the left side. internally the two pads test are connected together by a metal wire. figure 35. die pad location
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 62 www.emmicroelectronic.com 23. package & ordering information (1.27mm pitch, 300mils body width) sop-24 figure 36. sop 24 pin package figure 37. sop 28 pin package (1.27mm pitch, 300mils body width) sop-28
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 63 www.emmicroelectronic.com figure 38. tssop 28 pin package tssop28 (0.65mm pitch, 4.4mm body width)
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 64 www.emmicroelectronic.com figure 39. dip 24 pin package p-dip24 .300 inch body width figure 40. dip 28 pin package p-dip28 .300 inch body width
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 65 www.emmicroelectronic.com 23.1 ordering information note 1: please contact em microelectronic-marin s.a. for availability of dip package. in the 24 pin version the port c outputs pc[3] and pc[2] are not bonded and therefore not available for the user. ordering part number (selected examples) part number package/die form delivery form/thickness em6617%%%so28a 28 pin soic stick em6617%%%so28b 28 pin soic tape&reel em6617%%%so24a 24 pin soic stick em6617%%%so24b 24 pin soic tape&reel em6617%%%tp28a 28 pin tssop stick em6617%%%ws11 sawn wafer 11 mils em6617%%%wp11 die in waffle pack 11 mils please make sure to give the complete part number when ordering, including the 3-digit version. the version is made of 3 digits %%%: the first one is a letter and the last two are numbers, e.g. p01 , p12, etc. 23.2 package marking dip and soic marking: tssop marking: first line: em6617 0 %%y em6 6 1 7%% second line: p p p pppppppp p p p p p p p p third line: ccccccccccc c c c c c c y p where: %% = last two-digits of the customer-specific number given by em (e.g. 05, 12, etc.) y = year of assembly pp?p = production identification (date & lot number) of em microelectronic cc?c = customer specific package marking on third line, selected by customer 23.3 customer marking there are 11 digits available for customer marking on pdip24/28 and so24/28 . there are 6 digits available for customer marking on tssop28 . please specify below the desired customer marking. em microelectronic-marin sa cannot assume responsibility for use of any circuitry described other than circuitry entirely embodied in an em microelectronic-marin sa product. em microelectronic-marin sa reserves the right to change the circuitry and specifications without notice at any time. you are strongly urged to ensure that the information given has not been superseded by a more up-to-date version. packaged device: device in die form: customer version: customer version: customer-s p ecific numbe r customer-s p ecific numbe r given by em microelectronic given by em microelectronic packa g e: die form: so24, so28 = 24/28 p in soic ww = wafe r tp28 = 28 p in tssop ws = sawn wafer/frame dl24, dl28 = 24/28 p in dip ( note 1 ) wp = waffle pack thickness: deliver y form: 11 = 11 mils ( 280um ) , b y default a = stick 27 = 27 mils ( 686um ) , not backla pp ed b = tape&reel (for so and tp packages only) (for other thickness, contact em) em6617 %%% ws 11 em6617 %%% so28 b
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 66 www.emmicroelectronic.com updates date , name version chapter concerned old version (text, figure, etc.) new version (text, figure, etc.) 19.6.98 jag a/222 prelim. pages 1to3 - reverted pages 1 to 3 19.6.98 jag a/222 prelim. 20.4 20.5 active supply current eeprom read and write eeprom read and write current during activation pulse 19.6.98 jag a/222 prelim. 20.8 - added the mention : no missing code 4.8.98 jag a/222 prelim. 0 (at a glance) 2.6 to 5.5 battery voltage for adc (0.5lsb) 2.6 to 5.5 battery voltage for adc (0.2lsb) 4.8.98 jag a/222 prelim. 15 em6621 em6617-1 4.8.98 jag a/222 prelim. 20.3 ? lsb 0.2 lsb 4.8.98 jag a/222 prelim. 20.4 note 3 : the instruction loop ? note 3 : the instruction loop ? 4.8.98 jag a/222 prelim. 20.6 svld spec at ?20c temp koeff +/- 0.1 svld spec at ?40c temp koeff +/- 0.2 4.8.98 jag a/222 prelim. 20.9 read time typ .. read time typ 45us + note 9 12.8.97 jag a/222 prelim 19.15 19.16 default value ? user value ck[11], ck[14], 32khz, 128khz directly to be noted. 12.8.97 jag a/222 prelim 20.9 eeprom min eeprd 10us writ time typ 20ms eeprom min eeprd 20us writ time typ 24ms 12.8.97 jag a/222 prelim 7.1 - added m: pull-up, m: pull-down (default) for pb, pc in table 7.1.1 12.8.97 jag a/222 prelim 7.4.3 - updated figure 14, connection data to outen after mux 12.8.97 jag a/222 prelim 7.4.4 selecting ck[11] output on pb[1] ? selecting ck[16] output on pb[2] ? selecting ck[11] output on pb[2] ? selecting ck[16] output on pb[1] ? 12.8.97 jag a/222 prelim 7.6 - updated figure 15, 1 bit direction, pull, open drain 12.8.97 jag a/222 prelim 7.6.2 - updated figure 16 removed the mux 12.8.97 jag a/222 prelim 7.6.2 therefore, pull-downs in cmos ? are bit-wise configurable ? register therefore, pulld-owns in cmos ? are bit-wise configurable ? register. pulldowns are portwise? 12.8.97 jag a/222 prelim 11 - with the 128khz metal option the adding: eeread signal is 3.5 system clock cycles wide. using this option the user must use a nop instruction before actually reading the regeepdatal,h values 12.8.97 jag a/222 prelim 12.1 all this values are +/- 150mv over ? all this values are +/- 150mv over ? 12.8.97 jag a/222 prelim 13 - this behavior is different if swbauto updated the figure 29 with halt and swbempty signal. this behavior is blocked if swbauto 12.8.97 jag a/222 prelim 19.1.2 port a metal option deleted: title was there twice. 27.8.97 jag a/222 prelim 11 eeprdwr in read mode = 1 eeprdwr in write mode = 0 eeprdwr in read mode = 0 eeprdwr in write mode = 1 20.3.99 jag a/222 prelim 20 - new updated curves 20.3.99 jag a/222 prelim 9, 9.1, 9.2, 19.1.4 - added the description for the high impedance metal option on the swb outputs 20.3.99 jag a/222 prelim 18 - max memory size ? 5 instructions 20.3.99 jag a/222 prelim 19.1.7 - added; the customer should specify?
em6617 03/02 rev. c/442 copyright ? 2002, em microelectronic-marin sa 67 www.emmicroelectronic.com date , name version chapter concerned old version (text, figure, etc.) new version (text, figure, etc.) 20.3.99 jag a/222 prelim 24 new updated chapter for ordering information 16.6.99 jag 21.8 updated the adc spec. added unadj. err. spec 16.6.99 jag b258 jag contains all above described changes 21.9.99 0 adc input arrow new figure 1 with aib,bin,vgnd,vref arrows 01/11/01 all b258 jag c/399 change heater & footer add url. 22.03.02 23 & 24 c/442 change pad location diagram & ordering information

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