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| r01ds0043ej0010 rev.0.10 page 1 of 52 mar 15, 2011 r8c/54e group, r8c/54f group, r8c/54g gr oup, r8c/54h group renesas mcu preliminary datasheet specifications in this document are tentative and subject to change. 1. overview 1.1 features the r8c/54e group, r8c/54f group, r8c/54g group, r8 c/54h group single-chip microcontrollers (mcus) incorporate the r8c cpu core, which provides sophisticated instructions for a high level of efficiency. with 1 mbyte of address space, the cpu core is capable of execut ing instructions at high speed. in addition, it features a multiplier for high-speed arithmetic processing. power consumption is low, and additional power control is possible by selecting the operating mode. the r8c/54e group, r8c/54f group, r8c/54g group, r8c/54h group are also designed to ma ximize emi/ems performance. integration of many peripheral functions, including multif unction timer and serial interface on the same chip, reduces the number of system components. the r8c/54e group and r8c/54f group incorporate one channel of can module, id eal for the lan systems of automotive and factory automation applications. the r8c/54g group and r8c/54h group do not incorporate the can module. the r8c/54e group and r8c/54g group also have on-chip data flash (1 kb 4 blocks) with background operation (bgo) function. 1.1.1 applications automotive, etc. r01ds0043ej0010 rev.0.10 mar 15, 2011
r8c/54e group, r8c/54f group, r8c/54g group, r8c/54h group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 2 of 52 mar 15, 2011 1.1.2 specifications tables 1.1 and 1.2 outline the r8c/54e group specifi cations. tables 1.3 and 1.4 outline the r8c/54f group specifications. tables 1.5 and 1.6 outline the r8c/54g group specifications. tables 1.7 and 1.8 outline the r8c/54h group specifications. table 1.1 r8c/54e group specifications (1) item function description cpu central processing unit r8c cpu core ? number of fundamental instructions: 89 ? minimum instruction execution time: 31.25 ns (cpu clock = 32 mhz, vcc = 2.7 v to 5.5 v) 200 ns (cpu clock = 5 mhz, vcc = 1.8 v to 2.7 v) ? multiplier: 16 bits 16 bits ? 32 bits ? multiply-accumulate instruction: 16 bits 16 bits + 32 bits ? 32 bits ? operating mode: single-chip mode (address space: 1 mbyte) memory rom, ram, data flash see table 1.9 r8c/54e group product list . voltage detection voltage detection circuit ? power-on reset ? voltage detection with three check points (the detection levels for voltage detection 0 and voltage detection 1 can be selected.) i/o ports programmable i/o ports ? input only: 1 ? cmos i/o: 43, selectable pull-up resistor ? simplified peripheral mapping controller (pmc) allows communication function priority pin assignment selection. clock clock generation circuits ? 4 circuits: xin clock oscillation circuit, high-speed on-chip oscillator (wit h frequency adjustment function), low-speed on-chip oscillator, pll frequency synthesizer (up to 32 mhz), multiplied by 2, 4, 6, or 8 ? oscillation stop detection: xin clock oscillation stop detection function ? frequency divider circuit: divided by 1, 2, 4, 8, or 16 can be selected ? low-power mode: standard operating mode (high-speed clock, high-speed on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode interrupts ? number of interrupt vectors: 69 ? external interrupt inputs: 9 (int 5, key input 4) ? priority levels: 7 event link controller (elc) ? events output from periph eral functions can be linked to events input to different peripheral functions. (22 sources 7 types of event link operations) ? events can be handled independently from interrupt requests. watchdog timer ? 14 bits 1 ? selectable reset start function ? selectable low-speed on-chip oscillator for the watchdog timer dtc (data transfer controller) ? 1 channel ? activation sources: 36 ? transfer modes: 2 (normal mode, repeat mode) r8c/54e group, r8c/54f group, r8c/54g group, r8c/54h group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 3 of 52 mar 15, 2011 note: 1. specify the k version if it is to be used. table 1.2 r8c/54e group specifications (2) item function description timer timers rj_0 and rj_1 16 bits 1: 2 circuits integrated on-chip timer mode (periodic timer), pulse output mode (output level inverted every period), event counter mode, pulse wi dth measurement mode, pulse period measurement mode timers rb2_0 16 bits 1: 1 circuits integrated on-chip timer mode (periodic timer), programmable waveform generation mode (pwm output), programmable one-shot generation mode, programmable wait one-shot generation mode timers rc_0 16 bits (with 4 capture/compare re gisters) 1: 1 circuit integrated on-chip timer mode (input capture function, output compare function), pwm mode (output: 3 pins), pwm2 mode (pwm output: 1 pin) timers rd_0 16 bits (with 4 capture/compare re gisters) 2: 1 circuit integrated on-chip timer mode (input capture function, output compare function), pwm mode (output: 6 pins), reset synchronous pwm mode (three-phase waveform output (6 pins), sawtooth wave modulation ), complementary pwm mode (three- phase waveform output (6 pins), triangular wave modulation), pwm3 mode (pwm output with fixe d period: 2 pins) timer re2 8 bits 1 compare match timer mode serial interface uart0_0 and uart0_1 2 channels clock synchronous serial i/o mode, cl ock asynchronous serial i/o mode uart2 1 channel clock synchronous serial i/o mode, cl ock asynchronous serial i/o mode, special mode 3 (ie mode), multiprocessor communication mode clock synchronous serial interface (ssu) ssu_0 and ssu_1 2 channels (also used for the i 2 c bus) (2 channels can be used only for communic ation function priority pin assignment (only 1 channel for others)) (i 2 c bus) i 2 c_0 and i 2 c_1 2 channels (also used for the ssu) (2 channels can be used only for communic ation function priority pin assignment (only 1 channel for others)) lin module hw-lin_0 and hw-lin_1 hardware lin 2 channels (timers rj_0 and rj_1, uart0_0 and uart0_1 are used) can module can_0 1 channel: 16 mailboxes (iso11898-1 standard compliant) a/d converter resolution: 10 bits 12 channels, sample and hold function, sweep mode comparator b 2 circuits crc calculator crc-ccitt (x 16 + x 12 + x 5 + 1), crc-16 (x 16 + x 15 + x 2 + 1) compliant flash memory ? program/erase voltage: vcc = 2.7 v to 5.5 v ? read voltage: vcc = 1.8 v to 5.5 v ? program/erase endurance:10,000 times (data flash) 1,000 times (program rom) ? program security: rom code protect, id code check ? debug functions: on-chip debug, on-board flash rewrite function ? bgo (background operation) function (data flash) debug functions ? 1-wire debug interface provided (dedicated hardware provided) ? hot plug connection is supported, allowing the debugger interface to be connected during user mode operation. operating frequency/ power supply voltage cpu clock = 32 mhz (vcc = 2.7 v to 5.5 v) cpu clock = 5 mhz (vcc = 1.8 v to 2.7 v) current consumption t.b.d. operating ambient temperature -40 ?c to 85 ? c (j version) -40 ?c to 125 ? c (k version) (1) package 48-pin lqfp package code: plqp0048kb-a (previous code: 48p6q-a) r8c/54e group, r8c/54f group, r8c/54g group, r8c/54h group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 4 of 52 mar 15, 2011 table 1.3 r8c/54f group specifications (1) item function description cpu central processing unit r8c cpu core ? number of fundamental instructions: 89 ? minimum instruction execution time: 31.25 ns (cpu clock = 32 mhz, vcc = 2.7 v to 5.5 v) 200 ns (cpu clock = 5 mhz, vcc = 1.8 v to 2.7 v) ? multiplier: 16 bits 16 bits ? 32 bits ? multiply-accumulate instruction: 16 bits 16 bits + 32 bits ? 32 bits ? operating mode: single-chip mode (address space: 1 mbyte) memory rom, ram see table 1.10 r8c/54f group product list . voltage detection voltage detection circuit ? power-on reset ? voltage detection with three check points (the detection levels for voltage detection 0 and voltage detection 1 can be selected.) i/o ports programmable i/o ports ? input only: 1 ? cmos i/o: 43, selectable pull-up resistor ? simplified peripheral mapping controller (pmc) allows communication function priority pin assignment selection. clock clock generation circuits ? 4 circuits: xin clock oscillation circuit, high-speed on-chip oscillator (wit h frequency adjustment function), low-speed on-chip oscillator, pll frequency synthesizer (up to 32 mhz), multiplied by 2, 4, 6, or 8 ? oscillation stop detection: xin clock oscillation stop detection function ? frequency divider circuit: divided by 1, 2, 4, 8, or 16 can be selected ? low-power mode: standard operating mode (high-speed clock, high-speed on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode interrupts ? number of interrupt vectors: 69 ? external interrupt inputs: 9 (int 5, key input 4) ? priority levels: 7 event link controller (elc) ? events output from periph eral functions can be linked to events input to different peripheral functions. (22 sources 7 types of event link operations) ? events can be handled independently from interrupt requests. watchdog timer ? 14 bits 1 ? selectable reset start function ? selectable low-speed on-chip oscillator for the watchdog timer dtc (data transfer controller) ? 1 channel ? activation sources: 36 ? transfer modes: 2 (normal mode, repeat mode) r8c/54e group, r8c/54f group, r8c/54g group, r8c/54h group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 5 of 52 mar 15, 2011 note: 1. specify the k version if it is to be used. table 1.4 r8c/54f group specifications (2) item function description timer timers rj_0 and rj_1 16 bits 1: 2 circuits integrated on-chip timer mode (periodic timer), pulse output mode (output level inverted every period), event counter mode, pulse wi dth measurement mode, pulse period measurement mode timers rb2_0 16 bits 1: 1 circuits integrated on-chip timer mode (periodic timer), programmable waveform generation mode (pwm output), programmable one-shot generation mode, programmable wait one-shot generation mode timers rc_0 16 bits (with 4 capture/compare re gisters) 1: 1 circuit integrated on-chip timer mode (input capture function, output compare function), pwm mode (output: 3 pins), pwm2 mode (pwm output: 1 pin) timers rd_0 16 bits (with 4 capture/compare re gisters) 2: 1 circuit integrated on-chip timer mode (input capture function, output compare function), pwm mode (output: 6 pins), reset synchronous pwm mode (three-phase waveform output (6 pins), sawtooth wave modulation ), complementary pwm mode (three- phase waveform output (6 pins), triangular wave modulation), pwm3 mode (pwm output with fixe d period: 2 pins) timer re2 8 bits 1 compare match timer mode serial interface uart0_0 and uart0_1 2 channels clock synchronous serial i/o mode, cl ock asynchronous serial i/o mode uart2 1 channel clock synchronous serial i/o mode, cl ock asynchronous serial i/o mode, special mode 3 (ie mode), multiprocessor communication mode clock synchronous serial interface (ssu) ssu_0 and ssu_1 2 channels (also used for the i 2 c bus) (2 channels can be used only for communic ation function priority pin assignment (only 1 channel for others)) (i 2 c bus) i 2 c_0 and i 2 c_1 2 channels (also used for the ssu) (2 channels can be used only for communic ation function priority pin assignment (only 1 channel for others)) lin module hw-lin_0 and hw-lin_1 hardware lin 2 channels (timers rj_0 and rj_1, uart0_0 and uart0_1 are used) can module can_0 1 channel: 16 mailboxes (iso11898-1 standard compliant) a/d converter resolution: 10 bits 12 channels, sample and hold function, sweep mode comparator b 2 circuits crc calculator crc-ccitt (x 16 + x 12 + x 5 + 1), crc-16 (x 16 + x 15 + x 2 + 1) compliant flash memory ? program/erase voltage: vcc = 2.7 v to 5.5 v ? read voltage: vcc = 1.8 v to 5.5 v ? program/erase endurance: 1,000 times (program rom) ? program security: rom code protect, id code check ? debug functions: on-chip debug, on-board flash rewrite function debug functions ? 1-wire debug interface provided (dedicated hardware provided) ? hot plug connection is supported, allowing the debugger interface to be connected during user mode operation. operating frequency/ power supply voltage cpu clock = 32 mhz (vcc = 2.7 v to 5.5 v) cpu clock = 5 mhz (vcc = 1.8 v to 2.7 v) current consumption t.b.d. operating ambient temperature -40 ?c to 85 ? c (j version) -40 ?c to 125 ? c (k version) (1) package 48-pin lqfp package code: plqp0048kb-a (previous code: 48p6q-a) r8c/54e group, r8c/54f group, r8c/54g group, r8c/54h group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 6 of 52 mar 15, 2011 table 1.5 r8c/54g group specifications (1) item function description cpu central processing unit r8c cpu core ? number of fundamental instructions: 89 ? minimum instruction execution time: 31.25 ns (cpu clock = 32 mhz, vcc = 2.7 v to 5.5 v) 200 ns (cpu clock = 5 mhz, vcc = 1.8 v to 2.7 v) ? multiplier: 16 bits 16 bits ? 32 bits ? multiply-accumulate instruction: 16 bits 16 bits + 32 bits ? 32 bits ? operating mode: single-chip mode (address space: 1 mbyte) memory rom, ram, data flash see table 1.11 r8c/54g group product list . voltage detection voltage detection circuit ? power-on reset ? voltage detection with three check points (the detection levels for voltage detection 0 and voltage detection 1 can be selected.) i/o ports programmable i/o ports ? input only: 1 ? cmos i/o: 43, selectable pull-up resistor ? simplified peripheral mapping controller (pmc) allows communication function priority pin assignment selection. clock clock generation circuits ? 4 circuits: xin clock oscillation circuit, high-speed on-chip oscillator (wit h frequency adjustment function), low-speed on-chip oscillator, pll frequency synthesizer (up to 32 mhz), multiplied by 2, 4, 6, or 8 ? oscillation stop detection: xin clock oscillation stop detection function ? frequency divider circuit: divided by 1, 2, 4, 8, or 16 can be selected ? low-power mode: standard operating mode (high-speed clock, high-speed on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode interrupts ? number of interrupt vectors: 69 ? external interrupt inputs: 9 (int 5, key input 4) ? priority levels: 7 event link controller (elc) ? events output from periph eral functions can be linked to events input to different peripheral functions. (22 sources 7 types of event link operations) ? events can be handled independently from interrupt requests. watchdog timer ? 14 bits 1 ? selectable reset start function ? selectable low-speed on-chip oscillator for the watchdog timer dtc (data transfer controller) ? 1 channel ? activation sources: 36 ? transfer modes: 2 (normal mode, repeat mode) r8c/54e group, r8c/54f group, r8c/54g group, r8c/54h group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 7 of 52 mar 15, 2011 note: 1. specify the k version if it is to be used. table 1.6 r8c/54g group specifications (2) item function description timer timers rj_0 and rj_1 16 bits 1: 2 circuits integrated on-chip timer mode (periodic timer), pulse output mode (output level inverted every period), event counter mode, pulse wi dth measurement mode, pulse period measurement mode timers rb2_0 16 bits 1: 1 circuits integrated on-chip timer mode (periodic timer), programmable waveform generation mode (pwm output), programmable one-shot generation mode, programmable wait one-shot generation mode timers rc_0 16 bits (with 4 capture/compare re gisters) 1: 1 circuit integrated on-chip timer mode (input capture function, output compare function), pwm mode (output: 3 pins), pwm2 mode (pwm output: 1 pin) timers rd_0 16 bits (with 4 capture/compare re gisters) 2: 1 circuit integrated on-chip timer mode (input capture function, output compare function), pwm mode (output: 6 pins), reset synchronous pwm mode (three-phase waveform output (6 pins), sawtooth wave modulation ), complementary pwm mode (three- phase waveform output (6 pins), triangular wave modulation), pwm3 mode (pwm output with fixe d period: 2 pins) timer re2 8 bits 1 compare match timer mode serial interface uart0_0 and uart0_1 2 channels clock synchronous serial i/o mode, cl ock asynchronous serial i/o mode uart2 1 channel clock synchronous serial i/o mode, cl ock asynchronous serial i/o mode, special mode 3 (ie mode), multiprocessor communication mode clock synchronous serial interface (ssu) ssu_0 and ssu_1 2 channels (also used for the i 2 c bus) (2 channels can be used only for communic ation function priority pin assignment (only 1 channel for others)) (i 2 c bus) i 2 c_0 and i 2 c_1 2 channels (also used for the ssu) (2 channels can be used only for communic ation function priority pin assignment (only 1 channel for others)) lin module hw-lin_0 and hw-lin_1 hardware lin 2 channels (timers rj_0 and rj_1, uart0_0 and uart0_1 are used) a/d converter resolution: 10 bits 12 channels, sample and hold function, sweep mode comparator b 2 circuits crc calculator crc-ccitt (x 16 + x 12 + x 5 + 1), crc-16 (x 16 + x 15 + x 2 + 1) compliant flash memory ? program/erase voltage: vcc = 2.7 v to 5.5 v ? read voltage: vcc = 1.8 v to 5.5 v ? program/erase endurance:10,000 times (data flash) 1,000 times (program rom) ? program security: rom code protect, id code check ? debug functions: on-chip debug, on-board flash rewrite function ? bgo (background operation) function (data flash) debug functions ? 1-wire debug interface provided (dedicated hardware provided) ? hot plug connection is supported, allowing the debugger interface to be connected during user mode operation. operating frequency/ power supply voltage cpu clock = 32 mhz (vcc = 2.7 v to 5.5 v) cpu clock = 5 mhz (vcc = 1.8 v to 2.7 v) current consumption t.b.d. operating ambient temperature -40 ?c to 85 ? c (j version) -40 ?c to 125 ? c (k version) (1) package 48-pin lqfp package code: plqp0048kb-a (previous code: 48p6q-a) r8c/54e group, r8c/54f group, r8c/54g group, r8c/54h group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 8 of 52 mar 15, 2011 table 1.7 r8c/54h group specifications (1) item function description cpu central processing unit r8c cpu core ? number of fundamental instructions: 89 ? minimum instruction execution time: 31.25 ns (cpu clock = 32 mhz, vcc = 2.7 v to 5.5 v) 200 ns (cpu clock = 5 mhz, vcc = 1.8 v to 2.7 v) ? multiplier: 16 bits 16 bits ? 32 bits ? multiply-accumulate instruction: 16 bits 16 bits + 32 bits ? 32 bits ? operating mode: single-chip mode (address space: 1 mbyte) memory rom, ram see table 1.12 r8c/54h group product list . voltage detection voltage detection circuit ? power-on reset ? voltage detection with three check points (the detection levels for voltage detection 0 and voltage detection 1 can be selected.) i/o ports programmable i/o ports ? input only: 1 ? cmos i/o: 43, selectable pull-up resistor ? simplified peripheral mapping controller (pmc) allows communication function priority pin assignment selection. clock clock generation circuits ? 4 circuits: xin clock oscillation circuit, high-speed on-chip oscillator (wit h frequency adjustment function), low-speed on-chip oscillator, pll frequency synthesizer (up to 32 mhz), multiplied by 2, 4, 6, or 8 ? oscillation stop detection: xin clock oscillation stop detection function ? frequency divider circuit: divided by 1, 2, 4, 8, or 16 can be selected ? low-power mode: standard operating mode (high-speed clock, high-speed on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode interrupts ? number of interrupt vectors: 69 ? external interrupt inputs: 9 (int 5, key input 4) ? priority levels: 7 event link controller (elc) ? events output from periph eral functions can be linked to events input to different peripheral functions. (22 sources 7 types of event link operations) ? events can be handled independently from interrupt requests. watchdog timer ? 14 bits 1 ? selectable reset start function ? selectable low-speed on-chip oscillator for the watchdog timer dtc (data transfer controller) ? 1 channel ? activation sources: 36 ? transfer modes: 2 (normal mode, repeat mode) r8c/54e group, r8c/54f group, r8c/54g group, r8c/54h group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 9 of 52 mar 15, 2011 note: 1. specify the k version if it is to be used. table 1.8 r8c/54h group specifications (2) item function description timer timers rj_0 and rj_1 16 bits 1: 2 circuits integrated on-chip timer mode (periodic timer), pulse output mode (output level inverted every period), event counter mode, pulse wi dth measurement mode, pulse period measurement mode timers rb2_0 16 bits 1: 1 circuits integrated on-chip timer mode (periodic timer), programmable waveform generation mode (pwm output), programmable one-shot generation mode, programmable wait one-shot generation mode timers rc_0 16 bits (with 4 capture/compare re gisters) 1: 1 circuit integrated on-chip timer mode (input capture function, output compare function), pwm mode (output: 3 pins), pwm2 mode (pwm output: 1 pin) timers rd_0 16 bits (with 4 capture/compare re gisters) 2: 1 circuit integrated on-chip timer mode (input capture function, output compare function), pwm mode (output: 6 pins), reset synchronous pwm mode (three-phase waveform output (6 pins), sawtooth wave modulation ), complementary pwm mode (three- phase waveform output (6 pins), triangular wave modulation), pwm3 mode (pwm output with fixe d period: 2 pins) timer re2 8 bits 1 compare match timer mode serial interface uart0_0 and uart0_1 2 channels clock synchronous serial i/o mode, cl ock asynchronous serial i/o mode uart2 1 channel clock synchronous serial i/o mode, cl ock asynchronous serial i/o mode, special mode 3 (ie mode), multiprocessor communication mode clock synchronous serial interface (ssu) ssu_0 and ssu_1 2 channels (also used for the i 2 c bus) (2 channels can be used only for communic ation function priority pin assignment (only 1 channel for others)) (i 2 c bus) i 2 c_0 and i 2 c_1 2 channels (also used for the ssu) (2 channels can be used only for communic ation function priority pin assignment (only 1 channel for others)) lin module hw-lin_0 and hw-lin_1 hardware lin 2 channels (timers rj_0 and rj_1, uart0_0 and uart0_1 are used) a/d converter resolution: 10 bits 12 channels, sample and hold function, sweep mode comparator b 2 circuits crc calculator crc-ccitt (x 16 + x 12 + x 5 + 1), crc-16 (x 16 + x 15 + x 2 + 1) compliant flash memory ? program/erase voltage: vcc = 2.7 v to 5.5 v ? read voltage: vcc = 1.8 v to 5.5 v ? program/erase endurance: 1,000 times (program rom) ? program security: rom code protect, id code check ? debug functions: on-chip debug, on-board flash rewrite function debug functions ? 1-wire debug interface provided (dedicated hardware provided) ? hot plug connection is supported, allowing the debugger interface to be connected during user mode operation. operating frequency/ power supply voltage cpu clock = 32 mhz (vcc = 2.7 v to 5.5 v) cpu clock = 5 mhz (vcc = 1.8 v to 2.7 v) current consumption t.b.d. operating ambient temperature -40 ?c to 85 ? c (j version) -40 ?c to 125 ? c (k version) (1) package 48-pin lqfp package code: plqp0048kb-a (previous code: 48p6q-a) r8c/54e group, r8c/54f group, r8c/54g group, r8c/54h group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 10 of 52 mar 15, 2011 1.2 product list table 1.9 shows the r8c/54e group product list. figur e 1.1 shows the r8c/54e group product part number structure. table 1.10 shows the r8c/54f group product list. figure 1.2 shows the r8c/54f group product part number structure. table 1.11 shows the r8c/54g group product list. figure 1.3 shows the r8c/54g group product part number structure. table 1.12 shows the r8c/54h group product list. figure 1.4 shows the r8c/54h group product part number structure. figure 1.1 r8c/54e group product part number structure table 1.9 r8c/54e group product list part no. internal rom capacity internal ram capacity package type remarks program rom data flash r5f21546ejfp 32 kbytes 1 kbyte 4 2.5 kbytes plqp0048kb-a j version r5f21547ejfp 48 kbytes 4 kbytes R5F21548EJFP 64 kbytes 6 kbytes r5f2154aejfp 96 kbytes 8 kbytes r5f2154cejfp 128 kbytes 10 kbytes r5f21546ekfp 32 kbytes 2.5 kbytes k version r5f21547ekfp 48 kbytes 4 kbytes r5f21548ekfp 64 kbytes 6 kbytes r5f2154aekfp 96 kbytes 8 kbytes r5f2154cekfp 128 kbytes 10 kbytes current of mar 2011 part no. r 5 f 21 54 c e j fp package type: fp: plqp0048kb-a (0.5 mm pin pitch, 7 ? 7 mm square body) classification j: operating ambient temperature -40 c to 85 c k: operating ambient temperature -40 c to 125 c availability of can, data flash e: can module: yes; data flash: yes f: can module: yes; data flash: no g: can module: no; data flash: yes h: can module: no; data flash: no rom capacity 6: 32 kb 7: 48 kb 8: 64 kb a: 96 kb c: 128 kb r8c/54e group r8c/5x series memory type f: flash memory renesas mcu renesas semiconductor r8c/54e group, r8c/54f group, r8c/54g group, r8c/54h group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 11 of 52 mar 15, 2011 figure 1.2 r8c/54f group product part number structure table 1.10 r8c/54f group product list part no. internal rom capacity internal ram capacity package type remarks program rom r5f21546fjfp 32 kbytes 2.5 kbytes plqp0048kb-a j version r5f21547fjfp 48 kbytes 4 kbytes r5f21548fjfp 64 kbytes 6 kbytes r5f2154afjfp 96 kbytes 8 kbytes r5f2154cfjfp 128 kbytes 10 kbytes r5f21546fkfp 32 kbytes 2.5 kbytes k version r5f21547fkfp 48 kbytes 4 kbytes r5f21548fkfp 64 kbytes 6 kbytes r5f2154afkfp 96 kbytes 8 kbytes r5f2154cfkfp 128 kbytes 10 kbytes current of mar 2011 part no. r 5 f 21 54 c f j fp package type: fp: plqp0048kb-a (0.5 mm pin pitch, 7 ? 7 mm square body) classification j: operating ambient temperature -40 c to 85 c k: operating ambient temperature -40 c to 125 c availability of can, data flash e: can module: yes; data flash: yes f: can module: yes; data flash: no g: can module: no; data flash: yes h: can module: no; data flash: no rom capacity 6: 32 kb 7: 48 kb 8: 64 kb a: 96 kb c: 128 kb r8c/54f group r8c/5x series memory type f: flash memory renesas mcu renesas semiconductor r8c/54e group, r8c/54f group, r8c/54g group, r8c/54h group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 12 of 52 mar 15, 2011 figure 1.3 r8c/54g group product part number structure table 1.11 r8c/54g group product list part no. internal rom capacity internal ram capacity package type remarks program rom data flash r5f21546gjfp 32 kbytes 1 kbyte 4 2.5 kbytes plqp0048kb-a j version r5f21547gjfp 48 kbytes 4 kbytes r5f21548gjfp 64 kbytes 6 kbytes r5f2154agjfp 96 kbytes 8 kbytes r5f2154cgjfp 128 kbytes 10 kbytes r5f21546gkfp 32 kbytes 2.5 kbytes k version r5f21547gkfp 48 kbytes 4 kbytes r5f21548gkfp 64 kbytes 6 kbytes r5f2154agkfp 96 kbytes 8 kbytes r5f2154cgkfp 128 kbytes 10 kbytes current of mar 2011 part no. r 5 f 21 54 c g j fp package type: fp: plqp0048kb-a (0.5 mm pin pitch, 7 ? 7 mm square body) classification j: operating ambient temperature -40 c to 85 c k: operating ambient temperature -40 c to 125 c availability of can, data flash e: can module: yes; data flash: yes f: can module: yes; data flash: no g: can module: no; data flash: yes h: can module: no; data flash: no rom capacity 6: 32 kb 7: 48 kb 8: 64 kb a: 96 kb c: 128 kb r8c/54g group r8c/5x series memory type f: flash memory renesas mcu renesas semiconductor r8c/54e group, r8c/54f group, r8c/54g group, r8c/54h group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 13 of 52 mar 15, 2011 figure 1.4 r8c/54h group product part number structure table 1.12 r8c/54h group product list part no. internal rom capacity internal ram capacity package type remarks program rom r5f21546hjfp 32 kbytes 2.5 kbytes plqp0048kb-a j version r5f21547hjfp 48 kbytes 4 kbytes r5f21548hjfp 64 kbytes 6 kbytes r5f2154ahjfp 96 kbytes 8 kbytes r5f2154chjfp 128 kbytes 10 kbytes r5f21546hkfp 32 kbytes 2.5 kbytes k version r5f21547hkfp 48 kbytes 4 kbytes r5f21548hkfp 64 kbytes 6 kbytes r5f2154ahkfp 96 kbytes 8 kbytes r5f2154chkfp 128 kbytes 10 kbytes current of mar 2011 part no. r 5 f 21 54 c h j fp package type: fp: plqp0048kb-a (0.5 mm pin pitch, 7 ? 7 mm square body) classification j: operating ambient temperature -40 c to 85 c k: operating ambient temperature -40 c to 125 c availability of can, data flash e: can module: yes; data flash: yes f: can module: yes; data flash: no g: can module: no; data flash: yes h: can module: no; data flash: no rom capacity 6: 32 kb 7: 48 kb 8: 64 kb a: 96 kb c: 128 kb r8c/54h group r8c/5x series memory type f: flash memory renesas mcu renesas semiconductor r8c/54e group, r8c/54f group, r8c/54g group, r8c/54h group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 14 of 52 mar 15, 2011 1.3 block diagram figure 1.5 shows the block diagram. figure 1.5 block diagram dtc system clock generation circuit xin-xout high-speed on-chip oscillator low-speed on-chip oscillator low-speed on-chip oscillator (for watchdog timer) pll frequency synthesizer ram (3) multiplier timers timer rj (16 bits ? 2) timer rb2 (16 bits ? 1) timer rc (16 bits ? 1) timer rd (16 bits ? 2) timer re2 (8 bits ? 1) r8c cpu core memory r0h r0l r1h r2 r3 r1l a0 a1 fb sb usp isp intb pc flg i/o ports a/d converter (10 bits ? 12 channels) rom (2) peripheral functions watchdog timer (14 bits) synchronous serial communication unit (ssu/i 2 c) (8 bits ? 2 channels) event link controller crc calculator voltage detection circuit 4 port p9 8 port p0 8 port p1 6 port p3 5 1 port p4 8 port p6 port p2 8 pmc (peripheral mapping controller) pmc (peripheral mapping controller) uart2 (8 bits ? 1 channel) uart0 (8 bits ? 2 channels) notes: 1. available only in the r8c/54e group and the r8c/54f group. 2. rom size varies with the product. 3. ram size varies with the product. lin module (2 channels) can module (1) (1 channel) comparator b r8c/54e group, r8c/54f group, r8c/54g group, r8c/54h group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 15 of 52 mar 15, 2011 1.4 pin assignment figure 1.6 shows pin assignment (top view). tables 1.13 to 1.17 list the pin name information by pin number. figure 1.6 pin assignment (top view) 1 3 4 5 6 7 8 9 10 11 12 2 48 47 46 45 44 43 42 41 40 39 38 37 p0_6/an1/trciod_0 p0_5/an2/clk2/trciob_0 p0_4/an3/tmre2o/trciob_0 p4_2/vref p6_0/tmre2o p6_2/crx_0 (1) /clk_1 p6_1/ctx_0 (1) p0_3/an4/clk_1/trciob_0 p0_2/an5/rxd_1/trcioa_0/trctrg_0/trjio_1/int2 p0_1/an6/txd_1/trcioa_0/trctrg_0/trjo_1 p0_0/an7/txd2/trcioa_0/trctrg_0 p3_7/sso_0/txd2/rxd2/trjo_0/sda_0/int3 /trcclk_0/trdioc0_0 p1_3/ki3 /an11/trbo_0/trcioc_0/trdiod1_0 p1_4/txd_0/trcclk_0 p1_5/rxd_0/trjio_0/int1 p1_6/clk_0/ssi_0 p1_7/int1 /trjio_0 p2_0/trdioa0_0/trdclk_0/txd2/int1 /rxd2/trciob_0 p2_1/trdiob0_0/trdioc0_0/trcioc_0 p2_2/trdioc0_0/trdiob0_0/trciod_0 p2_3/trdiod0_0 p2_4/trdioa1_0/ivcmp3 p2_5/trdiob1_0/ivref3 p2_6/trdioc1_0 p 3 _ 5 / s c l _ 0 / s s c k _ 0 / t r c i o d _ 0 / c l k 2 / t r d i o d 1 _ 0 / t r d i o a 0 _ 0 / t r d c l k _ 0 p 3 _ 3 / s s i _ 0 / i n t 3 / t r c c l k _ 0 / s c s _ 0 / c t s 2 / r t s 2 / t r d i o d 0 _ 0 p 3 _ 4 / s d a _ 0 / s c s _ 0 / t r c i o c _ 0 / s s i _ 0 / r x d 2 / t x d 2 / t r d i o c 1 _ 0 / t r d i o b 0 _ 0 m o d e p 4 _ 3 p 4 _ 4 r e s e t p 4 _ 7 / x o u t v s s / a v s s p 4 _ 6 / x i n v c c / a v c c p 2 _ 7 / t r d i o d 1 _ 0 p 0 _ 7 / a n 0 / t r c i o c _ 0 p 6 _ 3 / t x d _ 1 / t r j o _ 1 p 6 _ 4 / r x d _ 1 / i n t 2 / t r j i o _ 1 p 6 _ 5 / i n t 4 / c l k 2 / c l k _ 1 / t r c i o b _ 0 p 3 _ 0 / t r j o _ 0 p 3 _ 1 / t r b o _ 0 / c t s 2 / r t s 2 p 1 _ 0 / k i 0 / a n 8 / t r c i o d _ 0 / t r d i o a 1 _ 0 / i v r e f 1 p 1 _ 1 / k i 1 / a n 9 / t r c i o a _ 0 / t r c t r g _ 0 / t r d i o b 1 _ 0 / i v c m p 1 p 1 _ 2 / k l2 / a n 1 0 / t r c i o b _ 0 / t r d i o c 1 _ 0 p 6 _ 7 / i n t 3 / r x d 2 / t r c i o d _ 0 p 6 _ 6 / i n t 2 / t x d 2 / t r c i o c _ 0 p 4 _ 5 / i n t 0 / r x d 2 r8c/54e group r8c/54f group r8c/54g group r8c/54h group plqp0048kb-a (48p6q-a) (top view) 24 13 14 15 16 17 18 19 20 21 22 23 36 35 34 33 32 31 30 29 28 27 26 25 note: 1. available only in the r8c/54e group and the r8c/54f group. r8c/54e group, r8c/54f group, r8c/54g group, r8c/54h group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 16 of 52 mar 15, 2011 note: 1. pin assignments change depending on the pmc function. table 1.13 pin name information by pin number (int, urat0, and uart2) port pin no. int uart0 uart2 int0 int1 int2 int3 int4 txd_0 txd_1 rxd_0 rxd_1 clk_0 clk_1 txd2 rxd2 cts2 rts2 clk2 p0_0 47 txd2 p0_1 46 txd_1 p0_2 45 int2 rxd_1 p0_3 44 clk_1 p0_4 39 p0_5 38 clk2 p0_6 37 p0_7 36 p1_0 30 p1_1 29 p1_2 28 p1_3 24 p1_4 23 txd_0 p1_5 22 int1 rxd_0 p1_6 21 clk_0 p1_7 20 int1 p2_0 19 (1) int1 txd2 rxd2 p2_1 18 (1) p2_2 17 (1) p2_3 16 (1) p2_4 15 p2_5 14 p2_6 13 p2_7 12 p3_0 32 p3_1 31 cts2 rts2 p3_3 2 int3 cts2 rts2 p3_4 3 txd2 rxd2 p3_5 1 clk2 p3_7 48 int3 txd2 rxd2 p4_2 40 p4_3 5 p4_4 6 p4_5 25 int0 rxd2 p4_6 10 p4_7 8 p6_0 41 p6_1 43 p6_2 42 clk_1 p6_3 35 txd_1 p6_4 34 int2 rxd_1 p6_5 33 int4 clk_1 clk2 p6_6 26 int2 txd2 p6_7 27 int3 rxd2 p9_4 19 (1) p9_5 18 (1) p9_6 17 (1) p9_7 16 (1) r8c/54e group, r8c/54f group, r8c/54g group, r8c/54h group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 17 of 52 mar 15, 2011 notes: 1. available only in the r8c/54e group and the r8c/54f group. 2. pin assignments change depending on the pmc function. table 1.14 pin name information by pin number (can and ssu) port pin no. can (1) ssu/i 2 c ctx_0 crx_0 scl_0 scl_1 sda_0 sda_1 ssi_0 ssi_1 scs_0 scs_1 ssck_0 ssck_1 sso_0 sso_1 p0_0 47 p0_1 46 p0_2 45 p0_3 44 p0_4 39 p0_5 38 p0_6 37 p0_7 36 p1_0 30 p1_1 29 p1_2 28 p1_3 24 p1_4 23 p1_5 22 p1_6 21 ssi_0 p1_7 20 p2_0 19 (2) p2_1 18 (2) p2_2 17 (2) p2_3 16 (2) p2_4 15 p2_5 14 p2_6 13 p2_7 12 p3_0 32 p3_1 31 p3_3 2 ssi_0 scs_0 p3_4 3 sda_0 ssi_0 scs_0 p3_5 1 scl_0 ssck_0 p3_7 48 sda_0 sso_0 p4_2 40 p4_3 5 p4_4 6 p4_5 25 p4_6 10 p4_7 8 p6_0 41 p6_1 43 ctx_0 p6_2 42 crx_0 p6_3 35 p6_4 34 p6_5 33 p6_6 26 p6_7 27 p9_4 19 (2) ssi_1 p9_5 18 (2) sda_1 scs_1 p9_6 17 (2) scl_1 ssck_1 p9_7 16 (2) sso_1 r8c/54e group, r8c/54f group, r8c/54g group, r8c/54h group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 18 of 52 mar 15, 2011 note: 1. pin assignments change depending on the pmc function. table 1.15 pin name information by pin numb er (timer rj, timer rb2, and timer rc) port pin no. timer rj timer rb2 timer rc trjo_0 trjo_1 trjio_0 trjio_1 trbo_0 trcclk_0 trcioa_0 trciob_0 trcioc_0 trciod_0 trctrg_0 p0_0 47 trcioa_0 trctrg_0 p0_1 46 trjo_1 trcioa_0 trctrg_0 p0_2 45 trjio_1 trcioa_0 trctrg_0 p0_3 44 trciob_0 p0_4 39 trciob_0 p0_5 38 trciob_0 p0_6 37 trciod_0 p0_7 36 trcioc_0 p1_0 30 trciod_0 p1_1 29 trcioa_0 trctrg_0 p1_2 28 trciob_0 p1_3 24 trbo_0 trcioc_0 p1_4 23 trcclk_0 p1_5 22 trjio_0 p1_6 21 p1_7 20 trjio_0 p2_0 19 (1) trciob_0 p2_1 18 (1) trcioc_0 p2_2 17 (1) trciod_0 p2_3 16 (1) p2_4 15 p2_5 14 p2_6 13 p2_7 12 p3_0 32 trjo_0 p3_1 31 trbo_0 p3_3 2 trcclk_0 p3_4 3 trcioc_0 p3_5 1 trciod_0 p3_7 48 trjo_0 trcclk_0 p4_2 40 p4_3 5 p4_4 6 p4_5 25 p4_6 10 p4_7 8 p6_0 41 p6_1 43 p6_2 42 p6_3 35 trjo_1 p6_4 34 trjio_1 p6_5 33 trciob_0 p6_6 26 trcioc_0 p6_7 27 trciod_0 p9_4 19 (1) p9_5 18 (1) p9_6 17 (1) p9_7 16 (1) r8c/54e group, r8c/54f group, r8c/54g group, r8c/54h group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 19 of 52 mar 15, 2011 note: 1. pin assignments change depending on the pmc function. table 1.16 pin name information by pin number (timer rd and timer re2) port pin no. timer rd timer re2 trdclk_0 trdioa0_0 trdiob0_0 trdioc0_0 trdiod0_0 t rdioa1_0 trdiob1_0 trdioc1_0 trdiod1_0 tmre2o p0_0 47 p0_1 46 p0_2 45 p0_3 44 p0_4 39 tmre2o p0_5 38 p0_6 37 p0_7 36 p1_0 30 trdioa1_0 p1_1 29 trdiob1_0 p1_2 28 trdioc1_0 p1_3 24 trdiod1_0 p1_4 23 p1_5 22 p1_6 21 p1_7 20 p2_0 19 (1) trdclk_0 trdioa0_0 p2_1 18 (1) trdiob0_0 trdioc0_0 p2_2 17 (1) trdiob0_0 trdioc0_0 p2_3 16 (1) trdiod0_0 p2_4 15 trdioa1_0 p2_5 14 trdiob1_0 p2_6 13 trdioc1_0 p2_7 12 trdiod1_0 p3_0 32 p3_1 31 p3_3 2 trdiod0_0 p3_4 3 trdiob0_0 trdioc1_0 p3_5 1 trdclk_0 trdioa0_0 trdiod1_0 p3_7 48 trdioc0_0 p4_2 40 p4_3 5 p4_4 6 p4_5 25 p4_6 10 p4_7 8 p6_0 41 tmre2o p6_1 43 p6_2 42 p6_3 35 p6_4 34 p6_5 33 p6_6 26 p6_7 27 p9_4 19 (1) p9_5 18 (1) p9_6 17 (1) p9_7 16 (1) r8c/54e group, r8c/54f group, r8c/54g group, r8c/54h group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 20 of 52 mar 15, 2011 note: 1. pin assignments change depending on the pmc function. table 1.17 pin name information by pin number (others) port pin no. others p0_0 47 an7 p0_1 46 an6 p0_2 45 an5 p0_3 44 an4 p0_4 39 an3 p0_5 38 an2 p0_6 37 an1 p0_7 36 an0 p1_0 30 ki0 an8 ivref1 p1_1 29 ki1 an9 ivcmp1 p1_2 28 ki2 an10 p1_3 24 ki3 an11 p1_4 23 p1_5 22 p1_6 21 p1_7 20 p2_0 19 (1) p2_1 18 (1) p2_2 17 (1) p2_3 16 (1) p2_4 15 ivcmp3 p2_5 14 ivref3 p2_6 13 p2_7 12 p3_0 32 p3_1 31 p3_3 2 p3_4 3 p3_5 1 p3_7 48 p4_2 40 vref p4_3 5 p4_4 6 p4_5 25 p4_6 10 xin p4_7 8 xout p6_0 41 p6_1 43 p6_2 42 p6_3 35 p6_4 34 p6_5 33 p6_6 26 p6_7 27 p9_4 19 (1) p9_5 18 (1) p9_6 17 (1) p9_7 16 (1) r8c/54e group, r8c/54f group, r8c/54g group, r8c/54h group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 21 of 52 mar 15, 2011 1.5 pin functions tables 1.18 and 1.19 list pin functions. note: 1. contact the oscillator manufacture r for oscillation characteristics. table 1.18 pin functions (1) item pin name i/o description power supply input vcc, vss ? apply 2. 7 v through 5.5 v to the vcc pin when the cpu clock = 32 mhz and apply 1.8 v through 2.7 v to this pin when the cpu clock = 5 mhz. apply 0 v to the vss pin. analog power supply input avcc, avss ? power supply input for the a/d converter. connect a capacitor between pins avcc and avss. reset input reset i applying a low level to this pin resets the mcu. mode mode i connect this pin to the vcc pin via a resistor. xin clock input xin i i/o for th e xin clock generation circuit. connect a ceramic resonator or a crystal oscillator between pins xin and xout. (1) to use an external clock, input it to the xin pin and leave the xout pin open. xin clock output xout i/o int interrupt input int0 to int4 i int interrupt input. key input interrupt ki0 to ki3 i key input interrupt input. timers rj_0 and rj_1 trjio_0, trj io_1 i/o input/output for timer rj. trjo_0, trjo_1 o output for timer rj. timers rb2_0 trbo_0 o output for timer rb2. timers rc_0 trcclk_0 i external clock input. trctrg_0 i external trigger input. trcioa_0, trciob_0, trcioc_0, trciod_0 i/o input/output for timer rc. timers rd_0 trdioa0_0, trdioa1_0, trdiob0_0, trdiob1_0, trdioc0_0, trdioc1_0, trdiod0_0, trdiod1_0 i/o input/output for timer rd. trdclk_0 i external clock input. timer re2 tmre2o o divided clock output. serial interface (uart0) clk_0, clk_1 i/o transf er clock input/output. rxd_0, rxd_1 i serial data input. txd_0, txd_1 o serial data output. serial interface (uart2) cts2 i input for transmission control. rts2 o output for reception control. rxd2 i serial data input. txd2 o serial data output. clk2 i/o transfer clock input/output. r8c/54e group, r8c/54f group, r8c/54g group, r8c/54h group 1. overview under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 22 of 52 mar 15, 2011 note: 1. available only in the r8c/54e group and the r8c/54f group. table 1.19 pin functions (2) item pin name i/o description synchronous serial communication unit (ssu_0, ssu_1) ssi_0, ssi_1 i/o data input/output. scs_0 , scs_1 i/o chip-select input/output. ssck_0, ssck_1 i/o clock input/output. sso_0, sso_1 i/o data input/output. i 2 c bus (i 2 c_0 and i 2 c_1) scl_0, scl_1 i/o clock input/output. sda_0, sda_1 i/o da ta input/output. can module (can_0) (1) crx_0 i data input for can. ctx_0 o data output for can. reference voltage input vref i reference voltage input for the a/d converter. a/d converter an0 to an11 i analog input for the a/d converter. comparator b ivcmp1, ivcmp3 i analog voltage input for comparator b. ivref1, ivref3 i reference voltage input for comparator b. i/o ports p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 and p3_1, p3_3 to p3_5, p3_7, p4_3 to p4_7, p6_0 to p6_7, p9_4 to p9_7 i/o 8-bit cmos input/output ports. each port has an i/o select direction register, enabling switching input and output for each pin. for input ports, the presence or absence of a pull-up resistor can be selected by a program. all ports can be used as led drive (high drive) ports. input port p4_2 i input-only port. r8c/54e group, r8c/54f group, r8 c/54g group, r8c/54h group 2. ce ntral processing unit (cpu) under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 23 of 52 mar 15, 2011 2. central processi ng unit (cpu) figure 2.1 shows the 13 cpu registers. the registers r0, r1 , r2, r3, a0, a1, and fb form a single register bank. the cpu has two register banks. figure 2.1 cpu registers the higher 4 bits of intb are intbh and the lower 16 bits of intb are intbl. interrupt table register data registers (1) address registers (1) frame base register (1) user stack pointer interrupt stack pointer static base register program counter carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved bits processor interrupt priority level reserved bit note: 1. these registers form a single register bank. the cpu has two register banks. flag register r3 r2 b31 b0 b15 fb r2 r3 a0 a1 r0h (r0 high-order byte) r1h (r1 high-order byte) r0l (r0 low-order byte) r1l (r1 low-order byte) intbh b19 b0 intbl b15 pc b19 b0 b15 b0 usp isp sb b15 b0 flg b15 b0 b8 b7 cdzsboiu ipl b8 b7 r8c/54e group, r8c/54f group, r8 c/54g group, r8c/54h group 2. ce ntral processing unit (cpu) under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 24 of 52 mar 15, 2011 2.1 data registers (r 0, r1, r2, and r3) r0 is a 16-bit register for transfer, arithmetic, and logic operations. the same applies to r1 through r3. r0 can be split into high-order (r0h) and low-order (r0l) re gisters to be used separate ly as 8-bit data registers. the same applies to r1h and r1l. r2 can be combined with r0 and used as a 32-bit data register (r2r0). in the same way as with r0 and r2, r3 and r1 can be used as a 32-bit data register (r3r1). 2.2 address registers (a0 and a1) a0 is a 16-bit register for address register indirect addr essing and address register relative addressing. it is also used for transfer, arithmetic, and logic operations. a1 f unctions in the same manner as a0. a1 can be combined with a0 and used as a 32-bit address register (a1a0). 2.3 frame base register (fb) fb is a 16-bit register used for fb relative addressing. 2.4 interrupt table register (intb) intb is a 20-bit register that indicates the start address of a re locatable interrupt vector table. 2.5 program counter (pc) pc is a 20-bit register that indicates the address of the next instruction to be executed. 2.6 user stack pointer (usp) a nd interrupt stack pointer (isp) the stack pointers (sp), usp and isp, are each 16 bits wi de. the u flag of the flg register is used to switch between usp and isp. 2.7 static base register (sb) sb is a 16-bit register used for sb relative addressing. 2.8 flag register (flg) flg is an 11-bit register th at indicates the cpu state. 2.8.1 carry flag (c) the c flag retains carry, borrow, or shift-out bits that have been generated in th e arithmetic and logic unit. 2.8.2 debug flag (d) the d flag is for debugging only. it must only be set to 0. 2.8.3 zero flag (z) the z flag is set to 1 when an arithmetic operation results in 0. otherwise it is set to 0. 2.8.4 sign flag (s) the s flag is set to 1 when an arithmetic operation results in a negative value. otherwise it is set to 0. 2.8.5 register bank select flag (b) register bank 0 is selected when the b flag is 0. register bank 1 is selected when this flag is 1. 2.8.6 overflow flag (o) the o flag is set to 1 when an operation resu lts in an overflow. otherwise it is set to 0. r8c/54e group, r8c/54f group, r8 c/54g group, r8c/54h group 2. ce ntral processing unit (cpu) under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 25 of 52 mar 15, 2011 2.8.7 interrupt enable flag (i) the i flag enables maskable interrupts. interrupts are disabled when the i fl ag is 0, and are enabled when the i flag is 1. the i flag is set to 0 when an interrupt request is acknowledged. 2.8.8 stack pointer select flag (u) isp is selected when the u flag is 0. usp is selected when the u flag is 1. the u flag is set to 0 when a hardware interrupt request is acknowledged or the int instruc tion for a software interrupt numbered from 0 to 31 is executed. 2.8.9 processor interrupt priority level (ipl) ipl is 3 bits wide and assigns eight processor interrupt priority levels from 0 to 7. if a requested interrupt has higher priority than ipl, the interrupt is enabled. 2.8.10 reserved bit the write value must be 0. the read value is undefined. r8c/54e group, r8c/54f gr oup, r8c/54g group, r8c/54 h group 3. address space under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 26 of 52 mar 15, 2011 3. address space 3.1 r8c/54e group memory map figure 3.1 shows the r8c/54e group memory map. the r8c/54e group has a 1-mbyte address space from addresses 00000h to fffffh. up to 32 kbytes of the in ternal rom (program rom) is allocated at lower addresses, beginning with a ddress 0ffffh. the area in excess of 32 kbytes is allocated at higher addresses, beginning with address 10000h. for example, a 64-kbyte inte rnal rom is allocated at addresses 08000h to 17fffh. the fixed interrupt vector ta ble is allocated at addresse s 0ffdch to 0ffffh. the start address of each interrupt routine is stored here. the internal rom (data flash) is allocated at addresses 07000h to 07fffh. the internal ram is allocated at hi gher addresses, beginning with address 00400h. for example, a 6-kbyte internal ram is allocated at addresses 00400h to 01bffh. the internal ram is used not only for data storage but also as a stack area when a subroutine is calle d or when an interrupt request is acknowledged. special function registers (sfrs) ar e allocated at addresses 00000h to 02fffh and addresses 06800h to 06fffh. peripheral function control registers are allocated here. a ll unallocated locations within the sfrs are reserved and cannot be accessed by users. figure 3.1 r8c/54e group memory map 0xxxxh 00000h internal rom (program rom) internal ram sfr internal rom (data flash) (1) 002ffh 00400h 07000h 07fffh 0yyyyh 0ffffh fffffh watchdog timer, oscillation stop detection, voltage monitor undefined instruction overflow brk instruction address match single-step address break (reserved) reset 0ffffh 0ffdch internal rom (program rom) zzzzzh 06fffh 06800h sfr (2) notes: 1. data flash indicates block a (1 kbyte), block b (1 kbyte), block c (1 kbyte), and block d (1 kbyte). 2. addresses 06800h to 06fffh are used for the can, dtc, and other sfr areas. 3. the blank areas are reserved. no access is allowed. part number r5f21546ejfp, r5f21546ekfp capacity address 0yyyyh internal rom address 0xxxxh capacity internal ram address zzzzzh r5f21547ejfp, r5f21547ekfp R5F21548EJFP, r5f21548ekfp r5f2154aejfp, r5f2154aekfp r5f2154cejfp, r5f2154cekfp 32 kbytes 48 kbytes 64 kbytes 96 kbytes 128 kbytes 08000h 08000h 08000h 08000h 08000h 0ffffh 13fffh 17fffh 1ffffh 27fffh 00dffh 013ffh 01bffh 023ffh 02bffh 2.5 kbytes 4 kbytes 6 kbytes 8 kbytes 10 kbytes r8c/54e group, r8c/54f gr oup, r8c/54g group, r8c/54 h group 3. address space under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 27 of 52 mar 15, 2011 3.2 r8c/54f group memory map figure 3.2 shows the r8c/54f group memory map. the r8c/54f group has a 1-mbyte address space from addresses 00000h to fffffh. up to 32 kbytes of the in ternal rom (program rom) is allocated at lower addresses, beginning with a ddress 0ffffh. the area in excess of 32 kbytes is allocated at higher addresses, beginning with address 10000h. for example, a 64-kbyte inte rnal rom is allocated at addresses 08000h to 17fffh. the fixed interrupt vector ta ble is allocated at addresse s 0ffdch to 0ffffh. the start address of each interrupt routine is stored here. the internal ram is allocated at hi gher addresses, beginning with address 00400h. for example, a 6-kbyte internal ram is allocated at addresses 00400h to 01bffh. the internal ram is used not only for data storage but also as a stack area when a subroutine is calle d or when an interrupt request is acknowledged. special function registers (sfrs) ar e allocated at addresses 00000h to 02fffh and addresses 06800h to 06fffh. peripheral function control registers are allocated here. a ll unallocated locations within the sfrs are reserved and cannot be accessed by users. figure 3.2 r8c/54f group memory map 0xxxxh 00000h internal rom (program rom) internal ram sfr 002ffh 00400h 0yyyyh 0ffffh fffffh watchdog timer, oscillation stop detection, voltage monitor undefined instruction overflow brk instruction address match single-step address break (reserved) reset 0ffffh 0ffdch internal rom (program rom) zzzzzh 06fffh 06800h sfr (1) notes: 1. addresses 06800h to 06fffh are used for the can, dtc, and other sfr areas. 2. the blank areas are reserved. no access is allowed. part number r5f21546fjfp, r5f21546fkfp capacity address 0yyyyh internal rom address 0xxxxh capacity internal ram address zzzzzh r5f21547fjfp, r5f21547fkfp r5f21548fjfp, r5f21548fkfp r5f2154afjfp, r5f2154afkfp r5f2154cfjfp, r5f2154cfkfp 32 kbytes 48 kbytes 64 kbytes 96 kbytes 128 kbytes 08000h 08000h 08000h 08000h 08000h 0ffffh 13fffh 17fffh 1ffffh 27fffh 00dffh 013ffh 01bffh 023ffh 02bffh 2.5 kbytes 4 kbytes 6 kbytes 8 kbytes 10 kbytes r8c/54e group, r8c/54f gr oup, r8c/54g group, r8c/54 h group 3. address space under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 28 of 52 mar 15, 2011 3.3 r8c/54g group memory map figure 3.3 shows the r8c/54g group memory map. th e r8c/54g group has a 1-mbyte address space from addresses 00000h to fffffh. up to 32 kbytes of the in ternal rom (program rom) is allocated at lower addresses, beginning with a ddress 0ffffh. the area in excess of 32 kbytes is allocated at higher addresses, beginning with address 10000h. for example, a 64-kbyte inte rnal rom is allocated at addresses 08000h to 17fffh. the fixed interrupt vector ta ble is allocated at addresse s 0ffdch to 0ffffh. the start address of each interrupt routine is stored here. the internal rom (data flash) is allocated at addresses 07000h to 07fffh. the internal ram is allocated at hi gher addresses, beginning with address 00400h. for example, a 6-kbyte internal ram is allocated at addresses 00400h to 01bffh. the internal ram is used not only for data storage but also as a stack area when a subroutine is calle d or when an interrupt request is acknowledged. special function registers (sfrs) ar e allocated at addresses 00000h to 02fffh and addresses 06800h to 06fffh. peripheral function control registers are allocated here. a ll unallocated locations within the sfrs are reserved and cannot be accessed by users. figure 3.3 r8c/54g group memory map 0xxxxh 00000h internal rom (program rom) internal ram sfr internal rom (data flash) (1) 002ffh 00400h 07000h 07fffh 0yyyyh 0ffffh fffffh watchdog timer, oscillation stop detection, voltage monitor undefined instruction overflow brk instruction address match single-step address break (reserved) reset 0ffffh 0ffdch internal rom (program rom) zzzzzh 06fffh 06800h sfr (2) notes: 1. data flash indicates block a (1 kbyte), block b (1 kbyte), block c (1 kbyte), and block d (1 kbyte). 2. addresses 06800h to 06fffh are used for the dtc and other sfr areas. 3. the blank areas are reserved. no access is allowed. part number r5f21546gjfp, r5f21546gkfp capacity address 0yyyyh internal rom address 0xxxxh capacity internal ram address zzzzzh r5f21547gjfp, r5f21547gkfp r5f21548gjfp, r5f21548gkfp r5f2154agjfp, r5f2154agkfp r5f2154cgjfp, r5f2154cgkfp 32 kbytes 48 kbytes 64 kbytes 96 kbytes 128 kbytes 08000h 08000h 08000h 08000h 08000h 0ffffh 13fffh 17fffh 1ffffh 27fffh 00dffh 013ffh 01bffh 023ffh 02bffh 2.5 kbytes 4 kbytes 6 kbytes 8 kbytes 10 kbytes r8c/54e group, r8c/54f gr oup, r8c/54g group, r8c/54 h group 3. address space under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 29 of 52 mar 15, 2011 3.4 r8c/54h group memory map figure 3.4 shows the r8c/54h group memory map. th e r8c/54h group has a 1-mbyte address space from addresses 00000h to fffffh. up to 32 kbytes of the in ternal rom (program rom) is allocated at lower addresses, beginning with a ddress 0ffffh. the area in excess of 32 kbytes is allocated at higher addresses, beginning with address 10000h. for example, a 64-kbyte inte rnal rom is allocated at addresses 08000h to 17fffh. the fixed interrupt vector ta ble is allocated at addresse s 0ffdch to 0ffffh. the start address of each interrupt routine is stored here. the internal ram is allocated at hi gher addresses, beginning with address 00400h. for example, a 6-kbyte internal ram is allocated at addresses 00400h to 01bffh. the internal ram is used not only for data storage but also as a stack area when a subroutine is calle d or when an interrupt request is acknowledged. special function registers (sfrs) ar e allocated at addresses 00000h to 02fffh and addresses 06800h to 06fffh. peripheral function control registers are allocated here. a ll unallocated locations within the sfrs are reserved and cannot be accessed by users. figure 3.4 r8c/54h group memory map 0xxxxh 00000h internal rom (program rom) internal ram sfr 002ffh 00400h 0yyyyh 0ffffh fffffh watchdog timer, oscillation stop detection, voltage monitor undefined instruction overflow brk instruction address match single-step address break (reserved) reset 0ffffh 0ffdch internal rom (program rom) zzzzzh 06fffh 06800h sfr (1) notes: 1. addresses 06800h to 06fffh are used for the dtc and other sfr areas. 2. the blank areas are reserved. no access is allowed. part number r5f21546hjfp, r5f21546hkfp capacity address 0yyyyh internal rom address 0xxxxh capacity internal ram address zzzzzh r5f21547hjfp, r5f21547hkfp r5f21548hjfp, r5f21548hkfp r5f2154ahjfp, r5f2154ahkfp r5f2154chjfp, r5f2154chkfp 32 kbytes 48 kbytes 64 kbytes 96 kbytes 128 kbytes 08000h 08000h 08000h 08000h 08000h 0ffffh 13fffh 17fffh 1ffffh 27fffh 00dffh 013ffh 01bffh 023ffh 02bffh 2.5 kbytes 4 kbytes 6 kbytes 8 kbytes 10 kbytes r8c/54e group, r8c/54f gr oup, r8c/54g group, r8c/54 h group 3. address space under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 30 of 52 mar 15, 2011 3.5 special function registers (sfrs) an sfr (special function register) is a control register for a peripheral function. tabl es 3.1 to 3.23 list the sfr information. table 3.23 lists the id code area, option function select area. x: undefined notes: 1. the blank areas are reserved. no access is allowed. 2. depends on the csproini bit in the ofs register. 3. depends on the lvdasi bit in the ofs register. table 3.1 sfr information (1) (1) address symbol register name after reset remarks 00000h 00001h 00002h 00003h 00004h pm0 processor mode register 0 00h 00005h pm1 processor mode register 1 10000000b 00006h 00007h prcr protect register 00h 00008h cm0 system clock control register 0 00101000b 00009h cm1 system clock control register 1 00100000b 0000ah ocd oscillation stop detection register 00h 0000bh cm3 system clock control register 3 00h 0000ch cm4 system clock control register 4 00000001b 0000dh 0000eh 0000fh pclkr1 peripheral clock select register 1 00h 00010h 00011h 00012h fra0 high-speed on-chip oscillator control register 0 00h 00013h 00014h fra2 high-speed on-chip oscillator control register 2 00h 00015h 00016h 00017h 00018h 00019h 0001ah 0001bh 0001ch plc0 pll control register 0 00010010b 0001dh plcf pll function clock control register 1 00h 0001eh 0001fh 00020h risr reset interrupt select register 10000000b or 00000000b (note 2) 00021h wdtr watchdog timer reset register ffh 00022h wdts watchdog timer start register ffh 00023h wdtc watchdog timer control register 011 11111b 00024h cspr count source protection mode register 10000000b or 00000000b (note 2) 00025h 00026h 00027h 00028h rstfr reset source determination register 00xxxxxxb 00029h 0002ah 0002bh 0002ch svdc stby vdc power control register 00h 0002dh 0002eh 0002fh 00030h cmpa voltage monitor circuit control register 00h 00031h vcac voltage monitor circuit edge select register 00h 00032h ocvrefcr on-chip reference voltage control register 00h 00033h 00034h vca2 voltage detection register 2 00000000b or 00100000b (note 3) 00035h 00036h vd1ls voltage detection 1 level select register 00000111b 00037h 00038h vw0c voltage monitor 0 circuit control register 11001010b or 11001011b (note 3) 00039h vw1c voltage monitor 1 circuit control register 10001010b r8c/54e group, r8c/54f gr oup, r8c/54g group, r8c/54 h group 3. address space under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 31 of 52 mar 15, 2011 note: 1. the blank areas are reserved. no access is allowed. table 3.2 sfr information (2) (1) address symbol register name after reset remarks 0003ah vw2c voltage monitor 2 circuit control register 10001010b 0003bh 0003ch 0003dh 0003eh 0003fh 00040h 00041h fmrdyic interrupt control register 00h 00042h trjic_1 interrupt control register 00h 00043h 00044h 00045h 00046h int4ic interrupt control register 00h 00047h trcic_0 interrupt control register 00h 00048h trd0ic_0 interrupt control register 00h 00049h trd1ic_0 interrupt control register 00h 0004ah tre2ic interrupt control register 00h 0004bh u2tic interrupt control register 00h 0004ch u2ric interrupt control register 00h 0004dh kupic interrupt control register 00h 0004eh adic interrupt control register 00h 0004fh ssuic_0/iicic_0 interrupt control register 00h 00050h 00051h u0tic_0 interrupt control register 00h 00052h u0ric_0 interrupt control register 00h 00053h u0tic_1 interrupt control register 00h 00054h u0ric_1 interrupt control register 00h 00055h int2ic interrupt control register 00h 00056h trjic_0 interrupt control register 00h 00057h 00058h trb2ic_0 interrupt control register 00h 00059h int1ic interrupt control register 00h 0005ah int3ic interrupt control register 00h 0005bh 0005ch 0005dh int0ic interrupt control register 00h 0005eh u2bcnic interrupt control register 00h 0005fh 00060h 00061h 00062h 00063h 00064h 00065h 00066h 00067h 00068h 00069h 0006ah 0006bh 0006ch canrxic_0 interrupt control register 00h 0006dh cantxic_0 interrupt control register 00h 0006eh caneric_0 interrupt control register 00h 0006fh 00070h 00071h 00072h vcmp1ic interrupt control register 00h 00073h vcmp2ic interrupt control register 00h 00074h 00075h 00076h 00077h 00078h 00079h ssuic_1/iicic_1 interrupt control register 00h r8c/54e group, r8c/54f gr oup, r8c/54g group, r8c/54 h group 3. address space under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 32 of 52 mar 15, 2011 x: undefined note: 1. the blank areas are reserved. no access is allowed. table 3.3 sfr information (3) (1) address symbol register name after reset remarks 0007ah 0007bh 0007ch 0007dh 0007eh 0007fh 00080h u0mr_0 uart0_0 transmit/receive mode register 00h 00081h u0brg_0 uart0_0 bit rate register xxh 00082h u0tb_0 uart0_0 transmit buffer register xxh 00083h xxh 00084h u0c0_0 uart0_0 transmit/recei ve control register 0 00001000b 00085h u0c1_0 uart0_0 transmit/receive control register 1 00000010b 00086h u0rb_0 uart0_0 receive buffer register xxxxh 00087h 00088h u0ir_0 uart0_0 interrupt flag and enable register 00h 00089h 0008ah 0008bh 0008ch lincr2_0 lin_0 spec ial function register 00h 0008dh 0008eh linct_0 lin_0 control register 00h 0008fh linst_0 lin_0 status register 00h 00090h u0mr_1 uart0_1 transmit/receive mode register 00h 00091h u0brg_1 uart0_1 bit rate register xxh 00092h u0tb_1 uart0_1 transmit buffer register xxh 00093h xxh 00094h u0c0_1 uart0_1 transmit/receive control register 0 00001000b 00095h u0c1_1 uart0_1 transmit/receive control register 1 00000010b 00096h u0rb_1 uart0_1 receive buffer register xxxxh 00097h 00098h u0ir_1 uart0_1 interrupt flag and enable register 00h 00099h 0009ah 0009bh 0009ch lincr2_1 lin_1 spec ial function register 00h 0009dh 0009eh linct_1 lin_1 control register 00h 0009fh linst_1 lin_1 status register 00h 000a0h 000a1h 000a2h 000a3h 000a4h 000a5h 000a6h 000a7h 000a8h 000a9h 000aah 000abh 000ach 000adh 000aeh 000afh 000b0h 000b1h 000b2h 000b3h 000b4h 000b5h 000b6h 000b7h 000b8h 000b9h r8c/54e group, r8c/54f gr oup, r8c/54g group, r8c/54 h group 3. address space under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 33 of 52 mar 15, 2011 x: undefined note: 1. the blank areas are reserved. no access is allowed. table 3.4 sfr information (4) (1) address symbol register name after reset remarks 000bah 000bbh 000bch 000bdh 000beh 000bfh 000c0h u2mr uart2 transmit/receive mode register 00h 000c1h u2brg uart2 bit rate register 00h 000c2h u2tb uart2 transmit buffer register 00h 000c3h 00h 000c4h u2c0 uart2 transmit/receive control register 0 00001000b 000c5h u2c1 uart2 transmit/receive control register 1 00000010b 000c6h u2rb uart2 receive buffer register 0000h 000c7h 000c8h u2rxdf uart2 digital filter function select register 00h 000c9h 000cah 000cbh 000cch 000cdh 000ceh 000cfh 000d0h u2smr5 uart2 special mode register 5 00h 000d1h 000d2h 000d3h 000d4h 000d5h u2smr3 uart2 special mode register 3 00h 000d6h 000d7h u2smr uart2 special mode register 00h 000d8h 000d9h 000dah 000dbh 000dch 000ddh 000deh 000dfh 000e0h iiccr_0 i 2 c_0 control register 00001110b 000e1h ssbr_0 ss_0 bit counter register 11111000b 000e2h sitdr_0 si_0 transmit data register ffh 000e3h ffh 000e4h sirdr_0 si_0 receive data register ffh 000e5h ffh 000e6h sicr1_0 si_0 control register 1 00h 000e7h sicr2_0 si_0 control register 2 01111101b 000e8h simr1_0 si_0 mode register 1 00010000b 000e9h sier_0 si_0 interrrupt enable register 00h 000eah sisr_0 si_0 status register 00h 000ebh simr2_0 si_0 mode register 2 00h 000ech 000edh 000eeh 000efh 000f0h iiccr_1 i 2 c_1 control register 00001110b 000f1h ssbr_1 ss_1 bit counter register 1 1111000b 000f2h sitdr_1 si_1 transmit data register ffh 000f3h ffh 000f4h sirdr_1 si_1 receive data register ffh 000f5h ffh 000f6h sicr1_1 si_1 cont rol register 1 00h 000f7h sicr2_1 si_1 control register 2 01111101b 000f8h simr1_1 si_1 mode register 1 00010000b 000f9h sier_1 si_1 interrrupt enable register 00h r8c/54e group, r8c/54f gr oup, r8c/54g group, r8c/54 h group 3. address space under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 34 of 52 mar 15, 2011 note: 1. the blank areas are reserved. no access is allowed. table 3.5 sfr information (5) (1) address symbol register name after reset remarks 000fah sisr_1 si_1 status register 00h 000fbh simr2_1 si_1 m ode register 2 00h 000fch 000fdh 000feh 000ffh 00100h 00101h 00102h 00103h 00104h 00105h 00106h 00107h 00108h 00109h 0010ah 0010bh 0010ch 0010dh 0010eh 0010fh 00110h trj_0 timer rj_0 counter register ffffh 00111h 00112h trjcr_0 timer rj _0 control register 00h 00113h trjioc_0 timer rj_0 i/o control register 00h 00114h trjmr_0 timer rj_0 mode register 00h 00115h trjisr_0 timer rj_0 event pin select register 00h 00116h 00117h 00118h trj_1 timer rj_1 counter register ffffh 00119h 0011ah trjcr_1 timer rj_1 control register 00h 0011bh trjioc_1 timer rj_1 i/o control register 00h 0011ch trjmr_1 timer rj_1 mode register 00h 0011dh trjisr_1 timer rj_1 ev ent pin select register 00h 0011eh 0011fh 00120h 00121h 00122h 00123h 00124h 00125h 00126h 00127h 00128h 00129h 0012ah 0012bh 0012ch 0012dh 0012eh 0012fh 00130h trbcr_0 timer rb2_0 control register 00h 00131h trbocr_0 timer rb2_0 one-shot control register 00h 00132h trbioc_0 timer rb2_0 i/o control register 00h 00133h trbmr_0 timer rb2_0 mode register 00h 00134h trbpre_0 timer rb2_0 prescaler register timer rb2_0 primary/secondary register (lower 8 bits) ffh 00135h trbpr_0 timer rb2_0 primary register timer rb2_0 primary register (higher 8 bits) ffh 00136h trbsc_0 timer rb2_0 secondary register timer rb2_0 secondary register (higher 8 bits) ffh 00137h trbir_0 timer rb2_0 interrupt request and status register 00h 00138h trccnt_0 timer rc_0 counter 0000h 00139h r8c/54e group, r8c/54f gr oup, r8c/54g group, r8c/54 h group 3. address space under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 35 of 52 mar 15, 2011 note: 1. the blank areas are reserved. no access is allowed. table 3.6 sfr information (6) (1) address symbol register name after reset remarks 0013ah trcgra_0 timer rc_0 general register a ffffh 0013bh 0013ch trcgrb_0 timer rc_0 general register b ffffh 0013dh 0013eh trcgrc_0 timer rc_0 general register c ffffh 0013fh 00140h trcgrd_0 timer rc_0 general register d ffffh 00141h 00142h trcmr_0 timer rc_0 mode register 01001000b 00143h trccr1_0 timer rc_0 control register 1 00h 00144h trcier_0 timer rc_0 interrupt enable register 01110000b 00145h trcsr_0 timer rc_0 status register 01110000b 00146h trcior0_0 timer rc_0 i/o control register 0 10001000b 00147h trcior1_0 timer rc_0 i/o control register 1 10001000b 00148h trccr2_0 timer rc_0 control register 2 00011000b 00149h trcdf_0 timer rc_0 digital filter function select register 00h 0014ah trcoer_0 timer rc_0 output enable register 01111111b 0014bh trcadcr_0 timer rc_0 a/d conversion trigger control register 11110000b 0014ch trcopr_0 timer rc_0 output waveform manipulation register 00h 0014dh trcelccr_0 timer rc_0 elc c ooperation control register 00h 0014eh 0014fh 00150h 00151h 00152h 00153h 00154h 00155h 00156h 00157h 00158h 00159h 0015ah 0015bh 0015ch 0015dh 0015eh 0015fh 00160h 00161h 00162h 00163h 00164h 00165h 00166h 00167h 00168h 00169h 0016ah 0016bh 0016ch 0016dh 0016eh 0016fh 00170h tresec timer re2 counter data register 00h 00171h tremin timer re2 compare data register 00h 00172h 00173h 00174h 00175h 00176h 00177h trecr timer re2 control register 00000100b 00178h trecsr timer re2 count source select register 00001000b 00179h r8c/54e group, r8c/54f gr oup, r8c/54g group, r8c/54 h group 3. address space under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 36 of 52 mar 15, 2011 note: 1. the blank areas are reserved. no access is allowed. table 3.7 sfr information (7) (1) address symbol register name after reset remarks 0017ah treifr timer re2 interrupt flag register 00h 0017bh treier timer re2 interrupt enable register 00h 0017ch 0017dh 0017eh 0017fh treprc timer re2 protect register 00h 00180h trdelc_0 timer rd_0 elc register 00h 00181h 00182h trdadcr_0 timer rd_0 trigger control register 00h 00183h trdstr_0 timer rd_0 start register 1 1111100b 00184h trdmr_0 timer rd_0 mode register 00001110b 00185h trdpmr_0 timer rd_0 pwm mode register 10001000b 00186h trdfcr_0 timer rd_0 func tion control register 10000000b 00187h trdoer1_0 timer rd_0 output master enable register 1 ffh 00188h trdoer2_0 timer rd_0 output master enable register 2 011 11111b 00189h trdocr_0 timer rd_0 output control register 00h 0018ah trddf0_0 timer rd_0 digital filter function select register 0 00h 0018bh trddf1_0 timer rd_0 digital filter function select register 1 00h 0018ch 0018dh 0018eh 0018fh 00190h trdcr0_0 timer rd_0 control register 0 00h 00191h trdiora0_0 timer rd_0 i/o control register a0 10001000b 00192h trdiorc0_0 timer rd_0 i/o control register c0 10001000b 00193h trdsr0_0 timer rd_0 status register 0 11100000b 00194h trdier0_0 timer rd_0 interrupt enable register 0 11100000b 00195h trdpocr0_0 timer rd_0 pwm mode output level control register 0 1 1111000b 00196h trd0_0 timer rd_0 counter 0 0000h 00197h 00198h trdgra0_0 timer rd_0 general register a0 ffffh 00199h 0019ah trdgrb0_0 timer rd_0 general register b0 ffffh 0019bh 0019ch trdgrc0_0 timer rd_0 general register c0 ffffh 0019dh 0019eh trdgrd0_0 timer rd_0 general register d0 ffffh 0019fh 001a0h trdcr1_0 timer rd_0 control register 1 00h 001a1h trdiora1_0 timer rd_0 i/o control register a1 10001000b 001a2h trdiorc1_0 timer rd_0 i/o control register c1 10001000b 001a3h trdsr1_0 timer rd_0 status register 1 11000000b 001a4h trdier1_0 timer rd_0 interrupt enable register 1 11100000b 001a5h trdpocr1_0 timer rd_0 pwm mode output level control register 1 11111000b 001a6h trd1_0 timer rd_0 counter 1 0000h 001a7h 001a8h trdgra1_0 timer rd_0 general register a1 ffffh 001a9h 001aah trdgrb1_0 timer rd_0 general register b1 ffffh 001abh 001ach trdgrc1_0 timer rd_0 general register c1 ffffh 001adh 001aeh trdgrd1_0 timer rd_0 general register d1 ffffh 001afh 001b0h to 001ffh r8c/54e group, r8c/54f gr oup, r8c/54g group, r8c/54 h group 3. address space under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 37 of 52 mar 15, 2011 note: 1. the blank areas are reserved. no access is allowed. table 3.8 sfr information (8) (1) address symbol register name after reset remarks 00200h ad0 a/d register 0 00h 00201h 00h 00202h ad1 a/d register 1 00h 00203h 00h 00204h ad2 a/d register 2 00h 00205h 00h 00206h ad3 a/d register 3 00h 00207h 00h 00208h ad4 a/d register 4 00h 00209h 00h 0020ah ad5 a/d register 5 00h 0020bh 00h 0020ch ad6 a/d register 6 00h 0020dh 00h 0020eh ad7 a/d register 7 00h 0020fh 00h 00210h 00211h 00212h 00213h 00214h admod a/d mode register 00h 00215h adinsel a/d input se lect register 11000000b 00216h adcon0 a/d control register 0 00h 00217h adcon1 a/d control register 1 00h 00218h 00219h 0021ah 0021bh 0021ch 0021dh 0021eh 0021fh 00220h 00221h 00222h 00223h 00224h 00225h 00226h 00227h 00228h intcmp comparator b control register 0 00h 00229h 0022ah 0022bh 0022ch 0022dh 0022eh 0022fh 00230h inten external input enable register 0 00h 00231h inten1 external input enable register 1 00h 00232h intf int input filter select register 0 00h 00233h intf1 int input filter select register 1 00h 00234h intpol int input pola rity switch register 00h 00235h 00236h kien key input interrupt enable register 00h 00237h 00238h mstcr0 module standby control register 0 00h 00239h mstcr1 module standby control register 1 00h 0023ah mstcr2 module standby control register 2 00h 0023bh mstcr3 module standby control register 3 00h 0023ch 0023dh 0023eh 0023fh r8c/54e group, r8c/54f gr oup, r8c/54g group, r8c/54 h group 3. address space under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 38 of 52 mar 15, 2011 x: undefined note: 1. the blank areas are reserved. no access is allowed. table 3.9 sfr information (9) (1) address symbol register name after reset remarks 00240h 00241h 00242h 00243h 00244h 00245h 00246h 00247h 00248h 00249h 0024ah 0024bh 0024ch 0024dh 0024eh 0024fh 00250h 00251h 00252h fst flash memory status register 10000x00b 00253h 00254h fmr0 flash memory control register 0 00h 00255h fmr1 flash memory control register 1 00h 00256h fmr2 flash memory control register 2 00h 00257h 00258h 00259h 0025ah 0025bh 0025ch 0025dh 0025eh 0025fh 00260h aiadr0l address match interrupt address 0l register xxxxh 00261h 00262h aiadr0h address match interrupt address 0h register 0000xxxxb 00263h aien0 address match interrupt enable 0 register 00h 00264h aiadr1l address match interrupt address 1l register xxxxh 00265h 00266h aiadr1h address match interrupt address 1h register 0000xxxxb 00267h aien1 address match interrupt enable 1 register 00h 00268h 00269h 0026ah 0026bh 0026ch 0026dh 0026eh 0026fh 00270h 00271h 00272h 00273h 00274h 00275h 00276h 00277h 00278h 00279h 0027ah 0027bh 0027ch 0027dh 0027eh 0027fh r8c/54e group, r8c/54f gr oup, r8c/54g group, r8c/54 h group 3. address space under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 39 of 52 mar 15, 2011 note: 1. the blank areas are reserved. no access is allowed. table 3.10 sfr information (10) (1) address symbol register name after reset remarks 00280h dtctl dtc activation control register 00h 00281h 00282h 00283h 00284h 00285h 00286h 00287h 00288h dtcen0 dtc activation enable register 0 00h 00289h dtcen1 dtc activation enable register 1 00h 0028ah dtcen2 dtc activation enable register 2 00h 0028bh dtcen3 dtc activation enable register 3 00h 0028ch dtcen4 dtc activation enable register 4 00h 0028dh dtcen5 dtc activation enable register 5 00h 0028eh dtcen6 dtc activation enable register 6 00h 0028fh 00290h crcsar sfr snoop address register 0000h 00291h 00292h crcmr crc control register 00h 00293h 00294h crcd crc data register 0000h 00295h 00296h crcin crc input register 00h 00297h 00298h 00299h 0029ah 0029bh 0029ch 0029dh 0029eh 0029fh 002a0h trj_0sr timer rj_0 pin select register 00h 002a1h trj_1sr timer rj_1 pin select register 00h 002a2h 002a3h 002a4h trbsr timer rb2 pin select register 00h 002a5h trcclksr timer rcclk pin select register 00h 002a6h trc_0sr0 timer rc_0 pin select register 0 00h 002a7h trc_0sr1 timer rc_0 pin select register 1 00h 002a8h 002a9h trd_0sr0 timer rd_0 pin select register 0 00h 002aah trd_0sr1 timer rd_0 pin select register 1 00h 002abh 002ach 002adh timsr timer pin select register 00h 002aeh u_0sr uart0_0 pin select register 00h 002afh u_1sr uart0_1 pin select register 00h 002b0h 002b1h 002b2h u2sr0 uart2 pin select register 0 00h 002b3h u2sr1 uart2 pin select register 1 00h 002b4h ssuiic_0sr ssu/iic_0 pin select register 00h 002b5h 002b6h intsr0 int interrupt input pin select register 0 00h 002b7h 002b8h 002b9h pinsr i/o function pin select register 00h 002bah 002bbh 002bch 002bdh 002beh pmcsel pin assignment select register 00h 002bfh r8c/54e group, r8c/54f gr oup, r8c/54g group, r8c/54 h group 3. address space under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 40 of 52 mar 15, 2011 note: 1. the blank areas are reserved. no access is allowed. table 3.11 sfr information (11) (1) address symbol register name after reset remarks 002c0h pur0 pull-up control register 0 00h 002c1h pur1 pull-up control register 1 00h 002c2h pur2 pull-up control register 2 00h 002c3h 002c4h 002c5h 002c6h 002c7h 002c8h p1drr port p1 drive capacity control register 00h 002c9h p2drr port p2 drive capacity control register 00h 002cah 002cbh 002cch drr0 drive capacity control register 0 00h 002cdh drr1 drive capacity control register 1 00h 002ceh drr2 drive capacity control register 2 00h 002cfh 002d0h vlt0 input threshold control register 0 00h 002d1h vlt1 input threshold control register 1 00h 002d2h vlt2 input threshold control register 2 00h 002d3h 002d4h 002d5h 002d6h 002d7h 002d8h 002d9h 002dah 002dbh 002dch 002ddh 002deh 002dfh 002e0h port0 port p0 register xxh 002e1h port1 port p1 register xxh 002e2h pd0 port p0 direction register 00h 002e3h pd1 port p1 direction register 00h 002e4h port2 port p2 register xxh 002e5h port3 port p3 register xxh 002e6h pd2 port p2 direction register 00h 002e7h pd3 port p3 direction register 00h 002e8h port4 port p4 register xxh 002e9h 002eah pd4 port p4 direction register 00h 002ebh 002ech port6 port p6 register xxh 002edh 002eeh pd6 port p6 direction register 00h 002efh 002f0h 002f1h port9 port p9 register xxh 002f2h 002f3h pd9 port p9 direction register 00h 002f4h 002f5h 002f6h 002f7h 002f8h 002f9h 002fah 002fbh 002fch 002fdh 002feh 002ffh 00300h to 003ffh on-chip ram for firmware on-chip ram for firmware r8c/54e group, r8c/54f gr oup, r8c/54g group, r8c/54 h group 3. address space under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 41 of 52 mar 15, 2011 x: undefined note: 1. the blank areas are reserved. no access is allowed. table 3.12 sfr information (12) (1) address symbol register name after reset remarks 00400h to 02bffh on-chip ram on-chip ram 02c00h to 069ffh 06a00h elselr0 event output destin ation select register 0 00h 06a01h elselr1 event output destin ation select register 1 00h 06a02h elselr2 event output destin ation select register 2 00h 06a03h elselr3 event output destin ation select register 3 00h 06a04h elselr4 event output destin ation select register 4 00h 06a05h 06a06h 06a07h 06a08h elselr8 event output destin ation select register 8 00h 06a09h elselr9 event output destin ation select register 9 00h 06a0ah elselr10 event output dest ination select register 10 00h 06a0bh elselr11 event output dest ination select register 11 00h 06a0ch elselr12 event output dest ination select register 12 00h 06a0dh elselr13 event output dest ination select register 13 00h 06a0eh elselr14 event output dest ination select register 14 00h 06a0fh elselr15 event output dest ination select register 15 00h 06a10h elselr16 event output dest ination select register 16 00h 06a11h elselr17 event output dest ination select register 17 00h 06a12h elselr18 event output dest ination select register 18 00h 06a13h elselr19 event output dest ination select register 19 00h 06a14h elselr20 event output dest ination select register 20 00h 06a15h elselr21 event output dest ination select register 21 00h 06a16h elselr22 event output dest ination select register 22 00h 06a17h elselr23 event output dest ination select register 23 00h 06a18h elselr24 event output dest ination select register 24 00h 06a19h 06a1ah 06a1bh 06a1ch 06a1dh 06a1eh 06a1fh 06a20h 06a21h 06a22h 06a23h 06a24h 06a25h 06a26h 06a27h 06a28h 06a29h 06a2ah 06a2bh 06a2ch 06a2dh 06a2eh 06a2fh 06a30h 06a31h to 06bffh 06c00h area for storing dtc transfer vector 0 xxh 06c01h area for storing dtc transfer vector 1 xxh 06c02h area for storing dtc transfer vector 2 xxh 06c03h area for storing dtc transfer vector 3 xxh 06c04h area for storing dtc transfer vector 4 xxh 06c05h 06c06h 06c07h 06c08h area for storing dtc transfer vector 8 xxh 06c09h area for storing dtc transfer vector 9 xxh r8c/54e group, r8c/54f gr oup, r8c/54g group, r8c/54 h group 3. address space under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 42 of 52 mar 15, 2011 x: undefined note: 1. the blank areas are reserved. no access is allowed. table 3.13 sfr information (13) (1) address symbol register name after reset remarks 06c0ah area for storing dtc transfer vector 10 xxh 06c0bh area for storing dtc transfer vector 11 xxh 06c0ch area for storing dtc transfer vector 12 xxh 06c0dh area for storing dtc transfer vector 13 xxh 06c0eh area for storing dtc transfer vector 14 xxh 06c0fh area for storing dtc transfer vector 15 xxh 06c10h area for storing dtc transfer vector 16 xxh 06c11h area for storing dtc transfer vector 17 xxh 06c12h area for storing dtc transfer vector 18 xxh 06c13h area for storing dtc transfer vector 19 xxh 06c14h area for storing dtc transfer vector 20 xxh 06c15h area for storing dtc transfer vector 21 xxh 06c16h area for storing dtc transfer vector 22 xxh 06c17h area for storing dtc transfer vector 23 xxh 06c18h area for storing dtc transfer vector 24 xxh 06c19h area for storing dtc transfer vector 25 xxh 06c1ah area for storing dtc transfer vector 26 xxh 06c1bh area for storing dtc transfer vector 27 xxh 06c1ch area for storing dtc transfer vector 28 xxh 06c1dh area for storing dtc transfer vector 29 xxh 06c1eh area for storing dtc transfer vector 30 xxh 06c1fh area for storing dtc transfer vector 31 xxh 06c20h area for storing dtc transfer vector 32 xxh 06c21h area for storing dtc transfer vector 33 xxh 06c22h 06c23h 06c24h 06c25h 06c26h area for storing dtc transfer vector 38 xxh 06c27h area for storing dtc transfer vector 39 xxh 06c28h 06c29h 06c2ah area for storing dtc transfer vector 42 xxh 06c2bh 06c2ch 06c2dh 06c2eh 06c2fh 06c30h 06c31h area for storing dtc transfer vector 49 xxh 06c32h area for storing dtc transfer vector 50 xxh 06c33h area for storing dtc transfer vector 51 xxh 06c34h area for storing dtc transfer vector 52 xxh 06c35h 06c36h 06c37h 06c38h 06c39h 06c3ah 06c3bh 06c3ch 06c3dh 06c3eh 06c3fh 06c40h dtccr0 dtc control register 0 xxh 06c41h dtbls0 dtc block size register 0 xxh 06c42h dtcct0 dtc transfer count register 0 xxh 06c43h dtrld0 dtc transfer count reload register 0 xxh 06c44h dtsar0 dtc source address register 0 xxxxh 06c45h 06c46h dtdar0 dtc destinati on address register 0 xxxxh 06c47h 06c48h dtccr1 dtc control register 1 xxh 06c49h dtbls1 dtc block size register 1 xxh r8c/54e group, r8c/54f gr oup, r8c/54g group, r8c/54 h group 3. address space under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 43 of 52 mar 15, 2011 x: undefined note: 1. the blank areas are reserved. no access is allowed. table 3.14 sfr information (14) (1) address symbol register name after reset remarks 06c4ah dtcct1 dtc transfer count register 1 xxh 06c4bh dtrld1 dtc transfer count reload register 1 xxh 06c4ch dtsar1 dtc source address register 1 xxxxh 06c4dh 06c4eh dtdar1 dtc destination address register 1 xxxxh 06c4fh 06c50h dtccr2 dtc control register 2 xxh 06c51h dtbls2 dtc block size register 2 xxh 06c52h dtcct2 dtc transfer count register 2 xxh 06c53h dtrld2 dtc transfer count reload register 2 xxh 06c54h dtsar2 dtc source address register 2 xxxxh 06c55h 06c56h dtdar2 dtc destinati on address register 2 xxxxh 06c57h 06c58h dtccr3 dtc control register 3 xxh 06c59h dtbls3 dtc block size register 3 xxh 06c5ah dtcct3 dtc transfer count register 3 xxh 06c5bh dtrld3 dtc transfer count reload register 3 xxh 06c5ch dtsar3 dtc source address register 3 xxxxh 06c5dh 06c5eh dtdar3 dtc destination address register 3 xxxxh 06c5fh 06c60h dtccr4 dtc control register 4 xxh 06c61h dtbls4 dtc block size register 4 xxh 06c62h dtcct4 dtc transfer count register 4 xxh 06c63h dtrld4 dtc transfer count reload register 4 xxh 06c64h dtsar4 dtc source address register 4 xxxxh 06c65h 06c66h dtdar4 dtc destinati on address register 4 xxxxh 06c67h 06c68h dtccr5 dtc control register 5 xxh 06c69h dtbls5 dtc block size register 5 xxh 06c6ah dtcct5 dtc transfer count register 5 xxh 06c6bh dtrld5 dtc transfer count reload register 5 xxh 06c6ch dtsar5 dtc source address register 5 xxxxh 06c6dh 06c6eh dtdar5 dtc destination address register 5 xxxxh 06c6fh 06c70h dtccr6 dtc control register 6 xxh 06c71h dtbls6 dtc block size register 6 xxh 06c72h dtcct6 dtc transfer count register 6 xxh 06c73h dtrld6 dtc transfer count reload register 6 xxh 06c74h dtsar6 dtc source address register 6 xxxxh 06c75h 06c76h dtdar6 dtc destinati on address register 6 xxxxh 06c77h 06c78h dtccr7 dtc control register 7 xxh 06c79h dtbls7 dtc block size register 7 xxh 06c7ah dtcct7 dtc transfer count register 7 xxh 06c7bh dtrld7 dtc transfer count reload register 7 xxh 06c7ch dtsar7 dtc source address register 7 xxxxh 06c7dh 06c7eh dtdar7 dtc destination address register 7 xxxxh 06c7fh 06c80h dtccr8 dtc control register 8 xxh 06c81h dtbls8 dtc block size register 8 xxh 06c82h dtcct8 dtc transfer count register 8 xxh 06c83h dtrld8 dtc transfer count reload register 8 xxh 06c84h dtsar8 dtc source address register 8 xxxxh 06c85h 06c86h dtdar8 dtc destinati on address register 8 xxxxh 06c87h 06c88h dtccr9 dtc control register 9 xxh 06c89h dtbls9 dtc block size register 9 xxh 06c8ah dtcct9 dtc transfer count register 9 xxh 06c8bh dtrld9 dtc transfer count reload register 9 xxh 06c8ch dtsar9 dtc source address register 9 xxxxh 06c8dh 06c8eh dtdar9 dtc destination address register 9 xxxxh 06c8fh r8c/54e group, r8c/54f gr oup, r8c/54g group, r8c/54 h group 3. address space under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 44 of 52 mar 15, 2011 x: undefined note: 1. the blank areas are reserved. no access is allowed. table 3.15 sfr information (15) (1) address symbol register name after reset remarks 06c90h dtccr10 dtc control register 10 xxh 06c91h dtbls10 dtc block size register 10 xxh 06c92h dtcct10 dtc transfer count register 10 xxh 06c93h dtrld10 dtc transfer count reload register 10 xxh 06c94h dtsar10 dtc source address register 10 xxxxh 06c95h 06c96h dtdar10 dtc destination address register 10 xxxxh 06c97h 06c98h dtccr11 dtc control register 11 xxh 06c99h dtbls11 dtc block size register 11 xxh 06c9ah dtcct11 dtc transfer count register 11 xxh 06c9bh dtrld11 dtc transfer count reload register 11 xxh 06c9ch dtsar11 dtc source address register 11 xxxxh 06c9dh 06c9eh dtdar11 dtc destinati on address register 11 xxxxh 06c9fh 06ca0h dtccr12 dtc control register 12 xxh 06ca1h dtbls12 dtc block size register 12 xxh 06ca2h dtcct12 dtc transfer count register 12 xxh 06ca3h dtrld12 dtc transfer count reload register 12 xxh 06ca4h dtsar12 dtc source address register 12 xxxxh 06ca5h 06ca6h dtdar12 dtc destinati on address register 12 xxxxh 06ca7h 06ca8h dtccr13 dtc control register 13 xxh 06ca9h dtbls13 dtc block size register 13 xxh 06caah dtcct13 dtc transfer count register 13 xxh 06cabh dtrld13 dtc transfer count reload register 13 xxh 06cach dtsar13 dtc source address register 13 xxxxh 06cadh 06caeh dtdar13 dtc destination address register 13 xxxxh 06cafh 06cb0h dtccr14 dtc control register 14 xxh 06cb1h dtbls14 dtc block size register 14 xxh 06cb2h dtcct14 dtc transfer count register 14 xxh 06cb3h dtrld14 dtc transfer count reload register 14 xxh 06cb4h dtsar14 dtc source address register 14 xxxxh 06cb5h 06cb6h dtdar14 dtc destinati on address register 14 xxxxh 06cb7h 06cb8h dtccr15 dtc control register 15 xxh 06cb9h dtbls15 dtc block size register 15 xxh 06cbah dtcct15 dtc transfer count register 15 xxh 06cbbh dtrld15 dtc transfer count reload register 15 xxh 06cbch dtsar15 dtc source address register 15 xxxxh 06cbdh 06cbeh dtdar15 dtc destination address register 15 xxxxh 06cbfh 06cc0h dtccr16 dtc control register 16 xxh 06cc1h dtbls16 dtc block size register 16 xxh 06cc2h dtcct16 dtc transfer count register 16 xxh 06cc3h dtrld16 dtc transfer count reload register 16 xxh 06cc4h dtsar16 dtc source address register 16 xxxxh 06cc5h 06cc6h dtdar16 dtc destinati on address register 16 xxxxh 06cc7h 06cc8h dtccr17 dtc control register 17 xxh 06cc9h dtbls17 dtc block size register 17 xxh 06ccah dtcct17 dtc transfer count register 17 xxh 06ccbh dtrld17 dtc transfer count reload register 17 xxh 06ccch dtsar17 dtc source address register 17 xxxxh 06ccdh 06cceh dtdar17 dtc destinati on address register 17 xxxxh 06ccfh r8c/54e group, r8c/54f gr oup, r8c/54g group, r8c/54 h group 3. address space under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 45 of 52 mar 15, 2011 x: undefined note: 1. the blank areas are reserved. no access is allowed. table 3.16 sfr information (16) (1) address symbol register name after reset remarks 06cd0h dtccr18 dtc control register 18 xxh 06cd1h dtbls18 dtc block size register 18 xxh 06cd2h dtcct18 dtc transfer count register 18 xxh 06cd3h dtrld18 dtc transfer count reload register 18 xxh 06cd4h dtsar18 dtc source address register 18 xxxxh 06cd5h 06cd6h dtdar18 dtc destinati on address register 18 xxxxh 06cd7h 06cd8h dtccr19 dtc control register 19 xxh 06cd9h dtbls19 dtc block size register 19 xxh 06cdah dtcct19 dtc transfer count register 19 xxh 06cdbh dtrld19 dtc transfer count reload register 19 xxh 06cdch dtsar19 dtc source address register 19 xxxxh 06cddh 06cdeh dtdar19 dtc destinati on address register 19 xxxxh 06cdfh 06ce0h dtccr20 dtc control register 20 xxh 06ce1h dtbls20 dtc block size register 20 xxh 06ce2h dtcct20 dtc transfer count register 20 xxh 06ce3h dtrld20 dtc transfer count reload register 20 xxh 06ce4h dtsar20 dtc source address register 20 xxxxh 06ce5h 06ce6h dtdar20 dtc destinati on address register 20 xxxxh 06ce7h 06ce8h dtccr21 dtc control register 21 xxh 06ce9h dtbls21 dtc block size register 21 xxh 06ceah dtcct21 dtc transfer count register 21 xxh 06cebh dtrld21 dtc transfer count reload register 21 xxh 06cech dtsar21 dtc source address register 21 xxxxh 06cedh 06ceeh dtdar21 dtc destination address register 21 xxxxh 06cefh 06cf0h dtccr22 dtc control register 22 xxh 06cf1h dtbls22 dtc block size register 22 xxh 06cf2h dtcct22 dtc transfer count register 22 xxh 06cf3h dtrld22 dtc transfer count reload register 22 xxh 06cf4h dtsar22 dtc source address register 22 xxxxh 06cf5h 06cf6h dtdar22 dtc destination address register 22 xxxxh 06cf7h 06cf8h dtccr23 dtc control register 23 xxh 06cf9h dtbls23 dtc block size register 23 xxh 06cfah dtcct23 dtc transfer count register 23 xxh 06cfbh dtrld23 dtc transfer count reload register 23 xxh 06cfch dtsar23 dtc source address register 23 xxxxh 06cfdh 06cfeh dtdar23 dtc destinati on address register 23 xxxxh 06cffh 06d00h to 06dffh 06e00h cmb0_0 can_0 mailbox 0 xxh 06e01h xxh 06e02h xxh 06e03h xxh 06e04h xxh 06e05h xxh 06e06h xxh 06e07h xxh 06e08h xxh 06e09h xxh 06e0ah xxh 06e0bh xxh 06e0ch xxh 06e0dh xxh 06e0eh xxh 06e0fh xxh r8c/54e group, r8c/54f gr oup, r8c/54g group, r8c/54 h group 3. address space under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 46 of 52 mar 15, 2011 x: undefined note: 1. the blank areas are reserved. no access is allowed. table 3.17 sfr information (17) (1) address symbol register name after reset remarks 06e10h cmb1_0 can_0 mailbox 1 xxh 06e11h xxh 06e12h xxh 06e13h xxh 06e14h xxh 06e15h xxh 06e16h xxh 06e17h xxh 06e18h xxh 06e19h xxh 06e1ah xxh 06e1bh xxh 06e1ch xxh 06e1dh xxh 06e1eh xxh 06e1fh xxh 06e20h cmb2_0 can_0 mailbox 2 xxh 06e21h xxh 06e22h xxh 06e23h xxh 06e24h xxh 06e25h xxh 06e26h xxh 06e27h xxh 06e28h xxh 06e29h xxh 06e2ah xxh 06e2bh xxh 06e2ch xxh 06e2dh xxh 06e2eh xxh 06e2fh xxh 06e30h cmb3_0 can_0 mailbox 3 xxh 06e31h xxh 06e32h xxh 06e33h xxh 06e34h xxh 06e35h xxh 06e36h xxh 06e37h xxh 06e38h xxh 06e39h xxh 06e3ah xxh 06e3bh xxh 06e3ch xxh 06e3dh xxh 06e3eh xxh 06e3fh xxh 06e40h cmb4_0 can_0 mailbox 4 xxh 06e41h xxh 06e42h xxh 06e43h xxh 06e44h xxh 06e45h xxh 06e46h xxh 06e47h xxh 06e 48h xxh 06e 49h xxh 06e4ah xxh 06e4bh xxh 06e4ch xxh 06e4dh xxh 06e4eh xxh 06e4fh xxh r8c/54e group, r8c/54f gr oup, r8c/54g group, r8c/54 h group 3. address space under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 47 of 52 mar 15, 2011 x: undefined note: 1. the blank areas are reserved. no access is allowed. table 3.18 sfr information (18) (1) address symbol register name after reset remarks 06e50h cmb5_0 can_0 mailbox 5 xxh 06e51h xxh 06e52h xxh 06e53h xxh 06e54h xxh 06e55h xxh 06e56h xxh 06e57h xxh 06e58h xxh 06e59h xxh 06e5ah xxh 06e5bh xxh 06e5ch xxh 06e5dh xxh 06e5eh xxh 06e5fh xxh 06e60h cmb6_0 can_0 mailbox 6 xxh 06e61h xxh 06e62h xxh 06e63h xxh 06e64h xxh 06e65h xxh 06e66h xxh 06e67h xxh 06e68h xxh 06e69h xxh 06e6ah xxh 06e6bh xxh 06e6ch xxh 06e6dh xxh 06e6eh xxh 06e6fh xxh 06e70h cmb7_0 can_0 mailbox 7 xxh 06e71h xxh 06e72h xxh 06e73h xxh 06e74h xxh 06e75h xxh 06e76h xxh 06e77h xxh 06e78h xxh 06e79h xxh 06e7ah xxh 06e7bh xxh 06e7ch xxh 06e7dh xxh 06e7eh xxh 06e7fh xxh 06e80h cmb8_0 can_0 mailbox 8 xxh 06e81h xxh 06e82h xxh 06e83h xxh 06e84h xxh 06e85h xxh 06e86h xxh 06e87h xxh 06e88h xxh 06e 89h xxh 06 e8ah xxh 06e8bh xxh 06e8ch xxh 06e8dh xxh 06e8eh xxh 06e8fh xxh r8c/54e group, r8c/54f gr oup, r8c/54g group, r8c/54 h group 3. address space under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 48 of 52 mar 15, 2011 x: undefined note: 1. the blank areas are reserved. no access is allowed. table 3.19 sfr information (19) (1) address symbol register name after reset remarks 06e90h cmb9_0 can_0 mailbox 9 xxh 06e91h xxh 06e92h xxh 06e93h xxh 06e94h xxh 06e95h xxh 06e96h xxh 06e97h xxh 06e98h xxh 06e99h xxh 06e9ah xxh 06e9bh xxh 06e9ch xxh 06e9dh xxh 06e9eh xxh 06e9fh xxh 06ea0h cmb10_0 can_0 mailbox 10 xxh 06ea1h xxh 06ea2h xxh 06ea3h xxh 06ea4h xxh 06ea5h xxh 06ea6h xxh 06ea7h xxh 06ea8h xxh 06ea9h xxh 06eaah xxh 06eabh xxh 06each xxh 06eadh xxh 06eaeh xxh 06eafh xxh 06eb0h cmb11_0 can_0 mailbox 11 xxh 06eb1h xxh 06eb2h xxh 06eb3h xxh 06eb4h xxh 06eb5h xxh 06eb6h xxh 06eb7h xxh 06eb8h xxh 06eb9h xxh 06ebah xxh 06ebbh xxh 06ebch xxh 06ebdh xxh 06ebeh xxh 06ebfh xxh 06ec0h cmb12_0 can_0 mailbox 12 xxh 06ec1h xxh 06ec2h xxh 06ec3h xxh 06ec4h xxh 06ec5h xxh 06ec6h xxh 06ec7h xxh 06ec8h xxh 06ec9 h xxh 06 ecah xxh 06ecbh xxh 06ecch xxh 06ecdh xxh 06eceh xxh 06ecfh xxh r8c/54e group, r8c/54f gr oup, r8c/54g group, r8c/54 h group 3. address space under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 49 of 52 mar 15, 2011 x: undefined note: 1. the blank areas are reserved. no access is allowed. table 3.20 sfr information (20) (1) address symbol register name after reset remarks 06ed0h cmb13_0 can_0 mailbox 13 xxh 06ed1h xxh 06ed2h xxh 06ed3h xxh 06ed4h xxh 06ed5h xxh 06ed6h xxh 06ed7h xxh 06ed8h xxh 06ed9h xxh 06edah xxh 06edbh xxh 06edch xxh 06eddh xxh 06edeh xxh 06edfh xxh 06ee0h cmb14_0 can_0 mailbox 14 xxh 06ee1h xxh 06ee2h xxh 06ee3h xxh 06ee4h xxh 06ee5h xxh 06ee6h xxh 06ee7h xxh 06ee8h xxh 06ee9h xxh 06eeah xxh 06eebh xxh 06eech xxh 06eedh xxh 06eeeh xxh 06eefh xxh 06ef0h cmb15_0 can_0 mailbox 15 xxh 06ef1h xxh 06ef2h xxh 06ef3h xxh 06ef4h xxh 06ef5h xxh 06ef6h xxh 06ef7h xxh 06ef8h xxh 06ef9h xxh 06efah xxh 06efbh xxh 06efch xxh 06efdh xxh 06efeh xxh 06effh xxh 06f00h 06f01h 06f02h 06f03h 06f04h 06f05h 06f06h 06f07h 06f08h 06f09h 06f0ah 06f0bh 06f0ch 06f0dh 06f0eh 06f0fh r8c/54e group, r8c/54f gr oup, r8c/54g group, r8c/54 h group 3. address space under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 50 of 52 mar 15, 2011 x: undefined note: 1. the blank areas are reserved. no access is allowed. table 3.21 sfr information (21) (1) address symbol register name after reset remarks 06f10h cmkr0_0 can_0 mask register 0 xxh 06f11h xxh 06f12h xxh 06f13h xxh 06f14h cmkr1_0 can_0 mask register 1 xxh 06f15h xxh 06f16h xxh 06f17h xxh 06f18h cmkr2_0 can_0 mask register 2 xxh 06f19h xxh 06f1ah xxh 06f1bh xxh 06f1ch cmkr3_0 can_0 mask register 3 xxh 06f1dh xxh 06f1eh xxh 06f1fh xxh 06f20h cfidcr0_0 can_0 fifo receiv ed id compare register 0 xxh 06f21h xxh 06f22h xxh 06f23h xxh 06f24h cfidcr1_0 can_0 fifo receiv ed id compare register 1 xxh 06f25h xxh 06f26h xxh 06f27h xxh 06f28h 06f29h 06f2ah cmkivlr_0 can_0 mask invalid register xxh 06f2bh xxh 06f2ch 06f2dh 06f2eh cmier_0 can_0 mailbox interrupt enable register xxh 06f2fh xxh 06f30h cmctl0_0 can_0 message control register 0 00h 06f31h cmctl1_0 can_0 message control register 1 00h 06f32h cmctl2_0 can_0 message control register 2 00h 06f33h cmctl3_0 can_0 message control register 3 00h 06f34h cmctl4_0 can_0 message control register 4 00h 06f35h cmctl5_0 can_0 message control register 5 00h 06f36h cmctl6_0 can_0 message control register 6 00h 06f37h cmctl7_0 can_0 message control register 7 00h 06f38h cmctl8_0 can_0 message control register 8 00h 06f39h cmctl9_0 can_0 message control register 9 00h 06f3ah cmctl10_0 can_0 message control register 10 00h 06f3bh cmctl11_0 can_0 message control register 11 00h 06f3ch cmctl12_0 can_0 message control register 12 00h 06f3dh cmctl13_0 can_0 message control register 13 00h 06f3eh cmctl14_0 can_0 message control register 14 00h 06f3fh cmctl15_0 can_0 message control register 15 00h 06f40h cctlr_0 can_0 control register 00000101b 06f41h 00h 06f42h cstr_0 can_0 status register 00000101b 06f43h 00h 06f44h cbcr_0 can_0 bit configuration register 00h 06f45h 00h 06f46h 00h 06f47h cclkr_0 can_0 clock select register 00h 06f48h crfcr_0 can_0 receive fifo control register 10000000b 06f49h crfpcr_0 can_0 receive fi fo pointer control register xxh 06f4ah ctfcr_0 can_0 transmit fifo control register 10000000b 06f4bh ctfpcr_0 can_0 transmit fifo pointer control register xxh 06f4ch ceier_0 can_0 error interrupt enable register 00h 06f4dh ceifr_0 can_0 error interrupt factor judge register 00h 06f4eh crecr_0 can_0 receive error count register 00h 06f4fh ctecr_0 can_0 transmit error count register 00h r8c/54e group, r8c/54f gr oup, r8c/54g group, r8c/54 h group 3. address space under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 51 of 52 mar 15, 2011 x: undefined note: 1. the blank areas are reserved. no access is allowed. note: 1. the option function select area is allocat ed in the flash memory, not in the sfrs. set appropriate values as rom data by a pr ogram. do not perform any additional writes to t he option function select area. erasure of t he block including the option function sel ect area will cause the option function select area to be set to ffh. table 3.22 sfr information (22) (1) address symbol register name after reset remarks 06f50h cecsr_0 can_0 error code store register 00h 06f51h ccssr_0 can_0 channel search support register xxh 06f52h cmssr_0 can_0 mailbox search status register 10000000b 06f53h cmsmr_0 can_0 mailbox search mode register 00h 06f54h ctsr_0 can_0 time stamp register 0000h 06f55h 06f56h cafsr_0 can_0 acceptance filter support register xxh 06f57h xxh 06f58h ctcr_0 can_0 test control register 00h 06f59h 06f5ah 06f5bh 06f5ch 06f5dh 06f5eh 06f5fh 06f60h 06f61h 06f62h 06f63h 06f64h 06f65h 06f66h 06f67h 06f68h 06f69h 06f6ah 06f6bh 06f6ch 06f6dh 06f6eh 06f6fh 06f70h 06f71h 06f72h 06f73h 06f74h 06f75h 06f76h 06f77h 06f78h 06f79h 06f7ah 06f7bh 06f7ch 06f7dh 06f7eh canisr_0 can_0 interrupt status register 00h 06f7fh canie_0 can_0 interru pt control register 00h 06f80h to 06fffh table 3.23 id code area, option function select area address symbol area name after reset address size : 0ffdbh ofs2 option function select register 2 : 0ffffh ofs option function select register r8c/54e group, r8c/54f group, r8c/54g group, r8c/54h group appendix 1. package dimensions under development preliminary document specifications in this document are tentative and subject to change. r01ds0043ej0010 rev.0.10 page 52 of 52 mar 15, 2011 appendix 1. package dimensions diagrams showing the latest package dimensions and moun ting information are available in the ?p ackages? section of the renesas electronics website. terminal cross section b 1 c 1 bp c 2. 1. dimensions " *1" and "*2" do not include mold flash. note) dimension "*3" does not include trim offset. detail f l 1 c a l a 1 a 2 *3 f 48 37 36 25 24 13 12 1 *1 *2 x index mark z e z d b p e h e h d d e previous code jeita package code renesas code plqp0048kb-a 48p6q-a mass[typ.] 0.2g p-lqfp48-7x7-0.50 1.0 0.125 0.20 0.75 0.75 0.08 0.20 0.145 0.09 0.270.22 0.17 maxnommin dimension in millimeters symbol reference 7.17.06.9 d 7.17.06.9 e 1.4 a 2 9.2 9.08.8 9.2 9.08.8 1.7 a 0.2 0.1 0 0.65 0.5 0.35 l x 8 0 c 0.5 e 0.10 y h d h e a 1 b p b 1 c 1 z d z e l 1 y s s c - 1 r8c/54e group, r8c/54f group, r8c/ 54g group, r8c/54h group datasheet rev. date description page summary 0.01 dec 17, 2010 ? first edition issued 0.10 mar 15, 2011 1 to 22 1. overview r8c/54f group, r8c/54g group, and r8c/54h group added 27 to 29 3.2, 3.3, and 3.4 added 40 table 3.11 port register symbol revised all trademarks and registered trademarks are the property of their respective owners. revision history general precautions in the handling of mpu/mcu products the following usage notes are applicable to all mpu/mcu products from renesas. for detailed usage notes on the products covered by this manual, refer to the rele vant sections of the manu al. if the descriptions under general precautions in the handling of mpu/mcu products and in the body of the manual differ from each other, the description in the bod y of the manual takes precedence. 1. handling of unused pins handle unused pins in accord with the directions given under handling of unused pins in the manual. ? the input pins of cmos products are general ly in the high-impedance state. in operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of lsi, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power-on the state of the product is undefined at the moment when power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. in a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. in a similar way, the states of pins in a pr oduct that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provided for the po ssible future expansion of functions. do not access these addresses; the correct operat ion of lsi is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during pr ogram execution, wait until the target clock signal has stabilized. ? when the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset li ne is only released after full stabilization of the clock signal. moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. differences between products before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems. ? the characteristics of mpu/mcu in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. when changing to products of different part numbe rs, implement a system-evaluation test for each of the products. notice 1. all information included in this document is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas electronics products listed herein, please confirm the latest product information with a renesas electronics sales office. also, please pay regular and careful attention to additional and different information to be disclosed by renesas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of renesas electronics products or technical information described in this document. no license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . 4. descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. you should not use renesas electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 7. renesas electronics products are classified according to the following three quality grades: "standard", "high quality", and "specific". the recommended applications for each renesas electronics product depends on the product's quality grade, as indicated below. you must check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application categorized as "specific" without the prior written consent of renesas electronics. further, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for an application categorized as "specific" or for which the product is not intended where you have failed to obtain the prior written consent of renesas electronics. the quality grade of each renesas electronics product is "standard" unless otherwise expressly specified in a renesas electronics data sheets or data books, etc. "standard": computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. "high quality": transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically designed for life support. "specific": aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life. 8. you should use the renesas electronics products described in this document within the range specified by renesas electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions or damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. further, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatibility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of renesas electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this document or renesas electronics products, or if you have any other inquiries. (note 1) "renesas electronics" as used in this document means renesas electronics corporation and also includes its majority-owned subsidiaries. (note 2) "renesas electronics product(s)" means any product developed or manufactured by or for renesas electronics. http://www.renesas.com refer to "http://www.renesas.com/" for the latest and detailed information. renesas electronics america inc. 2880 scott boulevard santa clara, ca 95050-2554, u.s.a. tel: +1-408-588-6000, fax: +1-408-588-6130 renesas electronics canada limited 1101 nicholson road, newmarket, ontario l3y 9c3, canada tel: +1-905-898-5441, fax: +1-905-898-3220 renesas electronics europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k tel: +44-1628-585-100, fax: +44-1628-585-900 renesas electronics europe gmbh arcadiastrasse 10, 40472 dsseldorf, germany tel: +49-211-65030, fax: +49-211-6503-1327 renesas electronics (china) co., ltd. 7th floor, quantum plaza, no.27 zhichunlu haidian district, beijing 100083, p.r.china tel: +86-10-8235-1155, fax: +86-10-8235-7679 renesas electronics (shanghai) co., ltd. unit 204, 205, azia center, no.1233 lujiazui ring rd., pudong district, shanghai 200120, china tel: +86-21-5877-1818, fax: +86-21-6887-7858 / -7898 renesas electronics hong kong limited unit 1601-1613, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: +852-2886-9318, fax: +852 2886-9022/9044 renesas electronics taiwan co., ltd. 13f, no. 363, fu shing north road, taipei, taiwan tel: +886-2-8175-9600, fax: +886 2-8175-9670 renesas electronics singapore pte. ltd. 1 harbourfront avenue, #06-10, keppel bay tower, singapore 098632 tel: +65-6213-0200, fax: +65-6278-8001 renesas electronics malaysia sdn.bhd. unit 906, block b, menara amcorp, amcorp trade centre, no. 18, jln persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: +60-3-7955-9390, fax: +60-3-7955-9510 renesas electronics korea co., ltd. 11f., samik lavied' or bldg., 720-2 yeoksam-dong, kangnam-ku, seoul 135-080, korea tel: +82-2-558-3737, fax: +82-2-558-5141 sales offices ? 2011 renesas electronics corporation. all rights reserved. colophon 1.1 |
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