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the sl1711 is a quadrature downconverter, intended primarily for application in professional and consumer digital satellite tuners. the device contains all elements necessary, with the exception of external local oscillator tank to form a complete system operating at standard satellite receiver intermediate frequencies. it is intended for use with external carrier recovery. the device includes a low noise rf input amplifier, a reference vco with prescaler output buffer and in-phase and quadrature mixers with baseband buffer amplifiers containing agc gain control. the sl1711 is optimised to drive a dual adc converter such as the vp216. the sl1711 utilises a power mp package, whereas the SL1711B variant uses a standard mp16 plastic package and features a revised operating temperature. features n single chip system for wideband quadrature downconversion n compatible with all standard high if frequencies n excellent gain and phase match up to 30mhz baseband n high output referred linearity for low distortion and multi channel application n simple low component application n fully balanced low radiation design with fully integrated quadrature generation n high operating input sensitivity n on-board agc facility n on chip oscillator for varactor tuning or saw resonator operation n esd protection (normal esd handling procedures should be observed) mh16 sl1711 116 vccc agc iout veea ifinb ifin ivcca qout veec vccb vcodis vco b vco a veeb pscal pscalb applications n satellite receiver systems n data communications systems n cable systems ordering information sl1711/kg/mh1p (sticks) sl1711/kg/mh1q (tape and reel) SL1711B/kg/mp1s (sticks) SL1711B/kg/mp1t (tape and reel) fig. 1 pin allocation mp16 SL1711B 116 vccc agc iout veea ifinb ifin ivcca qout veec vccb vcodis vco b vco a veeb pscal pscalb sl1711 quadrature downconverter preliminary information supersedes november 1996 version, ds4032 - 1.6 ds4032 - 4.0 october 1997
2 sl1711 quick reference data characteristic value units input noise figure, dsb 17 db maximum conversion gain 44 db minimum conversion gain 28 db ip3 2t output referred +8 dbv output clip voltage 1.5 vp-p gain match up to 22mhz 0.3 db gain match up to 30mhz 0.5 db phase match up to 30mhz 1.5 deg gain flatness up to 30mhz 0.5 db vco phase noise, ssb @ 10khz offset - 96 dbc/hz prescaler division ratio 32 prescaler output swing 1.6 vp-p fig. 2 sl1711 block diagram agc ifin vcodis vcoa agc agc ? 32 lo 0 deg 90 deg quadrature generator pscalb pscal q out i out ifinb vcob
3 sl1711 functional description the sl1711 is a wideband quadrature downconverter, optimised for application in both professional and consumer digital satellite receiver systems and requiring a minimum external component count. it contains all the elements required for construction of a quadrature demodulator, with the exception of tank circuit for the local oscillator. a block diagram is shown in fig. 2. the sl1711 oscillator can be used with either a varator tuned tank circuit or with a saw resonator. both configurations are described in the application notes section of this data sheet. a typical digital satellite tuner application from tuner input to data transport stream is shown in fig. 13 in normal application the second satellite if frequency of typically 402.75 or 479.5 mhz is fed from the tuner saw filter to the rf preamplifier, which is optimised for impedance match and signal handling. the amplifier output signal is then split into two balanced channels to drive the in-phase and quadrature mixers. the typical rf input impedance is shown in fig. 3 in-phase and quadrature lo signals for the mixers are derived from the on board local oscillator, which uses an external varactor tuned resonant network and is optimised for low phase noise. the vco also drives an on board divide by 32 prescaler whose outputs can be used for driving an external pll control loop for the vco, where the pll loop is contained within the qpsk demodulator, for example the vp305. for optimum performance in the varactor tuned application the vco should be fully symmetric. the vco has a disable facility by grounding pin 15, vcodis; in normal applications this pin is pulled to vcc via a 4k7 resistor. the mixer outputs are fed to balanced baseband agc amplifier stages, which provide for a minimum of 16 db of agc control. the typical agc characteristic is shown in fig. 4. these amplifiers then feed a low output impedance true differential to single-ended converter output stage. in normal application the output can be either directly ac coupled to the adc converter such as the vp216, which will generally have a high input impedance, or to drive an anti alias filter. in this later case the maximum load presented to the sl1711 must not exceed a parallel combination of 1k w and 20pf. the typical baseband output impedance is contained in fig. 5. it is recommended that the device is operated with an output amplitude of 760mv under lock conditions. under transient conditions the output should not exceed the clipping voltage. input and output interface circuitry is contained in fig. 6. the typical key performance figures at 480 mhz if, 5v vcc, 1 k w load and 25 deg c ambient are contained in table headed 'quick reference data'. with sawr oscillator application the gain and phase match performance will typically exceed these numbers.
4 sl1711 fig.3 typical rf input impedance -j0.2 0 +j0.2 +j0.5 +j1 +j2 -j2 -j1 -j0.5 0.2 0.5 1 start 350 mhz stop 650 mhz marker 1 480mhz zreal = 96 w zimag = 54 w x
5 sl1711 fig.4 typical agc characteristic fig. 5 typical baseband output impedance -j0.2 0 +j0.2 +j0.5 j1 +j2 -j2 -j1 -j0.5 0.2 0.5 1 x x 1 2 1 1mhz 2 15mhz 3 30mhz x 3 conversion gain db 15 20 25 30 35 40 45 50 55 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 3.75 4 4.25 4.5 agc control volts
6 sl1711 if input vco i & q baseband output vco disable input prescaler outputs agc input fig. 6 i/o port peripheral circuitry ifinb ifin vcc o/p o/p vcc vref agc 50k vref vco vco 2x20k vcodis 55k vref
7 sl1711 ch pump 1 xtal1 2 xtal2 3 sda 4 scl 5 p7 6 p6 7 p5 8 p4 9 p3 10 nc 11 vcc 12 rf i/p 13 rf i/p 14 vee 15 drv 16 ic2 sp5611 agc 1 iout 2 veea 3 ifinb 4 ifin 5 vcca 6 qout 7 veec 8 vccc 9 pscalb 10 pscal 11 veeb 12 vcoa 13 vcob 14 vcodis 15 vccb 16 /32 osc i mixer q mixer i c 1 sl1711 l1 12nh c12 3p9 d1 bb811 c13 3p3 1 4 2 3 lk2 t2 bcw31 5v r4 110r sk4 q ch o/p c11 220nf sw1 vco disable r2 4k7 5v sk1 rf in c1 100nf c2 100nf r1 75r l5 4u7 l6 4u7 c3 100nf c4 100pf c5 100nf c6 100pf c7 100nf c8 100pf + c9 47uf 5v 5v 5v 5v vr1 1k r5 680r r6 4k7 r7 680r t1 bcw31 1 4 2 3 lk1 r3 110r sk3 i ch o/p c10 220nf c14 10nf c15 10nf c19 220nf c20 47nf r8 22k r9 22k r10 4k7 t3 bcw31 r11 10k c21 10nf 30v c18 18pf x1 4 mhz c16 10nf c17 100pf 1 2 3 cn1 dc power 30v 5v sda5 3 5v0 4 gnd 5 scl5 6 sk4 i2c 5v fig.7 sl1711 standard evaluation board
8 sl1711 fig.8 fig.9
9 sl1711 agc 1 iout 2 veea 3 ifinb 4 ifin 5 vcca 6 qout 7 veec 8 vccc 9 pscalb 10 pscal 11 veeb 12 vcoa 13 vcob 14 vcodis 15 vccb 16 /32 osc i mixer q mixer ic1 sl1711 c1 100nf c2 100nf r1 75r c3 100pf c4 100nf c5 100pf c6 100nf c7 100pf c8 100nf sw1 vco disable r2 4k7 5v 5v t1 bcw31 r3 110r c10 220nf t2 bcw31 r4 110r c11 220nf 5v sk2 i ch out sk3 q ch out sk1 if in + c9 47uf r6 4k7 vr1 1k r5 680r r7 680r 1 4 2 3 lk2 1 4 2 3 lk1 c13 1nf tp1 agc volts 1 2 3 cn1 power 5v saw resonator 1 2 3 4 saw1 c12 1nf c14 100pf c15 100pf 5v 5v 5v fig.10. sl1711 i & q downconverter with saw resonator
10 sl1711 fig. 11 fig. 12
11 sl1711 application notes these application notes should be read in conjunction with circuit diagrams contained in fig. 7 and 10, and a recommended front end tuner solution contained in fig. 13. these boards have been designed to demonstrate performance and to allow for initial evaluation of the sl1711. varator tuned oscillator refer to fig. 7 circuit diagram and figs. 11 and 12 pcb layout. this application uses a synthesised vco with a tuning range of 460 mhz to 500 mhz. the surface mount inductor l1 is 12 nh. the vco frequency is controlled by the sp5611 synthesiser which is programmed via an i 2 c bus. the rf input to the synthesiser is from the sl1711 prescaler outputs coupled via rf inductors l3 and l4. for functional checking the vco can be tuned by physically shorting the base of transistor t3 to ground and then adjusting the +30 volt supply to tune the vco. under these conditions, due to the unlocked state of the lo, the board will not be representative of locked gain and phase match or phase noise performance. in real applications such the vco control voltage will be provided by the qpsk demodulator circuit, such as the vp305. this circuit provides a line voltage to align the reference lo in the 1711 in both frequency and phase to the centre of the modulation bandwidth, normally 402.75 or 479.5 mhz. as in all feedback loops the bandwidth of the varactor line must be optimised for the symbol rate of the received modulation. it is recommended for optimum performance that the vco application is implemented symmetrically, in presented drive and impedance to the vco ports, as demonstrated in the evaluation schematic and pcb. in the recommended application the varactor diodes are referenced to the vco port dc bias voltages. this limits the minimum tuning voltage on the varactor line to 3v. if lower tuning voltage is required the tank can be ac coupled to the vco ports by 390pf capacitor and a dc reference voltage for the varactor diodes applied by centre tapping the tank inductors. nb the varactor diodes require a minimum of 1v reverse bias for correct operation. in real applications the maximum tuning range required for the vco will be determined by the required lock range of the tuner and the manufacturing tolerance of the tank, assuming the quadrature downconverter section will be alignment free. this tuning range will be typically be much smaller than the demonstration board, which will consequently improve the vco phase noise performance. this application can be ported direct to real system implementations. normal good rf practice must be applied to the layout implementation. prescaler outputs (varactor tuned vco) the vco frequency divided by 32 is available at the differential prescaler outputs, pins 10 and 11. these enable the vco frequency to be synthesised by a pll frequency synthesiser; on the demo board an sp5611 is used for this function however in a real application this function will be provided by the qpsk demodulator function contained in for example the vp305 it is recommended that the prescaler outputs are loaded symmetrically to balance radiation effects. saw resonator oscillator refer to fig. 10 circuit diagram and figs 11 and 12 pcb layout. in the standard application the oscillator uses a varactor diode tuned tank circuit which allows fine tuning of the oscillator frequency via a voltage control line. this control voltage is usually derived from the qpsk/fec decoder vp305/vp306 certain applications do not require this fine tune facility so a fixed frequency application using a saw resonator has been developed. in this application the frequency of the oscillator is determined by the saw resonator. the saw is ac coupled into the vco pins of the device pins 13 and 14 via 100pf coupling capacitors. the saw resonator used in this application is a ; murata part no sar479.45mb10x200 prescaler outputs (sawr tuned vco) the vco frequency divided by 32 is available at the differential prescaler outputs, pins 10 and 11. normally these outputs will not be required since the derotation and fine tuning required will be processed by the qpsk demodulator. however these frequencies could be used if required for other system reference frequencies or clocks. if used it is recommended that the prescaler outputs are loaded symmetrically to balance radiation effects. vco disable the on-chip oscillator can be disabled by connecting vcodis, pin 15, to ground and enabled by connecting to vcc via a 4k7 w pull up resistor. agc the agc facility can be used to control the conversion gain of the sl1711. on the demonstration boards the conversion gain is adjusted by means of a potentiometer, which is set to 2.5v so giving a conversion gain of 38 db. the voltage adjustment range for the agc is approximately 1.5 to 3.5 v. it is important that the agc voltage minimum does not give a conversion gain of greater than 44dbs otherwise the channel amplitude match may be degraded. in real applications the agc can be either set at a fixed control voltage or controlled by means of the agc control signal from the qpsk demodulator dependant on the overall dynamic range requirement of the tuner and its gain distribution.
12 sl1711 i & q baseband outputs the sl1711 offers a greatly improved drive capability over the sl1710 and as such is much less sensitive to the load conditions. it is still important however to carefully balance the loads presented to the sl1711 to ensure no differential gain or phase degradation is introduced by the load circuits, which will also include effects due to track striplines etc. for demonstration purposes the output is unsuitable for connection via co-axial cables to standard test equipment, where such equipment is normally 50 w or highly capacitive. to overcome this problem the outputs of the sl1711 are therefore buffered through emitter followers which are optimised to drive 50 w loads without appreciable degradation in the sl1711 performance. these buffer stages are selectable so enabling the outputs to be loaded directly for interfacing direct with an adc via a low capacitive link. in most applications the sl1711 will normally interface direct into the adc converter such as the vp216, which will present a >1 k w low capacitive load, though it can interface with lower impedances if desired. the output is optimised for typical drive levels of 760 mvp-p and the onset of clipping is typically > 1.5v. care must be taken with system design to ensure that the i and q baseband output signals never exceed 1.2v pk-pk. any gross distortion in the output waveform caused by overdriving the output stages will compromise the system performance. device performance characteristics can only be guaranteed if the device is operated below the onset of clipping. sl1711 evaluation board this board has been created to show the operation of the sl1711 i/q downconverter. it does not attempt to simulate a real system, since in practice the 479.5mhz if oscillator on the sl1711and the 60mhz clock on the subsequent adc would be controlled via the baseband iq demodulator chip such as the vp305 which follows the dual channel adc. for simplicity, the vco is locked using mitel semiconductor sp5611 synthesiser, con- trolled via an i2c bus. for full evaluation, 30v and 5v supplies are necessary. supplies the board must be provided with the following supplies: a) 5v for the sl1711 and sp5611 and 30v for the varactor line. the supply connector is a 3 pin 0.1" pitch pin header. the centre pin of the connector is gnd. outputs driven into hard clipping can exhibit amplitude decline. agc loops should be designed to take account of this. i 2 c bus connections the board is provided with an rj11 i 2 c bus connector which feeds directly to the sp5611 synthesiser. this connects to a standard 6-way connector cable which is supplied with the i 2 c/3-wire bus interface box. input and output connections the board is provided with the following connectors: a) if i/p sma connector sk1 which is ac coupled to the rf input of the sl1711. b) i ch out sk2 and q ch out (sk3) which provide either a buffered or direct baseband output signal from the sl1711 (depending on which way the links lk1 and lk2 are set). the output buffers should be used when driving 50 w test equipment or co-axial lines. links and switches the board is provided with the following: vco disable switch this disables the vco of the sl1711. it does not power down the chip. agc adjust potentiometer the potentiometer sets the agc input voltage of the sl1711 which controls the gain of the chip. tp1 is provided as a means of monitoring the agc voltage. lk1 and lk2 these are links which may be placed either vertically or horizontally to connect the outputs of the sl1711 either directly or via buffers to the sma output connectors of the board. if the links are placed vertically 1-2 and 3- the outputs are connected directly. if the links are placed horizontally 1-3 and 2- the ouputs are connected via buffers.
13 sl1711 programming of synthesisers a sp5611 synthesiser is used to set the frequency of the sl1711 vco 480mhz. since the sl1711 incorporates a divide by 32 the synthesised frequency that the sp5611 must be programmed to is 480/32=15mhz. example a) to program the sl1711 to 480mhz. i2c byte hex code byte 1 (address) c2 byte 2 (programmable divider 8 msbs) 00 byte 3 (programmable divider 8 lsbs) f0 byte 4 (control data) ce byte 5 (port data) 00 c2 is the address byte byte 1. 0f00 is the programmable divider information bytes 2 and 3. ce is the control data information byte 4. **note - the programmable divider information should be set to program 480mhz /32 = 15mhz since the sl1711 provides a divide by 32 prescaler output rather than the vco carrier frequency. it is not possible to program the vco to 479.5mhz when using a 7.8125khz phase comparator frequency. the mini- mum step size is 7.8125khz x 8 (rf prescaler inside sp5611) x 32 (sl1711 output prescaler) = 2mhz. if the reference divider is set to 1024 mode3.90625khz phase comparator frequency, the minimum step size will be 1mhz. this may be achieved by programming the control byte to cc and modifying the programmable divider information for the new step size. sl1711 operation the sl1711 will mix an if input with its own local oscillator. this is controlled as above via a sp5611 synthesiser. normally the vco will be set to the same frequency as the if input, and the signal mixed directly down to baseband. alternatively, a cw rf source may be fed into the input of the sl1711 which is deliberately offset from the vco. by varying the offset from 0-20mhz and monitoring the i and q channel baseband outputs, the flatness response of the chip/ output filter can be measured. the sl1711 oscillator may also be disabled by setting the on-vco-off switch to the off position. an agc voltage adjust pot marked agc adjust is provided, together with a test point. measurement of gain and phase match. a) synthesise the required frequency 480mhz is used in the example above. b) connect an rf signal generator to the input. c)input a signal which should give an output of approx 0dbm (0.707v p-p), in combination with the appropriate agc set- ting. d) connect a vector voltmeter to the buffered outputs when using 50 w inputs. when using high impedance probes, the direct outputs may be used. selection of outputs is via the on board u links. e) calibrate the vector voltmeter and the leads to be used. the calibration should be performed at the chosen baseband frequency and level for maximum accuracy. f) vary the rf input frequency either side of the lo and note the relative i and q gain and phase reading. if you experience any difficulties with this board, or require further help, please contact robert marsh on 01793 518234 or fred herman on 01793 518423
14 sl1711 fig.13 example digital front end architecture note: all ics shown in fig. 13 are available from mitel semiconductor. agc rf i/p from lnb i/p filter 950mhz 2.15ghz tuner (sl2015) tank circuit 480mhz if if filter rf tuner module agc tank agc vco i q pll synth. options (sp5658) (3w bus) (sp5055) (i 2 c bus) (sp5655) (i 2 c bus) (sp5659) (i 2 c bus) 0.22mhz 0.7v pk-pk (sl1711) 2x6 bit, 90ms/s adc (vp216) vco i/p loop/line filters qpsk demod & fec (vp305) data stream
15 sl1711 electrical characteristics test conditions (unless otherwise stated) t amb = 0 o c to 85 o c , * v ee = 0v, vcc = 4.75 to 5.25 v, fif = 479.5 mhz, if bandwidth 22 mhz, output amplitude -11dbv these characteristics are guaranteed by either production test or design. they apply within the specified ambient temperature and supply voltage unless otherwise stated. characteristic pin min typ max units conditions supply voltage 6,9,16 4.75 5.25 v supply current 6,9,16 109 125 ma if input operating 4, 5 350 550 mhz frequency (1) if input impedance 4, 5 75 w over specified frequency operating range, see fig. 6. input return loss 4, 5 12 db over specified frequency operating range, see fig. 6. input noise figure, dsb 4, 5 17 19 db maximum gain setting variation in nf with gain 1 db/db setting vco operation range 350 550 mhz centre frequency and tuning range determined by application. vco phase noise, ssb 96 -85 dbc/hz varactor tuned, determined @ 10khz offset by application. vco vcc sensitivity 2e3 ppm/v free running vco temperature 100 ppm/ c uncompensated stability prescaler output swing 10, 11 1.2 1.6 vp-p prescaler output duty 10, 11 40 50 60 % cycle conversion gain for see fig. 4 agc setting of; 1.5v 44 db terminated voltage conversion gain from 50 w source to 1k w load 2.5v 38 db 3.5v 28 db agc input current 1 100 m a all agc settings i q gain match 0.3 1 db see note 3. i q gain match 0.5 1 db see note 4. i q phase match 1.5 3 deg see note 4. i & q channel in band ripple 0.3 1 db see note 3. i & q channel in band ripple 0.5 1 db see note 4. i q crosstalk -29 -20 db see note 4 and note 2 for derivation of cross modulation
16 sl1711 electrical characteristics (continued) test conditions (unless otherwise stated) t amb = 0 o c to 85 o c, * v ee = 0v, vcc = 4.75 to 5.25 v, fif = 479.5 mhz, if bandwidth +- 22 mhz these characteristics are guaranteed by either production test or design. they apply within the specified ambient temperature and supply voltage unless otherwise stated. characteristic pin min typ max units conditions i & q baseband output 2,7 8 20 w see note (5), and fig. 5. impedance i & q baseband output 2, 7 1.2 1.5 vp-p see note(6), into 1k w load up to clipping level 22mhz baseband ip3 2t , output referred +3 +9 dbv 2 input carriers at -39 dbv within if bandwidth of 22mhz agc set to give composite output of -11 dbv, im3 tone within baseband bandwidth im3 2t output referred -40 dbc 2 input carriers within if bandwidth of 22mhz, agc set to give composite output of -11 dbv, im3 tone within baseband bandwidth all prescaler and other -30 dbc 0.1 - 100mhz, referred to output spurs in i & q baseband amplitude of - 11 dbv. output. power supply rejection 20 dbc attenuation vcc to i & q outputs, over 0-500khz notes: 1. performance not guaranteed over full specified if input operating range 2. i q crosstalk is determined from the gain and phase match by the following formula crosstalk = 20* log (tan(phase error + atan (1+amplitude imbalance) -45 )) 3. over specified gain dynamic, 1k w load up to 22mhz baseband 4. over specified gain dynamic range, 1k w load up to 30mhz baseband 5. baseband bandwidth 0.1 to 22mhz 6. the device should not be operated beyond the point of output clipping. the quality and amplitude of the baseband output signals cannot be guaranteed once this level has been exceeded. 7. * operating temperature range for the SL1711B is 0 c to 70 c. this applies to applications featuring a double sided copper board. for other applications not using such a board, the maximum operating temperature may be reduced. 8. the above device characteristics are guaranteed provided the output is maintained below the onset of clipping.
17 sl1711 absolute maximum ratings all voltages are reffered to vee at 0v characteristics min max units conditions supply voltage, vcc -0.3 7 v iffin &ifinb input voltage 2.5 vp-p ifin & ifinb input dc offset -0.3 vcc+0.3 v iout & qout dc offset -0.3 vcc+0.3 v agc dc offset -0.3 vcc+0.3 v vco1 & 2 dc offset -0.3 vcc+0.3 v vcoddis dc offset -0.3 vcc+0.3 v pscal & pscalb dc offset -0.3 vcc+0.3 storage temperature -55 125 c junction temperature 150 c psop16 package thermal tba c/w resistance, chip to ambient psop16 package thermal tba c/w resitance, chip to case mp16 package thermal resistance 81 c/w chip to ambient mp16 package thermal resistance 28 c/w chip to case power consumption at 5.25v 657 mw esd protection 2 kv mil std 883b method 3015 cat 1 additional information regarding the psop package. the following information should be noted when using the psop package fitted to the sl1711. (a) this package uses the standard soic 16 footprint. (b) there is no need to make a thermal connection between the package and the board. if such a connection is made using a thermal adhesive this will enhance the long term reliability of the product by reducing the junction temperature. (c) the heatsink that is evident on the base of the package is solderable. (d) there is no direct electrical connection between any of the device pins and the metal heatsinkslug. however if the heatsink is to be electrically connected to the pcb these connections should be confined to the ground plane.

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