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IS31AP4088A integrated silicon solution, inc. ? www.issi.com rev.a, 12/21/2011 1 dual 2.84w stereo audio amplifier plus headphone driver january 2012 general description the IS31AP4088A is a dual bridge-connected audio power amplifier which, when connected to a 5v supply, will deliver 2.84w to a 4 ? load. to simplify audio system design, the IS31AP4088A combines dual bridge speaker amplifiers and stereo headphone amplifiers on one chip. the IS31AP4088A features a low-power consumption shutdown mode and thermal shutdown protection. it also utilizes circuitry to reduce ?clicks and pops? during device turn-on. applications ? cell phones, pda, mp4, pmp ? portable and desktop computers ? desktops audio system ? multimedia monitors key specifications ? p o at 1% thd+n, v dd = 5v r l = 4 ? ----------------------------- 2.30w (typ.) r l = 8 ? ----------------------------- 1.38w (typ.) ? p o at 10% thd+n, v dd = 5v r l = 4 ? ----------------------------- 2.84w (typ.) r l = 8 ? ----------------------------- 1.71w (typ.) ? p o at 1% thd+n, v dd = 4v r l = 4 ? ----------------------------- 1.40w (typ.) r l = 8 ? ----------------------------- 0.89w (typ.) ? shutdown current ------------------ 0.04 a (typ.) ? supply voltage range -------------- 2.7v ~ 5.5v ? qfn-16(4mm 4mm) package features ? suppress ?click-and-pop? ? thermal shutdown protection circuitry ? stereo headphone amplifier mode ? micro power shutdown mode typical application circuit r3 20k r1 20k r2 20k r4 20k vdd -outa +outa +outb -outb bypass gnd ina inb + - - - - + + + 4 9 8 5,6,7,13,16 10 12 1 3 2,11 shutdown 15 vcc vcc c3 1uf c4 1uf c2 0.22uf c1 0.22uf working shutdown inb bnc ina bnc r8 100k p honejack ( stereo) r7 100k vcc c5 100uf c6 100uf r5 1k r6 1k hp sense 14 figure 1 typical application circuit
IS31AP4088A integrated silicon solution, inc. ? www.issi.com rev.a, 12/21/2011 2 pin configuration package pin configuration (top view) qfn-16 1 2 3 4 12 11 10 9 +outa vdd -outa ina +outb vdd -outb bypass pin description no. pin description 1 +outa left channel +output. 2,11 vdd supply voltage. 3 -outa left channel ?output. 4 ina left channel input. 5~7,13,16 gnd gnd. 8 inb right channel input. 9 bypass bypass capacitor which provides the common mode voltage. 10 -outb right channel ?output. 12 +outb right channel +output. 14 hp sense headphone sense control. 15 shutdown ???????? shut down control, hold low for shutdown mode. thermal pad connect to gnd.
IS31AP4088A integrated silicon solution, inc. ? www.issi.com rev.a, 12/21/2011 3 ordering information industrial range: -40c to +85c order part no. package qty/reel IS31AP4088A-qfls2-tr qfn-16, lead-free 2500
IS31AP4088A integrated silicon solution, inc. ? www.issi.com rev.a, 12/21/2011 4 absolute maximum ratings supply voltage, v dd -0.3v ~ +6.0v voltage at any input pin -0.3v ~ v dd +0.3v maximum junction temperature, t jmax 150c stora g e temperature r an g e, t stg -65c ~ +150c operating temperature range, t a ? 40c ~ +85c solder information, vapor phase (60s) infrared (15s) 215c 220c note: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the sp ecifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. electrical characteristics the following specifications apply for v dd = 5v, unless otherwise noted. limits apply for t a = 25c. symbol parameter condition typ. limit unit v dd supply voltage 2.7 v(min.) 5.5 v(max.) i dd quiescent power supply current vin = 0v, io = 0a, btl vin = 0v, io = 0a, se 5.7 3 7.5 5.5 ma(max.) ma(max.) i sd shutdown current gnd applied to the shutdown pin 0.036 2 a(max.) v ih_sdb shutdown input voltage high 1.4 v(min.) v il_sdb shutdown input voltage low 0.4 v(max.) v ih_hps hp sense input voltage high 3.8 v(min.) v il_hps hp sense input voltage low 2.8 v(max.) t wu turn on time 1 f bypass cap(c4) 113 ms electrical characteristics operation the following specifications apply for v dd = 5v, unless otherwise noted. limits apply for t a = 25c. symbol parameter condition typ. limit unit vos output offset voltage v in = 0v 5 30 mv(max.) po output power thd+n = 1%, f = 1khz, r l = 8 ? , btl mode 1.38 1.2 w(min.) thd+n = 10%, f = 1khz, r l = 8 ? , btl mode 1.71 1.5 w(min.) thd+n = 1%, f = 1khz, r l = 4 ? , btl mode 2.30 2.0 w(min.) thd+n = 10%, f = 1khz, r l = 4 ? , btl mode 2.84 2.5 w(min.) thd+n total harmonic distortion +noise 1khz, avd = 2, r l = 8 ? , po = 0.4w 0.055 % psrr power supply rejection ratio input floating, 217hz, v ripple = 200mv p-p c4 = 1 f, r l = 8 ? 82 db input floating 1khz, v ripple = 200mv p-p c4 = 1 f, r l = 8 ? 70 db input gnd 217hz, v ripple = 200mv p-p c4 = 1 f, r l = 8 ? 80 db input gnd 1khz v ripple = 200mv p-p c4 = 1 f, r l = 8 ? 75 db x talk channel separation f = 1khz, c4 = 1 f, btl mode, 8 ? -91 db v no output noise voltage 1khz, a-weighted 30 v
IS31AP4088A integrated silicon solution, inc. ? www.issi.com rev.a, 12/21/2011 5 electrical characteristics for single-ended operation the following specifications apply for v dd = 5v, unless otherwise noted. limits apply for t a = 25c. symbol parameter condition typ. limit unit po output power thd+n = 0.5%,f = 1khz r l = 32 ? , se mode 98.5 83 mw(min.) thd+n total harmonic distortion+noise po = 20mw, 1khz, r l = 32 ? 0.013 % psrr power supply rejection raito input floating, 217hz, v ripple = 200mv p-p c4 = 1 f, r l = 8 ? 84 db input floating 1khz, v ripple = 200mv p-p c4 = 1 f, r l = 8 ? 80 db input gnd 217hz, v ripple = 200mv p-p c4 = 1 f, r l = 8 ? 82 db input gnd 1khz v ripple = 200mv p-p c4 = 1 f, r l = 8 ? 80 db x talk channel separation f = 1khz, c6 = 1 f stereo enhanced control = low -68 db v no output noise voltage 1khz, a-weighted 20 v electrical characteristics the following specifications apply for v dd = 3v, unless otherwise noted. limits apply for t a = 25c. symbol parameter condition typ. limit unit i dd quiescent power supply current vin = 0v, io = 0a, btl vin = 0v, io = 0a, se 5 2.6 ma ma i sd shutdown current gnd applied to the shutdown pin 0.02 a v ih_sdb shutdown input voltage high 1.4 v(min) v il_sdb shutdown input voltage low 0.4 v(max) v ih_hps hp sense input voltage high 3.8 v(min) v il_hps hp sense input voltage low 2.8 v(max) t wu turn on time 1 f bypass cap(c4) 120 ms
IS31AP4088A integrated silicon solution, inc. ? www.issi.com rev.a, 12/21/2011 6 electrical characteristics operation the following specifications apply for v dd = 3v, unless otherwise noted. limits apply for t a = 25c. symbol parameter condition typ. limit unit vos output offset voltage v in =0v 2.5 mv po output power thd+n = 1%, f = 1khz,r l = 8 ? , btl mode 0.48 w(min.) thd+n = 10%, f = 1khzr l = 8 ? , btl mode 0.6 w(min.) thd+n = 1%, f = 1khz,r l = 4 ? , btl mode 0.78 w(min.) thd+n = 10%, f = 1khz,r l = 4 ? , btl mode 0.97 w(min.) thd+n tot al ha r m o n i c distortion+noise 1khz, avd = 2, r l = 8 ? , po = 0.15w 0.078 % psrr power supply rejection ratio input floating, 217hz, v ripple = 200mv p-p c4 = 1 f, r l = 8 ? 85 db input floating 1khz, v ripple = 200mv p-p c4 = 1 f, r l = 8 ? 75 db input gnd 217hz, v ripple = 200mv p-p c4 = 1 f, r l = 8 ? 84 db input gnd 1khz v ripple = 200mv p-p c4 = 1 f, r l = 8 ? 75 db x talk channel separation f = 1khz, c4 = 1 f -92 db v no output noise voltage 1khz, a-weighted 30 v electrical characteristics for single-ended operation the following specifications apply for v dd = 3v, unless otherwise noted. limits apply for t a = 25c. symbol parameter condition typ. limit unit po output power thd+n = 0.5%, f = 1khz, r l = 32 ? 36.7 mw thd+n total harmonic distortion+noise po = 20mw, 1khz, r l = 32 ? 0.016 % psrr power supply rejection raito input floating, 217hz, v ripple = 200mv p-p c6 = 1 f, r l = 32 ? 87 db input floating 1khz, v ripple = 200mv p-p c6 = 1 f, r l = 32 ? 80 db input gnd 217hz, v ripple = 200mv p-p c6 = 1 f, r l = 32 ? 82 db input gnd 1khz v ripple = 200mv p-p c6 = 1 f, r l = 32 ? 82 db x talk channel separation f = 1khz, c6 = 1 f stereo enhanced control= low -66 db v no output noise voltage 1khz, a-weighted 20 v
IS31AP4088A integrated silicon solution, inc. ? www.issi.com rev.a, 12/21/2011 7 typical performance characteristics 0.01 20 0.02 0.05 0.1 0.2 0.5 1 2 5 10 10m 2 20m 50m 100m 200m 500m 1 figure 2 thd+n vs. output power 5v, 8ohm, btl at f=1khz 0.001 20 0.01 0.1 0.2 0.5 1 10 1m 200m 2m 5m 10m 20m 50m figure 4 thd+n vs. output power se mode, 5v, 32ohm, f=1khz 0 .01 20 0 .02 0 .05 0.1 0.2 0.5 1 2 5 10 10m 3 20m 50m 100m 500m 1 2 figure 6 thd+n vs. output power 0.01 20 0.02 0.05 0.1 0.2 0.5 1 2 5 10 1m 1 2m 5m 10m 20m 100m 500m figure 3 thd+n vs. output power 3v, 8ohm, btl at f=1khz 0.01 20 0.02 0.05 0.1 0.2 0.5 1 2 5 10 1m 60m 2m 3m 5m 7m 10m 20m 30m figure 5 thd+n vs. output power se mode, 3v, 32ohm, f=1khz 0.01 20 0.02 0.05 0.1 0.2 0.5 1 2 5 10 10m 2 20m 50m 100m 200m 500m 1 figure 7 thd+n vs. output power btl mode, 3v, 4ohm, f=1khz
IS31AP4088A integrated silicon solution, inc. ? www.issi.com rev.a, 12/21/2011 8 0.01 10 0.02 0.05 0.1 0.2 0.5 1 2 5 20 20k 50 100 200 500 1k 2k 5k figure 8 thd+n vs. frequency btl mode, 5v, 8ohm, po=800mw 0.001 10 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 20 20k 50 100 200 500 1k 2k 5k figure 10 thd+n vs. frequency se mode, 5v, 32ohm, po=70mw 0.01 10 0.02 0.05 0.1 0.2 0.5 1 2 5 20 20k 50 100 200 500 1k 2k 5k figure 12 thd+n vs. frequency btl mode, 5v, 4ohm, po=1w 0.01 10 0.02 0.05 0.1 0.2 0.5 1 2 5 20 20k 50 100 200 500 1k 2k 5k figure 9 thd+n vs. frequency btl mode, 3v, 8ohm, po=300mw 0.001 10 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 20 20k 50 100 200 500 1k 2k 5k figure 11 thd+n vs. frequency se mode, 3v, 32ohm, po=20mw 0.01 10 0.02 0.05 0.1 0.2 0.5 1 2 5 20 20k 50 100 200 500 1k 2k 5k figure 13 thd+n vs. frequency btl mode, 3v, 4ohm, po=500mw
IS31AP4088A integrated silicon solution, inc. ? www.issi.com rev.a, 12/21/2011 9 figure 14 psrr vs. freq btl mode, 5v, 8ohm, 200mvpp input terminated figure 16 psrr vs. freq btl mode, 5v, 8ohm, 200mvpp input unterminated figure 18 psrr vs. freq se mode, 5v, 32ohm, 200mvpp input terminated figure 15 psrr vs. freq btl mode, 3v, 8ohm, 200mvpp input terminated figure 17 psrr vs. freq btl mode, 3v, 8ohm, 200mvpp input unterminated figure 19 psrr vs. freq se mode, 3v, 32ohm, 200mvpp input terminated
IS31AP4088A integrated silicon solution, inc. ? www.issi.com rev.a, 12/21/2011 10 figure 20 psrr vs. freq se mode, 5v, 32ohm, 200mvpp input unterminated -6 +3 -5 -4 -3 -2 -1 +0 +1 +2 20 20k 50 100 200 500 1k 2k 5k figure 22 frequency response btl mode, 5v, 8ohm -17.5 +2.5 -15 -12.5 -10 -7.5 -5 -2.5 +0 20 20k 50 100 200 500 1k 2k 5k figure 24 frequency response se mode, 5v, 32ohm, c5/c6=220uf figure 21 psrr vs. freq se mode, 3v, 32ohm, 200mvpp input unterminated -6 +3 -5 -4 -3 -2 -1 +0 +1 +2 20 20k 50 100 200 500 1k 2k 5k figure 23 frequency response btl mode, 3v, 8ohm -17.5 +2.5 -15 -12.5 -10 -7.5 -5 -2.5 +0 20 2 0 k 50 100 20 0 50 0 1k 2 k 5 k figure 25 frequency response se mode, 3v, 32ohm, c5/c6=220uf
IS31AP4088A integrated silicon solution, inc. ? www.issi.com rev.a, 12/21/2011 11 -120 +0 -100 -80 -60 -40 -20 20 20k 50 100 200 500 1k 2k 5k figure 26 crosstalk btl mode, 5v, 8ohm, po=1w -100 +0 -80 -60 -40 -20 20 20k 50 100 200 500 1k 2k 5k figure 28 crosstalk se mode, 5v, 32ohm, po=80mw 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 250 500 750 1000 1250 output power/mw power dissipation figure 30 power dissipation vs. output power btl mode, 5v, f=1 khz, rl=8ohm, thd+n<=1% -120 +0 -100 -80 -60 -40 -20 20 20k 50 100 200 500 1k 2k 5k figure 27 crosstalk btl mode, 3v, 8ohm, po=0.3w -100 +0 -80 -60 -40 -20 20 20k 50 100 200 500 1k 2k 5k figure 29 crosstalk se mode, 3v, 32ohm, po=30mw 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 20406080 output power/mw power dissipation figure 31 power dissipation vs. output power se mode, 5v, f=1 khz, rl=32ohm a to b a to b b to a b to a b to a b to a a to b a to b
IS31AP4088A integrated silicon solution, inc. ? www.issi.com rev.a, 12/21/2011 12 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.533.544.555.5 supply voltage/v output power/mw 1%thd+n 10%thd+n figure 32 output power vs. power supply btl mode, f=1 khz, rl=8 ohm
IS31AP4088A integrated silicon solution, inc. ? www.issi.com rev.a, 12/21/2011 13 application information exposed-dap package pcb mounting considerations the IS31AP4088A?s qfn (die attach paddle) package provides a low thermal resistance between the die and the pcb to which the part is mounted and soldered. this allows rapid heat transfer from the die to the surrounding pcb copper traces, ground plane and, finally, surrounding air. the qfn package must have its dap soldered to a copper pad on the pcb. the dap?s pcb copper pad is connected to a large plane of continuous unbroken copper. this plane forms a thermal mass and heat sink and radiation area. place the heat sink area on either outside plane in the case of a two-sided pcb, or on an inner layer of a board with more than two layers. bridge configuration explanation as shown in figure 2, the IS31AP4088A consists of two pairs of operational amplifiers, forming a two-channel (channel a and channel b) stereo amplifier. external feedback resistors r2, r4 and input resistors r1 and r3 set the closed-loop gain of amp a (-out) and amp b (-out) whereas two internal 20k ? resistors set amp a?s (+out) and amp b?s (+out) gain at 1. the IS31AP4088A drives a load, such speaker, connected between the two amplifier outputs, ? outa and +outa. figure 2 shows that amp a?s (-out) output serves as amp a?s (+out) input. this results in both amplifiers producing signals identical in magnitude, but 180 out of phase. taking advantage of this phase difference, a load is placed between ? outa and +outa and driven differentially (commonly referred to as ?bridge mode?). this results in a differential gain of a vd = 2(rf/ri) (1) or a vd = 2(r2/r1) bridge mode amplifiers are different from single-ended amplifiers that drive loads connected between a single amplifier?s output and ground. for a given supply voltage, bridge mode has a distinct advantage over the single-ended configuration: its differential output doubles the voltage swing across the load. this produces four times the output power when compared to a single-ended amplifier under the same conditions. this increase in attainable output power assumes that the amplifier is not current limited another advantage of the differential bridge output is no net dc voltage across the load. this is accomplished by biasing channel a?s and channel b?s outputs at half-supply. this eliminates the coupling capacitor that single supply, single ended amplifiers require. eliminating an output coupling capacitor in a single-ended configuration forces a single-supply amplifier?s half-supply bias voltage across the load. this increases internal ic power dissipation and may permanently damage loads such as speakers. power dissipation power dissipation is a major concern when designing a successful single-ended or bridged amplifier. equation (2) states the maximum power dissipation point for a single ended amplifier operating at a given supply voltage and driving a specified output load. p dmax = (v dd ) 2 /(2 2 r l ) single-ended (2) however, a direct consequence of the increased power delivered to the load by a bridge amplifier is higher internal power dissipation for the same conditions. the IS31AP4088A has two operational amplifiers per channel. the maximum internal power dissipation per channel operating in the bridge mode is four times that of a single-ended amplifier. from equation (3), assuming a 5v power supply and an 8 ? load, the maximum single ended amplifier power dissipation is 0.63w or 1.23w for btl mode per channel. p dmax = 4(v dd ) 2 /(2 2 r l ) bridge mode (3) the IS31AP4088A?s power dissipation is twice that given by equation (2) or equation (3) when operating in the stereo mode. and in stereo mode, twice the maximum power dissipation point given by equation (3) must not exceed the power dissipation given by equation (4): p dmax ' = (t jmax ? t a )/ ja (4) the IS31AP4088A?s t jmax = 150c. in the qfn package soldered to a dap pad that expands to a copper area of 5in2 on a pcb, the IS31AP4088A?s ja is 20c/w. at any given ambient temperature ta, use equation (4) to find the maximum internal power dissipation supported by the ic packaging. rearranging equation (4) and substituting p dmax for p dmax' results in equation (5). this equation gives the maximum ambient temperature that still allows maximum stereo power dissipation without violating the IS31AP4088A?s maximum junction temperature. t a = t jmax ? 2p dmax ja (5) for a typical application with a 5v power supply and a 4 ? load, the maximum ambient temperature that allows maximum stereo power dissipation without exceeding the maximum junction temperature is approximately 99c for the qfn package. t jmax = p dmax ja + t a (6) equation (6) gives the maximum junction temperature t jmax . if the result violates the IS31AP4088A?s 150c, reduce the maximum junction temperature by reducing the power supply voltage or increasing the load
IS31AP4088A integrated silicon solution, inc. ? www.issi.com rev.a, 12/21/2011 14 resistance. further allowance should be made for increased ambient temperatures. the above examples assume that a device is a surface mount part operating around the maximum power dissipation point. since internal power dissipation is a function of output power, higher ambient temperatures are allowed as output power or duty cycle decreases. if the result of equation (2) is greater than that of equation (3), then decrease the supply voltage, increase the load impedance, or reduce the ambient temperature. if these measures are insufficient, a heat sink can be added to reduce ja . the heat sink can be created using additional copper area around the package, with connections to the ground pin(s), supply pin and amplifier output pins. external, solder attached smt heat sinks such as the thermally 7106d can also improve power dissipation. when adding a heat sink, the ja is the sum of jc , cs , and sa . ( jc is the junction-to-case thermal impedance, cs is the case-to-sink thermal impedance, and sa is the sink-to-ambient thermal impedance.) refer to the typical performance characteristics curves for power dissipation information at lower output power levels. power supply bypassing as with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply rejection. applications that employ a 5v regulator typically use a 10 f in parallel with a 0.1 f filter capacitor to stabilize the regulator?s output, reduce noise on the supply line, and improve the supply?s transient response. however, their presence does not eliminate the need for a local 1.0 f tantalum bypass capacitance connected between the IS31AP4088A?s supply pins and ground. do not substitute a ceramic capacitor for the tantalum. doing so may cause oscillation. keep the length of leads and traces that connect capacitors between the IS31AP4088A?s power supply pin and ground as short as possible. micro-power shutdown the voltage applied to the shutdown pin controls the IS31AP4088A?s shutdown function. activate micro-power shutdown by applying gnd to the shutdown pin. when active, the IS31AP4088A?s micro-power shutdown feature turns off the amplifier?s bias circuitry, reducing the supply current. the low 0.04 a typical shutdown current is achieved by applying a voltage that is as near as gnd as possible to the shutdown pin. table 1 shows the logic signal levels that activate and deactivate micro-power shutdown and headphone amplifier operation. there are a few ways to control the micro-power shutdown. these include using a single-pole, single-throw switch, a microprocessor, or a microcontroller. when use a switch, connect an external 100k resistor between the shutdown pin and gnd. select normal amplifier operation by closing the switch. opening the switch sets the shutdown pin to gnd through the 100k resistor, which activates the micro power shutdown. the switch and resistor guarantee that the shutdown pin will not float. this prevents unwanted state changes. in a system with a microprocessor or a microcontroller, use a digital output to apply the control voltage to the shutdown pin. driving the shutdown pin with active circuitry eliminates the pull up resistor. shutdown pin headphone jack sense pin operational shutdown mode logic high low(hp not plugged in) bridged /btl logic high high(hp plugged in) single ended logic low don?t care micro power shutdown applying a logic level to the IS31AP4088A?s hp sense headphone control pin turns off amp a (+out) and amp b (+out) muting a bridged-connected load. quiescent current consumption is reduced when the ic is in this single-ended mode. figure 33 shows the implementation of the IS31AP4088A?s headphone control function. with no headphones connected to the headphone jack, the r5-r8 voltage divider sets the voltage applied to the hp sense pin (pin 14) at approximately 50mv. this 50mv enables amp a (+out) and amp b (+out) placing the IS31AP4088A in bridged mode operation. while the IS31AP4088A operates in bridged mode, the dc potential across the load is essentially 0v. therefore, even in an ideal situation, the output swing cannot cause a false single ended trigger. connecting headphones to the headphone jack disconnects the headphone jack contact pin from ? outa and allows r7. to pull the hp sense pin up to v dd. this enables the headphone function, turns off amp a (+out) and amp b (+out) which mutes the bridged speaker. the amplifier then drives the headphones, whose impedance is in parallel with resistors r5 and r6. these resistors have negligible effect on the
IS31AP4088A integrated silicon solution, inc. ? www.issi.com rev.a, 12/21/2011 15 IS31AP4088A?s output drive capability since the typical impedance of headphones is 32 ? . figure 33 also shows the suggested headphone jack electrical connections. the jack is designed to mate with a three wire plug. the plug?s tip and ring should each carry one of the two stereo output signals, whereas the sleeve should carry the ground return. a headphone jack with one control pin contact is sufficient to drive the hp sense pin when connecting headphones. figure 33 headphone circuit selecting proper external components optimizing the IS31AP4088A?s performance requires properly selecting external components. though the IS31AP4088A operates well when using external components with wide tolerances, best performance is achieved by optimizing component values. the IS31AP4088A is unity-gain stable, giving a designer maximum design flexibility. the gain should be set to no more than a given application requires. this allows the amplifier to achieve minimum thd+n and maximum signal-to-noise ratio. these parameters are compromised as the closed-loop gain increases. however, low gain demands input signals with greater voltage swings to achieve maximum output power. fortunately, many signal sources such as audio codecs have outputs of 1vrms (2.83v p-p ). please refer to the audio power amplifier design section for more information on selecting the proper gain. input capacitor value selection amplifying the lowest audio frequencies requires high value input coupling capacitors (c1 and c2) in figure 2. a high value capacitor can be expensive and may compromise space efficiency in portable designs. in many cases, however, the speakers used in portable systems, whether internal or external, have little ability to reproduce signals below 150 hz. applications using speakers with this limited frequency response reap little improvement by using large input capacitor. besides effecting system cost and size, c1 and c2 have an effect on the IS31AP4088A?s click and pop performance. when the supply voltage is first applied, a transient (pop) is created as the charge on the input capacitor changes from zero to a quiescent state. the magnitude of the pop is directly proportional to the input capacitor?s size. higher value capacitors need more time to reach a quiescent dc voltage (usually v dd /2) when charged with a fixed current. the amplifier?s output charges the input capacitor through the feedback resistors, r2 and r8. thus, pops can be minimized by selecting an input capacitor value that is no higher than necessary to meet the desired ? 3db frequency. a shown in figure 2, the input resistors (r1, 4, 5, and 6) and the input capacitors, c1 and c2 produce a ? 3db high pass filter cutoff frequency that is found using equation (7). f -3db = 1/2 r in c in = 1/2 r1c1 (7) as an example when using a speaker with a low frequency limit of 150hz, c1, using equation (7) is 0.053 f. the 0.33 f c1 shown in figure 1 allows the IS31AP4088A to drive high efficiency, full range speaker whose response extends below 30hz. bypass capacitor value selection besides minimizing the input capacitor size, careful consideration should be paid to value of c6, the capacitor connected to the bypass pin. since c6 determines how fast the IS31AP4088A settles to quiescent operation, its value is critical when minimizing turn-on pops. the slower the IS31AP4088A?s outputs ramp to their quiescent dc voltage (nominally 1/2 vdd), the smaller the turn-on pop. choosing c6 equal to 1.0 f along with a small value of c1 (in the range of 0.1 f to 0.39 f), produces a click-less and pop-less shutdown function. as discussed above, choosing c1 no larger than necessary for the desired bandwidth helps minimize clicks and pops. connecting a 1 f capacitor, c6, between the bypass pin and ground improves the internal bias voltage?s stability and improves the amplifier?s psrr. optimizing click and pop reduction performance the IS31AP4088A contains circuitry that minimizes turn-on and shutdown transients or ?clicks and pop?. for this discussion, turn-on refers to either applying the power supply voltage or when the shutdown mode is deactivated. when the part is turned on, an internal current source changes the voltage of the bypass pin in a controlled, linear manner. ideally, the input and outputs track the voltage applied to the bypass pin. the gain of the internal amplifiers remains unity until the voltage on the bypass pin reaches 1/2 v dd . as soon as the voltage on the bypass pin is stable, the IS31AP4088A
IS31AP4088A integrated silicon solution, inc. ? www.issi.com rev.a, 12/21/2011 16 device becomes fully operational. although the bypass pin current cannot be modified, changing the size of c6 alters the device?s turn-on time and the magnitude of ?clicks and pops?. increasing the value of c6 reduces the magnitude of turn-on pops. however, this presents a tradeoff: as the size of c6 increases, the turn-on time increases. there is a linear relationship between the size of c6 and the turn-on time. here are some typical turn-on times for various values of c6 (all tested at v dd = 5v): c6 t on 0.01 f 13ms 0.1 f 26ms 0.22 f 44ms 0.47 f 68ms 1.0 f 113ms in order to eliminate ?clicks and pops?, all capacitors must be discharged before turn-on. rapidly switching v dd on and off may not allow the capacitors to fully discharge, which may cause ?click-and-pop?. audio power amplifier design audio amplifier design: driving 1w into an 8 ? load. the following are the desired operational parameters: power output: 1wrms load impedance: 8 ? input level: 1vrms input impedance: 20k ? bandwidth: 100hz ? 20khz 0.25db the design begins by specifying the minimum supply voltage necessary to obtain the specified output power. one way to find the minimum supply voltage is to use the output power vs. supply voltage curve in the typical performance characteristics section. another way, using equation (8), is to calculate the peak output voltage necessary to achieve the desired output power for a given load impedance. to account for the amplifier?s dropout voltage, two additional voltages, based on the dropout voltage vs. supply voltage in the typical performance characteristics curves, must be added to the result obtained by equation (8). the result is in equation (9). (8) v dd (v outpeak + (v odtop + v odbot )) (9) the output power vs. supply voltage graph for an 8 ? load indicates a minimum supply voltage of 4.35v for a 1w output at 1% thd+n. this is easily met by the commonly used 5v supply voltage. the additional voltage creates the benefit of headroom, allowing the IS31AP4088A to produce peak output power in excess of 1.2w at 5v of vdd and 1% thd+n without clipping or other audible distortion. the choice of supply voltage must also not create a situation that violates maximum power dissipation as explained above in the power dissipation section. after satisfying the IS31AP4088A?s power dissipation requirements, the minimum differential gain needed to achieve 1w dissipation in an 8 ? load is found using equation (10). (10) thus, a minimum gain of 2.83 allows the IS31AP4088A?s to reach full output swing and maintain low noise and thd+n performance. for this example, let a vd = 3. the amplifier?s overall gain (non stereo enhanced mode) is set using the input (r1 and r9) and feedback resistors r2 and r8. with the desired input impedance set at 20k ? , the feedback resistor is found using equation (11). r2/r1 = a vd /2 (11) the value of r f is 30k ? . the last step in this design example is setting the amplifier?s ? 3db frequency bandwidth. to achieve the desired 0.25db pass band magnitude variation limit, the low frequency response must extend to at least one-fifth the lower bandwidth limit and the high frequency response must extend to at least five times the upper bandwidth limit. the gain variation for both response limits is 0.17db, well within the 0.25db desired limit. the results are an f l = 100hz/5 = 20hz and an f h = 20khz5 = 100khz. as mentioned in the external components section, r1 and c1 create a high pass filter that sets the amplifier?s lower band pass frequency limit. find the coupling capacitor?s value using equation (12). c1 1/(2 r1f l ) (12) the result is 1/(2 20k ? 20hz) = 0.398 f use a 0.39 f capacitor, the closest standard value. the product of the desired high frequency cutoff (100 khz in this example) and the differential gain, a vd , determines the upper pass band response limit. with a vd = 3 and f h = 100khz, the closed-loop gain bandwidth product (gbwp) is 300 khz. this is less than the IS31AP4088A?s 3.5mhz gbwp. with this margin, the amplifier can be used in designs that
IS31AP4088A integrated silicon solution, inc. ? www.issi.com rev.a, 12/21/2011 17 require more differential gain while avoiding performance-restricting bandwidth limitations. stereo enhanced stereo enhancement the IS31AP4088A features a stereo enhanced audio enhancement effect that widens the perceived soundstage from a stereo audio signal. the stereo enhanced audio enhancement improves the apparent stereo channel separation whenever the left and right speakers are too close to one another, due to system size constraints or equipment limitations. an external rc network, shown in figure 2, is required to enable the stereo enhanced effect. the amount of the stereo enhanced effect is set by the r5 and c7 or cadj. decreasing the value of r5 will increase the stereo enhanced effect. increasing the value of the capacitors (c7 or cadj) will decrease the low cutoff frequency at which the stereo enhanced effect starts to occur, as shown by equation 13. f (?3db) = 1 / 2 r5cadj (13) the amount of perceived stereo enhanced is also dependent on many other factors such as speaker placement and the distance to the listener. therefore, it is recommended that the user try various values of r5 and cadj to get a feel for how the stereo enhanced effect works in the application. there is not a ?right or wrong? for the effect, it is merely what is most pleasing to the individual user. take note that r3 and r4 replace r2, and r7 and r6 replace r8 when stereo enhanced mode is enabled.
IS31AP4088A integrated silicon solution, inc. ? www.issi.com rev.a, 12/21/2011 18 classification reflow profiles profile feature pb-free assembly preheat & soak temperature min (tsmin) temperature max (tsmax) time (tsmin to tsmax) (ts) 150c 200c 60-120 seconds average ramp-up rate (tsmax to tp) 3c/second max. liquidous temperature (tl) time at liquidous (tl) 217c 60-150 seconds peak package body temperature (tp)* max 260c time (tp)** within 5c of the specified classification temperature (tc) max 30 seconds average ramp-down rate (tp to tsmax) 6c/second max. time 25c to peak temperature 8 minutes max. figure 34 classification profile
IS31AP4088A integrated silicon solution, inc. ? www.issi.com rev.a, 12/21/2011 19 tape and reel information
IS31AP4088A integrated silicon solution, inc. ? www.issi.com rev.a, 12/21/2011 20 package information qfn-16 note: all dimensions in millimeters unless otherwise stated.

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